TWI334490B

TWI334490B - Test board

Info

Publication number: TWI334490B
Application number: TW96126602A
Authority: TW
Inventors: Ching Chun Wang; Tong-Hong Wang; Chang Lin Yeh; Yi Shao Lai
Original assignee: Advanced Semiconductor Eng
Priority date: 2007-07-20
Filing date: 2007-07-20
Publication date: 2010-12-11
Also published as: TW200905222A

Description

1334490 ASEKI922-NEW-FINAL-TW-2〇〇7〇72〇九、發明說明：【發明所屬之技術領域】本發明是有關於—種職餘，且制是有關於用於晶片接合之可靠度泪,】試的測試載板。【先前技術】 ^積體電路或晶{的$造過財，不管是在哪一個階二、，對積體電路或晶片進行電性的測試都是必的。母一個積體電路不管是在晶圓的型離或是、 Ϊ性都以確定其是否為良品以及讀定其電性更::::構也日趨複雜，是以高速且精確的中制為習知—種測試載板之俯視圖，® 1Β為圖1Α "°載板承載一封裝元件之剖示圖。請來昭圖1Α以及 = '習_式载板1〇〇包括一介電層m、多個接; -声墊13G以及多條導線140。介電層110具有 ' 2 ’而表面U2具有一元件接合區112a，其中接介雷分佈於元件接合區ll2a内。測試塾130配置於續執之表面U2上，且位於元件接合區112a外。測導綠14Π與接墊120透過配置於介電層110之表面112之導線140電性連接。封裝元件5〇與元件接合區U2a内之接墊以〇電性連。使用者可由部份的測試墊13〇輸入-測試訊號至封裝 1334490 ASEK1922-NEW-FINAL-TW-20070720 元件50，並由另一部份的測試墊i3〇讀取測試結果。由於習知測試載板100之導線14〇是配置於介電層 110之表面112上’因此容易在封裝元件50與測試載板1〇〇接合後受到結構上之應力集中或是外力作用，而使得導線 H0在應力集中區150形成斷路’如此將導致在測試時無法判斷測得的錯誤是由封裝元件5 〇與測試載板丨〇〇之間的接合不f所造成的或是由測試載板1〇〇本身之斷線所造成，。換s之，此可靠度不佳的測試載板設計將直接影響測試時的準確度。【發明内容】連接板’其測試塾與接塾間之電性 =開而具有車父向的可靠度與測試準確度。1334490 ASEKI922-NEW-FINAL-TW-2〇〇7〇72〇9, invention description: [Technical field of the invention] The present invention relates to a kind of occupation, and the system is related to reliability for wafer bonding Tears,] test the test board. [Prior Art] ^Integrated circuits or crystals have been made, and no matter which stage is used, electrical testing of integrated circuits or wafers is a must. The mother's integrated circuit, whether it is in the wafer's type or ambiguity, determines whether it is good or not, and the electrical properties are more:::: The structure is becoming more and more complex, with high speed and accurate medium system. A top view of a test carrier is shown in Fig. 1 Α "° The carrier plate carries a cross-sectional view of a package component. Please refer to FIG. 1 and = 'X-type carrier 1' includes a dielectric layer m, a plurality of connections; - an acoustic pad 13G and a plurality of wires 140. The dielectric layer 110 has '2' and the surface U2 has a component land 112a in which the interface lightning is distributed within the element land 11b. The test cartridge 130 is disposed on the surface U2 of the continuation and is located outside the component land 112a. The green guide 14 is electrically connected to the pad 120 through a wire 140 disposed on the surface 112 of the dielectric layer 110. The package component 5 is electrically connected to the pads in the component bonding region U2a. The user can input a test signal from a portion of the test pad 13 to the package 1334490 ASEK1922-NEW-FINAL-TW-20070720 component 50 and read the test result from another portion of the test pad i3〇. Since the wires 14 of the conventional test carrier 100 are disposed on the surface 112 of the dielectric layer 110, it is easy to be subjected to structural stress concentration or external force after the package component 50 is bonded to the test carrier 1 . The wire H0 is caused to open in the stress concentration region 150. This will result in the failure to judge during the test that the measured error is caused by the joint f between the package component 5 and the test carrier, or by the test load. The board 1 is caused by the disconnection of itself. In other words, this poorly designed test carrier design will directly affect the accuracy of the test. SUMMARY OF THE INVENTION The connection board ''''''''''''''

其具有’多層本:明之内容’在此提出-種測試载板，塾。上述載拓呈^内層線路層電性連接接塾與測試件，以對以;二=區，用以承載-封裳元 —表層線路層、至a、一測忒栽板包括多個介電層、試墊。表層線路層“介;外多個接墊以及多個測兩相鄰的介電屛之門，取外側。内層線路層位於置“區内線路!。接塾可疋件接合，且接墊電性：：線路層上，用以與封裝測試塾配置於 ^層線路層與内層線路層。由内層線路層電表層缘路層上，且測試塾藉〜生連接至其觸應的部份接^ 错 1334490 ASEKl 922-NEW-FINAL-TW-20070720 上述測試載板更可包括-保護層，其覆蓋表層線路層’並暴露出接墊以及測試塾。在本發明之-實施例中，上述内層線路層包括多 H用时別連翻試塾以及其所對應的部份接塾， ^表^路制可包括錄第二導線，且第二導線分別歲It has a 'multi-layered version: the content of the Ming' is proposed here - a test carrier, 塾. The above-mentioned loading and unloading layer is electrically connected to the inner layer and the test piece is opposite to the test piece, and the second layer is used to carry the - seal body-surface layer, to a, and the test board comprises a plurality of dielectrics. Layer, test pad. The surface layer of the surface layer is “intermediate; multiple external pads and multiple adjacent dielectric gates are taken from the outside. The inner layer is located in the “area line!”. The interface can be bonded to the device, and the electrical properties of the pad are: on the circuit layer, and are arranged on the circuit layer and the inner circuit layer with the package test. From the inner layer of the circuit layer on the edge layer of the circuit board, and the test is connected to the part of the touch that is connected to it. 1334490 ASEKl 922-NEW-FINAL-TW-20070720 The above test carrier may further include a protective layer. It covers the surface circuit layer 'and exposes the pads and test flaws. In the embodiment of the present invention, the inner layer circuit layer includes a multi-H time-in-time test and a corresponding partial connection, and the surface circuit system may include a second wire, and the second wire is respectively

，另提出一種測試載板，其為一單;= I封裝元件，測試載板包括—介電層、多個接墊、一接塾連接線路、多侧餘以及多條第—特。介電异 -第-表面以及與其相對之—第二表面，第—表^具有 1件接合H，用以承載封I元件。接塾可呈陣列配置於兀件接合區⑽帛-表面上’㈣與锻元件接合务連接線路位於第一表面與第二表面至少其中之一上，並性連接至接墊。測試墊g:置於元件接合區外的第―表面iAnother test carrier is provided, which is a single package; = I package component, the test carrier includes a dielectric layer, a plurality of pads, a connection line, a plurality of sides, and a plurality of sections. The dielectric iso-first surface and the second surface opposite thereto, the first surface, have a joint H for carrying the I-I element. The contacts may be arranged in an array on the 接合-engagement region (10) 表面-surface ′ (4) and the wrought component bonding connection line is located on at least one of the first surface and the second surface, and is connected to the pad. Test pad g: the first surface i placed outside the component joint area

上。第一導線配置於第二表面上，且測試墊分別藉由第一導線而電性連接至其所對應的部份接墊。曰上述測試載板更可包括-保護層，其覆蓋表層線路層’並暴露出接墊以及測試墊。在本發明之-實施射，上述賴載板更包括 -導線，配置於第-表社’並分職第—導線並聯於试塾以及其所對應的部份接墊之間。 ' 基於上述’本發明因以内層線路層電性連接接塾試墊’或是在測試載板為單層板的情況下，將電捲接塾與測試私第—導雜置於職紐之下方。因此，可 1334490 ASEK1922-NEW-FINAL-TW-20070720 避免連接於接墊與測試墊之間的導線受載板之間的應力作用而產生斷線。如此，η 件與測試的可靠度，並可避免測試時將測試栽拓1提间測。式载板封裝元件與測試載板之間的接合不良，^斷線誤判為準確度。而提高測試載板的為讓本發明之上述特徵和優點能更明舉實施例，並配合所附圖式，作詳細說明如下。，下文特【實施方式】 n林發明-實施财觀额之俯· 為圖2Α中測試載板承載一封裝元件之剖示圖。請夹Β 測試載板2〇0可應用於測試—封裝元件50，測试載板包括-介電層21G、多個接墊22()、—接塾接線路232、多個測試墊24〇以及多條第—導線μ〗介電層210具有一第—表面犯以及與其相 ^弟二表面214，第一表面212上具有一元件接合區用財載封裝元件5〇。接塾22〇例如呈陣列配置，其位於元件接合區212a内的第一表面212上，用以與封裝凡件50接合。接墊連接線路232位於第一表面212上並電性連接至接塾22〇。值得—提的是，_在本實施例中乂接塾連接線路232位於第—表面212上為例說明，但接墊連接線路232亦可配置於其他位置，例如第二表面214 上。測試墊240配置於元件接合區212a外的第一表面212 上而第一導線252配置於第二表面214上，且測試墊240 1334490 ASEK1922-NEW-FINAL-TW-20070720 =藉由第-導線252而電性連接至其所對應的部份接塾由於本實施例藉由位於介電層210之第二表面214的第一導線252電性連接接墊220與測試墊24〇，因此在封裝元件50與接墊220接合時，第一導線252不易受到封裝元件50與測試載板200接合後的應力作用而產生斷線。^ 此，將有助於提高測試載板200的可靠度，進而可確保進行測試時的準確度。 ” 圖2C為圖2A中測試載板與封裝元件之另—種配置方式剖視圖。請參照圖2A及圖2C，上述測試載板2〇〇更可包括一保護層260，配置於介電層210上以保護測試載板 200，且暴露出接墊220以供封裝元件5〇接合，並暴露出測試墊240以供測試。此外，測試載板2〇〇更可包括多條第一導線234，配置於第一表面212上，並分別與第一導線252並聯於測試墊240以及其所對應的部份接墊22〇之間。以下配合圖式說明本發明之另一實施例。圖3A為本發明另一實施例中測試載板承載一封裝元件之剖視圖，圖 3B為圖3A中測試載板與封裝元件之另一種配置方式剖視圖。需先說明的是，測試載板2〇〇a與上述測試載板200 大致相同，且在上述實施例與本實施例中，相同或相似的元件標號代表相同或相似的元件。以下將針對兩實施例不同之處詳加說明，相同之處便不再贅述。請參照圖3A，本實施例之測試載板200a與上述測試載板200之不同處在 1334490 ASEK1922-NE W-FINAL-T W-20070720 於，測試載板200a包括多個介電層210，且以多個内層線路層250取代第一導線252，並以一表層線路層230取代接墊連接線路232 (請參照圖2A)以及第二導線234。on. The first wire is disposed on the second surface, and the test pads are electrically connected to the corresponding partial pads by the first wires.曰 The above test carrier may further include a protective layer covering the surface wiring layer ′ and exposing the pads and the test pads. In the present invention, the above-mentioned slab is further provided with a wire disposed at the first table and connected to the first wire in parallel between the test piece and its corresponding partial pad. 'Based on the above invention, the inner layer is electrically connected to the test pad' or the test carrier is a single layer, and the electric coil is connected to the test. Below. Therefore, 1334490 ASEK1922-NEW-FINAL-TW-20070720 avoids the occurrence of wire breakage caused by the stress between the wires connected to the pads and the test pads. In this way, the reliability of the η piece and the test can be avoided, and the test can be avoided during the test. The carrier board has poor bonding between the package component and the test carrier board, and the wire breakage is misjudged as accuracy. The above-described features and advantages of the present invention will be described in more detail in conjunction with the accompanying drawings. [Embodiment] n-Lin invention-implementation of the financial amount of the figure is a cross-sectional view of the test carrier carrying a package component in FIG. Please clamp the test carrier 2〇0 to be applied to the test-package component 50. The test carrier includes a dielectric layer 21G, a plurality of pads 22 (), a connection line 232, and a plurality of test pads 24 And a plurality of first-wires, the dielectric layer 210 has a first surface and a second surface 214, and the first surface 212 has a component bonding area for the package. The pads 22 are, for example, in an array configuration that is located on the first surface 212 within the component landing 212a for engagement with the package member 50. The pad connection line 232 is located on the first surface 212 and is electrically connected to the interface 22A. It is worth mentioning that, in the present embodiment, the connection line 232 is located on the first surface 212 as an example, but the pad connection line 232 may also be disposed at other locations, such as the second surface 214. The test pad 240 is disposed on the first surface 212 outside the component land 212a and the first wire 252 is disposed on the second surface 214, and the test pad 240 1334490 ASEK1922-NEW-FINAL-TW-20070720 = by the first wire 252 The electrical connection to the corresponding portion of the interface is electrically connected to the test pad 24 by the first wire 252 of the second surface 214 of the dielectric layer 210. When the 50 is bonded to the pad 220, the first wire 252 is less susceptible to stress caused by the bonding of the package component 50 and the test carrier 200 to cause disconnection. ^ This will help to improve the reliability of the test carrier 200, which in turn ensures the accuracy of the test. 2C is a cross-sectional view showing another configuration of the test carrier and the package component of FIG. 2A. Referring to FIG. 2A and FIG. 2C, the test carrier 2 can further include a protective layer 260 disposed on the dielectric layer 210. The test carrier 200 is protected to expose the pad 220 for bonding the package component 5 and exposes the test pad 240 for testing. Further, the test carrier 2 may further include a plurality of first wires 234, The first surface 212 is disposed on the first surface 212 and is respectively connected between the test pad 240 and the corresponding partial pads 22A of the first wire 252. Another embodiment of the present invention will be described below with reference to the drawings. In another embodiment of the present invention, a test carrier carries a package component, and FIG. 3B is a cross-sectional view of another configuration of the test carrier and the package component of FIG. 3A. First, the test carrier 2A and The above test carrier 200 is substantially the same, and in the above embodiments and the present embodiment, the same or similar component numbers denote the same or similar components. The differences between the two embodiments will be described in detail below, and the same is not the same. Let me repeat 3A, the test carrier 200a of the present embodiment is different from the test carrier 200 described above at 1334490 ASEK1922-NE W-FINAL-T W-20070720. The test carrier 200a includes a plurality of dielectric layers 210, and more The inner layer circuit layer 250 replaces the first wire 252 and replaces the pad connection line 232 (please refer to FIG. 2A) and the second wire 234 with a surface layer 230.

具體而言，内層線路層250配置於兩相鄰之介電層210 之間，其電性連接測試墊240及其所對應的部份接墊220，其中内層線路層250例如由多條上述之第一導線252所組成。另外，表層線路層230位於介電層210的最外側，其中表層線路層230例如是由多條上述之接墊連接線路232 (請參照圖2A)與第二導線234所構成。值知·注思的是，在本實施例中雖以多個内層線路層 250為例說明，但亦可僅配置一内層線路層25〇，本發明並不以此為限。另外’如圖3B所示，測試载板施亦可不，有第二導線234而僅以内層線路層250連接測試塾24〇及其所對應的部份接墊220。Specifically, the inner layer circuit layer 250 is disposed between the two adjacent dielectric layers 210, and electrically connected to the test pad 240 and its corresponding partial pads 220, wherein the inner layer circuit layer 250 is, for example, a plurality of the above-mentioned The first wire 252 is composed of. Further, the surface wiring layer 230 is located at the outermost side of the dielectric layer 210, and the surface wiring layer 230 is composed of, for example, a plurality of the above-mentioned pad connection lines 232 (please refer to FIG. 2A) and the second wires 234. It is to be noted that in the present embodiment, a plurality of inner layer wiring layers 250 are exemplified, but only one inner wiring layer 25 may be disposed, and the present invention is not limited thereto. In addition, as shown in FIG. 3B, the test carrier may or may not be provided with the second wire 234 and only the inner layer 250 is connected to the test pad 24 and its corresponding partial pad 220.

’’’不上所述，本發明之測試載板以配置於介電層之第二 ίΓΙΐ—ί線或内層線路層取代習知測試載板酉日己置於ΐ 2導線。SUb，在難元件與測試倾接合時，接 2塾之間的電性連接不易gj封裝元 ^ 尚測i式載板的準確度。民雖然本發明已以實施例揭露如上’然其並非用而提以限定 1334490 ASEK1922-NE W-FINAL-T W-20070720 本發明’任何所屬技術領域巾具有通常知識者，在不脫離本發明之精神域圍内，當可作些許之更動與潤掷，因此本發明之髓範圍當視_之巾料鄕圍所界定者為準0 【圖式簡單說明】圖1A為習知一種測試載板之俯視圖。As noted above, the test carrier of the present invention has been placed on the ΐ 2 conductor by replacing the conventional test carrier with a second or inner wiring layer disposed on the dielectric layer. SUb, when the difficult component is connected to the test, the electrical connection between the two is not easy to gj package. ^ The accuracy of the i-type carrier is still measured. Although the present invention has been disclosed in the above embodiments by way of example, it is not intended to be used as a limitation. 1334490 ASEK1922-NE W-FINAL-T W-20070720 The present invention is generally known to those skilled in the art without departing from the invention. Within the spiritual domain, when some changes and run-ups can be made, the scope of the invention is determined by the definition of the towel. [Simplified illustration] FIG. 1A is a conventional test carrier. Top view.

圖1B為圖1A中測試載板承載一封裂元件之剖視圖。圖2A為本發明一實施例中測試载板之俯視圖。圖迚為圖2A巾測試載板承載— 式：。為㈣懷載板與封裝元件之另Figure 1B is a cross-sectional view of the test carrier of Figure 1A carrying a split element. 2A is a top plan view of a test carrier in accordance with an embodiment of the present invention. Figure 2A shows the test carrier carrying capacity of Figure 2A. For (4) another board and package components

圖3A為本發明另一實施例中測試載板承件之剖視圖。取封裝7G 圖為圖3A中測試載板與封裝元件之式剖視圖。一種配置方Figure 3A is a cross-sectional view of a test carrier assembly in accordance with another embodiment of the present invention. Take the package 7G as a cross-sectional view of the test carrier and package components in Figure 3A. Configuration side

【主要元件符號說明】 50 :封裝元件 100 :測試載板 110 :介電層 120 :接墊 13〇 =測試墊 140 :導線 c S > 11 1334490 ASEK1922-NEW-FINAL-TW-20070720 150 :應力集中區 112 :表面 112a :元件接合區 200a、200 :測試載板 210 :介電層 212 :第一表面 212a :元件接合區 214 :第二表面 220 :接墊 230 :表層線路層 232 :接墊連接線路 234 :第二導線 240 :測試墊 250 :内層線路層 252 :第一導線 260 :保護層 12[Main component symbol description] 50: package component 100: test carrier 110: dielectric layer 120: pad 13 〇 = test pad 140: wire c S > 11 1334490 ASEK1922-NEW-FINAL-TW-20070720 150 : stress Concentration zone 112: surface 112a: component bonding zone 200a, 200: test carrier 210: dielectric layer 212: first surface 212a: component bonding region 214: second surface 220: pad 230: surface wiring layer 232: pad Connection line 234: second wire 240: test pad 250: inner layer circuit layer 252: first wire 260: protective layer 12

Claims

1334490 ASEK1922-NEW-FINAL-TW-20070720 十、申請專利範固： ^ _試載板，具有—_接合區，肋承載一封 ^個^該驗元件進行測試，制試餘包括：多個介電層；一表層線路層’位於該些介電層的最外側；性二位於兩相鄰的介電層之間，並電 ^個，塾’配置於該元件接合區内的該表層線路層 ^ ’用以與朗裝元件接合，且魅接墊電層線路層與該内層線路層；以及接該表多侧試墊，配置於該元件接合區外的該 ^且該侧試墊藉線路層電性連接至其的部份該些接墊。了應伴^如專利範圍第1項所述之測試載板，更包括— 覆盍該表層線路層，並暴露出該些接塾以及該些 3.如中請專利範圍第】項所述之賴載板其中該内 j路層〇括多條第―導線，用以分職接該些測試塾以及其所對應的部份該些接塑ι。岸娃4 專利範圍第3項所述之測試載板，其中該表 ^線路層Ο括夕條第二導線，且該些第二導線分別與該些 ^導線_於該些測離以及其所對應的雜該些接墊 5·如申°月專利範圍第1項所述之測試載板，其中該些 13 ASEK1922-NEW-FINAL-TW-20070720 接墊呈陣列配置。勹括6種測忒載板，用以測試一封裝元件，該測試载板一介電層，具有一第一表面以及與其相對之—第二面’·該第-表面上具有—元件接合區，心承載該封^ 件，多個接墊，配置於該元件接合區内的該第一表用以與該封裝元件接合；工，一接墊連接線路，位於該第—表面與該第二表面至少其中之一上，並電性連接至該些接墊；多個測試墊’配置於該元件接合區上；以及 _ 多條第-導綠，配置於該第二表面上，且該些分別藉由該些第-導線而電性連接至其所縣的部份該些接塾。一 7·如申請專利範圍第6項所述之職載板，更包括一保護層，配置於該第—表面上，並暴露出該些測試墊。 & 8」如申請專利範圍以項所述之測試載板，更包括多、一導，線酉己置於該第一表面上，並分別與該些第一導線並聯於該些測試塾以及其所對應的部份該些接塾之間。 9.如申請專利範圍第6項所述之測試載板，其中該些接墊呈陣列配置。 —1334490 ASEK1922-NEW-FINAL-TW-20070720 X. Patent application: ^ _ test carrier, with -_ joint area, rib carrying a ^ ^ test component for testing, including: An electric layer; a surface circuit layer 'is located at the outermost side of the dielectric layers; and a second layer between the two adjacent dielectric layers, and is electrically connected to the surface layer of the surface layer of the component ^ 'for engaging with the mounting component, and connecting the electrical wiring layer and the inner wiring layer; and connecting the multi-sided test pad of the table, and the side test pad is disposed outside the component bonding area The pads are electrically connected to a portion of the pads. The test carrier board as described in item 1 of the patent scope, further includes - covering the surface layer of the surface layer, and exposing the plurality of joints and the three parts as described in the patent scope In the carrier board, the inner j layer includes a plurality of first-wires for separately connecting the test files and the corresponding portions thereof. The test carrier of the third aspect of the invention, wherein the circuit layer includes a second wire, and the second wires are respectively associated with the wires and the Corresponding miscellaneous pads 5, such as the test carrier described in claim 1 of the patent application, wherein the 13 ASEK1922-NEW-FINAL-TW-20070720 pads are arranged in an array. Included in the six test carrier plates for testing a package component, the test carrier has a dielectric layer having a first surface and opposite thereto - a second surface 'the surface having the component bonding area The core carries the sealing member, the plurality of pads, the first table disposed in the bonding region of the component is configured to be engaged with the packaging component; and the bonding pad connection line is located at the first surface and the second At least one of the surfaces is electrically connected to the pads; a plurality of test pads are disposed on the component landing zone; and _ a plurality of first-leading greens are disposed on the second surface, and the The plurality of junctions are electrically connected to portions of the county by the first-wires. A working board as described in claim 6 further comprising a protective layer disposed on the first surface and exposing the test pads. &8> as in the test carrier of the scope of the patent application, further comprising a plurality of wires, the wire is placed on the first surface, and is respectively connected to the test wires in parallel with the first wires and The corresponding part is between the joints. 9. The test carrier of claim 6, wherein the pads are in an array configuration. -