TWI331367B - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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TWI331367B
TWI331367B TW095148037A TW95148037A TWI331367B TW I331367 B TWI331367 B TW I331367B TW 095148037 A TW095148037 A TW 095148037A TW 95148037 A TW95148037 A TW 95148037A TW I331367 B TWI331367 B TW I331367B
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semiconductor device
semiconductor
channel
manufacturing
forming
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TW095148037A
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TW200744133A (en
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Kazuhiko Ito
Kyosuke Endo
Hideyuki Tsukamoto
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Shindengen Electric Mfg
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3178Coating or filling in grooves made in the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Dicing (AREA)
  • Thyristors (AREA)
  • Semiconductor Lasers (AREA)
  • Formation Of Insulating Films (AREA)

Description

1331367 • 九、發明說明: 【發明所屬之技術領域】 本發明係有關半導體裝置之製造方法。 【先則技術】 ,眾所周知台面型半導體裝置係高耐壓的半導體裝置,於溝之部分戴斷 半導體晶“予製1至於此種台面型半導體裝置之製造方法已知有包 括於溝底面設置溝道饋環(stopper)之步驟的半導體裝置之製造方法= 修如參閱下述專利文獻⑽)。若依此種台面型半導體裝置之製造方法時, 則使台面型半導體裝置進一步高耐壓化即成為可能。 第6圖係為說明專利文獻㈣述的半導體裝置之製造方法而用的示意圖 。第6圖(a)〜第6圖(e)係表示各步驟之圖。 . 專利文獻1所述的半導體裝置的製造方法,如第6圖所示,依序包括: 準備η型半導體層801之η型半導體層準備步驟[參閱第6圖(a)]、於n型半 導體層801之第1主面上的元件形成區域(未予圖示)之周遭形成η+型溝道 % 戴斷環8〇6之溝道截斷環形成步驟[參閱第6圖(b)]、於η型半導體層801之 第1主面側上形成ρ型磊晶層802的ρ型磊晶層形成步驟[參閱第6圖(c)]、 自第1主面側蝕刻ρ型磊晶層802並形成到達溝道截斷環806的溝811之溝形 成步驟[參閱第6圖(d)]、於溝811之内部形成鈍化膜805a之鈍化膜形成步 驟(未予圖示)及於溝811之部分截斷半導體裝置進並行晶片化的截斷步驟 [參閱第6圖(e)]。 第7圖係為說明專利文獻2所述的半導體裝置之製造方法而用的示意 圖。第7圖(a)〜第7圖(f)係表示各步驟之圖。 5 1331367 • 專利文獻2所述的半導體裝置之製造方法,如第7圖所示,依序包括: 準備η型半導體層911之n型半導體層準備步驟(未予圖示)、於趣半導趙 層911之第1主面上的元件形成區域(未予圖示)之周遭形成η+型擴散層925 的同時於η型半導體層911之第2主面側形成η+型擴散層❾^的…型擴散層形 成步驟[參閱第7圖(a)]、於η型半導體層911之第!主面側形成型擴散層 913的p+型擴散層形成步驟[參閱第7圖(b)]、自第丨主面側蝕刻口+型擴散層 913及η型半導體層911並於形成溝916的同時形成溝道截斷環918之溝•溝 Φ 道截斷環形成步驟[參閱第7圖(c)]、於溝916之内部形成鈍化膜917的鈍 化膜形成步驟[參閱第7圖(d)]、於ρ+型擴散層913之表面及η+型擴散層912 之表面各自形成電極915及電極914的電極形成步驟[參閱第7圖(e)]及於 溝916之部分截斷半導體裝置進行晶片化的截斷步驟[參閱第了圖(f) 若依此等專利文獻1所述的半導體裝置之製造方法或專利文獻2所述的 半導體裝置之製造方法時,由於可於台面型半導體裝置之溝底面設置溝道 截斷環’即使pn接面(junction)之乏層(depletion layer)於高電壓下 ® 増寬時,該乏層也亦以溝道截斷環為終端而不於晶片截斷面露出。結果使 台面型半導體裝置可予進一步的高耐壓化。此外,由於不使該乏層露出於 晶片戴斷面,並無挖深溝道而予形成的必要,可抑制碎片或裂痕等的發生 成為可能,提高半導體裝置之可靠性成為可能。 [專利文獻1]日本特開平9-8274號公報(第2圖) [專利文獻2]曰本特開昭63-313859號公報(第5圖) 【發明内容】 6 1331367 然而,於專利文獻〗所述的半導體裝置之製造方法或專利文獻2所述的 半導體裝置之觀方法,由於糾需要為戦溝道^的掩膜形成 步驟,有步驟較繁雜的問題存在著》 此外,於專利文獻1職解導财置之餘方法鱗歡獻2所述的 半導體裝置之製造方法,於職料,尚有於縣面使溝道_環適當的 露出而需採用精密蝕刻技術之問題存在著。 因此,本發明係為解決此等問題而予完成者,係於溝底面製造已設置 籲溝道鑛環之台面型半導體裝置的半導體裝置之製造方法,其目的係提供 不需為形成溝道截斷環而用的掩膜形成步驟,且於形成溝之際不需精密的 银刻技術之半導體裝置的製造方法。 ⑴與本發明有_半導體裝置之製造方法,其特徵在於,具有第上 導電型之第丨半_及經予配置於該第丨半_之第1主面側而與該 第1導電翻反轉電型之第2導電_第2半導_,於鱗丨半導體 T第2半導體層的接合部準備_面已予形成的半導體基體之半導體 _準備步驟、自料導體之該第1主關形射越戦pn接面深度 机成步驟、至少供給第丨導電雜質至姆絲之雜質供給步驟、 形====川娜麵卿1輸編部以 層形成步驟 環形成步驟、於該溝之内部形成鈍化層的鈍化 因此, 1331367 . 置即成可能。 此外,若依與本發明有關的半導體裝置之製造方法時,則因於已預先 供給第1導電型之雜質的狀態之溝底面照射雷射使第1導電型之雜質雛至 第1半導體層的内部以形成溝道截斷環,故掃描雷射以形成溝道截斷環即成 可能,故不需供形成溝道截斷環而用的掩膜形成步驟。 此外,若依與本發明有關的半導體裝置之製造方法時,則因於形成溝 之後形成_細環,故於軸溝之際*需精密_刻技術。 • 因此,與本發明有關的半導體裝置之製造方法,係於溝底面製造已設 置溝道截魄之台面型半導财置的半導雖置之製造方法,不需供形成 溝道截斷環而用的掩膜形成步驟,且於形成溝之際不需精密的敍刻技術之 半導體裝置的製造方法。 • 於與本發财_半導體裝置之製造方法,至於雷射,雖可使用可見 光雷射(例如綠色雷射)或近紅外光雷射(例如Nd YAG雷射),但尤宜使 用可見光雷射。 籲自於可見光雷射對Si、sic等組成的半導體基體之光透射係數較低而光 吸收係數較两,藉由上述方法,第1半導體層之加熱時的控制即成容易,不 致使第1半導體層自身蒸發,而可使第1導電型雜質擴散至第1半導趙層之内 部,以形成溝道截斷環。 進行射的雷射之辨、光束直徑、發散肖及照射方法(脈波或連續) 等的雷射卿餅,斜適#的設定至^使第$導體層自絲發,可使第 1導電型雜質擴散至第1半導體層之内部,以形成溝道截斷環。 8 1331367 * 於與本發明有關的半導體裝置之製造方法,宜為於溝道截斷環形成步 驟及鈍化層形成步驟之間再包括去除殘餘的第1導電型雜質之姓刻步驟。 藉由實行此種方法,淨化溝之内面即成可能,使台面型半導體裝置更 具高耐壓化的同時成為高可靠性者。 至於姓刻液,可宜為使用氫氟酸、硝酸及水之混合液(例如JJP : Hn〇3出〇 =3:2:60)。 供給至溝底面之第1導電型雜質的量,係予調整至形成於溝底面之溝道 • 截斷環的雜質濃度成最適的濃度(例如lxl〇19cm-3)。 於溝道截斷環之第1導電獅質的雜質濃度、槪分料,係予調整至 即使pn接面之乏層於高電壓下增寬時,該乏層亦以溝道截斷環為終端而不 露出於晶片截斷面。 ’ 於與本發财關料導難置之製造方法,缝半導體基體,亦可使 用於第1半導體層之第2主面側再具有含有較糾半導體層較高濃度的以導 電型雜質之第3半導體層的半導體基體。 _ 至於可義與本發财_半賴裝置之製造方法的半導體裝置,可 例舉有二極體(例如即二極體、pin二極體及肖特基二極體等)、電晶體(例 如雙極型電晶體、隱ET及膽等)、晶·、三端雙向可财元件及其 他的電力用半導體裝置。 、 且,於此說明書,第i主面係指形成溝之側面。又,第2主面係指與第i 主面相反側之面。 ⑵於與本發明有_半導體裝置之製造方法該雜質供給步称宜為 9 1331367 至少塗布含有第1導電型雜質之液體於該溝底面的步驟。 藉由實行此種方法,供給適量的幻導電型雜質於溝底面即成可能。 ;3有第1導電型雜質之液體,可宜為使用例如使碟化合物(例如焦 填酸)祕有機賴(例如乙醇)的紐。至於塗布方法,可使用浸潰法、 旋塗法及噴布法等公知的方法。 (3)於與本發财_半導體裝置之製造方法,該雜質供給步驟亦可 為至少供給含有第1導電型雜質之氣體至該溝底面的步驟。 即使藉由實行此種方法,亦可供給第1導電型雜質至溝底面。 至於含有第1導電型雜質之氣體,可宜為使用例如膦(ph〇sphine)及 惰性氣體之齡氣體。錄縣方法,可使驗半導體⑼曝露於該氣體 大氣中的方法》 ⑷於與本發日3有的半導H裝置之製^,於該溝道斷娜成 步驟’該溝錢斷環宜為形成沿賴延伸的2個溝道戴斷環。 然而,通常已知採用切割以鎖不同硬度的媒質之經予接合的部分時, 較容易發生晶片的破片或裂痕等。因此,若採用切割以截斷溝道截斷環及 第1半導體層之齡接合_分時,級溝道贿環之硬度及幻半導艘層 之硬度不同,故可預想容易發生晶片之破片或裂痕等現象。 對此,藉由實行上述的方法,若於其後的半導體基體截斷步驟對2個溝 道戴斷環之間進械_,不必饋溝道_環及糾半導體層之經予 接合的部分,因此可抑制asB#之破#或織等的發生,使製造高可靠性的 半導體裝置成為可能。 1331367 ’ ;、本發月有關的半導體裝置之製造方法,宜為形成隔離3G#m以上並 形成2個溝道截斷環。 藉由實行此種方法,於其後的半導體基體酬步料容㈣截斷2個溝 道截斷環之間。 (5)於與本發明有_半導體裝置之製紗法,宜絲該鈍化層形成 步驟之後’再包括於沿該溝延伸的2個溝道觸環之間截_半導體基體 之基體截斷步驟。 Φ 藉由實行此種方法’製造出高耐壓、高可靠性的台面型半導體裝置即 成可能。 ⑻於與本發明有關的半導體裝置之製造方法,於該溝道截斷環形成步 驟,至於溝道戴斷環宜為於該半導體裝置之元件形成區域及切割線之間形 成圍繞該元件形成區域之溝道截斷環。 糟由實行此種方法’由於不需饋溝道截斷環及第1半導體層之經予接 合的。P分’故可抑制晶片之破片或裂痕等的發生,使製造出高可靠性的半 • 導體裝置成為可能。 於與本發明有關的半導體裝置之製造方法,宜為自切割線隔離15歸X 上並配置溝道截斷環。 藉由實行此種方法,使於晶片端面防止溝道截斷環露出於晶片端面露 出的情況發生即成可能。 【實施方式】 以下,依圖示的實施形態說明與本發明有關的半導體裝置之製造方法。1331367 • IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of fabricating a semiconductor device. [First-Leading Technology] It is known that a mesa-type semiconductor device is a high-voltage-resistant semiconductor device, and a semiconductor crystal is shunted in a portion of the trench. "Preparation 1 is a method for manufacturing such a mesa-type semiconductor device. Method for manufacturing a semiconductor device in the step of a gate feeder = Refer to the following Patent Document (10)). According to the method for manufacturing a mesa-type semiconductor device, the mesa-type semiconductor device is further increased in pressure resistance. Fig. 6 is a schematic view for explaining a method of manufacturing a semiconductor device described in Patent Document (4). Fig. 6(a) to Fig. 6(e) are diagrams showing respective steps. As shown in FIG. 6, the method of manufacturing the semiconductor device includes: preparing an n-type semiconductor layer preparation step of the n-type semiconductor layer 801 [see FIG. 6(a)], and forming the first in the n-type semiconductor layer 801. The channel formation region (not shown) on the main surface is formed with a n + type channel %. The channel cut ring forming step of the break ring 8 〇 6 [see Fig. 6 (b)], in the n-type semiconductor layer Formed on the first main surface side of 801 The p-type epitaxial layer forming step of the epitaxial layer 802 (see FIG. 6(c)), the p-type epitaxial layer 802 is etched from the first main surface side, and the groove forming of the trench 811 reaching the channel stop ring 806 is formed. Step [Refer to FIG. 6(d)], a passivation film forming step (not shown) for forming a passivation film 805a inside the trench 811, and a step of cutting off the parallelization of the semiconductor device in the portion of the trench 811 [Refer to 6(e)] Fig. 7 is a schematic view for explaining a method of manufacturing a semiconductor device described in Patent Document 2. Fig. 7(a) to Fig. 7(f) are diagrams showing respective steps. 1331367 • The method for manufacturing a semiconductor device according to Patent Document 2, as shown in FIG. 7, sequentially includes: an n-type semiconductor layer preparation step (not shown) for preparing an n-type semiconductor layer 911, and a semi-guided semiconductor The n + -type diffusion layer 925 is formed around the element formation region (not shown) on the first main surface of the layer 911, and the n + -type diffusion layer is formed on the second main surface side of the n-type semiconductor layer 911. a type of diffusion layer forming step [see Fig. 7 (a)], forming a diffusion layer on the main surface side of the n-type semiconductor layer 911 The p+ type diffusion layer forming step of 913 [refer to FIG. 7(b)], the etching port + type diffusion layer 913 and the n-type semiconductor layer 911 from the first major surface side and forming the channel cut ring 918 while forming the groove 916 The groove/ditch Φ channel cut ring forming step [refer to Fig. 7 (c)], the passivation film forming step of forming the passivation film 917 inside the groove 916 [refer to Fig. 7 (d)], and the ρ+ type diffusion layer The surface of the 913 and the surface of the η+-type diffusion layer 912 each form an electrode forming step of the electrode 915 and the electrode 914 [see FIG. 7(e)] and a portion of the trench 916 that cuts off the semiconductor device for wafer formation. (f) In the method of manufacturing the semiconductor device described in Patent Document 1, or the method of manufacturing the semiconductor device described in Patent Document 2, a channel cut ring can be provided on the bottom surface of the trench of the mesa-type semiconductor device. Even if the depletion layer of the pn junction is at a high voltage, the layer is also terminated by the channel stop ring and not exposed to the wafer section. As a result, the mesa-type semiconductor device can be further subjected to higher withstand voltage. Further, since the layer is not exposed to the wafer wearing section, it is not necessary to dig deep trenches, and it is possible to suppress the occurrence of chips or cracks, and it is possible to improve the reliability of the semiconductor device. [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei 9-8274 (Patent No. 2) [Patent Document 2] JP-A-63-313859 (Patent 5) [Summary of the Invention] 6 1331367 However, in the patent literature In the method of manufacturing the semiconductor device or the method of viewing the semiconductor device described in Patent Document 2, since the mask forming step of the 戦 channel is required, there is a problem that the steps are complicated. In addition, in Patent Document 1, The method of manufacturing the semiconductor device described in the above-mentioned method is not limited to the problem that the channel_ring is appropriately exposed and the precision etching technique is required in the county. Accordingly, the present invention has been made in order to solve the above problems, and is a method of manufacturing a semiconductor device in which a mesa-type semiconductor device having a channel ring is provided on a trench bottom surface, and the object of the invention is to provide a channel cutoff without forming A mask forming step for ring formation, and a method of manufacturing a semiconductor device which does not require a precise silver engraving technique when forming a trench. (1) A method of manufacturing a semiconductor device according to the invention, characterized in that the third half of the upper conductivity type is disposed on the first main surface side of the third half and is reversed from the first conductive surface The second conductivity_second half-conductor of the power conversion type, the semiconductor of the semiconductor substrate in which the surface of the second semiconductor layer of the squamous semiconductor T is prepared is prepared. The preparation step and the first main gate of the self-material conductor Forming a step of a pn junction depth machine, supplying at least a third conductive impurity to the impurity supply step of the filament, and forming a step forming step in the layer forming step The passivation of the passivation layer formed inside is therefore possible, 1331367. Further, according to the method of manufacturing a semiconductor device according to the present invention, the first conductivity type impurity is immersed in the first semiconductor layer by irradiating a laser beam to the bottom surface of the groove in which the impurity of the first conductivity type is supplied in advance. The inside is formed to form a channel stop ring, so that it is possible to scan the laser to form a channel cut-off ring, so that a mask forming step for forming a channel cut-off ring is not required. Further, according to the method of manufacturing a semiconductor device according to the present invention, since a thin ring is formed after the formation of the groove, it is necessary to perform a precise technique in the case of the axial groove. Therefore, the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a mesa-type semiconductor material in which a channel junction is provided on the bottom surface of the trench, without forming a channel cut-off ring. A mask forming step is used, and a method of manufacturing a semiconductor device which does not require a precise lithography technique when forming a trench. • For the production method of semiconductor devices, as for the laser, although visible lasers (such as green lasers) or near-infrared lasers (such as Nd YAG lasers) can be used, it is preferable to use visible lasers. . It is claimed that the visible light laser has a low light transmission coefficient and a light absorption coefficient of a semiconductor substrate composed of Si, sic or the like. By the above method, the control of heating of the first semiconductor layer is easy, and the first one is not caused. The semiconductor layer evaporates by itself, and the first conductivity type impurity can be diffused into the inside of the first semiconductor layer to form a channel stop ring. The laser beam of the laser, the beam diameter, the divergence, and the irradiation method (pulse wave or continuous), etc., are set to ^ so that the first conductor layer is self-wired, so that the first conductive can be made. The type impurity diffuses into the inside of the first semiconductor layer to form a channel cut ring. 8 1331367 * In the method of fabricating the semiconductor device according to the present invention, it is preferable to further include a step of removing the residual first conductivity type impurity between the channel stop ring forming step and the passivation layer forming step. By carrying out such a method, it is possible to purify the inner surface of the trench, and it is possible to make the mesa-type semiconductor device more high in pressure resistance and high reliability. As for the surname engraving, it is preferable to use a mixture of hydrofluoric acid, nitric acid and water (for example, JJP: Hn〇3 〇 = 3:2:60). The amount of the first conductivity type impurity supplied to the bottom surface of the groove is adjusted to the channel formed on the bottom surface of the groove. • The impurity concentration of the cut ring is at an optimum concentration (for example, lxl 〇 19 cm -3 ). The impurity concentration of the first conductive lion in the channel cut-off ring and the germanium material are adjusted so that even if the layer of the pn junction is widened at a high voltage, the layer is terminated by the channel cut-off ring. Not exposed to the cross section of the wafer. In the manufacturing method of the present invention, the semiconductor substrate can be used, and the second semiconductor surface of the first semiconductor layer can be used to have a higher concentration of conductive impurities in the semiconductor layer. 3 semiconductor substrate of the semiconductor layer. _ As for the semiconductor device of the method of manufacturing the semiconductor device, the diode device may be a diode (for example, a diode, a pin diode, a Schottky diode, etc.) or a transistor (for example). For example, bipolar transistors, hidden ETs, and gallbladders, crystal, triacs, and other power semiconductor devices. Moreover, in this specification, the i-th main surface refers to the side surface forming the groove. Further, the second main surface means a surface opposite to the i-th main surface. (2) In the method of manufacturing a semiconductor device according to the present invention, the impurity supply step is preferably 9 1331367. A step of applying at least a liquid containing a first conductivity type impurity to the bottom surface of the trench. By carrying out such a method, it is possible to supply an appropriate amount of magic conductive impurities to the bottom surface of the trench. 3) A liquid having a first conductivity type impurity, and it is preferred to use, for example, a catalyst which makes a dish compound (e.g., a pyrolysis acid). As the coating method, a known method such as a dipping method, a spin coating method, or a spray method can be used. (3) In the method of manufacturing a semiconductor device according to the present invention, the impurity supply step may be a step of supplying at least a gas containing the first conductivity type impurity to the bottom surface of the trench. Even by carrying out such a method, the first conductivity type impurity can be supplied to the bottom surface of the trench. As the gas containing the first conductivity type impurity, it is preferable to use a gas such as phosphine and an inert gas. The method of recording the county can make the method of exposing the semiconductor (9) to the atmosphere of the gas. (4) The method of the semi-conducting H device which is available on the third day of the present invention, and the step of breaking the ring into the channel A break ring is formed for forming two channels extending along the ridge. However, it is generally known that when a portion to be bonded to lock a medium having a different hardness is used, chipping or cracking of the wafer or the like is more likely to occur. Therefore, if the cutting is used to cut off the channel-cut ring and the first semiconductor layer, the hardness of the level channel brittle ring and the hardness of the magic semi-conducting layer are different, so that chip fragments or cracks are expected to occur easily. And so on. In this regard, by performing the above method, if the subsequent semiconductor substrate cutting step is performed between the two channel wear-breaking rings, it is not necessary to feed the channel-ring and the pre-bonded portion of the semiconductor layer. Therefore, it is possible to suppress the occurrence of breakage or the like of asB#, and it is possible to manufacture a highly reliable semiconductor device. 1331367 ’; The manufacturing method of the semiconductor device according to this month is preferably to form an isolation 3G#m or more and form two channel cut-off rings. By carrying out this method, the subsequent semiconductor substrate retreats (4) to cut off between the two trench cut-off rings. (5) In the yarn forming method of the semiconductor device of the present invention, after the step of forming the passivation layer, the step of forming the substrate is further included in the step of cutting the semiconductor substrate between the two channel contact rings extending along the groove. Φ By implementing such a method, it is possible to manufacture a mesa-type semiconductor device having high withstand voltage and high reliability. (8) In the method of fabricating a semiconductor device according to the present invention, in the step of forming a channel stop ring, it is preferable that a channel wear ring is formed between the element formation region of the semiconductor device and the dicing line around the element formation region. Channel truncation ring. The method of performing this method is because the channel cut-off ring and the first semiconductor layer are not required to be joined. The P-parts can suppress the occurrence of fragments or cracks in the wafer, and it is possible to manufacture a highly reliable semi-conductor device. In the method of fabricating the semiconductor device according to the present invention, it is preferable to arrange the channel cut-off ring from the self-cut line isolation. By carrying out such a method, it is possible to prevent the wafer end face from being exposed to the exposed end face of the wafer. [Embodiment] Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the embodiments shown in the drawings.

實施例1 第1圖係供說明與實施例1有關的半導體裝置之製造方法所製造的半導 、置100之不意圖。第(a)係半導體裝置100之的剖視圖,第1圖(b) ^圖(a)之圖號A表示的部分之放大圖,第旧⑹係第工圖⑻之圖 '表不的#分之放大圖。第2圖及第3圖43係表示用於說明實施模式1的半 體裝置的製造方法的圖。第2圖⑷〜第2圖⑷及第3圖⑷〜第3圖 (C)係各步驟中的半導體裝置腕之剖視圖。第圖4係供說明實施例1之半 導體基體截斷步驟的不意圖。第圖4⑷係截斷之前的半導體裝置⑽a之 平面圖’第4圖⑻係截斷之前的半導體裝置100a之剖視圖,第4圖(c) 係截斷之後的半導體裝置lGGa之剖視圖。 如第1圖所由與實關1«的半導體裝置之製造方法所製造的半 導體裝置1GG ’係於雜之底面上已予設置溝道躺環22的半導體裝置。 半_裝置100係具有n-型(第i導電型)之第j半導體層1〇、經予配置 於第1半導體層10之第1主面側的p+型(第2導電型)之第2半導體層12及經 予配置於第1半導體層1〇之第2主面側的n+型(第!導電型)力第3半導體層 14、以於第1半導體層10及第2半導體層12之接合部經予形成卯接面的半導 體基體為起始材料而予製造的。 半導體裝置10係0具有越過pn接面深度之溝18。因此,於溝18之底面正 予形成著沿溝18延伸的2個溝道截斷環22,22[參閱第1圖及第4圖(a)]。 溝18之寬度為例如3〇〇"m,溝道截斷環22之寬度為例如6〇“m,2個溝 道截斷環22之間的間隔d[參閱第圖1 (b)]為例如60/zm。 12 “3!367 屢道截斷環22㈣預先已供給n獅獅的織τ之賴的底面照射 雷射,使該η型雜質2〇經予紐至第!半導體層1〇之内部而形成[對於η型雜 質,請參閱第2圖(c)]。 如第1圖(c)所示’溝道_環22係由含有高濃度的η型雜f支單晶趙 區域26及含有高濃度的n型雜f之非晶體物㈣賴組成的。 如第1圖(a)及第1圖⑻所示,於溝18之内部正予形成鈍化層28。 此外’於第1圖,圖號3〇係表示經予形成於第2半導體層之表面的電極, 鲁圖號32係表示經予形成於第3半導體層之表面的電極。 如第2圖及糾類示’與實關1有_半導體裝置之製造方法依序包 括以下步驟。以下,依序說明各步驟。 (1) 半導體基體準備步驟 半導體基體準備步驟係對具有!!-型之第J半導體層1〇、經予配置於第! 半導體層10之第1主面側的P+型的第2半導體層12及經予配置於第#導體層 10之第2主面側的n+型的第3半導體層14、於第!半導體層1〇及第2半導體層12 鲁之接合部準備Pn接面經予形成的半導體基體之步驟[參閱第2圖⑷]。扪 半導體層10之雜質濃度為例如2χ i〇l4cm-3,第2半導體層12之雜質漠度為例 如2xlO】W3,第3半導體層14之雜質濃度為例如2xl〇1W3e此外,第i半導 體層10之厚度為例如150#m,第2半導體層12之厚度為例如6〇_,第3半 導體層14之厚度為例如40/zm。 (2) 溝形成步驟 溝形成步驟係自半導體基體之第一主面側形成越過卯接面深度的溝18 13 1331367 • 之步驟[參閱第2圖⑻]。溝18之寬度為例如300㈣,溝18之深度為例如 90/zm。溝形成例如利用蝕刻進行。至於蝕刻液,使用氫氟酸、硝酸及醋 酸之混合液(例如HF: HN03:CH3C00H=1:4:1)。 (3)雜質供給步驟 雜質供給步驟係至少塗布含有0型雜質2〇之液體於溝18的底面之步驟 [參閱第2圖(c)]。 至於含有η型雜質20之液體,宜為可使用例如使填化合物(例如焦磷酸) # 溶於有機溶劑(例如乙醇)的液體等。至於塗布方法,可使用浸潰法、旋 塗法及喷射法等公知的方法。 供給至溝18底面之η型雜質20的量,係予調整至使形成於溝18底面之溝 道截斷環22的雜質濃度成最適的濃度(例如lxl〇19cm-3)。 • (4)溝道截斷環形成步驟 溝道截斷環形成步驟係以照射雷射於溝丨8之底面使n型雜質2〇擴散至 第1半導體層10的内部並形成溝道截斷環22之步驟[參閱第3圖(a) ]» ® 至於雷射,係使用可見光雷射(例如波長532nm之綠色雷射)。例如使 以30KHz發生脈波,以3〇〇_/秒之速度沿溝18的乂方向及7方向進行掃描。 於此步驟,至於溝道截斷環22係形成沿溝is延伸的2個溝道截斷環22 , 22[參閱第4圖(a) ]。2個溝道截斷環22係僅相互隔離60#m而予形成著。 (5)蝕刻步驟 姓刻步驟係去除殘餘的η型雜質20之步驟[參閱第3圖(b) ]» 至於蝕刻液,可使用氫氟酸、硝酸及水之混合液(例 14 1331367 . =3:2:60)。 (6) 純化層形成步驟 鈍化層形成步驟係於溝18之内部形成鈍化層28的步驟[參閱細⑷ ]。此步驟係藉由利用網版印刷法印刷玻璃材料並予燒成而進行的。 (7) 電極形成步驟 電極形成步驟係於第2半導體層12之第!主面側及第3半導體㈣之第2 主面側分獅成電極電極32的步驟(未予圖示)。此外,第3圖⑷ • 所示的氧化膜16係於電極形成步驟之前先藉由蝕刻而予去除著。 (8) 半導體基體截斷步驟 半導體基體截斷步驟係藉由使用切割鑛刀沿第4圖⑷所示的切割線 DL進行切割。切割係於2個溝道截斷環22 , 22之間進行。 若依包括上述的步驟之與實施例丨有關的半導體裝置之製造方法時,於 溝18之底面形成溝道饋環22,因此製造出於溝底面已設置溝道截斷環之 台面形半導體裝置100即成可能。 鲁此外’魏與實_1有關醉導體裝置之製造方_,由於以對預先 已供給η型雜質20的狀態下之溝18的底面照射雷射’使η型雜質2〇經予擴散 至第1半導體之内《臟溝道饋環22,以雷崎描即可形成溝道截 斷環22,因此不需供形成溝道截斷環而用的掩膜形成步驟。 此外,若依與實施例1有關的半導體裝置之製造方法時,因於形成溝18 之後形成溝道截斷環22,故於形成溝18之際成為不需精密的蝕刻技術。 因此,與實施例1有關的半導體裝置之製造方法,係於溝底面製造已設 15 1331367 -置溝道麟環之台面鲜導财置辭導體裝置之製造方法,不需供形成 溝道麟環而用的掩膜形成步驟,且於形成溝之際不需精密的飯刻技術之 半導體裝置的製造方法。 此外,於與實施傾有關的半導體裝置之製造方法,至於雷射由於使用 可見光雷射’因此使第1半導體層10於加熱之際的控制可容易進行不使第 1羊導體層10自身蒸發’使n型雜質20擴散至幻半導體層1〇之内部而可形成 溝道截斷環22。 • 此外’於與實施例1有關的半導體裝置之製造方法,由於於溝道截斷環 形成步驟及鈍化層形成步驟之間再包括去除殘餘伽型雜質2〇之餘刻步驟, 使溝18之内面可予淨化成為可能,使台面型半導體裝置再予高耐遂化的同 時’兼具高可靠性即成可能。 此外,於與實_財_半賴裝置之製造方法,肺供給步驟係至 少為塗布含有η型雜質20之液體於雜之底面的步驟,故供給適量細型雜 質20於溝18之底面即成可能。 # 此外’於與實施例1有關的半導體裝置之製造方法,對於該溝道截斷環 形成步驟’溝道_環因係職沿溝18延伸的2姆道峨微,没,若於 其後的半導體基體分斷步驟於2個溝道截斷環22,22之間進行截斷時由於 不必截斷溝道截斷環22及第4導體層10經予接合的部分,因此可抑制晶片 之發生破4或裂痕等’使製造出高可靠性的半導體裝置即成可能。 此外,於與實施職_半導體裝置之妓方法,由於僅峨〇錄 _成2輯錢_22,22,因此於錢的半導縣體分斷步财容易的 16 1331367 於2個溝道截斷環22,22之間進行戴斷。 於與實施例1有關的半導體裝置之製造方法,於鈍化層形成步驟之後, 由於再包括於沿溝難伸的2個溝道_微,22之間進行截斷半導體基體 之半導體基賴斷步驟,因此製造出高耐壓、高可靠性的台面形半導體裝 置即成可能。 實施例2 與實施例2有_半導雜置之製造方法,基本上係包括與實施例味 # _半導齡置之製造方法相_挪,㈣_給步驟财同於與實施 佩有關的半導體裝置之製造方法者4即,於與實施例2有關的半導體裝 置之製造方法,雜雜給步驟敍少綠給含有㈣雜質之氣體至溝底面的 步驟。 減,與實補2有_轉«置之製造方法,賴雜㈣給步驟传 與實施例1«醉導雜置之製造方法者不同,㈣使藉由錄方法,盘 實施例i有關的半導體裝置之製造方法相同,亦可供給η型雜質於溝底面。 籲目此,射關2有_铸體裝置之製造方法,軸實補丨有關的半導 體裝置之製造方法_,係於溝底面製造已設置溝·斷環之台面型半導 體裝置的料财置之製造方法,不職财_環而_掩膜形成 步驟’且賴溝之際不㈣侧技術之半導體灯㈣造方法。 此外,於財_2㈣料導财置之製造方法,至於含有η型雜質 之氣體,宜為可制例如膦及惰性氣體之混合氣體4於供給方法,可使 用使半導體晶片曝露於該氣體大氣中的方法。 1331367 , 此外,由於與實施例2有關的半導體裝置之製造方法,除此點以外具有 與實施例1有關的半導體裝置之製造方法相同的步驟,因此具有與實施例j 有關的半導體裝置之製造方法所具有的功效中相同的功效。 實施例3 第5圖係供說明與實施例3有關的半導體基體截斷步驟之示意圖。第5圖 係與第4圖(a)相同的表示截斷之前的半導體裝置1〇4a之平面圖。 與實施例3有_半導體裝置之製造紐,絲本上包域實施例味 籲關的半導體裝置之製造方法相_步驟,但溝道截斷環之平面形狀則與實 施例1有關的半導體裝置之製造方法不同。脚如第5_示,於與實施例3 有關的半導體裝置之製造方法,溝道截斷環22係於元件形成區颠及切割 線DL之間圍繞元件形成區域34而予形成著。 如此,與實施例3有關的半導體裝置之製造方法,雖然溝道截斷環之平 面形狀與實施例丨有關的半導體裝置之製造方法者不同,但與實施例】有關 的半導體裝置之f造方法者相同,由於储由騎雷躲賴之底面使趣 雜質20擴散至第1半導體之内部以形成溝道_職,因此與實施州 有關的半導體裝置之製造方法相同,·造於溝底面已設置溝道截斷環之 台面型半導體裝置的半導體裝置之製造方法,不需供形麟道截斷環而用 的掩膜形成步驟且形成溝之際不需_的_技術之半導體裝置的製造方 法。 且,由於與實_3有_半賴裝置之製妨法,除無耕具有與 實施例1有_半導體裝置之製造綠相_步驟,具有與實施例β 1331367 ._半導體裝置之製造方法所具有的姐減的功效。 以上’基於上述各實施例說明與本發明有關的半導體裝置之製造方法, 但本發明並非受上述各實施例所限制者,於不脫離其要旨的範圍内均可實 施各種形態,例如可以進行如下的修飾例。 (1) 於上述各實施例,雖然已說明第丨導電型為n型、第2導電型為口型, 但本發明並不為此所限制,亦可以第1導電型為ρ型、第2導電型為η型。 (2) 於上述各實施例,雷射雖然使用綠色雷射,但本發明並不為此所 籲限制。雷射亦可宜為使用綠色雷射以外的可見光雷射或近紅外光雷射(例 如Nd-YAG雷射)。 (3) 於上述實施例丨,含有n型雜質之液體雖可使用使焦磷酸溶於有機 丨的紐’但本發明並不為此舰L,料以使肢純酸以外 的磷化合物或砷化合物溶於各種有機溶劑的液體。 (4)於上述各實關,至於台面型半導齡置雖以即二極體為例予 以說明本發明,但本發明並不為此所限制。例如,本發明可適用於卯二極 •體以外的二極體(例如、pin二極體及肖特基二極體等)、電晶體(例如雙 極型電晶體、M0霜及等)、晶閘管、三端雙向可控料件及其他的 電力用半導體裝置。 【圓式簡單說明】 第1圖係供說明與實施例1有關的半導體裝置1〇〇之示意圖。 第2圖係供說明與實施例i有關的半導體裝置之製造方法的示意圖。 第3圖係供說明與實施例i有關的半導體裝置之製造方法的示意圖。 19 1331367 第4圖係供說明與實施例1有關的半導體基體截斷步驟之示意圖。 第5圖係供說明與實施例3有關的半導體基體截斷步驟之示奄圖。 第6圖係供說明專利文獻1所述的半導體裝置之製造方法的示意圖。 第7圖係供說明專利文獻2所述的半導體裝置之製造方法的示音圖。 【主要元件圓號說明】 [習知] 80l··· η型半導體層(集電極區域)801a…η+型半導體層 φ 801b η-型半導體層 803…發射極區域 805a…鈍化膜 807…集電極電極 809…發射極電極 81l·.·溝 813…氧化膜 φ 911_··η型半導體層 913…ρ+型擴散層 916…溝 918…溝道截斷環 [本發明] 10…第1半導體層 14···第3半導體層 802···ρ型磊晶層(基極區域) 805…絕緣膜 806…溝道截斷環 808…基極電極 810···ρη 接面 812…乏層 813a…開口部 912 ’ 925...n+型擴散層 914,915…電極 917…鈍化膜 926 ’ 928."氧化膜 12…第2半導體層 16…氧化膜 20 1331367 18…溝 22…溝道截斷環 26…單晶體區域 30、32…電極 20···η型雜質 24…非晶態物質區域 28…鈍化層 34…元件形成區域 100···半導體裝置(晶片化之後) 100a、104a···半導體裝置(晶片化之前)DL···切割線[Embodiment 1] Fig. 1 is a view for explaining the semiconductors and the 100 manufactured by the method for manufacturing a semiconductor device according to the first embodiment. (a) is a cross-sectional view of the semiconductor device 100, Fig. 1 (b) is an enlarged view of a portion indicated by a figure A of the figure (a), and the old (6) is a figure of the figure of the figure (8) Magnified view. Fig. 2 and Fig. 43 are views showing a method of manufacturing the semiconductor device according to the first embodiment. Fig. 2 (4) to Fig. 2 (4) and Fig. 3 (4) to Fig. 3 (C) are cross-sectional views of the semiconductor device wrist in each step. Fig. 4 is a schematic view for explaining the step of cutting off the semiconductor substrate of the embodiment 1. 4(4) is a plan view of the semiconductor device (10)a before the cutting. FIG. 4(8) is a cross-sectional view of the semiconductor device 100a before the cutting, and FIG. 4(c) is a cross-sectional view of the semiconductor device 1GGa after the cutting. The semiconductor device 1GG' manufactured by the method for manufacturing a semiconductor device according to Fig. 1 is a semiconductor device in which a trench ring 22 is provided on the bottom surface of the dummy. The half-device 100 has the n-type (i-th conductivity type) j-th semiconductor layer 1 and the second p+ type (second conductivity type) which is disposed on the first main surface side of the first semiconductor layer 10 The semiconductor layer 12 and the n+ type (first conductivity type) force third semiconductor layer 14 disposed on the second main surface side of the first semiconductor layer 1 are formed on the first semiconductor layer 10 and the second semiconductor layer 12 The joint is fabricated from a semiconductor substrate to which the splicing surface is formed as a starting material. The semiconductor device 10 has a trench 18 that passes over the depth of the pn junction. Therefore, two channel cut-off rings 22, 22 extending along the groove 18 are formed on the bottom surface of the groove 18 [see Fig. 1 and Fig. 4(a)]. The width of the groove 18 is, for example, 3 〇〇 " m, and the width of the channel cut-off ring 22 is, for example, 6 〇 "m, and the interval d between the two channel cut-off rings 22 [see FIG. 1 (b)] is, for example. 60/zm. 12 "3!367 Repeated cut-off ring 22 (four) has been supplied to the bottom of the n lion's woven τ ray to irradiate the laser, so that the n-type impurity 2 is passed to the first! The inside of the semiconductor layer 1 is formed [for the n-type impurity, refer to Fig. 2 (c)]. As shown in Fig. 1(c), the 'channel_ring 22 is composed of a high-concentration n-type hetero-f-cell single crystal region 26 and an amorphous material (d) containing a high concentration of n-type heterologous f. As shown in Fig. 1 (a) and Fig. 1 (8), a passivation layer 28 is formed inside the trench 18. Further, in Fig. 1, reference numeral 3 denotes an electrode which is formed on the surface of the second semiconductor layer, and FIG. 32 shows an electrode which is formed on the surface of the third semiconductor layer. The manufacturing method of the semiconductor device as shown in Fig. 2 and the correction type and the actual shutdown 1 includes the following steps in sequence. Hereinafter, each step will be described in order. (1) Semiconductor Substrate Preparation Step The semiconductor substrate preparation step is performed on the J-th semiconductor layer having the !!-type, and is placed in the first! The P + -type second semiconductor layer 12 on the first main surface side of the semiconductor layer 10 and the n + -type third semiconductor layer 14 on the second main surface side of the first conductor layer 10 are placed on the first! A step of preparing a semiconductor substrate on which a Pn junction is formed by preparing a junction between the semiconductor layer 1 and the second semiconductor layer 12 [see Fig. 2 (4)]. The impurity concentration of the germanium semiconductor layer 10 is, for example, 2 χ i 〇 14 cm -3 , the impurity gradient of the second semiconductor layer 12 is, for example, 2×10 −W 3 , and the impurity concentration of the third semiconductor layer 14 is, for example, 2×10 −1 W 3 e . Further, the ith semiconductor layer The thickness of 10 is, for example, 150 #m, the thickness of the second semiconductor layer 12 is, for example, 6 Å, and the thickness of the third semiconductor layer 14 is, for example, 40/zm. (2) Groove forming step The groove forming step is a step of forming a groove 18 13 1331367 from the first main surface side of the semiconductor substrate over the depth of the splicing surface. [Refer to Fig. 2 (8)]. The width of the groove 18 is, for example, 300 (four), and the depth of the groove 18 is, for example, 90/zm. The trench formation is performed, for example, by etching. As the etching solution, a mixture of hydrofluoric acid, nitric acid and acetic acid (e.g., HF: HN03: CH3C00H = 1:4:1) is used. (3) Impurity Supply Step The impurity supply step is a step of applying at least a liquid containing the 0-type impurity 2〇 to the bottom surface of the trench 18 [see Fig. 2(c)]. As the liquid containing the n-type impurity 20, it is preferred to use, for example, a liquid in which a compound (e.g., pyrophosphoric acid) # is dissolved in an organic solvent (e.g., ethanol). As the coating method, a known method such as a dipping method, a spin coating method, or a spraying method can be used. The amount of the n-type impurity 20 supplied to the bottom surface of the trench 18 is adjusted so that the impurity concentration of the channel cut-off ring 22 formed on the bottom surface of the trench 18 is at an optimum concentration (e.g., lxl 〇 19 cm -3 ). (4) Channel cut-off ring forming step The channel cut-off ring forming step is to irradiate the laser to the bottom surface of the trench 8 to diffuse the n-type impurity 2〇 into the inside of the first semiconductor layer 10 and form the channel cut-off ring 22 Step [Refer to Figure 3 (a)]» ® For lasers, use a visible laser (for example, a green laser with a wavelength of 532 nm). For example, a pulse wave is generated at 30 kHz, and scanning is performed in the 乂 direction and the 7 direction of the groove 18 at a speed of 3 〇〇 / / sec. In this step, as for the channel shutoff ring 22, two channel cut-off rings 22, 22 extending along the groove is formed [see Fig. 4(a)]. The two channel shutoff rings 22 are formed by separating only 60#m from each other. (5) Etching step The step of surname is the step of removing the residual n-type impurity 20 [see Fig. 3(b)]» As for the etching solution, a mixture of hydrofluoric acid, nitric acid and water can be used (Example 14 1331367 . 3:2:60). (6) Purification layer formation step The passivation layer formation step is a step of forming the passivation layer 28 inside the trench 18 [see detail (4)]. This step is carried out by printing a glass material by screen printing and baking it. (7) Electrode forming step The electrode forming step is the second semiconductor layer 12! The main surface side and the second main surface side of the third semiconductor (four) are divided into lion electrode electrodes 32 (not shown). Further, the oxide film 16 shown in Fig. 3 (4) is removed by etching before the electrode forming step. (8) Semiconductor substrate cutting step The semiconductor substrate cutting step is performed by cutting line DL shown in Fig. 4 (4) by using a dicing cutter. The cutting is performed between the two channel cut-off rings 22, 22. According to the manufacturing method of the semiconductor device according to the embodiment described above, the channel feed ring 22 is formed on the bottom surface of the trench 18, so that the mesa-shaped semiconductor device 100 in which the trench stop ring is provided on the bottom surface of the trench is manufactured. It is possible. In addition to the manufacturing method of the drunk conductor device of the "Wei and Shi _1", the η-type impurity 2 is pre-diffused by irradiating the laser to the bottom surface of the groove 18 in the state in which the n-type impurity 20 has been supplied in advance. 1 The dirty channel feed ring 22 in the semiconductor can form the channel cut-off ring 22 by Raisaki, so there is no need for a mask forming step for forming the channel cut-off ring. Further, according to the method of manufacturing the semiconductor device according to the first embodiment, since the trench stop ring 22 is formed after the trench 18 is formed, the etching process is not required when the trench 18 is formed. Therefore, the method for fabricating the semiconductor device according to the first embodiment is to manufacture a method for manufacturing a conductor device having a 15 1331367-channel trench ring on the bottom surface of the trench, without forming a channel ring. The mask forming step is used, and the manufacturing method of the semiconductor device which does not require a precise rice cooking technique is formed at the time of forming the groove. Further, in the method of manufacturing a semiconductor device relating to tilting, since the laser uses a visible light laser, the control of the first semiconductor layer 10 during heating can be easily performed without evaporating the first sheep conductor layer 10 itself. The channel cut-off ring 22 can be formed by diffusing the n-type impurity 20 into the inside of the magic semiconductor layer 1''. Further, in the manufacturing method of the semiconductor device according to the first embodiment, since the step of removing the residual gamma impurity 2 再 between the channel cut ring forming step and the passivation layer forming step, the inner surface of the trench 18 is made It is possible to purify, and to make the mesa-type semiconductor device highly resistant to enthalpy, and to achieve high reliability. Further, in the manufacturing method of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . In addition, in the method of manufacturing the semiconductor device according to the first embodiment, the channel cut-off loop forming step 'channel_ring' is extended by the gate line 18, which is not followed by In the semiconductor substrate breaking step, when the two channel cut-off rings 22, 22 are cut off, since the portions of the channel cut-off ring 22 and the fourth conductor layer 10 which are pre-bonded are not necessarily cut, the occurrence of cracks or cracks in the wafer can be suppressed. It is possible to make a semiconductor device with high reliability. In addition, in the method of the implementation of the _ semiconductor device, because only the record _ into 2 series of money _22,22, so the semi-guided county of the money is easy to break 16 1331367 on two channels cut off The rings 22, 22 are worn between the rings. In the method of fabricating the semiconductor device according to the first embodiment, after the passivation layer forming step, the semiconductor substrate is cut off between the two channels _micro, 22 which are difficult to extend along the trench, Therefore, it is possible to manufacture a mesa-shaped semiconductor device having high withstand voltage and high reliability. Embodiment 2 There is a manufacturing method of _semiconducting miscellaneous in the second embodiment, which basically includes the manufacturing method of the embodiment #味_半导导置__, (4) _ the step is the same as the implementation In the method of manufacturing a semiconductor device according to the second embodiment, the method of manufacturing the semiconductor device according to the second embodiment is a step of introducing a gas containing (4) impurities to the bottom surface of the trench. Subtraction, and the actual complement 2 have _ turn «the manufacturing method, the ambiguous (four) to the step is different from the manufacturing method of the example 1 « drunk guide miscellaneous, (4) by the recording method, the semiconductor of the disk example i The device is manufactured in the same manner, and an n-type impurity can be supplied to the bottom surface of the groove. In view of the above, the method of manufacturing a semiconductor device according to the method of manufacturing a shaft device, and the manufacturing method of a semiconductor device for manufacturing a shaft and a broken ring are manufactured on the bottom surface of the groove. Manufacturing method, not working _ ring and _ mask forming step 'and the semiconductor lamp (4) manufacturing method without the (four) side technology. In addition, in the manufacturing method of Yucai 2 (4), the gas containing the n-type impurity is preferably a method for supplying a mixed gas 4 such as a phosphine and an inert gas, and the semiconductor wafer can be exposed to the atmosphere of the gas. Methods. Further, since the manufacturing method of the semiconductor device according to the second embodiment has the same steps as the method of manufacturing the semiconductor device according to the first embodiment, the method of manufacturing the semiconductor device according to the embodiment j is provided. The same effect in the efficacy. Embodiment 3 Fig. 5 is a view for explaining a semiconductor substrate cutting step associated with Embodiment 3. Fig. 5 is a plan view showing the semiconductor device 1A4a before the truncation, similar to Fig. 4(a). In the third embodiment, there is a manufacturing method of a semiconductor device, and a method for manufacturing a semiconductor device of the embodiment of the present invention, but the planar shape of the channel interrupting ring is the same as that of the semiconductor device according to the first embodiment. The manufacturing method is different. As shown in Fig. 5, in the method of manufacturing a semiconductor device according to the third embodiment, the channel stop ring 22 is formed around the element formation region 34 between the element formation region and the dicing line DL. As described above, in the method of manufacturing a semiconductor device according to the third embodiment, the planar shape of the trench cut ring is different from that of the semiconductor device according to the embodiment, but the method of fabricating the semiconductor device according to the embodiment is described. In the same way, since the storage of the impurity impurity 20 is diffused into the inside of the first semiconductor to form a channel, the manufacturing method of the semiconductor device related to the state is implemented, and the trench is provided on the bottom surface of the trench. The method for manufacturing a semiconductor device of a mesa-type semiconductor device having a channel cut-off ring does not require a mask forming step for forming a channel cut-off ring, and a method for manufacturing a semiconductor device which does not require a technique. Moreover, since there is a method for manufacturing a semiconductor device, the method of manufacturing a semiconductor device is the same as that of the first embodiment, and the method for manufacturing a semiconductor device is the same as the embodiment. Have the effect of sister reduction. In the above, the method of manufacturing the semiconductor device according to the present invention will be described based on the above embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention. Modifications. (1) In the above embodiments, the first conductivity type is the n-type and the second conductivity type is the lip shape. However, the present invention is not limited thereto, and the first conductivity type may be the p-type and the second conductivity. The conductivity type is η type. (2) In the above embodiments, although the laser uses a green laser, the present invention is not limited by this. The laser may also be a visible laser or a near-infrared laser other than a green laser (for example, a Nd-YAG laser). (3) In the above embodiment, the liquid containing the n-type impurity may be a one which dissolves pyrophosphoric acid into the organic hydrazine, but the present invention is not used for the ship L, so as to make the phosphorus compound or arsenic other than the pure acid of the limb. A compound that dissolves in a liquid of various organic solvents. (4) In the above-mentioned respective aspects, the present invention is described by taking the diode as an example, but the present invention is not limited thereto. For example, the present invention can be applied to a diode other than a dipole body (for example, a pin diode and a Schottky diode), a transistor (for example, a bipolar transistor, a M0 cream, etc.), Thyristor, three-terminal bidirectional controllable material and other power semiconductor devices. [Circular Simple Description] Fig. 1 is a schematic view for explaining a semiconductor device 1 according to the first embodiment. Fig. 2 is a schematic view for explaining a method of manufacturing a semiconductor device related to Embodiment i. Fig. 3 is a schematic view for explaining a method of manufacturing a semiconductor device related to Embodiment i. 19 1331367 Figure 4 is a schematic view showing the semiconductor substrate cutting step associated with Example 1. Fig. 5 is a view for explaining the semiconductor substrate cutting step associated with the third embodiment. Fig. 6 is a schematic view for explaining a method of manufacturing the semiconductor device described in Patent Document 1. Fig. 7 is a sound diagram for explaining a method of manufacturing a semiconductor device described in Patent Document 2. [Explanation of main element horn] [Practical] 80l··· n-type semiconductor layer (collector region) 801a...n+ type semiconductor layer φ 801b η-type semiconductor layer 803...emitter region 805a...passivation film 807...collector Electrode 809: Emitter electrode 81l·.·Ditch 813... Oxide film φ 911_··n-type semiconductor layer 913...p+ type diffusion layer 916...groove 918...channel cut ring [Invention] 10...first semiconductor layer 14 ···3rd semiconductor layer 802···p-type epitaxial layer (base region) 805...insulating film 806...channel cut-off ring 808...base electrode 810···ρη junction 812...saturated layer 813a...opening Portion 912 '925...n+ type diffusion layer 914,915...electrode 917...passivation film 926' 928." oxide film 12... second semiconductor layer 16... oxide film 20 1331367 18... groove 22... channel cut ring 26 ...single crystal region 30, 32...electrode 20·n-type impurity 24...amorphous material region 28...passivation layer 34...element forming region 100···semiconductor device (after wafer formation) 100a, 104a···semiconductor device (Before wafer formation) DL··· cutting line

Claims (1)

1331367 十、申請專利範圍: h —種半導體裝置之製造方法,其特徵在於包括: 具有第1導電塑之第1半導體層及經予配置於該第1半導體層之第j 主面側而與該第1導電型相反的導電型之第2導電型的第2半導體層, 於該第1半導體層及該第2半導體層的接合部準備如接面已予形成的半 導體基體之半導體基體準備步驟; 自該半導體基體之該第1主©娜射越過該ρη^崎度的溝之溝形 ^ 成步驟; 至少供給第1導電型雜質至該溝底面之雜質供給步驟; 於該溝底面照射雷射使該第1導電型雜質擴散至該第丨半導體層的内 部以形成溝道截斷環之溝道截斷環形成步驟;及 . 於該溝之内部形成鈍化層的鈍化層形成步驟。 2.如請求項1所述的半導體裝置之製造方法,其中該雜質供給步驟係至少 塗布含有第1導電型雜質之液體於該溝底面的步驟。 φ 3.如請求項i所述的半導體裝置之製造方法,其中該雜質供給步驟係至少 供給含有第1導電型雜質之氣體至該溝底面的步帮。 4.如請求項丨至3之任-項所述的半導體裝置之製造方法,其中於該溝道 _環形成辦’該溝道截斷環·成沿該溝延伸的2個溝道截斷環。 5·如請求項4所述的半導體裝置之製造方法,其中於該鈍化層形成步驟之 後’再包括於沿該溝延伸的2個溝道截斷環之間截斷該半導體基體之基 體截斷步驟。 6·如請求項1裏3之任-項所述的半導體裝置之製造方法其中於該溝道 22 1331367 截斷環形成步驟,於該半導體裝置之元件形成區域及切割線之間形成圍 繞該元件形成區域之溝道截斷環。1331367 X. Patent application scope: The method for manufacturing a semiconductor device, comprising: a first semiconductor layer having a first conductive film and a j-th main surface side disposed on the first semiconductor layer; a second semiconductor layer of a second conductivity type of a conductivity type opposite to the first conductivity type, and a semiconductor substrate preparation step of preparing a semiconductor substrate formed as a junction surface at a junction portion between the first semiconductor layer and the second semiconductor layer; a step of forming a groove from the first main surface of the semiconductor substrate over the groove of the ρη^ roughness; an impurity supply step of supplying at least a first conductivity type impurity to the bottom surface of the groove; and irradiating the laser beam on the bottom surface of the groove a channel cut-off ring forming step of diffusing the first conductive type impurity into the second germanium semiconductor layer to form a channel cut ring; and a passivation layer forming step of forming a passivation layer inside the trench. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity supply step is a step of applying at least a liquid containing the first conductivity type impurity to the bottom surface of the trench. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity supply step supplies at least a gas containing a gas of the first conductivity type impurity to the bottom surface of the trench. 4. The method of fabricating a semiconductor device according to claim 3, wherein the channel-forming ring is formed by two channel-cut rings extending along the groove. The method of fabricating a semiconductor device according to claim 4, wherein after the step of forming the passivation layer, a step of intercepting the substrate of the semiconductor substrate is further included between the two channel cut-off rings extending along the trench. 6. The method of fabricating a semiconductor device according to claim 3, wherein the trench 22 forming step is formed in the channel 22 1331367, forming a surrounding portion between the element forming region and the dicing line of the semiconductor device. The channel of the area is cut off. 23twenty three
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