CN112133743A - Silicon controlled rectifier structure and manufacturing method thereof - Google Patents
Silicon controlled rectifier structure and manufacturing method thereof Download PDFInfo
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- CN112133743A CN112133743A CN202011332865.XA CN202011332865A CN112133743A CN 112133743 A CN112133743 A CN 112133743A CN 202011332865 A CN202011332865 A CN 202011332865A CN 112133743 A CN112133743 A CN 112133743A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 57
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 57
- 239000010703 silicon Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 96
- 238000009792 diffusion process Methods 0.000 claims abstract description 39
- 239000011241 protective layer Substances 0.000 claims abstract description 36
- 238000002347 injection Methods 0.000 claims description 83
- 239000007924 injection Substances 0.000 claims description 83
- 238000000034 method Methods 0.000 claims description 25
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 230000036961 partial effect Effects 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 6
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000005260 corrosion Methods 0.000 abstract 1
- 230000007797 corrosion Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 238000002513 implantation Methods 0.000 description 48
- 235000012431 wafers Nutrition 0.000 description 32
- 238000010586 diagram Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000002829 reductive effect Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- WABPQHHGFIMREM-NOHWODKXSA-N lead-200 Chemical compound [200Pb] WABPQHHGFIMREM-NOHWODKXSA-N 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
A silicon controlled structure and its manufacturing method, including mesa ditch groove and surrounding the protective layer located at mesa ditch groove bottom, surround the doping type of the protective layer for N type doping or P type doping corresponding to base region doping type, and surround the doping concentration of the protective layer and is greater than the doping concentration of the base region, because the too wide mesa width in the mesa type silicon controlled device has influenced the area of the silicon controlled device passthrough area of the area, through setting up surrounding the protective layer in the end that the corrosion removes, surround the protective layer for the diffusion layer of the high concentration, the diffusion layer of this high concentration can compress the electric field in the widening of the low doping area, thus can narrow the width of the mesa, thus improve the utilization factor of the effective area of the crystal circle, in order to achieve the purpose to reduce the device manufacturing cost.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a silicon controlled rectifier structure and a manufacturing method thereof.
Background
The controllable silicon is widely applied to the fields of alternating-current contactless switches, household appliance control circuits, industrial control and the like.
At present, the production of the silicon controlled products mainly adopts a table-board process, and the process flow is as follows: growing a masking oxide layer on a wafer with the maximum size of 4 inches, then performing isolation and penetration diffusion on the wafer, and then performing base region and emitter region diffusion; after the emitter region is finished, a groove with the depth of more than 50 micrometers and the width of more than 150 micrometers needs to be etched between the front isolation region and the base region, a layer of glass cement is manually coated in the groove, a protective layer is formed through high-temperature sintering, and finally an aluminum layer and a back process are finished to form the 4-layer PNPN structure silicon controlled rectifier. Since the trench to be etched in the mesa process generally has a depth exceeding 50 μm and a width exceeding 150 μm, the wider the trench, the smaller the leakage current in the mesa, in order to achieve a sufficient voltage protection effect, however, the wider the mesa surface, which affects the area of the device current area, reduces the number of devices that can be fabricated on the same large wafer, i.e. reduces the utilization rate thereof, and increases the device fabrication cost.
Therefore, it is desirable to provide a thyristor device structure that improves the utilization of the wafer area and reduces the device manufacturing cost.
Disclosure of Invention
The invention provides a silicon controlled device structure, which can improve the utilization rate of the wafer area and reduce the width of a table board, thereby improving the utilization rate of the wafer area and achieving the purpose of reducing the manufacturing cost of the device.
According to a first aspect, there is provided in an embodiment a thyristor structure comprising:
the base region is doped in an N type or a P type mode and is provided with a first surface and a second surface opposite to the first surface;
the first injection region is positioned on the first surface of the base region, corresponds to the doping type of the base region and is doped in a P type or N type;
the second injection region is positioned on the second surface of the base region, corresponds to the doping type of the base region and is doped in a P type or N type;
the third injection region is positioned on the partial surface of the second injection region, the doping type of the third injection region corresponds to the doping type of the second injection region, and the third injection region is N-type doping or P-type doping;
an anode electrode is arranged on the surface of the first injection region, a gate electrode is arranged on the surface of the rest part of the second injection region, a cathode electrode is arranged on the surface of the third injection region, and the gate electrode and the cathode electrode are insulated;
the mesa groove is arranged around the peripheries of the gate electrode and the cathode electrode, or is arranged around the periphery of the anode electrode, and the depth of the mesa groove extends into the base region;
and the surrounding protective layer is positioned at the bottom of the groove of the table top, the doping type of the surrounding protective layer is the same as that of the base region, the surrounding protective layer is N-type doping or P-type doping, and the doping concentration of the surrounding protective layer is greater than that of the base region.
In some embodiments, the doping concentration and depth of the surrounding protection layer are the same as those of the third implantation region.
In some embodiments, the mesa trench further has a passivation layer thereon.
In some embodiments, the third implant region has a plurality of shorting dots therein.
According to a second aspect, an embodiment provides a method for manufacturing a thyristor structure, including:
selecting a proper silicon wafer, and defining a chip region and an isolation region, wherein the silicon wafer is of a first doping type, the first doping type is N-type doping or P-type doping, and the silicon wafer is provided with a first surface and a second surface opposite to the first surface;
performing a diffusion process of a second doping type on the first surface and the second surface of the silicon wafer, wherein the second doping type is P-type doping or N-type doping corresponding to the first doping type, so as to form a first injection region in the first surface of the silicon wafer and a second injection region in the second surface of the silicon wafer, and a base region is arranged between the first injection region and the second injection region;
etching the defined isolation region to the bottom of the base region to form a mesa groove, wherein two adjacent chip regions share one mesa groove;
forming a patterned oxide layer on part of the surface of the mesa groove, the surface of the first injection region and the surface of the second injection region, wherein the patterned oxide layer exposes a third injection region window and a surrounding protective layer window; the third injection region window is positioned on the partial surface of the second injection region, and the surrounding protective layer window is positioned at the bottom of the mesa groove;
performing a first doping type diffusion process on the silicon wafer by taking the patterned oxide layer as a mask, wherein the diffusion concentration is greater than the doping concentration of the base region, so as to form a third injection region on part of the surface of the second injection region and form a surrounding protective layer at the bottom of the mesa groove;
and respectively forming electrode pins on the surface of the first injection region, the surface of the second injection region and the surface of the third injection region, wherein the electrode pins are insulated and isolated.
In some embodiments, forming a patterned oxide layer on the surface of the mesa trench, the surface of the first implant region, and the surface of the second implant region comprises:
covering oxide layers on the surface of the mesa groove, the surface of the first injection region and the surface of the second injection region;
forming a graphical photoresist layer on the surface of the oxide layer, wherein the graphical photoresist layer exposes the third injection region window and the surrounding protection layer window; the third injection region window is positioned on the partial surface of the second injection region, and the surrounding protective layer window is positioned at the bottom of the mesa groove;
and etching the oxide layer by taking the patterned photoresist layer as a mask so as to transfer the pattern of the patterned photoresist into the oxide layer to form a patterned oxide layer.
In some embodiments, after performing a diffusion process of a first doping type on the silicon wafer by using the patterned oxide layer as a mask, the method further includes: and removing the patterned oxide layer by using hydrofluoric acid.
In some embodiments, after removing the patterned oxide layer by using hydrofluoric acid, the method further includes: and carrying out a passivation treatment process on the surface of the mesa groove to form a passivation layer.
In some embodiments, further comprising: and performing enhanced diffusion process treatment on the surface of the first injection region, wherein the diffusion type of the enhanced diffusion process is the same as the doping type of the first injection region, and an enhancement region with the doping concentration higher than that of the first injection region is formed.
In some embodiments, further comprising: controlling the doping concentration of the surrounding protective layer; controlling the doping concentration of the surrounding protective layer comprises: the square resistance of the control diffusion chip is less than 10.
According to the silicon controlled structure and the manufacturing method thereof of the embodiment, the silicon controlled structure comprises the surrounding protective layer positioned at the bottom of the groove of the mesa, the doping type of the surrounding protective layer is N-type doping or P-type doping corresponding to the doping type of the base region, and the doping concentration of the surrounding protective layer is greater than that of the base region.
Drawings
Fig. 1 is a schematic structural diagram of a thyristor device provided in an embodiment of the invention;
fig. 2 is a top view of a thyristor device structure provided in an embodiment of the invention;
FIG. 3 is a flow chart of a method for manufacturing a thyristor according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a portion of a structure in a manufacturing process according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a portion of a structure in a manufacturing process according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a portion of a structure in a manufacturing process according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a portion of a structure in a manufacturing process according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a portion of a structure in a manufacturing process according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a portion of a structure in a manufacturing process according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a part of the manufacturing process provided in the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
It is analyzed that the surface electric field is reduced by removing a portion of the PN junction depletion layer by etching, so that the withstand voltage characteristics of the device are good, but the area used in the through-flow region of the device is affected by the excessively wide surface width due to the removal of a portion of the mesa trench.
The silicon controlled device structure comprises a surrounding protective layer positioned at the bottom of a groove of a table top, wherein the doping type of the surrounding protective layer is N-type doping or P-type doping corresponding to the doping type of a base region, and the doping concentration of the surrounding protective layer is greater than that of the base region.
Referring to fig. 1 and fig. 2, an embodiment of the present invention provides a silicon controlled rectifier structure, including a base region 100, a first implantation region 101, a second implantation region 102, a third implantation region 103, an anode electrode 210 on a surface of the first implantation region 102, a gate electrode 230 on a portion of a surface of the second implantation region 102, and a cathode electrode 220 on a surface of the third implantation region 103, further including: a mesa trench 300 and a surrounding protection layer 310 at the bottom of the mesa trench 300.
The base region 100 is doped P-type or N-type, and the base region 100 has a first surface and a second surface opposite to the first surface.
In this embodiment, the base region is an N-type doped silicon substrate.
The first injection region 101 is located on a first surface of the base region 100, and the first injection region 101 is N-type doped or P-type doped corresponding to a doping type of the base region 100. For example, since the base region is doped N-type in this embodiment, the first implantation region 101 is doped P-type.
In some embodiments, the doping of the first implantation region 101 may be heavily doped, which may be understood as the concentration of the heavily doped region is greater than the concentration of the P-type doping in the base region 100. For example, in this embodiment, the first implantation region 101 is a diffusion region+A region, i.e., a highly doped P-type region.
The second injection region 102 is located on a second surface of the base region 100, and the second injection region 102 is N-type doped or P-type doped corresponding to the doping type of the base region 100. For example, since the base region in this embodiment is doped N-type, the second implantation region 102 is doped P-type, which is the same as the first implantation region 101.
The third implantation region 103 is located on a portion of the surface of the second implantation region 102, and the third implantation region 103 is doped P-type or N-type corresponding to the doping type of the second implantation region 102. For example, in this embodiment, the base region 100 is doped N-type, and the third implantation region 103 is correspondingly doped N-type.
In some embodiments, the N-type doping of the third implantation region 103 is heavily doped, it being understood that the concentration of the heavily doped region is greater than the concentration of the doping in the base region 100. For example, in this embodiment, the third implantation region is heavily doped with N+And (4) a zone.
The anode electrode 210, the gate electrode 230, and the cathode electrode 220 are insulated from each other.
It should be noted that the surface of the first implantation region 101, the surface of the second implantation region 102, and the surface of the third implantation region 103 have electrode pins 200, each electrode pin is isolated from another electrode pin in an insulating manner, and the anode electrode 210, the gate electrode 230, and the cathode electrode 220 are respectively formed on the electrode pins 200.
In this embodiment, the mesa trench 300 is disposed around the peripheries of the gate electrode 230 and the cathode electrode 220, or the mesa trench 300 is disposed around the periphery of the anode electrode 210, and the depth of the mesa trench 300 extends into the base region 100.
It should be noted that, in the wafer, two adjacent chip regions 10 are defined to have a mesa therebetween, and it is understood that two adjacent chip regions 10 share one mesa trench 300.
The doping type of the surrounding protection layer 310 is N-type doping or P-type doping corresponding to the doping type of the base region 100, and the doping concentration of the surrounding protection layer 310 is greater than the doping concentration of the base region 100.
In this embodiment, since the doping type of the base region 100 is N type, the doping type of the surrounding protection layer 310 is N type. And, the surrounding passivation layer 310 is an N-layer+A region, i.e., a highly doped N-type region.
In this embodiment, a surrounding protection layer 310, i.e., a high concentration of N, is added to the bottom of the mesa trench (i.e., mesa) at the interface of the PN junction+Diffusion layer of N+The diffusion layer can shorten the broadening width of an electric field in a low-doped region, and simultaneously has high concentration of N+The diffusion layer can neutralize and absorb surface charges, so that the mesa leakage current of the device can be reduced, and the voltage resistance of the device is further improved.
In some embodiments, the sheet resistance of the N + diffusion of the dopant concentration surrounding the protection layer is preferably less than 10.
In this embodiment, the surface of the mesa trench 300 further has a passivation layer, and the passivation layer is silicon dioxide.
In some embodiments, the third implantation region 103 has a plurality of shorting dots 500 therein, and the shorting dots 500 are formed as an integral part of the third implantation region and function to directly short the third implantation region 103 when the blocking voltage is tested, thereby improving the high temperature characteristics of the product.
In this embodiment, an insulating protection layer 400 is further disposed on the periphery of the silicon controlled rectifier chip, and the insulating protection layer 400 wraps the silicon controlled rectifier device and exposes the anode electrode 210, the gate electrode 230, and the cathode electrode 220 to protect the internal structure of the silicon controlled rectifier chip and improve the reliability and stability of the device.
Referring to fig. 2 to 10, in this embodiment, a method for manufacturing a silicon controlled rectifier structure is further provided, where the method is used to manufacture the silicon controlled rectifier structure in the above embodiment, and the method includes the steps of:
In the embodiment, a proper N-type silicon wafer is selected, and different resistivity can be selected according to different withstand voltage requirements; the thickness of the dielectric layer is selected from 220 μm to 460 μm according to the designed wafer withstand voltage.
And 2, performing a second doping type diffusion process on the first surface and the second surface of the silicon wafer.
The second doping type is P-type doping or N-type doping corresponding to the first doping type, so as to form a first injection region 101 in the first surface of the silicon wafer, and form a second injection region 102 in the second surface of the silicon wafer, and a base region is arranged between the first injection region 101 and the second injection region 102.
The front surface and the back surface of the silicon wafer are respectively a first surface and a second surface, and in this embodiment, since the silicon wafer is doped N-type, the first injection region 101 and the second injection region 102 are both doped P-type.
In some embodiments, the doping of the second implantation region 102 may be further controlled to be heavily doped, which is understood to be a doping concentration greater than the P-type doping concentration in the base region 100. For example, in the present embodiment, the second implantation region 102 is a diffusion region+A region, i.e., a highly doped P-type region.
In some embodiments, diffusion may be further performed on the surface of the first implantation region 101 to form an enhancement region with a high concentration of P+Zone, high concentration of P+The doping concentration of the region is heavily doped.
In some embodiments, the first implantation region 101 may be directly controlled to be heavily doped. It is understood that the heavily doped concentration is a concentration of doping greater than the concentration of P-type doping in the base region 100. For example, the present embodimentIn (1), the first implantation region 101 is a diffusion P+A region, i.e., a highly doped P-type region.
And step 3, etching the defined isolation region to the bottom of the base region 100 to form a mesa groove 300, wherein two adjacent chip regions share one mesa groove 300.
Referring to fig. 4, fig. 4 is a schematic structural diagram of the mesa trench 300 etched. The etching method can be dry etching or wet etching.
Step 4, forming a patterned oxide layer 320.
Referring to fig. 5, a patterned oxide layer 320 is formed on a portion of the surface of the mesa trench 300, the surface of the first implantation region 101, and a portion of the surface of the second implantation region 102, where the patterned oxide layer 320 exposes a third implantation region window and a surrounding protection layer window; wherein the third implantation region window is located on a part of the surface of the second implantation region, and the surrounding protection layer window is located at the bottom of the mesa trench 300.
In this embodiment, the patterned oxide layer 320 is silicon dioxide with a thickness of 0.5um to 2 um.
Step 5, forming a third implantation region 103 on a portion of the surface of the second implantation region 102, and forming a surrounding protection layer 310 on the bottom of the mesa trench 300.
Referring to fig. 6, a first doping type diffusion process is performed on the silicon wafer with the patterned oxide layer 320 as a mask, and the diffusion concentration is greater than the doping concentration of the base region 100, so that a third implantation region 103 is formed in a portion of the surface of the second implantation region 102, and a surrounding protection layer 310 is formed at the bottom of the mesa trench 300.
In this embodiment, the third implantation region 103 and the surrounding protection layer 310 are doped N-type correspondingly.
In this embodiment, the N-type doping of the third implantation region 103 is heavily doped, which can be understood as the concentration of heavily doped doping is greater than the concentration of doping in the base region 100. For example, in this embodiment, the third implantation region is heavily doped with N+And (4) a zone.
It should be noted that, in the manufacturing process, it is often necessary to control the diffusion concentration, and in this embodiment, the manner of controlling the diffusion concentration includes: the diffusion concentration of the silicon wafer is controlled by measuring the surface sheet resistance of the accompanying wafer which enters the furnace together with the silicon wafer for diffusion. Correspondingly, in this embodiment, controlling the doping concentration of the ring protection layer includes: the sheet resistance of the diffusion wafers fed into the furnace together with the silicon wafers was controlled to be less than 10.
Referring to fig. 7, in the present embodiment, after the third implantation region 103 and the surrounding protection layer 310 are formed, the removing of the patterned oxide layer 320 is further included.
In this embodiment, the patterned oxide layer 320 is removed by hydrofluoric acid.
In this embodiment, after the patterned oxide layer 320 is removed by hydrofluoric acid, a passivation process is performed on the surface of the mesa trench 300 to form a passivation layer (not shown). The passivation layer may be silicon oxide.
In this embodiment, the step of forming the patterned oxide layer 320 includes:
first, an oxide layer, which may be silicon dioxide, is covered on the surface of the mesa trench 300, the surface of the first implantation region 101, and the surface of the second implantation region 102.
Then, forming a graphical photoresist layer on the surface of the oxide layer, wherein the graphical photoresist layer exposes a third injection region window and a surrounding protective layer window; the third injection region window is positioned on the partial surface of the second injection region, and the surrounding protective layer window is positioned at the bottom of the mesa groove.
Finally, the oxide layer is etched by using the patterned photoresist layer as a mask, so that the pattern of the patterned photoresist is transferred into the oxide layer, thereby forming the patterned oxide layer 320.
Referring to fig. 9, in the present embodiment, metal electrodes, namely an anode electrode 210 on the surface of the first injection region 102, a gate electrode 230 on a portion of the surface of the second injection region 102, and a cathode electrode 220 on the surface of the third injection region 103, are respectively welded on the surface of the first injection region 101, the surface of the second injection region 102, and the electrode lead 200 of the third injection region 103.
Referring to fig. 10, after the electrodes are formed, the silicon controlled device is manufactured, in this embodiment, an insulating protective layer 400 is further disposed around the silicon controlled chip by an injection molding or encapsulation process, and the insulating protective layer 400 wraps the silicon controlled device and exposes the anode electrode 210, the gate electrode 230, and the cathode electrode 220, so as to protect the internal structure of the silicon controlled chip and improve the reliability and stability of the device.
In this embodiment, the surrounding protection layer 310, i.e., the high concentration of N, is added at the bottom of the mesa trench (i.e., mesa)+The diffusion layer, the structure of the mesa can be regarded as PNN + structure, in the test process, along with the continuous rise of voltage, after the broadening of the space charge region reaches the N + layer, the broadening of the space charge region becomes very small due to the high impurity concentration of the N + layer, at the moment, the size of the mesa junction can be correspondingly shortened, so that along with the introduction of the high-concentration layer of the N + layer, the N + layer can be introduced+The diffusion layer can shorten the broadening width of an electric field in a low-doped region, and simultaneously has high concentration of N+The diffusion layer can neutralize and absorb surface charges, so that the mesa leakage current of the device can be reduced, the withstand voltage characteristic of the device can be further improved, and meanwhile, the withstand voltage is widened in the base region, so that the width of a mesa groove can be narrowed, and the utilization rate of the wafer area can be improved.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A thyristor structure, comprising:
the base region is doped in an N type or a P type mode and is provided with a first surface and a second surface opposite to the first surface;
the first injection region is positioned on the first surface of the base region, corresponds to the doping type of the base region and is doped in a P type or N type;
the second injection region is positioned on the second surface of the base region, corresponds to the doping type of the base region and is doped in a P type or N type;
the third injection region is positioned on the partial surface of the second injection region, the doping type of the third injection region corresponds to the doping type of the second injection region, and the third injection region is N-type doping or P-type doping;
an anode electrode is arranged on the surface of the first injection region, a gate electrode is arranged on the surface of the rest part of the second injection region, a cathode electrode is arranged on the surface of the third injection region, and the gate electrode and the cathode electrode are insulated;
the mesa groove is arranged around the peripheries of the gate electrode and the cathode electrode, or is arranged around the periphery of the anode electrode, and the depth of the mesa groove extends into the base region;
and the surrounding protective layer is positioned at the bottom of the groove of the table top, the doping type of the surrounding protective layer is the same as that of the base region, the surrounding protective layer is N-type doping or P-type doping, and the doping concentration of the surrounding protective layer is greater than that of the base region.
2. The silicon controlled structure of claim 1, wherein the doping concentration and depth of the surrounding protection layer are the same as the concentration and depth of the third implanted region.
3. The silicon controlled structure of claim 1, further comprising a passivation layer on the mesa trench.
4. The silicon controlled structure of claim 1, wherein the third implant region has a plurality of shorting dots therein.
5. A method for manufacturing a silicon controlled rectifier structure is characterized by comprising the following steps:
selecting a proper silicon wafer, and defining a chip region and an isolation region, wherein the silicon wafer is of a first doping type, the first doping type is N-type doping or P-type doping, and the silicon wafer is provided with a first surface and a second surface opposite to the first surface;
performing a diffusion process of a second doping type on the first surface and the second surface of the silicon wafer, wherein the second doping type is P-type doping or N-type doping corresponding to the first doping type, so as to form a first injection region in the first surface of the silicon wafer and a second injection region in the second surface of the silicon wafer, and a base region is arranged between the first injection region and the second injection region;
etching the defined isolation region to the bottom of the base region to form a mesa groove, wherein two adjacent chip regions share one mesa groove;
forming a patterned oxide layer on part of the surface of the mesa groove, the surface of the first injection region and the surface of the second injection region, wherein the patterned oxide layer exposes a third injection region window and a surrounding protective layer window; the third injection region window is positioned on the partial surface of the second injection region, and the surrounding protective layer window is positioned at the bottom of the mesa groove;
performing a first doping type diffusion process on the silicon wafer by taking the patterned oxide layer as a mask, wherein the diffusion concentration is greater than the doping concentration of the base region, so as to form a third injection region on part of the surface of the second injection region and form a surrounding protective layer at the bottom of the mesa groove;
and respectively forming electrode pins on the surface of the first injection region, the surface of the second injection region and the surface of the third injection region, wherein the electrode pins are insulated and isolated.
6. The method of claim 5, wherein forming a patterned oxide layer on a surface of the mesa trench, a surface of the first implant region, and a surface of the second implant region comprises:
covering oxide layers on the surface of the mesa groove, the surface of the first injection region and the surface of the second injection region;
forming a graphical photoresist layer on the surface of the oxide layer, wherein the graphical photoresist layer exposes the third injection region window and the surrounding protection layer window; the third injection region window is positioned on the partial surface of the second injection region, and the surrounding protective layer window is positioned at the bottom of the mesa groove;
and etching the oxide layer by taking the patterned photoresist layer as a mask so as to transfer the pattern of the patterned photoresist into the oxide layer to form a patterned oxide layer.
7. The method of claim 6, wherein after performing a first doping type diffusion process on the silicon wafer using the patterned oxide layer as a mask, further comprising: and removing the patterned oxide layer by using hydrofluoric acid.
8. The method of claim 7, wherein after removing the patterned oxide layer using hydrofluoric acid, further comprising: and carrying out a passivation treatment process on the surface of the mesa groove to form a passivation layer.
9. The method of claim 5, further comprising: and performing enhanced diffusion process treatment on the surface of the first injection region, wherein the diffusion type of the enhanced diffusion process is the same as the doping type of the first injection region, and an enhancement region with the doping concentration higher than that of the first injection region is formed.
10. The method of claim 5, further comprising: controlling the doping concentration of the surrounding protective layer;
controlling the doping concentration of the surrounding protective layer comprises: the square resistance of the control diffusion chip is less than 10.
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