丄J26910 ‘九、發明說明： “【發明所屬之技術領域】 本發明係有關搭載半導體元件等並接合於配線基板等 .之半導體模組及其製造方法。 【先前技術】 菖行動電話、個人數位助理（pers〇nal dighai assistant， PDA)、數位攝影機（叫如1 video camera，dvc)、數位相機 鲁(jigital still camera，DSC)等之攜帶式電子機器加速進行 间機能化時，為了使這樣的產品在市場上可被接受，還必 須進行小型.輕量化。而為了實現這樣的需求而必須尋求 高積體化的系統大型積體（large scale integration，^^技 術另方面，對這些電子機器而言，也需要有更加好用 而便利的性能，而必須對在機器上使用的LSI要求高機能 化、高性能化。為此，伴隨著LSI晶片之高積體化之輸入/ 輸出點數的增加，使封裝本身之小型化的要求也增強，為 齡了使這些需求可並存，而強烈地要求對適合於高密度半導 體零件之基板組裝的半導體封裝技術進行開發。為了配合 這樣的要求，而進行稱為晶片級封裝（Chip Size Package， CSP)之封裝技術的各種開發。 目丽已知有球開陣列封裝（Ball Grid Array，BGA)可作 為如此的封裝例。BGA係在封裝用基板上上安裝半導體元 件’將其以樹脂模製之後，在對向側之表面形成作為外部 接點之區域狀銲錫球。在BGA中，因為以面狀形成組裝區 域使封裝月b比車父容易小型化。此外，因為在電路基板側 315641D01 5 1326910 、上也沒有配合狭小間距的必要，而不需要高精確度的組裝 、技術，所以使用BGA的話，即使封裝成本在多少較高的情 況下，總組裝成本仍可能降低。 第1圖係表示一般之BGA的概要結構圖。BGA1〇〇具有 在玻璃環氧（Glass-Epoxy)基板106上，透過接著層1〇8搭載 LSI晶片102的構造。其中，藉由封裝樹脂11〇對Lsi晶片 進行模製（molding^而將LSI晶片1〇2以及玻璃環氧基板 106間以金屬線1〇4電性連接。在玻璃環氧基板1〇6的背 面，銲錫球112以陣列狀排列。再透過該銲錫球112，將 BGA100安裝於印刷線路基板。 在專利文獻1中記載有其他CSP的例子。在該公報記載 中，並揭露搭載高頻用LSI的系統級封裝件（8%丨灿比 package)。該封裝件係於基底（base)基板上形成多層線路構 造，而在該基板上首先形成高頻用LSI之半導體元件。多 層線路構造係為核心（core)*板以及附加樹脂之銅箔等之 鲁疊層構造。 但是，由這些習知的CSP卻難以在攜帶式電子機器等 方面實現如目前希望之水準的小型化、薄型化、輕量化。 其係因為習知的CSP具有支撐元件之基板的關係。由於支 撐基板的存在，使封裝全體變厚，而使小型化、薄型化、 輕量化有其界限。此外，散熱性的改善也有一定的界限。 U X料日本國專利2002-94247號公報丄J26910 'Nine, the invention is related to the invention. The present invention relates to a semiconductor module in which a semiconductor element or the like is mounted and bonded to a wiring board or the like, and a method of manufacturing the same. [Prior Art] 菖Mobile phone, personal digital device When a portable electronic device such as an assistant (pers〇nal dighai assistant, PDA), a digital camera (called a video camera, dvc), or a jigital still camera (DSC) accelerates the inter-function, in order to make such Products can be accepted in the market, and must be small and lightweight. In order to achieve such a demand, it is necessary to seek a large scale integration system (large scale integration, ^^ technology, on these other electronic devices In other words, it is necessary to have higher performance and more convenient performance, and it is necessary to have high performance and high performance for the LSI used in the machine. For this reason, the number of input/output points of the LSI chip is high. The increase, the requirement for miniaturization of the package itself is also enhanced, so that these requirements can coexist, and it is strongly required to be suitable for high-density semiconductor Development of a semiconductor package technology for substrate assembly of body parts. In order to meet such requirements, various developments of a package technology called Chip Size Package (CSP) have been carried out. A ball open array package (Ball is known) Grid Array (BGA) can be used as such a package example. BGA mounts a semiconductor element on a package substrate. After molding it with a resin, a region-shaped solder ball as an external contact is formed on the surface on the opposite side. In the BGA, since the assembly area is formed in a planar shape, the package month b is easier to be miniaturized than the driver. Further, since the circuit board side 315641D01 5 1326910 does not have a narrow pitch, it is not required to be assembled with high precision. Technology, so if BGA is used, the total assembly cost may be reduced even if the package cost is high. Figure 1 shows the general structure diagram of the general BGA. BGA1〇〇 has glass epoxy (Glass-Epoxy) The structure of the LSI wafer 102 is mounted on the substrate 106 through the bonding layer 1 to 8. The LSi wafer is molded by the encapsulating resin 11 (molding^ The LSI wafer 1〇2 and the glass epoxy substrate 106 are electrically connected by a metal wire 1〇4. On the back surface of the glass epoxy substrate 1〇6, the solder balls 112 are arranged in an array, and the solder balls 112 are further transmitted through the solder balls 112. The BGA 100 is mounted on a printed circuit board. An example of another CSP is described in Patent Document 1. In the description of the publication, a system-in-package (8% package) in which a high-frequency LSI is mounted is disclosed. A multilayer wiring structure is formed on a base substrate, and a semiconductor element of a high frequency LSI is first formed on the substrate. The multi-layer line structure is a laminated structure of a core* plate and a copper foil with an additional resin. However, these conventional CSPs are difficult to achieve miniaturization, thinning, and weight reduction as currently desired in portable electronic devices and the like. This is because the conventional CSP has a relationship of the substrate supporting the element. Due to the presence of the supporting substrate, the entire package is made thick, and there is a limit to miniaturization, thinning, and weight reduction. In addition, there is a certain limit to the improvement of heat dissipation. U X material Japanese Patent No. 2002-94247
Ajj文獻曰本國專利2002-110717號公敎 【發明内容】 315641D01 fel·欲解決的期 在以上所述之BGA等封裝件中’封裝件之支樓基板和 θ 70件之封裝樹脂間之充分緊密結合性十分重要，特別 後述之半導體模組因為沒有支撐基板，因此 •子”面緊密結合性的要求十分嚴格。 树明係有鑑於上述問題所開發者，其目的為，在半 r 2 ―’模組件中’將絕緣基材和形成於絕緣基材上的 :半導體元件之封裝樹脂或接著材料間的緊密 本發明之半導體模組所具有的特徵為：包含設置 電路的絕緣基材，形成於节έ„縫其 ¥ ①底於H緣基材上的半導體元件，以 =該絕緣基材以及該半導體元件㈣立的絕緣體，·以 =在該絕緣基材之連接該絕緣體的表面上，形成微小突起 阻、中，半導體元件係包含半導體晶片、晶片電 日日片電奋、晶片電導（chip conductor)等。 模組因為在絕緣基材之連接絕緣體的表面上 ^小4群’使得於絕緣基材和絕緣體之界 結合性變得良好。 苳在 此外，絕緣體可以是密封半導體元件的 可，置於半導體元件和絕緣基材之間的接著材: *此外’在絕緣基材之連接絕緣體的表面上，也 複數之火山口（crater)狀凹部，而火 〆 在cu咖以上、lum以下。山口狀凹部之直徑也可 315641D0] 7 1326910 # 口為除了在絕緣基材之連接絕缘體的 表面上形成微小突起群外m + 以下夕箱叙, 卜並形成直徑〇·1 μπι以上、1 μπι 以下之複數之火山口狀 的緊密結合性變得良好。使、讀基材和絕緣體之界面 起。t 含有平均直徑1 ―至2。nm的複數之突 XV 2 ”密度宜為。.5X103 -·2以上，更宜為〇·8 2〇二Γ —2 咖2。特別是5最宜為1.6xH)、m-2至 面的X緊二」藉此’可明顯改善於絕緣基材和絕緣體之界 面的緊密結合性。 導辦雷^本發刀月之另+導體模組之特徵為：包含設置有 …的、％緣基材，形成於該⑽基材上的半導體元 連接該絕緣基材以及該半導體元件的絕緣體；以 緣基材之連接該絕緣體的表面中，該絕緣基材係 衣我樹脂材料構成，而於該表面之附近的又線光電子分 光譜（SPeCt_)中，當將束缚能舰5eV的檢測強度當作 將束縛強度-286 eV的檢測強度當和的時候，力的數 值為0.4以上。 於此，束缚能-286 eV屬於結構(：=〇結合的as電子。 另一方面，束缚能_284 5 6乂屬於結構c—〇結合或n結 合的Cls電子，這些比值在滿足上述條件時，可明顯改盖= 絕緣基材和絕緣體之界面的緊密結合性。還有，將ye之 數值的上限設為例如3以下。 有關本發明之再一半導體模組之特徵為：包含設置導 體電路的絕緣基材，形成於該絕緣基材上的半導體元件， 315641D01 8 1326910 以及連接該絕緣基材以及 頌鏠其从―* 千^體兀件的絕緣體；以及嗲 縣基材之連接該絕緣體的區域 及这 觸角為30度至12Q&。 心其對純水之接 藉由使用具有此接觸角的樹脂材料，可 絕緣基材和絕緣體之界面的緊密結合性。 、Q ·、 ^述之半導體模組，例如，可藉由在沒有施加㈣（ 的預疋條件下進行電漿（plasma)處理而得到。 丨有關本發明之又—半導體模組之特徵為：包 導體電路的的絕緣基材’形成於該絕緣基材上的半=體元 件’以及連接絕緣基材和半導體元件的絕緣體；以及絕緣 基材係為含有多官能氧環丁烧（〇xetane)化合 樹脂 化合物的光硬化性·熱硬化性樹脂。 乳樹月曰 該半導體模組的絕緣基材，因為具有含有多官能氧環 丁烷化合物或環氧樹脂化合物的光硬化性·熱硬化性2 脂，而可進行型樣化（patterning) ’同時，可明顯地改善對 絕緣基材和絕緣體的界面的緊密結合性。 13 有關本發明之又一半導體模組的特徵為：包含有基 材，形成於基材上的元件，以及連接基材以及元件的絕緣 體；以及在基材之連接絕緣體的表面上，形成微小突起群。 該模組因為在基材之連接絕緣體的表面上形成微小突 起群’使得於基材和絕緣體的界面之緊密結合性變得良 好。 315641D01 9 1326910 ' 此外，在基材之連結絕緣體的表面上，也可以形成複 .數的火山口狀凹部，而該微小突起群也可以含有平均 】nm至20nm之複數個突起。 二 、再者，本發明之半導體模組的製造方法係為製作上述 之f導體模組的方法，其特徵為··包含對設立有導體電路 的絕緣基材的表面進行電漿處理的步驟，以及在該絕緣基 材上，形成半導體元件以及連接該半導體元件之絕緣體二 籲步驟；以及在不對該基板施加偏壓（bias)〒，用含有惰性 氣體（惰性氣體）之電漿氣體進行該電漿處理。 月 藉由進行如上述之電漿處理，而能安定地得到對絕緣 基材和絕緣體之界面具有卓越的緊密結合性之半導體模 組。還有，所謂「偏壓」係不包括基板本身的偏麗。、 再者，本發明之模組的製造方法係為製作上述之模組 的方法，其特徵為：包含對基材之表面進行電漿處理的步 驟以及在基材上形成疋件和連接元件之絕緣體的步驟. 以及在不對縣板施加㈣下，料有舰鐘之氣 體進行該電漿處理。 7 ” 猎由進行如上述之電聚處理，而能安定地得到對基材 和絕緣體之界面具有卓越的緊密結合性之半導體模組。還 有’所謂「偏壓」係不包括基板本身的偏壓。 在本發明中，在半導體元件為裸晶片（barechip)，而絕 緣體係由密封裸晶狀封_脂構成時，特別具有效果。 在採用相關結構的情況下’以薄型化而能實現輕量之封裝 315641D01 10 良:=::果於::基，封裝樹脂之間有緊密結合不 本發明中之即可有效解決這樣的問題。 # * 明導體電路，係為形成於基材内部或基 由鋼線路等構成的電路。所謂絕緣基材，夂 而戶^ 件以及與其連接之導體電路的絕緣性基材， 而=謂絕_係為，例如，對設立於絕緣基材上之半=體 2進灯在封之封裝樹脂或，配置於絕緣基材和半導體元 之間的絕緣層或接著部材等。 &1月的效果 如果根據本發明，在半導體模組等模組方面，可將絕 緣基材形成於絕緣基材上的絕緣體、以及例如半導體元 件之封裝樹脂間的緊密結合性提高。 【實施方式】 以下將說明有關本發明之實施形態，然而在進入說明 之刖，先對在實施形態中採用的ISB構造相關進行說明。 φ ISB(Integrated System in Board ;註冊商標），是根據本申 請案所開發之原創封裝件。ISB係以半導體裸晶片為中心 之電子電路封裝件，而不使用到含有以銅製作之線路型樣 並用來支撐電路零件的核心（基材）的原創無核心 系統級封 裝件（coreless system in package) 〇 第2圖係表示ISB之一範例的概要結構圖。於此，為了 容易知道ISB的全體構造，而僅顯示單一線路層，然而實 際上係由複數之線路層形成層疊構造。在該ISB中，lsi 裸晶片201、Tr裸晶片202以及晶片CR 203形成藉由以銅型 11 315641D01 1326910 -構成之線路進行接線的構造。在LSI裸晶片2〇1中， ，猎由鋅接（bonding)金線204而導通引屮當搞劣碎 裸晶片2〇1的正下方，咬置有出電極和線路。在⑽ 卜万°又置有導電膏206,並透過該導電春 =安裝於印刷線路基板上。而⑽全體則藉由以環氧； 月曰專構成的樹脂封裝體2〇7進行密封。 .若藉由此封裝，則能得到以下的優點。 (i) 因為月5 益·核心；隹；^ An壯 fAjj 曰 曰 曰 2002 2002 -1 -1 -1 2002 2002 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 315 欲 欲 欲 欲 欲 欲 欲The bonding is very important. In particular, the semiconductor module described later does not have a supporting substrate, so the requirements for the tight bonding of the sub-surface are very strict. The tree is developed by the above-mentioned problem, and its purpose is to be half-r 2 ―' In the mold assembly, the insulating substrate and the encapsulating resin of the semiconductor element or the bonding material between the materials are formed on the insulating substrate. The semiconductor module of the present invention has the following features: an insulating substrate including a circuit is formed. έ έ έ ¥ ¥ ¥ ¥ ¥ ¥ ¥ 底 底 底 底 底 底 底 底 底 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体In the formation of minute protrusion resistance, the semiconductor element includes a semiconductor wafer, a wafer, a chip, and a chip conductor. Since the module has a small group of 4 on the surface of the insulating substrate of the insulating substrate, the bonding property between the insulating substrate and the insulator becomes good. Further, the insulator may be a sealable semiconductor element, and a bonding material interposed between the semiconductor element and the insulating substrate: * In addition, on the surface of the insulating substrate of the insulating substrate, a plurality of craters are also formed. The recess is in the fire, and the fire is below the cu coffee and below the lum. The diameter of the mountain pass can also be 315641D0] 7 1326910 # The mouth is formed by forming a small protrusion group on the surface of the insulating substrate of the insulating substrate, and forming a diameter of 〇·1 μπι or more, 1 μπι. The following volcanic mouth-like tight bondability becomes good. The interface between the substrate and the insulator is read and read. t contains an average diameter of 1 to 2. The complex XV 2 ” density of nm is preferably .5×103 -·2 or more, more preferably 〇·8 2〇二Γ—2 coffee 2. Especially 5 is best 1.6xH), m-2 to the surface The X tightness "by this" can significantly improve the tight bond between the insulating substrate and the interface of the insulator. The other + conductor module of the guide is characterized in that: a % edge substrate provided with ..., a semiconductor element formed on the (10) substrate is connected to the insulating substrate and an insulator of the semiconductor element In the surface of the insulator connected by the edge substrate, the insulating substrate is made of a resin material, and in the line photoelectron spectroscopy (SPeCt_) near the surface, when the detection energy of the detachable energy ship 5eV is to be bound When the detection strength of the binding strength -286 eV is taken as the sum, the force value is 0.4 or more. Here, the binding energy -286 eV belongs to the structure (:=〇 combined as electron. On the other hand, the binding energy _284 5 6乂 belongs to the structure c-〇 bond or n-bonded Cls electron, and these ratios satisfy the above conditions. The cover can be clearly modified = the tightness of the interface between the insulating substrate and the insulator. Further, the upper limit of the value of ye is set to, for example, 3 or less. Further semiconductor module of the present invention is characterized in that it includes a conductor circuit. An insulating substrate, a semiconductor element formed on the insulating substrate, 315641D01 8 1326910, and an insulator connecting the insulating substrate and the ** ^ 兀 ;; and the connection of the 基材 基材 substrate to the insulator The area and the antennae are 30 degrees to 12Q& The heart is connected to pure water by using a resin material having such a contact angle, and the interface between the insulating substrate and the insulator can be tightly combined. The module can be obtained, for example, by plasma treatment without applying (4). 又In accordance with the invention, the semiconductor module is characterized by: insulation of the package conductor circuit a material "a half body element formed on the insulating substrate" and an insulator connecting the insulating substrate and the semiconductor element; and the insulating substrate is a photocurable property containing a polyfunctional oxycyclobutane compound resin compound Thermosetting resin. The insulating base material of the semiconductor module of the present invention has a photocurable thermosetting 2 resin containing a polyfunctional oxycyclobutane compound or an epoxy resin compound, and can be patterned. At the same time, the tight bonding of the interface between the insulating substrate and the insulator can be remarkably improved. 13 Another semiconductor module according to the present invention is characterized in that: a substrate comprising a substrate and a component formed on the substrate And an insulator that connects the substrate and the component; and forms a minute protrusion group on the surface of the connection insulator of the substrate. The module is formed on the substrate and the insulator by forming a minute protrusion group on the surface of the connection insulator of the substrate The tight bond of the interface becomes good. 315641D01 9 1326910 ' In addition, a complex number of fires can be formed on the surface of the bonded insulator of the substrate. a cavity-shaped recess, and the micro-protrusion group may also include a plurality of protrusions having an average thickness of from nm to 20 nm. Further, the method for fabricating the semiconductor module of the present invention is a method for fabricating the above-described f-conductor module, and its characteristics a step of performing a plasma treatment on a surface of an insulating substrate on which a conductor circuit is formed, and a step of forming a semiconductor element and an insulator connecting the semiconductor element on the insulating substrate; and applying the substrate Bias 〒, the plasma treatment is carried out with a plasma gas containing an inert gas (inert gas). By performing the plasma treatment as described above, the interface between the insulating substrate and the insulator can be stably obtained. Excellent tightly integrated semiconductor modules. Further, the "bias" does not include the bias of the substrate itself. Furthermore, the method for manufacturing a module of the present invention is a method for fabricating the above-described module, which comprises the steps of performing a plasma treatment on the surface of the substrate and forming a member and a connecting member on the substrate. The step of the insulator. And under the application of the county plate (4), the gas of the ship bell is used for the plasma treatment. 7" Hunting is performed by the above-mentioned electropolymerization process, and it is possible to stably obtain a semiconductor module having excellent close bonding to the interface between the substrate and the insulator. Also, the so-called "bias" does not include the bias of the substrate itself. Pressure. In the present invention, it is particularly effective when the semiconductor element is a bare chip and the insulating system is composed of a sealed bare crystalline seal. In the case of adopting the related structure, it is possible to solve such a problem by thinning and achieving a lightweight package 315641D01 10 good:=:: fruit:: base, there is a tight bond between the encapsulating resins. . # * The conductor circuit is a circuit formed inside the substrate or based on a steel line or the like. The so-called insulating substrate, the insulating substrate of the conductor circuit and the conductor circuit connected thereto, and the like is, for example, a half-body 2-in-light package which is set on the insulating substrate. A resin or an insulating layer or a bonding member disposed between the insulating substrate and the semiconductor element. & January effect According to the present invention, in terms of a module such as a semiconductor module, the adhesion between the insulator formed on the insulating base material and the sealing resin of the semiconductor element can be improved. [Embodiment] Hereinafter, embodiments of the present invention will be described. However, in the description, the relevant ISB structure used in the embodiment will be described. φ ISB (Integrated System in Board; registered trademark) is an original package developed according to this application. ISB is an electronic circuit package centered on a semiconductor bare die, without using an original coreless system in package containing a copper-made line pattern and a core (substrate) for supporting circuit parts (coreless system in package) ) Figure 2 shows a schematic block diagram of an example of an ISB. Here, in order to easily recognize the entire structure of the ISB, only a single wiring layer is displayed. However, in actuality, a plurality of wiring layers are formed in a laminated structure. In the ISB, the lsi bare wafer 201, the Tr bare wafer 202, and the wafer CR 203 are formed by wiring in a line formed of copper type 11 315641D01 1326910 -. In the LSI bare wafer 2〇1, the hunting is performed by bonding the gold wire 204 and turning on the lead. Immediately below the bare chip 2〇1, the electrode and the line are bitten. A conductive paste 206 is placed on (10) Buwan, and is mounted on the printed circuit board through the conductive spring. On the other hand, (10) is sealed by a resin package 2〇7 composed of an epoxy resin; With this package, the following advantages can be obtained. (i) Because of the month 5 benefits · core; 隹; ^ An strong f
…、 進订，、且裝，而可貫現電晶體、IC、LST 的小型.薄型化。 (U)二111成及封裝由電晶體到系統LSI，還有晶片形式 (sip :益以及電阻’而能實現高度化系統級封裝件 (⑽，System in Package)。 (iii)因為可組合現有的本道辨-y4_ 即可開發出 體疋件，使系統⑶在短期間 (v)=將半導體裸晶片直接裝在正下方的銅材上，而能 传到良好的散熱性。 沒有電路線路係銅材之核心材，而具有低介電係 厂的電路線路’在快速資料傳送以及高頻電路上可 發揮優越的特性。 ㈤=電極係為在封裝件内部的埋人構造，故可抑制電 料之微粒污染（Particle contamination)的發生。 封裝尺寸沒有限制（free)，而因為將相當於㈣封裝件 ^廢料與64腳(pin)2SQFp封裝件比較，僅有約则的 里，因此能降低環境的負擔。 315641D01 12 1326910 * (viii)從搭載零件的印刷電路基板，到置入機能的電路基板 _ 中’都能實現新的概念的系統結構。 (ix) ISB的型樣設計如同印刷電路基板之型樣設計般容 易，製造商的工程師也可以自行設計。 其次對關於ISB之製造流程上的優點進行說明。第3圖 係為習知之csp以及有關本發明之ISB製造流程的對照 圖。第3(B)圖係表示習知之CSP的製造流程。首先在基底 基板上形成框架（frame)，在由各框架所劃分之元件形成區 域上安裝晶片。之後，在各元件上藉由熱硬化性樹脂設置 封裝體。之後，在每個元件上利用模具進行衝壓。在最後 步驟的衝壓中，因為模製樹脂以及基底基板同時被切斷， 而產生切斷面之表面龜裂等問題。此外因為衝壓結束之後 大1產生廢料，而有環境負擔的問題。 另方面，第3(A)圖係表示ISB的製造流程圖。首先， 在金屬落上設置框架，在各模組形成區域上，形成線路型 拳樣’並於其上搭載LSI等電路元件。其次在每個模組上施 =封裝，沿著刮割（scribe)區域進行切塊（dicing)工程以 仔到產…。封裴結束後，在到割步驟前，因為先除去做為 f底的金屬治’所以在刮割步驟的切塊工程中，只有對樹 曰進行切斷。因此，得以抑制切斷面的龜裂，並使切塊 的正確性提高。 以下，有關本發明的較佳實施形態，將以具有前述mb 每的半‘體杈組當作例子進行說明。第4圖係有關本實 315641D01 1326910 *施形態的半導體模組的斷面構造的表示圖。該半導體模組 •係由，將由線路407所構成的線路層以複數層層疊後於最 上層形成抗銲層（s〇lder resist)408之多層線路構造體，以及 在其表面所形成之元件410a以及41〇b所構成。其中，該線 路層係由層間絕緣膜405以及銅所構成。在多層線路構造 體的背面，設置有銲錫球420。元件41〇a以及41〇b係為以 模製樹脂415所封模的構造體。在第4(b)圖中，相對於第4(幻 鲁圖的構造，更進一步設置了由金屬材料構成的假（d·㈣ 線路435。由此，可提高多層線路構造體和模製樹脂415之 間的緊密結合性。 有關元件41〇a的組裝方法中，雖然在第4圖中採用了銲 線銲接方式（wire bonding)，然而也可如第10圖所示把元件 41〇a以面朝下（face d〇wn)配置之方式進行覆晶式chip) 組裝。 在如第1圖所示之習知半導體模組中，LSI晶片1〇2具有 •藉由封袁樹脂密封裸晶片之晶片構造。相對於此，在第4 圖的半導體模組中，元件410係具有沒有藉由封裝樹脂封 裝的裸晶片。為此’必須更加確實地實行吸濕對策。在模 製樹脂415和多層線路構造之間的界面若產生剝離，則例 如在銲錫步驟中，水分會由該處浸入，使裸晶片直接受到 水分的影響。在此情況，會造成晶片之性能大幅度損害的 結果。由此，在如第4圖所示之ISB構造的半導體模組中， 如何改善該界面的緊密結合性而充分抑制水分的透過係 已成為重要的技術課題。 315641D01 14 U26910 為了解決這樣的課題，在本實施形態中，藉由選擇預 疋ir、件之電漿處理，對抗銲層4〇8的表面進行改質。具體而 言，係在抗銲層408之與模製樹脂415連接側的表面上，形 成微小突起群。此外，在抗銲層4〇8的上述表面上，當將束 4月b -284.5 eV的檢測強度當作x，將束縛能_286 eV的檢測 強度當作3^時，使X線光電子分光分析光譜之y/x之值於〇4 以上。 還有，使抗銲層408之連接模製樹脂415的區域在 ¥ ’對純水的接觸角係於3〇至12〇度範圍内。 可各自獨立選擇樹脂材料作為構成抗銲層4〇8、層間絕 緣膜405以及模製樹脂415的材料，例如，可列出bt樹脂 (Resin)等之三聚氰胺（melamine)衍生物、液晶聚合物 加如⑺、環氧樹月旨、PPE樹脂、聚醯亞胺（p〇iyimide)樹 脂、氟樹脂、酚（phenol)樹脂、聚醯胺雙馬來醯亞胺 (polyamide bismaleimide)等之熱硬化性樹脂。其中，較宜 1使用在高頻特性方面較卓越的液晶聚合物、環氧樹脂、BT 樹脂等之三聚氰胺誘導體。除了這些樹脂，也 加填充物（filler)或添加劑。 '另外，宜使用環氧樹月旨、Βτ樹脂、液晶聚合物等作為 構成本發明之絕緣基材的材料。藉由使料樣的樹脂，可 得到具有卓越之高㈣性以及產品可靠性的半導體模組。 办其次，關於如第4⑷圖所示之半導體模、组的製造方 將麥照第5至7圖進行說明。首先，如第 400之箱在金屬落 之預疋表面上選擇形成導電被覆膜402。具體而言，以 315641D01 15 1326910 .光阻（沖0比resist)401覆蓋金屬羯4〇〇之後，藉由電場電鍍 -法，在金屬箔4〇〇的露出面上形成導電被覆膜4〇2。將導電 ，覆膜402的膜厚形成為例如1至1〇 μπι的程度。由於該導 電破覆膜402最終成為半導體模組的背面電極，所以較宜使 用與銲錫等銲料之接著性良好的金或銀形成。 其次，如第5(B)圖所示，在金屬箔4〇〇上，形成第一層 的線路型樣（pattern)。首先對金屬箱4 〇 〇進行化學研磨以^ 籲行表面清潔和表面粗化。其次，在金屬箱4〇〇上以埶硬化性 =脂覆蓋導電被覆膜402之全面，對其加熱硬化使其成為呈 有平坦表面的膜體。其次，在該膜中，形成到達導電被覆 = 402之直輕_左右的通孔（仏h〇le)例。有關設置通孔 的方法在本貝施形態中係以雷射加工進行，然而除此 之外’也可使用機械加工、藉由藥液之化學钱刻加工、使 =電漿的乾蝕刻法等。之後’以雷射照射除去蝕刻殘渣之 以填埋通孔4〇4之方式在全面上形成銅電鍍層。之後， 鲁2阻作為遮罩（maSk)錢刻銅電鐘層，而形成由銅構成 的線路407。例如，可在從光阻露出的部位上，嘴灑化學飯 刻液，將不需要的銅箱餘刻除去，而形成線路型樣。 如以上所述，藉由反覆進行層間絕緣臈405的形成、通 孔形成:銅電錢層的形成以及銅電鐘層之型樣化之步驟， 二圖所示’由線路4°7以及層間絕緣膜405構成 之線路層層豐而形成多層線路構造。 其次，如第6(A)圖所示，在形成抗銲層4⑽之 雷射加工在抗銲層彻中形成接觸孔—__421。其 315641D01 16 1326910 I構可有/太絲之環氧樹脂系絕緣膜作為抗詳層4 0 8 二=料在本貫施形態中係藉由雷射加工進行，然而 ?機械加工、藉由藥液之化學姓刻加工、 二，藉由電漿照射除去做蝕刻殘清。在本 中，係使用由氬以及氧構成的電襞氣體進行該電 為形成具有前述形態（morphol〇gy)以及樹脂特性的表 :層：：按照所使用的樹脂材料適宜地設定電漿照射條 件。還有’較宜不對基板施加偏壓。例如可用如 件進行。 ^ 偏塵：無施加 電衆氣體：氬10至20sccm，氧〇至1〇sccm 藉由該電衆照射，除了除去線路4〇7表面㈣刻殘清 外，也對抗銲層408的表面進行改質，而形成具有前述形 態以及樹脂特性之表面層。 其次如第6(B)圖所示’在抗銲層術上搭載元件他、 410b。有關元件410，可採用電晶體、二極體、1(：晶片等半 導體元件，或晶片電容、晶片電阻等被動元件。=有，也 可安裝CSI-BGA等面朝下的半導體元件。在第6(b)圖的 構造中，元件410a是未封著之裸半導體元件（電晶體晶 片），而元件機是晶片電容器。將這些元件固定於抗鮮: 408上。以此狀態再度進行電漿處理。為形成具有前述形: 以及樹脂特性的表面層，而按照所使用的樹脂材料適宜地..., order, and install, but can be small, thin and thin for transistors, ICs, and LSTs. (U) Two 111% and package from transistor to system LSI, as well as wafer form (sip: benefit and resistance ' can achieve highly system-level package ((10), System in Package). (iii) because it can be combined with existing The original method -y4_ can be developed to make the system (3) in a short period of time (v) = directly mount the semiconductor bare wafer directly under the copper material, and can pass good heat dissipation. The core material of copper, and the circuit line with low dielectric system 'excellent in high-speed data transmission and high-frequency circuits. (5) = electrode system is embedded in the package, so it can suppress electricity The occurrence of particulate contamination of the material. The package size is not limited, and because it is equivalent to (4) package ^ scrap and 64 pin 2SQFp package, only about the same, so can be reduced Environmental burden 315641D01 12 1326910 * (viii) A new concept system structure can be realized from the printed circuit board on which the component is mounted to the circuit board in which the function is placed. (ix) The design of the ISB is like a printed circuit. Substrate The design is as easy as the design, and the engineer's engineer can also design it. Secondly, the advantages of the ISB manufacturing process are explained. Figure 3 is a comparison of the conventional csp and the ISB manufacturing process of the present invention. (B) shows a manufacturing flow of a conventional CSP. First, a frame is formed on a base substrate, and a wafer is mounted on a component forming region divided by each frame. Thereafter, a thermosetting resin is used on each component. After the stamping is performed, the stamping is performed on each of the components by the mold. In the stamping of the final step, since the molding resin and the base substrate are simultaneously cut, problems such as surface cracking of the cut surface are caused. After the end, the large 1 produces waste, and there is a problem of environmental burden. On the other hand, the third (A) diagram shows the manufacturing flow chart of the ISB. First, a frame is placed on the metal drop, and a line is formed on each module forming region. The type of boxing 'and the circuit components such as LSI are mounted on it. Secondly, the package is applied to each module, and the dicing process is performed along the scribe area. Production... After the sealing is completed, before the cutting step, because the metal treatment as the bottom of the f is removed first, in the cutting process of the scraping step, only the tree shrew is cut. Therefore, the cutting is suppressed. The surface is cracked and the correctness of the dicing is improved. Hereinafter, in the preferred embodiment of the present invention, a half-body group having the above mb will be described as an example. 315641D01 1326910 A diagram showing a cross-sectional structure of a semiconductor module according to the embodiment. The semiconductor module is formed by laminating a plurality of wiring layers formed by a line 407 and forming a solder resist layer on the uppermost layer. The multilayer circuit structure of 408, and the elements 410a and 41b formed on the surface thereof. Here, the wiring layer is composed of an interlayer insulating film 405 and copper. A solder ball 420 is provided on the back surface of the multilayer wiring structure. The elements 41A and 41B are structural bodies that are molded by the molding resin 415. In the fourth (b) diagram, a dummy (d·(iv) line 435 made of a metal material is further provided with respect to the fourth (the structure of the magic diagram). Thereby, the multilayer wiring structure and the molded resin can be improved. Tight bonding between 415. In the assembly method of the element 41〇a, although wire bonding is employed in Fig. 4, the element 41〇a may be used as shown in Fig. 10. In a conventional semiconductor module as shown in FIG. 1 , the LSI wafer 1 〇 2 has a sealed semiconductor wafer by sealing Yuan resin. In contrast, in the semiconductor module of Fig. 4, the element 410 has a bare wafer which is not encapsulated by a sealing resin. Therefore, it is necessary to more reliably perform moisture absorption measures. In the molding resin 415 and If the interface between the multilayer wiring structures is peeled off, for example, in the soldering step, moisture is immersed therein, and the bare wafer is directly affected by moisture. In this case, the performance of the wafer is greatly impaired. So, in the ISB as shown in Figure 4 In the semiconductor module, how to improve the adhesion of the interface and sufficiently suppress the moisture transmission system has become an important technical issue. 315641D01 14 U26910 In order to solve such a problem, in the present embodiment, by selecting the pre-疋ir The surface of the anti-welding layer 408 is modified on the surface of the solder resist layer 408 which is connected to the molding resin 415. Specifically, in the anti-welding layer 408, the surface of the solder resist layer 408 is formed on the side of the connection side of the mold resin 415. On the above surface of the solder layer 4〇8, when the detection intensity of the beam b b-284.5 eV is regarded as x, and the detection intensity of the binding energy _286 eV is regarded as 3^, the X-ray photoelectron spectroscopic analysis spectrum is The value of /x is 〇4 or more. Further, the area of the solder resist layer 408 to which the mold resin 415 is bonded is in the range of 3 〇 to 12 在 in the contact angle of pure water. As the material constituting the solder resist layer 4〇8, the interlayer insulating film 405, and the mold resin 415, for example, a melamine derivative such as bt resin (Resin), a liquid crystal polymer such as (7), and an epoxy resin may be listed. Shuyue, PPE resin, polyimine (p〇i Yimide) a thermosetting resin such as a resin, a fluororesin, a phenol resin, or a polyamide bismaleimide. Among them, a liquid crystal polymer superior in high frequency characteristics is preferably used. A melamine inducer such as an epoxy resin or a BT resin. A filler or an additive is added in addition to these resins. In addition, an epoxy resin, a ruthenium resin, a liquid crystal polymer or the like is preferably used as the constitution of the present invention. The material of the insulating substrate. By using the resin of the material, a semiconductor module having excellent high (four) properties and product reliability can be obtained. The manufacturer of the semiconductor molds and groups as shown in Fig. 4(4) will be described with reference to Figs. 5 to 7. First, a box of the 400th is selected to form the conductive coating film 402 on the pre-twisted surface of the metal. Specifically, after the metal 羯4〇〇 is covered by the photoresist 315 641 D01 15 1326910. The electric conductive coating film is formed on the exposed surface of the metal foil 4 by the electric field electroplating method. 2. The film thickness of the conductive film 402 is formed to, for example, about 1 to 1 μm. Since the conductive breaker 402 eventually becomes the back surface electrode of the semiconductor module, it is preferably formed of gold or silver having good adhesion to solder such as solder. Next, as shown in Fig. 5(B), a line pattern of the first layer is formed on the metal foil 4?. First, chemically grind the metal box 4 〇 以 to call for surface cleaning and surface roughening. Next, the entire surface of the conductive coating film 402 is covered with a crucible hardening property on the metal case 4, and heat-hardened to form a film body having a flat surface. Next, in the film, an example of a through hole (about 〇h〇le) which reaches the right side of the conductive coating = 402 is formed. The method of setting the through hole is performed by laser processing in the form of the Bebesch, but in addition, it is also possible to use mechanical processing, chemical processing by chemical liquid, dry etching of plasma, etc. . Thereafter, the copper plating layer is formed over the entire surface by removing the etching residue by laser irradiation to fill the via holes 4〇4. Thereafter, Lu 2 is used as a mask (maSk) to engrave the copper clock layer, and a line 407 composed of copper is formed. For example, the chemical rice can be sprinkled over the exposed portion of the photoresist, and the unnecessary copper box can be removed to form a line pattern. As described above, the formation of the interlayer insulating crucible 405 and the formation of the via holes are repeated: the formation of the copper electric money layer and the formation of the copper electric clock layer, as shown in the second figure by the line 4° 7 and the interlayer The wiring layer formed by the insulating film 405 is abundance and forms a multilayer wiring structure. Next, as shown in Fig. 6(A), the laser processing for forming the solder resist layer 4 (10) forms a contact hole - __421 in the solder resist layer. The 315641D01 16 1326910 I structure can have a / epoxy resin-based insulating film as the anti-detail layer 4 0 8 2 = material in the present embodiment by laser processing, however, mechanical processing, by medicine The chemical chemistry of the liquid is processed by the surname, and the etching residue is removed by plasma irradiation. In the present embodiment, the electricity is formed by using an electric argon gas composed of argon and oxygen to form a surface having the above-described morphology and resin properties. Layer:: Plasma irradiation conditions are appropriately set in accordance with the resin material to be used. . Also, it is preferable not to apply a bias to the substrate. For example, it can be done as a piece. ^ Dust: no gas applied: argon 10 to 20 sccm, oxygen enthalpy to 1 〇 sccm. By the electric field illumination, in addition to removing the surface of the line 4〇7 (4), the surface of the anti-welding layer 408 is also modified. The surface layer having the above-described morphology and resin properties is formed. Next, as shown in Fig. 6(B), the component, 410b, is mounted on the solder resist layer. The element 410 may be a transistor, a diode, a semiconductor device such as a wafer, or a passive device such as a chip capacitor or a chip resistor. = Yes, a face-down semiconductor device such as a CSI-BGA may be mounted. In the construction of Fig. 6(b), the element 410a is an unsealed bare semiconductor element (transistor wafer), and the component machine is a wafer capacitor. These elements are fixed on the anti-fresh: 408. The plasma is again re-pulled in this state. To form a surface layer having the foregoing shape and resin characteristics, suitably in accordance with the resin material used
315641D0I 17 丄丄u =電，Kh射條件。還有，較宜*對基板施加偏Μ 可用如以下的條件進行。 偏壓：無施加 ftAH： & 10^20 sccm 〇^1〇sccm 藉由該電水π、射’除了可除去線路術表面的姓刻殘澄 來能也可層彻的表面進行改質，而形成具有前述 _> L以及樹脂特性的表面層。 蛊之後’透過經形成之通孔，藉由線路407以及金線412 ^接讀41如之後，以模製樹脂（m〇lding resin)4丨5對這些315641D0I 17 丄丄u = electric, Kh shooting condition. Further, it is preferable to apply a bias to the substrate by the following conditions. Bias: no application of ftAH: & 10^20 sccm 〇^1〇sccm With the electro-hydraulic π, shot 'except for the surname of the surface of the circuit that can be removed, the surface can be modified. On the other hand, a surface layer having the aforementioned _> L and resin characteristics was formed. After 蛊, through the formed via, the line 407 and the gold line 412 ^ are read 41, and then, by molding the resin (m〇lding resin) 4丨5 pairs of these
St:封裝。第7(A)圖表示被封裝後的情況。半導體元 ^ 對設置於金射 1彻上之複數個模組，用模呈 ^進行。該步驟可藉由轉移成模⑽_ 射出、 ⑽聰则⑷1埋法（帅㈣或浸潰法（diPping) :現。在樹脂材料中，環氧樹脂等熱硬化性樹脂可用在 ==或膠埋法中實行’而聚酿亞胺樹脂等熱塑性樹脂 則可在射出成型中實行。 彻7議所示，從多層線路構造除去金屬落 I : 上形成銲錫球42〇〇其中，可藉由拋光 '研 nl Λ射之金屬蒸發等進行金屬落400的除去。在本 將：屬知用以下的方法。亦即，藉由拋光裝置或研磨 :=r刻除去。還有，也可以藉由-刻除』 藉由透航樣的㈣，在搭載半導體元件側之 對向側的表面上，使第1層線路術的背面露出。據此，由 315641D01 18 1326910 本貫施形態得到之模組的背面可變得平坦，而可具有此製 私上的優點·在安裝半導體模組時，能藉由鲜錫等表面張 而X平矛夕動’而容易進行自對準（self_aHgn)等。其次， =路出之‘電被覆膜4G2上被覆固著銲錫等導電材，並形成 :錫球420 ’而完成半導體模组。之後，藉由切塊製程切斷 姑圓（wafer) ’而可得到半導體模組晶片。直到上述之金屬 = 400之除去步驟為止，係將金屬㈣q當作支樓基板。在 作^4()7$成％的電解電鏡步驟中，也可利用金屬落400當 、極此外，當使模製樹脂415成模 之料、模具U⑽純㈣良好。進行如以=具 而可传到如第4(A)圖所示之構造的半導體模板。 彻^半^!莫組，在第6⑻圖之步驟中，因為對抗銲層 和模制H化處理’而進打表面改質的關係’使抗輝層408 果’、衣、曰之間的界面緊密結合性明顯地改善。其結 ，可使半導體模組的可靠性明顯提高。 也可㈣含有多官能氧環丁燒化合 月曰化合物的光硬化性·埶硬化 飞衣氧树 的材料。，作為構成抗銲層408 火山二==了微小突起’還可在表面形成複數 狀凹。卩，而可更加改善緊密結合性。 至於抗銲層408的表面是否存在 層408,使用掃y刑雷：&* 隹凹凸狀，可斜切斷抗銲 此外鏡觀察等分析其斷面而確切。 樹腊化封裝的部份之表面是否有 ，有藉由輪製 描型電子顯微鏡觀察等進行該表面之分析而確=能使用掃St: Package. Fig. 7(A) shows the case after being packaged. The semiconductor element ^ is performed on a plurality of modules set on the gold shot 1 by using the mold. This step can be carried out by transferring to mold (10)_, (10) Cong (4) 1 buried method (handsome (four) or dipping method (diPping): now. In resin materials, epoxy resin and other thermosetting resin can be used in == or glued The method is carried out in the process, and a thermoplastic resin such as a polyurethane resin can be used in injection molding. As shown in the discussion, the metal drop is removed from the multilayer wiring structure: a solder ball 42 is formed thereon, which can be polished by The metal drop 400 is removed by evaporating the metal of the nl ray, etc. In the present invention, the following method is known: that is, it is removed by a polishing apparatus or polishing: = r. In addition, the back surface of the first layer of the circuit is exposed on the surface on the opposite side of the semiconductor element side by the (4) of the air-permeable sample. Accordingly, the back surface of the module obtained by the present embodiment is 315641D01 18 1326910. It can be made flat, and it can have the advantage of this system. When mounting a semiconductor module, it is easy to perform self-alignment (self_aHgn) by a surface of a bright tin or the like. =The electric coating of the electric coating 4G2 is covered with a conductive material such as solder. And forming a solder ball 420' to complete the semiconductor module. Thereafter, the semiconductor module wafer is obtained by cutting the wafer ' by a dicing process. Until the metal=400 removal step, the metal is removed. (4) q is used as the base plate of the branch. In the step of electrolyzing electron microscopy of 4% to 4%, it is also possible to use the metal to be 400, and in addition, when the molding resin 415 is molded, the mold U(10) is pure (four) good. The semiconductor template can be transferred to the structure as shown in Fig. 4(A) as in the case of Fig. 4(A). In the step of Fig. 6(8), because of the anti-welding layer and the molding H The relationship between the treatment and the surface modification improves the tightness of the interface between the anti-glaze layer 408, the clothing and the crucible. The junction can significantly improve the reliability of the semiconductor module. A material containing a photocurable ruthenium-cured fly ash tree containing a polyfunctional oxycyclobutane compounded ruthenium compound. As a solder resist layer 408, a volcano 2 = a microprotrusion can be formed on the surface. , and the tight bonding can be further improved. As to whether the surface of the solder resist layer 408 is There is a layer 408, which uses a sweeping y-throat: &* 隹 embossed, can be obliquely cut and welded, and the cross-section of the mirror is analyzed to determine the cross-section and the exact surface. Whether the surface of the waxed package is present, there is a wheel The observation of the surface is performed by a scanning electron microscope observation, etc.
31564ID0J 19 1326910 i二實施形熊 '在第一貫施开》態中，具有在抗銲層4〇8上由銲錫固定元 件410a、元件4l〇b的結構，然而若不利用銲錫，也能以接 著劑等固著元件。在該情況下，也可形成沒有設置抗焊層 408的構造。 第9圖係表示沒有抗銲層時，直接將元件接著於線路上 的結構。多層線路構造係具有於第一實施形態中所說明者 之相同構造。在本實施形態中，係使用環氧樹脂作為層間 胃絕緣膜405。 該半導體模組可如以下所述般進行製造。首先進行到 第5(C)圖為止的步驟。隨後，如第8圖般藉由接著劑而固著 元件410a、元件410b。在該狀態下對元件形成面進行電漿 處理。電衆處理係以第-實施形態之同樣方式進行。藉由 該電漿照射’使線路術的表面具有清潔的狀態，而使元件 41〇^、元件410b以及線路4〇7間可具有良好的接線。此外， φ此時並藉由電漿處理而同時對層間絕緣膜4〇5的表面進行 改質，而形成具有前述之形態以及樹脂特性的表面層。 之後，藉由線路407和金線412對元件4i〇a進行接線之 後’以模製樹脂415對這些結構進行封模。根據以上之步驟 而可得到如第9圖所示之構造的半導體模組。該半導體模組 在第8圖的步驟中，因為對層間絕緣磨4〇5進行氯電黎處 理，而進行表面改質的關係，使層間絕緣膜4〇5和模製樹脂 415之間的界面緊密結合性明顯改善。該結果可使半導體模 組的可靠性明顯提高。· 、 315641D01 20 1326910 =此，也可以用含有多官能氧環丁烷化合 月曰化5物的光硬化性.熱硬化性樹脂， 門= 磨請的材料。藉此，因為除了微小突起，還== 成稷數火山口狀凹部’而可更加改善緊密結合性。、/ 此外’可斜切斷層間絕緣膜層彻後，使用婦描型 顯微鏡觀察等分析其斷面而進行在絕緣膜層他的表面θ 否有凹凸狀存在之確認。 疋 此外，例如，在如絕緣膜層405端部等部位沒有 ^樹脂415封裝的部份之表面是否有凹凸狀存在，也能使用 掃描型電子顯微鏡觀察等進行該表面之分析而確認。 I三實施形能 一在本貫施形態中，如第15圖所示，透過接著材料51〇 將元件502接著於基板5〇6上。 據此，在元件502和基板506間界面之緊密結合性不佳 的話，會有從該地方發生元件502剝離的疑慮，而造成半導 _體模組之可靠性大幅度損害的結杲。 為了解決這樣的課題，在本實施形態中，藉由選擇和 第貫施形態以及第二實施型態相同的條件之電漿處理， 而對連接接著材料510之基板506的表面進行改質。其中， 該接著材料510係連接元件502的下表面。具體而言，係.在 基板506具有線路層的表面上，形成微小突起群和，例如， 直徑100 nm以上之複數火山口狀凹部。此外，在基板5〇2 之上述表面上，當將束縛能-284.5 eV的檢測強度當作x， 315641D01 21 1326910 -將束縛旎-286 eV的檢測強度當作7時，係使χ線光電子分光 -分析光譜之y/χ之值於〇.4以上。 士還有，在露出基板506之與模製樹脂415連接的區域 打，其對純水的接觸角係在3〇至12〇度的範圍内。 在每裡，也可以用含有多官能氧環丁烷化合物或環氧 化合，的光硬化性.熱硬化性樹月旨作為構成基板506的材 料藉此，因為除了微小突起外，還在表面形成複數之火 _山口狀凹部，而可改善緊密結合性。 此外，可斜切斷基板506後，藉由使用掃描型電子顯微 鏡觀察等分析其斷面而進行在基板5〇6的表面是 狀存在之確認。 ^此外，例如，在如基板506端部等部位沒有藉由模製樹 =5封裝的部份之表面是否有凹凸狀存在，也能藉由使用 掃描型電子顯微鏡觀察等進行該表面之分析而確認。 以上說明了適合本發明之實施形態。但是，本發明非 籲僅限2上述之實施形態，本業者在本發明的範圍内當然 也了貝行上述之實施形態的變型。 、—例如，有關上述之實施形態中，係對半導體模組相j 進行說明，然而本發明也可適用於半㈣模組以外的模组 此外，有關上述之實施形態中，係對採用設置有線石 *的抗I干層4〇8之形態進行說明，然而，也可以採用例」 有導線架（lead frame)等之線路4〇7以外之導電體的4 315641D01 22 1326910 .此外，有關上述之實施形態中，係針對使用抗銲層408 . 為絕緣基材的形態進行說明，然而也可以使用絕緣基材以 外的基材。 實施例 實施例1 在銅箔表面貼上乾抗#膜（dry film resist)(商品名 PDF300，新日鐵.彳h聲钍盤Μ之德，對該抗.蝕膜進扞刑楛化， 而露出銅箔表面之一部份。在該狀態下，對含銅箔露出面 •以及乾抗蝕膜面之全面進行氬電漿處理。其中，改變電漿 氣體裏面的氧濃度而製造出2種類的樣品。 偏壓電壓：無施加 電漿氣體：樣品1 氬10 seem，氧0 seem 樣品 2 氬 10 seem，氧 10 seem RF功率（W) : 500 壓力（Pa) : 20 鲁處理時間（sec) : 20 藉由掃描型電子顯微鏡，而對電漿照射前後的乾抗蝕 膜表面進行了觀察。結果如第11圖、第12圖以及第13圖所 示。第11圖表示樣品1、第12圖表示樣品2、第13圖表示未 電漿處理之外觀。可清楚地瞭解，藉由電漿照射可在樹脂 表面形成複數之微小突起。使用藉由掃描型電子顯微鏡觀 察所得到的晝像資料，對微小突起的平均直徑以及密度進 行測定。密度係對長度1 μιη之直線上之微小突起數量（線密 23 315641D01 1326910 .度）進行測定，並將該數量乘以2後而求得。將結果於以下 . 表示。 樣品1 平均直徑4 nm 數量密度1.2xl〇3個/gm2 樣品2 平均直徑4 nm 數量密度1·6χ1〇3個/μπι231564ID0J 19 1326910 The second embodiment of the shape of the bear 'in the first open state" has a structure of fixing the element 410a and the element 4l〇b on the solder resist layer 4〇8, but if the solder is not used, The component is fixed by a subsequent agent or the like. In this case, a configuration in which the solder resist layer 408 is not provided can also be formed. Fig. 9 is a view showing the structure in which the element is directly attached to the line when there is no solder resist layer. The multilayer wiring structure has the same structure as that described in the first embodiment. In the present embodiment, an epoxy resin is used as the interlayer gastric insulating film 405. The semiconductor module can be fabricated as described below. First, the steps up to the fifth (C) chart are performed. Subsequently, the element 410a and the element 410b are fixed by an adhesive as in Fig. 8. In this state, the element forming surface is subjected to plasma treatment. The electric power treatment is carried out in the same manner as in the first embodiment. By the plasma irradiation, the surface of the circuit is cleaned, and the wiring between the element 41, the element 410b and the line 4〇7 can be made. Further, at this time, φ is simultaneously subjected to plasma treatment to simultaneously modify the surface of the interlayer insulating film 4〇5 to form a surface layer having the above-described form and resin characteristics. Thereafter, the components 4i〇a are wired by the wiring 407 and the gold wire 412, and these structures are sealed by the molding resin 415. According to the above steps, a semiconductor module having the structure shown in Fig. 9 can be obtained. In the step of Fig. 8, the semiconductor module performs the surface modification relationship by performing the chloro-electrical treatment on the interlayer insulating mill 4〇5, so that the interface between the interlayer insulating film 4〇5 and the molding resin 415 is obtained. The tight binding is significantly improved. This result can significantly improve the reliability of the semiconductor module. · 315641D01 20 1326910 = In this case, it is also possible to use a photocurable thermosetting resin containing a polyfunctional oxygen cyclobutane compound, and a door = abrasive material. Thereby, the tight bondability can be further improved because the number of crater-like recesses is reduced in addition to the minute protrusions. In addition, after the layer of the interlayer insulating film is cut obliquely, the cross section of the insulating film layer is analyzed by a woman-like microscope or the like, and the surface θ of the insulating film layer is confirmed to have irregularities. In addition, for example, if the surface of the portion where the resin 415 is not encapsulated is not present in the portion such as the end portion of the insulating film layer 405, it can be confirmed by scanning electron microscopic observation or the like. I. Embodiment 3 In the present embodiment, as shown in Fig. 15, the element 502 is attached to the substrate 5〇6 via the bonding material 51〇. Accordingly, if the interface between the element 502 and the substrate 506 is not tightly bonded, there is a concern that the element 502 is peeled off from the place, and the reliability of the semiconductor module is greatly impaired. In order to solve such a problem, in the present embodiment, the surface of the substrate 506 to which the bonding material 510 is bonded is modified by plasma treatment which is selected under the same conditions as the first embodiment and the second embodiment. Wherein, the bonding material 510 is a lower surface of the connecting member 502. Specifically, on the surface of the substrate 506 having the wiring layer, a minute protrusion group and, for example, a plurality of crater-shaped recesses having a diameter of 100 nm or more are formed. Further, on the above surface of the substrate 5〇2, when the detection intensity of the binding energy of -284.5 eV is regarded as x, 315641D01 21 1326910 - the detection intensity of the bound 旎-286 eV is regarded as 7, the ray line photoelectron is split. - The value of y/χ of the analytical spectrum is above 〇.4. Further, in the region where the exposed substrate 506 is joined to the molding resin 415, the contact angle with respect to the pure water is in the range of 3 Torr to 12 Torr. In each case, a photocurable thermosetting hardening compound containing a polyfunctional oxycyclobutane compound or an epoxidized group can also be used as a material constituting the substrate 506 because, in addition to the minute protrusions, it is formed on the surface. A plurality of fires - a mountain-shaped recess, which improves the tight bond. Further, after the substrate 506 is obliquely cut, the cross section of the substrate 5〇6 is confirmed by analyzing the cross section by scanning electron microscopic observation or the like. Further, for example, if the surface of the portion which is not packaged by the molding tree = 5 is present at the end such as the end portion of the substrate 506, it is possible to perform the analysis of the surface by observation using a scanning electron microscope or the like. confirm. The embodiments that are suitable for the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and it is of course within the scope of the present invention that the above-described embodiments are modified. For example, in the above-described embodiments, the semiconductor module phase j will be described. However, the present invention is also applicable to modules other than the semi-four module, and in the above embodiments, the cable is set to be used. The shape of the anti-I dry layer 4〇8 of the stone* will be described. However, it is also possible to use the example of the electric conductor 4 315641D01 22 1326910 other than the line 4〇7 of the lead frame. In the embodiment, the solder resist layer 408 is used as the insulating base material. However, a substrate other than the insulating base material may be used. EXAMPLES Example 1 A dry film resist was attached to the surface of a copper foil (trade name PDF300, Nippon Steel Co., Ltd.), and the anti-corrosion film was smashed. And exposing a part of the surface of the copper foil. In this state, the argon plasma treatment is performed on the exposed surface of the copper-containing foil and the dry resist film surface, wherein the oxygen concentration in the plasma gas is changed to produce 2 Type of sample Bias voltage: No applied plasma gas: Sample 1 Argon 10 seem, Oxygen 0 seem Sample 2 Argon 10 seem, Oxygen 10 seem RF power (W): 500 Pressure (Pa): 20 Lu processing time (sec ) : 20 The surface of the dry resist film before and after the plasma irradiation was observed by a scanning electron microscope. The results are shown in Fig. 11, Fig. 12, and Fig. 13. Fig. 11 shows sample 1, Figure 12 shows Sample 2 and Figure 13 shows the appearance of the non-plasma treatment. It is clearly understood that a plurality of minute protrusions can be formed on the surface of the resin by plasma irradiation. The image obtained by observation by a scanning electron microscope is used. The data was measured for the average diameter and density of the microprotrusions. The degree of microscopic protrusions on the straight line of length 1 μηη (line density 23 315641D01 1326910 .degree.) was measured and multiplied by 2 to obtain the result. The result is shown below. Sample 1 average diameter 4 nm Quantity density 1.2xl〇3/gm2 Sample 2 Average diameter 4 nm Number density 1·6χ1〇3/μπι2
I 其次，對該樣品1、2相關進行X線光電子分光分析。 將結果表示於第14圖。在圖中，除了樣品丨、2外，也顯示 了氬電漿處理前的曲線以作為參照。可知道藉由電漿照 射在有關286 eV的C=0結合而來的強度增加的同時，有 關284.5 eV之C—〇結合或c—N結合而來的強度反而減 =。把有關284.5 eV的C—0結合或c —N結合而來的強度 •虽作X，把有關286 eV的c=〇結合而來的強度當作丫時，在 有關本實施例之模組之y/χ的數值中，樣品1、2都大約為 0.44。 續之，對該樣品1、2測量接觸角。在抗蝕膜表面上滴 下純水後，以放大鏡觀察水滴形狀並測量其接觸角。該接 觸角之測定係於樣品製作2天後進行。所得到的接觸角數值 係如下所示。據此，可知在採用乾抗姓膜（商品名PDF则， =日鐵化學社製）的樣品卜樣品2中，具有接觸角為3〇至7〇 度之令人滿意的表現。 315641D01 24 1326910 .樣品1 52.0度 . 樣品2 53.6度 於第一實施型態所陳述之製程中，應用與上記樣品1 以及樣品2同樣之成模、電漿處理製程以製造半導體模組。 該半導體模組將樣品1、2的乾抗蝕膜作為抗銲層，並於其 表面搭載有半導體元件。對該半導體模組進行評價後，除 了熱循環（heat cycle)性十分卓越外，於壓力銷（pressure 鲁cooker)試驗也有良好的結果。 實施例2 在銅箔表面上貼上乾抗蝕膜（商品名AUS402，太陽 INK社製）之後，對該抗蝕膜進行型樣化，而露出銅箔表面 之一部份。在該狀態下，對含銅箔露出面以及環氧樹脂系 抗蝕膜面之全面進行氬電漿處理。 此外，於此，上述之乾抗蝕膜（商品名AUS402，太陽 • INK社製）因為係使用含有多官能氧環丁烷化合物或環氧 化合物的光硬化性.熱硬化性樹脂所製造出，而在表面存 在有火山口狀凹部。 偏壓：無施加 電漿氣體：氬10 seem，氧0 seem RF功率（W) : 500 壓力（Pa) : 20 處理時間：樣品3 : 20(sec) 樣品 4 : 60(sec) 25 315641D01 藉由掃榣型電子顯微鏡，對電漿照射前後的乾抗蝕膜 ♦ ^行了觀祭。結果如第16圖、第17圖以及第18圖所 不二第16圖係表示樣品3、第17圖係表示樣品4、第18圖係 表:未電漿處理之外觀。可清楚地瞭解，藉由電裝照射可 在樹脂表面形成複數之微小突起。使用藉由掃描型電子顯 $鏡觀察所得到的畫像資料’對微小突起的平均直徑以及 _ :度進行測定。密度係對長度1 μιη之直線上之微小突起數 里（線岔度）進行測定，並將該數量乘以2後而求得。將結果 於以下表示。 樣品3 平均直徑4 nm 數量密度2xl〇3個/μιη2 樣品4 謇平均直徑4 nm 數量密度2xl〇3個/μιη2 其久’對上述樣品進行X線光電子分光分析。將結果表 示於第19圖。在圖中，係將氬電漿處理前的曲線作為參照 而顯示樣品4的曲線。可知道藉由電漿照射，在有關286 eV 的C=〇結合而來的強度增加的同時，有關284 5 eV之c_〇 結合或C—N結合而來的強度反而減少。把有關284.5 eV的 C—0結合或c — N結合而來的強度當作X，把有關286 e V的 315641D01 26 1326910 〇〇結合而來的強度當 的數值約為〇.4。 '，有關本實施例的模組之y/x '，，貝之’對上34樣品進行接觸 上滴下紬尨，丨v 丄 則。在^几姓膜表面 上滴下、'，屯水後，以放大鏡觀察水滴形狀並測 該接觸角之測定係於樣品製 /、接觸角。 的數值係如下所示。1作2天後進订。所得到的接觸角 樣品3 8 0度 樣品4 1〇5度 於第-貫施型態所陳述之製程中，應用與上述樣品同 樣之成模、電漿處理製程’而製造半導體模組。該半導體 模組將上述樣品的乾抗蝕膜作為抗銲層，並於其表面搭載 有半導體元件。對該半導體模組進行評價後，❺了熱循環 性十分卓越外，於壓力鋼試驗也具有良好的結果。 【圖式簡單說明】 第1圖係為B G A構造的說明圖。 第2圖係為ISB(登錄商標）構造的說明圖。 第3(A)及3(B)圖係為BGA以及ISB(登錄商標）之製造 流程的說明圖。 弟4(a)及4(b)圖係為相關半導體模組之構造的說明 圖。 第5(A)至5(C)圖係為相關半導體模组之製造方法的 說明圖。 第6(A)及6(B)圖係為相關半導體模組之製造方法的 27 315641D01 1326910 • 說明圖。 . 第7(A)及7(B)圖係為相關半導體模組之製造方法 5兄明圖。 、 第8圖係為相關半導體模組之製造方法的說明圖。 第9(A)及9(B)圖係為相關半導體模組之製造方法 說明圖。 、 第10(a)及10(b)圖係為相關半導體模組之構造的 圖。 第11圖係藉由掃瞄型電子顯微鏡觀察電漿處理後之 抗姑膜表面的結果的表示圖。 第12圖係藉由掃瞄型電子顯微鏡觀察電漿處理後之 抗钱膜表面的結果的表示圖。 第13圖係藉由掃瞄型電子顯微鏡觀察電漿處理後之 抗钱膜表面的結果的表示圖。 第14圖係為電漿處理後之抗蝕膜表面之X線光電子 籲分光分析結果的表示圖。 第15圖係為相關半導體模組之構造的說明圖。 第圖係藉由掃瞄型電子顯微鏡觀察電漿處理後之 抗姓膜表面的結果的表示圖。 第17圖係藉由掃瞄型電子顯微鏡觀察電漿處理後之 抗蝕膜表面的結果的表示圖。 第18圖係藉由掃瞄型電子顯微鏡觀察電漿處理後之 抗蝕膜表面的結果的表示圖。 第19圖係為電漿處理後之抗蝕膜表面之X線光電子 28 315641D01 1326910 - 分光分析結果的表示圖。 【主要元件符號說明】 100 球閘陣列封裝（BGA) 102 L SI晶片 104 金屬線 106 環氧基板 108 接著層 110 封裝樹脂 112 鲜錫球 201 LSI裸晶片 202 Tr裸晶片 203 晶片CR 204 金線 205 銅型樣 206 導電膏 207 樹脂封裝體 208 鮮錫球 400 金屬箔 401 光阻 402 導電被覆膜 404 通孑L 405 層間絕緣膜 407 線路 408 抗辉層 410s l, 410b元件 412 金線 415 模製樹脂 420 鮮錫球 421 接觸孔 435 假線路 502 元件 506 基板 510 接著材料 29 315641D01I Next, X-ray photoelectron spectroscopy analysis was performed on the samples 1 and 2. The results are shown in Fig. 14. In the figure, in addition to the samples 丨, 2, the curve before the argon plasma treatment is also shown as a reference. It can be seen that while the intensity of the C = 0 binding of 286 eV is increased by the plasma irradiation, the intensity of the C-〇 combination or the c-N combination of 284.5 eV is decreased. Combining the strength of the C-0 combination or c-N of 284.5 eV. Although X, the strength of the combination of c=〇 of 286 eV is regarded as 丫, in the module of the present embodiment. In the values of y/χ, both samples 1 and 2 were approximately 0.44. Continued, the contact angles were measured for samples 1, 2. After dropping pure water on the surface of the resist film, the shape of the water drop was observed with a magnifying glass and the contact angle was measured. The measurement of the contact angle was carried out 2 days after the preparation of the sample. The values of the contact angles obtained are as follows. According to this, it was found that the sample 2 sample of the dry anti-film (trade name PDF, manufactured by Nippon Steel Chemical Co., Ltd.) had a satisfactory expression of a contact angle of 3 〇 to 7 〇. 315641D01 24 1326910. Sample 1 52.0 degrees. Sample 2 53.6 degrees In the process described in the first embodiment, the same mold and plasma processing procedures as in the above sample 1 and sample 2 were applied to fabricate a semiconductor module. This semiconductor module has a dry resist film of the samples 1 and 2 as a solder resist layer, and a semiconductor element is mounted on the surface thereof. After evaluating the semiconductor module, in addition to the excellent heat cycle, the pressure pin (cooker) test also had good results. Example 2 After a dry resist film (trade name: AUS402, manufactured by Sun Ink Co., Ltd.) was attached to the surface of a copper foil, the resist film was patterned to expose a part of the surface of the copper foil. In this state, argon plasma treatment was performed on the entire surface of the copper-containing foil exposed surface and the epoxy resin resist film surface. In addition, the above-mentioned dry resist film (trade name: AUS402, manufactured by Sun Ink Co., Ltd.) is produced by using a photocurable thermosetting resin containing a polyfunctional oxycyclobutane compound or an epoxy compound. There is a crater-like recess on the surface. Bias: No applied plasma gas: Argon 10 seem, Oxygen 0 seem RF power (W): 500 Pressure (Pa): 20 Processing time: Sample 3: 20 (sec) Sample 4: 60 (sec) 25 315641D01 A broom-type electron microscope was used to observe the dry resist film before and after the plasma irradiation. The results are shown in Fig. 16, Fig. 17, and Fig. 18. Fig. 16 shows the sample 3, and Fig. 17 shows the sample 4 and Fig. 18: the appearance of the non-plasma treatment. It is clearly understood that a plurality of minute protrusions can be formed on the surface of the resin by electro-optic irradiation. The average image diameter and _: degree of the microprotrusions were measured using the image data obtained by observation by a scanning electron microscope. The density is determined by measuring the number of microprotrusions on the straight line of length 1 μιη (line twist) and multiplying the number by two. The results are shown below. Sample 3 Average diameter 4 nm Number density 2xl 〇 3 / μιη2 Sample 4 謇 Average diameter 4 nm Number density 2xl 〇 3 / μιη2 For a long time X-ray photoelectron spectroscopy analysis was performed on the above samples. The results are shown in Fig. 19. In the figure, the curve of the sample 4 is shown by taking the curve before the argon plasma treatment as a reference. It can be seen that by plasma irradiation, while the intensity of C=〇 combined with 286 eV is increased, the intensity of c_〇 binding or C-N bonding of 284 5 eV is reduced. The intensity of the combination of C-0 combination or c-N for 284.5 eV is taken as X, and the strength of 315641D01 26 1326910 有关 for 286 e V is about 〇.4. ', Regarding the y/x ' of the module of the present embodiment, the sputum was dropped on the upper 34 sample, and 丨v 丄 was applied. Drop on the surface of the film, and after drowning, observe the shape of the water droplet with a magnifying glass and measure the contact angle based on the sample preparation/contact angle. The values are as follows. 1 made 2 days later to order. The resulting contact angle sample 3 80 degrees sample 4 1 〇 5 degrees In the process described in the first embodiment, a semiconductor module was fabricated using the same molding and plasma treatment process as the above sample. This semiconductor module has a dry resist film of the above sample as a solder resist layer, and a semiconductor element is mounted on the surface thereof. After evaluating the semiconductor module, the thermal cycle test was excellent, and the pressure steel test also had good results. [Simple description of the drawing] Fig. 1 is an explanatory diagram of the B G A structure. Fig. 2 is an explanatory diagram of an ISB (registered trademark) structure. The 3(A) and 3(B) drawings are explanatory diagrams of the manufacturing flow of the BGA and the ISB (registered trademark). Diagrams 4(a) and 4(b) are diagrams showing the structure of the relevant semiconductor module. The fifth (A) to (c) drawings are explanatory diagrams of the manufacturing method of the related semiconductor module. 6(A) and 6(B) are diagrams of the related semiconductor module manufacturing method. 27 315641D01 1326910 • Explanatory diagram. 7(A) and 7(B) are diagrams of the manufacturing method of the related semiconductor module. Fig. 8 is an explanatory diagram of a method of manufacturing a related semiconductor module. The figures 9(A) and 9(B) are explanatory diagrams of the manufacturing method of the related semiconductor module. Figures 10(a) and 10(b) are diagrams showing the construction of related semiconductor modules. Fig. 11 is a view showing the results of observing the surface of the anti-guar film after the plasma treatment by a scanning electron microscope. Fig. 12 is a view showing the results of observing the surface of the anti-drug film after the plasma treatment by a scanning electron microscope. Fig. 13 is a view showing the result of observing the surface of the anti-drug film after the plasma treatment by a scanning electron microscope. Fig. 14 is a view showing the results of X-ray photoelectron spectroscopy analysis of the surface of the resist film after plasma treatment. Fig. 15 is an explanatory view showing the configuration of a related semiconductor module. The figure is a representation of the results of the anti-surname film surface after plasma treatment by a scanning electron microscope. Fig. 17 is a view showing the result of observing the surface of the resist film after the plasma treatment by a scanning electron microscope. Fig. 18 is a view showing the result of observing the surface of the resist film after the plasma treatment by a scanning electron microscope. Figure 19 is an X-ray photoelectron on the surface of a resist film after plasma treatment. 28 315641D01 1326910 - A representation of the results of spectroscopic analysis. [Main component symbol description] 100 Ball Gate Array Package (BGA) 102 L SI Chip 104 Metal Wire 106 Epoxy Substrate 108 Next Layer 110 Package Resin 112 Fresh Tin Ball 201 LSI Bare Chip 202 Tr Bare Chip 203 Wafer CR 204 Gold Line 205 Copper Type 206 Conductive Paste 207 Resin Packing 208 Fresh Tin Ball 400 Metal Foil 401 Photoresist 402 Conductive Coating Film 404 Passing L 405 Interlayer Insulation Film 407 Line 408 Anti-Glow Layer 410s l, 410b Element 412 Gold Line 415 Molding Resin 420 Fresh Tin Ball 421 Contact Hole 435 Fake Line 502 Element 506 Substrate 510 Next Material 29 315641D01