JP4425072B2 - Circuit device and manufacturing method thereof - Google Patents

Circuit device and manufacturing method thereof Download PDF

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JP4425072B2
JP4425072B2 JP2004191884A JP2004191884A JP4425072B2 JP 4425072 B2 JP4425072 B2 JP 4425072B2 JP 2004191884 A JP2004191884 A JP 2004191884A JP 2004191884 A JP2004191884 A JP 2004191884A JP 4425072 B2 JP4425072 B2 JP 4425072B2
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insulating resin
resin film
film
circuit device
base material
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JP2006013370A (en
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良輔 臼井
秀樹 水原
恭典 井上
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to TW094120741A priority patent/TW200605169A/en
Priority to US11/168,655 priority patent/US8022533B2/en
Priority to CN2008102128216A priority patent/CN101419949B/en
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Description

本発明は、回路装置およびその製造方法に関する。   The present invention relates to a circuit device and a manufacturing method thereof.

携帯電話、ＰＤＡ、ＤＶＣ、ＤＳＣといったポータブルエレクトロニクス機器の高機能化が加速するなか、こうした製品が市場で受け入れられるためには小型・軽量化が必須となっており、その実現のために高集積のシステムＬＳＩが求められている。一方、これらのエレクトロニクス機器に対しては、より使い易く便利なものが求められており、機器に使用されるＬＳＩに対し、高機能化、高性能化が要求されている。このため、ＬＳＩチップの高集積化にともないそのＩ／Ｏ数が増大する一方でパッケージ自体の小型化要求も強く、これらを両立させるために、半導体部品の高密度な基板実装に適合した半導体パッケージの開発が強く求められている。こうした要求に対応するため、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）と呼ばれるパッケージ技術が種々開発されている。   As portable electronics devices such as mobile phones, PDAs, DVCs, and DSCs are accelerating their functions, miniaturization and weight reduction are essential for these products to be accepted in the market. There is a need for a system LSI. On the other hand, these electronic devices are required to be more convenient and convenient, and higher functionality and higher performance are required for LSIs used in the devices. For this reason, as the number of I / Os increases with higher integration of LSI chips, there is a strong demand for miniaturization of the package itself. In order to achieve both, a semiconductor package suitable for high-density board mounting of semiconductor components Development is strongly demanded. In order to meet such demands, various package technologies called CSP (Chip Size Package) have been developed.

こうしたパッケージの例として、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａy）が知られている。ＢＧＡは、パッケージ用基板の上に半導体チップを実装し、それを樹脂モールディングした後、反対側の面に外部端子としてハンダボールをエリア状に形成したものである。ＢＧＡでは、実装エリアが面で達成されるので、パッケージを比較的容易に小型化することができる。また、回路基板側でも狭ピッチ対応とする必要がなく、高精度な実装技術も不要となるので、ＢＧＡを用いると、パッケージコストが多少高い場合でもトータルな実装コストとしては低減することが可能となる。   As an example of such a package, BGA (Ball Grid Array) is known. In the BGA, a semiconductor chip is mounted on a package substrate, resin-molded, and then solder balls are formed in an area as external terminals on the opposite surface. In BGA, since the mounting area is achieved in terms of surface, the package can be reduced in size relatively easily. In addition, it is not necessary to support narrow pitches on the circuit board side, and high-precision mounting technology is not required. Therefore, if BGA is used, the total mounting cost can be reduced even if the package cost is somewhat high. Become.

このようなパッケージにおいて、半導体チップの封止には、たとえばトランスファーモールド、インジェクションモールド、ポッティングまたはディッピング等が用いられている（たとえば、特許文献１参照）。   In such a package, for example, a transfer mold, an injection mold, potting or dipping is used for sealing a semiconductor chip (see, for example, Patent Document 1).

また、さらに高精度、高機能で薄型化されたシステムＬＳＩを実現するために、ベース基板部の上部に、薄膜技術や厚膜技術によって、誘電絶縁層を介してベース基板側から電源あるいは信号の供給を受ける抵抗体部、キャパシタ部あるいはパターン配線部からなる受動素子を含有する層を構成する技術も開示されている（たとえば、特許文献２参照）。   In addition, in order to realize a highly accurate, highly functional and thin system LSI, a thin film technology or a thick film technology is applied to the upper portion of the base substrate portion from the base substrate side via a dielectric insulating layer. A technique for forming a layer containing a passive element including a resistor part, a capacitor part, or a pattern wiring part to be supplied is also disclosed (for example, see Patent Document 2).

また、システムＬＳＩの放熱性を高める試みとして、基板に金属あるいは半導体を用いる技術が開示されている（たとえば、特許文献３参照）。
特開平８−１６２４８６号公報 特開２００２−９４２４７号公報 特開平１０−２２３８３２号公報 Further, as an attempt to increase the heat dissipation of the system LSI, a technique using a metal or a semiconductor for a substrate has been disclosed (for example, see Patent Document 3).
JP-A-8-162486 JP 2002-94247 A Japanese Patent Laid-Open No. 10-223832

しかしながら、特許文献１に開示されるような、これら従来のＣＳＰでは、ポータブルエレクトロニクス機器等において現在望まれている水準の小型化、薄型化、軽量化を実現することは難しかった。また、放熱性の改善にも一定の限界があった。   However, with these conventional CSPs as disclosed in Patent Document 1, it has been difficult to achieve the level of size reduction, thickness reduction, and weight reduction currently desired in portable electronic devices and the like. There was also a certain limit to the improvement of heat dissipation.

また、特許文献２に開示されるような、抵抗体部、キャパシタ部あるいはパターン配線部からなる受動素子を含有する層を構成する技術においては、薄膜または厚膜形成工程として、非常に複雑な工程が用いられており、受動素子の製造コストの面でさらなる改善の余地があった。また、このような複雑な工程において、受動素子の表面を平坦にすることが困難であり、製造安定性の面でもさらなる改善の余地があった。   Further, in the technology for forming a layer containing a passive element composed of a resistor part, a capacitor part, or a pattern wiring part as disclosed in Patent Document 2, a very complicated process as a thin film or thick film forming process Is used, and there is room for further improvement in terms of manufacturing cost of the passive element. Further, in such a complicated process, it is difficult to flatten the surface of the passive element, and there is room for further improvement in terms of manufacturing stability.

また、特許文献３に開示されるような、基板に金属あるいは半導体を用いる場合には、基板と絶縁膜との接着性、密着性が十分でないために、剥離が生じる可能性があり、歩留まりの低下の要因となりうる。さらに、ＩＣチップ等の電子部品を基板に実装する場合に、位置精度が十分でないために、電子部品が所定位置からずれる可能性があり、これも歩留まりの低下の要因となりうる。   In addition, when a metal or a semiconductor is used for the substrate as disclosed in Patent Document 3, the adhesion and adhesion between the substrate and the insulating film are not sufficient, and peeling may occur. It can be a factor of decline. Furthermore, when an electronic component such as an IC chip is mounted on a substrate, the positional accuracy is not sufficient, so that the electronic component may be displaced from a predetermined position, which may be a cause of a decrease in yield.

本発明は上記事情を踏まえてなされたものであり、本発明の目的は、回路装置の放熱性を向上させる技術を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique for improving the heat dissipation of a circuit device.

本発明によれば、金属性の基材と、基材の上に設けられた絶縁樹脂膜と、絶縁樹脂膜に埋め込まれた複数の回路素子と、を備え、基材に、複数の回路素子に対応する複数の溝が形成され、複数の回路素子が、それぞれに対応する溝にはめ込まれていることを特徴とする回路装置が提供される。これによれば、回路素子の位置合わせが容易となり、回路装置製造の歩留まりが向上する。また、溝に回路素子をはめ込むことにより、溝の側壁と回路素子とが接触する領域が生じるため、回路素子から基材への熱伝導経路が増加し、放熱性がより高まる。   According to the present invention, a metallic base material, an insulating resin film provided on the base material, and a plurality of circuit elements embedded in the insulating resin film are provided. Is provided, and a plurality of circuit elements are fitted in the corresponding grooves, thereby providing a circuit device. This facilitates the alignment of the circuit elements and improves the yield of circuit device manufacture. Moreover, since the area | region where the side wall of a groove | channel and a circuit element contact arises by inserting a circuit element in a groove | channel, the heat conduction path | route from a circuit element to a base material increases, and heat dissipation is improved more.

上記構成において、基材と絶縁樹脂膜との間に、接着層が設けられていてもよい。これによれば、基材と絶縁樹脂膜との密着性を向上させることができる。   In the above configuration, an adhesive layer may be provided between the base material and the insulating resin film. According to this, the adhesion between the base material and the insulating resin film can be improved.

上記構成において、基材の表面に絶縁膜が形成されていることが望ましい。絶縁膜としては、金属酸化膜、窒化膜、シリコン酸化膜などを用いることができる。これによれば、基材と回路素子との絶縁耐圧を向上させることができる。   In the above configuration, it is desirable that an insulating film be formed on the surface of the base material. As the insulating film, a metal oxide film, a nitride film, a silicon oxide film, or the like can be used. According to this, the withstand voltage of a base material and a circuit element can be improved.

本発明の回路装置の製造方法は、の表面に複数の回路素子に対応する複数の溝を形成する工程と、前記複数の回路素子を対応する溝にはめ込むとともに、絶縁樹脂膜に埋め込む工程と、前記絶縁樹脂膜を前記基材に接合する工程と、を備えることを特徴とする。これによれば、回路素子の位置合わせが容易に行うことができ、回路装置製造の歩留まりが向上する。また、溝に回路素子をはめ込むことにより、溝の側壁と回路素子とが接触する領域が生じるため、回路素子から基材への熱伝導経路が増加し、放熱性をより高めることができる。   The method for manufacturing a circuit device of the present invention includes a step of forming a plurality of grooves corresponding to a plurality of circuit elements on a surface thereof, a step of fitting the plurality of circuit elements into the corresponding grooves and embedding in an insulating resin film, Bonding the insulating resin film to the base material. According to this, the alignment of the circuit elements can be easily performed, and the yield of circuit device manufacture is improved. Moreover, since the area | region where the side wall of a groove | channel and a circuit element contact arises by inserting a circuit element in a groove | channel, the heat conduction path | route from a circuit element to a base material increases, and it can improve heat dissipation.

以上、本発明の構成について説明したが、これらの構成を任意に組み合わせたものも本発明の態様として有効である。また、本発明の表現を他のカテゴリーに変換したものもまた本発明の態様として有効である。   As mentioned above, although the structure of this invention was demonstrated, what combined these structures arbitrarily is effective as an aspect of this invention. Moreover, what converted the expression of this invention into the other category is also effective as an aspect of this invention.

本発明によれば、回路装置の放熱性を向上させることができる。   According to the present invention, the heat dissipation of the circuit device can be improved.

以下、本発明の実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。なお、本明細書において、「上」方向とは、膜の積層の順番により決まる概念であり、先に積層される膜の側から見て後から積層される膜の存在する方向が上であると規定している。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate. In this specification, the “upward” direction is a concept determined by the order of stacking of films, and the direction in which a film to be stacked later is present is the top as viewed from the side of the film to be stacked first. It stipulates.

図１は、本実施の形態における回路装置に用いられる基材の製造工程を示す断面図である。基材１４０としては、熱膨張係数が0.5〜5.0x10-6/Kの金属と熱伝導率が200〜500W/mKの金属とを組み合わせたクラッド材を用いることができる。熱膨張係数が0.5〜5.0x10-6/Kの金属としては、Ｆｅ、Ｎｉ、Ｃｏの合金が好適であるが、熱膨張係数が上記範囲内であれば、他の金属を含んでもよい。熱伝導率が200〜500W/mKの金属としては、Ａｌ、Ａｕ、Ａｇ、Ｃｕおよびその合金が好適であるが、熱伝導率が上記範囲内であれば、他の金属を含んでもよい。実施の形態では、図１（ａ）に示すように、基材１４０としてインバー合金からなる第２の金属層１５２を両側から銅あるいはアルミニウムで構成された第１の金属層１５０および銅で構成された第３の金属層１５４で挟み込んで圧延することにより得られる３層構造のクラッド材が例示される。クラッド材の各層の膜厚は任意に設定可能であるが、クラッド材を厚板とする場合には、第１の金属層１５０の膜厚を200±100μm、第２の金属層１５２の膜厚を600±150μm、第３の金属層１５４を200±100μmとすることができる。また、クラッド材を薄板とする場合には、第１の金属層１５０の膜厚を70±30μm、第２の金属層１５２の膜厚を100±50μm、第３の金属層１５４を30±20μmとすることができる。これによれば、熱伝導性と低熱膨張性のバランスがとれたクラッド材が得られ、回路装置の放熱性を向上させるとともに、基材１４０の熱による反りを抑制し、後述する絶縁樹脂膜との密着性を向上させることができる。 FIG. 1 is a cross-sectional view showing a manufacturing process of a substrate used in the circuit device according to the present embodiment. As the base material 140, a clad material in which a metal having a thermal expansion coefficient of 0.5 to 5.0 × 10 −6 / K and a metal having a thermal conductivity of 200 to 500 W / mK can be used. As the metal having a thermal expansion coefficient of 0.5 to 5.0 × 10 −6 / K, an alloy of Fe, Ni, and Co is suitable, but other metals may be included as long as the thermal expansion coefficient is within the above range. As the metal having a thermal conductivity of 200 to 500 W / mK, Al, Au, Ag, Cu, and alloys thereof are suitable, but other metals may be included as long as the thermal conductivity is within the above range. In the embodiment, as shown in FIG. 1A, a second metal layer 152 made of an Invar alloy is formed as a base material 140 from both sides by using a first metal layer 150 made of copper or aluminum and copper. Further, a clad material having a three-layer structure obtained by sandwiching and rolling between the third metal layers 154 is exemplified. The thickness of each layer of the clad material can be arbitrarily set. However, when the clad material is a thick plate, the thickness of the first metal layer 150 is 200 ± 100 μm and the thickness of the second metal layer 152 is Can be 600 ± 150 μm, and the third metal layer 154 can be 200 ± 100 μm. When the clad material is a thin plate, the thickness of the first metal layer 150 is 70 ± 30 μm, the thickness of the second metal layer 152 is 100 ± 50 μm, and the third metal layer 154 is 30 ± 20 μm. It can be. According to this, a clad material having a balance between thermal conductivity and low thermal expansion is obtained, improving the heat dissipation of the circuit device, suppressing warpage due to heat of the base material 140, and an insulating resin film described later. It is possible to improve the adhesion.

続いて、回路素子を搭載する領域が開口になるように、第１の金属層１５０の表面にパターニング用レジスト膜（図示せず）を形成する。その後、図１（ａ）に示すように、パターニング用レジスト膜をマスクとして、第１の金属層１５０の表面をエッチングし、回路素子を搭載する領域に溝１５５を形成する。このように、回路素子を搭載する領域に合わせて第１の金属層１５０の表面に溝１５５を形成することにより、基材１４０に回路素子を搭載する際に、溝１５５に回路素子をはめ込むだけで、基材１４０に回路素子を容易かつ正確に載置することができる。回路素子の位置合わせが容易となることで、製造工程の簡略化や、歩留まりの向上が期待される。また、溝１５５に回路素子をはめ込むことにより、溝１５５の側壁と回路素子とが接触する領域が生じるため、回路素子から基材１４０への熱伝導経路が増加し、放熱性をより高めることができる。なお、第１の金属層１５０の表面に形成される溝１５５の深さは、回路素子の位置決めの確実性および放熱性の向上の観点から、20〜200μmが好ましく、50〜100μmがより好ましい。   Subsequently, a patterning resist film (not shown) is formed on the surface of the first metal layer 150 so that the region where the circuit element is mounted becomes an opening. Thereafter, as shown in FIG. 1A, using the patterning resist film as a mask, the surface of the first metal layer 150 is etched to form a groove 155 in the region where the circuit element is mounted. In this way, by forming the groove 155 on the surface of the first metal layer 150 in accordance with the region where the circuit element is mounted, when the circuit element is mounted on the substrate 140, the circuit element is simply fitted into the groove 155. Thus, the circuit element can be easily and accurately placed on the substrate 140. Simplification of the manufacturing process and improvement in yield are expected due to the easy alignment of the circuit elements. Further, by inserting the circuit element into the groove 155, a region where the side wall of the groove 155 and the circuit element are in contact with each other is generated, so that a heat conduction path from the circuit element to the base material 140 is increased, and heat dissipation is further improved. it can. The depth of the groove 155 formed on the surface of the first metal layer 150 is preferably 20 to 200 μm, and more preferably 50 to 100 μm, from the viewpoint of the reliability of circuit element positioning and the improvement of heat dissipation.

次に、第１の金属層１５０の表面を、ウェットエッチングなどにより粗化する。たとえば、銅をウェットエッチングすると、銅の結晶粒に応じて銅の表面に凹凸を生じさせることができる。このように、第１の金属層１５０の表面に凹凸をつけることにより、第１の金属層１５０と基材１４０に搭載される回路素子および絶縁樹脂膜との間でアンカー効果がより発揮されやすくなるので、基材１４０と回路素子および絶縁樹脂膜との密着性、接着性を高めることができる。第１の金属層１５０の表面に付与される凹凸のRaは、密着性、接着性を確保する観点から、0.3〜10μmが好ましく、1〜3μmがより好ましい。第１の金属層１５０の表面のRaは、触針式表面形状測定器で計測することができる。   Next, the surface of the first metal layer 150 is roughened by wet etching or the like. For example, when copper is wet-etched, irregularities can be generated on the surface of copper according to the crystal grains of copper. As described above, by providing unevenness on the surface of the first metal layer 150, the anchor effect is more easily exhibited between the first metal layer 150 and the circuit element and the insulating resin film mounted on the base material 140. As a result, the adhesion and adhesion between the substrate 140, the circuit element, and the insulating resin film can be improved. The unevenness Ra given to the surface of the first metal layer 150 is preferably 0.3 to 10 μm and more preferably 1 to 3 μm from the viewpoint of ensuring adhesion and adhesion. Ra of the surface of the first metal layer 150 can be measured with a stylus type surface shape measuring instrument.

なお、本実施の形態では、第１の金属層１５０の表面は全面にわたり粗化されるが、レーザなどのエネルギ照射によって、接着性を高めたい部分に凹凸を局所的に形成してもよい。   Note that in this embodiment mode, the surface of the first metal layer 150 is roughened over the entire surface, but unevenness may be locally formed in a portion where adhesion is desired to be increased by irradiation with energy such as laser.

図２は、粗化処理前の第１の金属層１５０の表面の電子顕微鏡像である。図２（ａ）および図２（ｂ）の電子顕微鏡像の倍率は、それぞれ10,000倍、50,000倍である。また、図３は、粗化処理後の第１の金属層１５０の表面の電子顕微鏡像である。図３（ａ）および図３（ｂ）の電子顕微鏡像の倍率は、それぞれ10,000倍、50,000倍である。図２と図３とを比較すると、粗化処理後の第１の金属層１５０の表面は、銅の結晶粒が顕わになり、輪郭に沿って凹凸が生じていることがわかる。銅の結晶粒が一定方向に長軸を有するため、粗化処理後の第１の金属層１５０の表面の凹凸に異方性が生じている。このように、第１の金属層１５０の表面に形成される凹凸に異方性を持たせることにより、アンカー効果が働きやすくなるので、後述する絶縁樹脂膜との密着性を向上させることができる。第１の金属層１５０の表面の凹凸が異方性を有することによるアンカー効果の向上については以下のように理解される。   FIG. 2 is an electron microscope image of the surface of the first metal layer 150 before the roughening treatment. The magnifications of the electron microscope images in FIGS. 2 (a) and 2 (b) are 10,000 times and 50,000 times, respectively. FIG. 3 is an electron microscope image of the surface of the first metal layer 150 after the roughening treatment. The magnifications of the electron microscope images in FIGS. 3 (a) and 3 (b) are 10,000 times and 50,000 times, respectively. Comparing FIG. 2 and FIG. 3, it can be seen that the surface of the first metal layer 150 after the roughening treatment reveals copper crystal grains and has irregularities along the contour. Since the copper crystal grains have a major axis in a certain direction, anisotropy occurs in the irregularities on the surface of the first metal layer 150 after the roughening treatment. As described above, by providing anisotropy to the unevenness formed on the surface of the first metal layer 150, the anchor effect can be easily achieved, so that adhesion to an insulating resin film described later can be improved. . The improvement of the anchor effect due to the anisotropy of the irregularities on the surface of the first metal layer 150 is understood as follows.

図４（ａ）は、第１の金属層１５０の表面の凹凸が異方性を有しない場合の結晶粒３１０を模式的に表す平面図であり、図４（ｂ）は、第１の金属層１５０の表面の凹凸が異方性を有する場合の結晶粒３１２を模式的に表す平面図である。図４（ａ）のように結晶粒３１０が異方性を有しない場合には、単位長あたりの結晶粒界数は方向（矢印３１０ａ）に依存して増減せず、異方性を持たない。一方、図４（ｂ）のように結晶粒３１２が異方性を有する場合には、単位長あたりの結晶粒界数は、結晶粒の長手方向（矢印３１２ａ）と短手方向（矢印３１２ｂ）とで異なり、異方性を持つ。ここで、各結晶粒が立体構造を有することを考慮すると、結晶粒界は段差を持つ（図３参照）ことから、異方性の結晶構造では、平面状は同一長さであっても、立体的には界面の全体長に差が生じる。したがって、第１の金属層１５０の表面の凹凸が異方性を有する場合に、第１の金属層１５０とその上に形成される絶縁樹脂膜とが剥離する際に、界面剥離の進行に異方性が生じる。このような界面剥離の進行の異方性を利用し、界面剥離の生じやすい方向（チップが長方形の場合など）に結晶粒界が多くなるように、第１の金属層１５０の素材を配置し、第１の金属層１５０の表面の粗化処理後に、回路素子を実装することにより、密着性の向上を図ることができ、より信頼性の高い半導体モジュールが製造可能となる。   FIG. 4A is a plan view schematically showing the crystal grain 310 when the unevenness of the surface of the first metal layer 150 does not have anisotropy, and FIG. 4B shows the first metal. FIG. 6 is a plan view schematically showing crystal grains 312 when the surface unevenness of the layer 150 has anisotropy. When the crystal grains 310 do not have anisotropy as shown in FIG. 4A, the number of crystal grain boundaries per unit length does not increase or decrease depending on the direction (arrow 310a) and does not have anisotropy. . On the other hand, when the crystal grains 312 have anisotropy as shown in FIG. 4B, the number of crystal grain boundaries per unit length is the longitudinal direction (arrow 312a) and the short direction (arrow 312b) of the crystal grains. And has anisotropy. Here, considering that each crystal grain has a three-dimensional structure, since the grain boundary has a step (see FIG. 3), in the anisotropic crystal structure, even if the planar shape has the same length, Three-dimensionally, there is a difference in the overall length of the interface. Therefore, when the unevenness of the surface of the first metal layer 150 has anisotropy, when the first metal layer 150 and the insulating resin film formed on the first metal layer 150 are peeled off, the progress of interfacial peeling is different. Anisotropy arises. Utilizing such anisotropy of the progress of interfacial delamination, the material of the first metal layer 150 is arranged so that the number of crystal grain boundaries increases in the direction in which interfacial delamination is likely to occur (such as when the chip is rectangular). By mounting the circuit element after the surface roughening treatment of the first metal layer 150, the adhesion can be improved, and a more reliable semiconductor module can be manufactured.

ここで、基材１４０の加工方法の説明に戻り、基材１４０を酸素中に暴露することにより、第１の金属層１５０の表面に金属酸化膜を形成する。第１の金属層１５０の表面に金属酸化膜を形成することにより、基材１４０の絶縁耐圧を向上させることができる。たとえば、第１の金属層１５０に銅が用いられた場合には、第１の金属層１５０の表面に酸化銅（ＣｕＯ）または亜酸化銅（Ｃｕ２Ｏ）が形成される。また、第１の金属層１５０にアルミニウムが用いられた場合には、第１の金属層１５０の表面にアルマイト（Ａｌ２Ｏ３）が形成される。 Here, returning to the description of the processing method of the base material 140, the base material 140 is exposed to oxygen to form a metal oxide film on the surface of the first metal layer 150. By forming a metal oxide film on the surface of the first metal layer 150, the withstand voltage of the substrate 140 can be improved. For example, when copper is used for the first metal layer 150, copper oxide (CuO) or cuprous oxide (Cu 2 O) is formed on the surface of the first metal layer 150. Further, when aluminum is used for the first metal layer 150, alumite (Al 2 O 3 ) is formed on the surface of the first metal layer 150.

なお、第１の金属層１５０の表面に金属酸化膜を形成することに代えて、プラズマＣＶＤ法などにより第１の金属層１５０の上にシリコン酸化膜を形成してもよく、プラズマ窒化プロセスにより第１の金属層１５０の表層を窒化しても、基材１４０の絶縁耐圧を向上させることができる。なお、第１の金属層１５０の上に絶縁ペースト、銀ペーストなどの接着層を塗布してもよい。これによれば、基材１４０と回路素子との密着性をさらに向上させることができる。   Instead of forming a metal oxide film on the surface of the first metal layer 150, a silicon oxide film may be formed on the first metal layer 150 by a plasma CVD method or the like. Even if the surface layer of the first metal layer 150 is nitrided, the withstand voltage of the substrate 140 can be improved. Note that an adhesive layer such as an insulating paste or a silver paste may be applied on the first metal layer 150. According to this, the adhesiveness between the substrate 140 and the circuit element can be further improved.

第１の金属層１５０の表面に設けられる金属酸化膜、シリコン酸化膜、窒化膜などの絶縁膜の層厚としては、0.5〜10μmが好ましい。絶縁膜の層厚が0.5μmより薄いと絶縁耐圧が不十分となり、絶縁膜の層厚が10μmより厚いと絶縁樹脂膜との密着性が不十分となる。   The layer thickness of an insulating film such as a metal oxide film, a silicon oxide film, or a nitride film provided on the surface of the first metal layer 150 is preferably 0.5 to 10 μm. When the thickness of the insulating film is less than 0.5 μm, the withstand voltage is insufficient, and when the thickness of the insulating film is greater than 10 μm, the adhesion with the insulating resin film is insufficient.

図５は、半導体素子１４２ａの放熱性を高めるための加工方法を示す断面図である。まず、図５（ａ）に示すように、基材１４０に面する半導体素子１４２ａの裏面（基材１４０側の面）に複数の開口を有するフォトレジスト３００を形成する。続いて、図５（ｂ）に示すように、フォトレジスト３００をマスクとして、エッチングにより半導体素子１４２ａに複数の凹部３０２を選択的に形成する。さらに、フォトレジスト３００を除去した後、図５（ｃ）に示すように、凹部３０２に、金属下地膜としてのシード膜を形成した後、電解めっきにより凹部３０２に銅などの熱伝導性に優れる金属を埋め込む。   FIG. 5 is a cross-sectional view showing a processing method for improving the heat dissipation of the semiconductor element 142a. First, as shown in FIG. 5A, a photoresist 300 having a plurality of openings is formed on the back surface (surface on the base material 140 side) of the semiconductor element 142 a facing the base material 140. Subsequently, as shown in FIG. 5B, a plurality of recesses 302 are selectively formed in the semiconductor element 142a by etching using the photoresist 300 as a mask. Further, after removing the photoresist 300, as shown in FIG. 5C, after forming a seed film as a metal base film in the recess 302, the recess 302 is excellent in thermal conductivity such as copper by electrolytic plating. Embed metal.

このように、半導体素子１４２ａの裏面に、金属が埋め込まれた凹部３０２を形成することにより、半導体素子１４２ａに蓄積された熱が凹部３０２内の金属によって容易に移動できるので、半導体素子１４２ａの放熱性が向上する。   As described above, by forming the concave portion 302 in which the metal is embedded on the back surface of the semiconductor element 142a, the heat accumulated in the semiconductor element 142a can be easily moved by the metal in the concave portion 302. Improves.

なお、半導体素子１４２ａに複数の貫通穴を形成した後、複数の貫通穴に熱伝導性に優れる金属を埋め込んでもよい。これによっても、半導体素子１４２ａの放熱性を向上させることができる。また、凹部３０２が形成される面は、半導体素子１４２ａの裏面に限られず、表面でもよく、裏面および表面の両方であってもよい。このうち、放熱性向上の観点から、半導体素子１４２ａの裏面に凹部３０２を設けることがより望ましい。   Note that after forming a plurality of through holes in the semiconductor element 142a, a metal having excellent thermal conductivity may be embedded in the plurality of through holes. Also by this, the heat dissipation of the semiconductor element 142a can be improved. Further, the surface on which the recess 302 is formed is not limited to the back surface of the semiconductor element 142a, and may be the front surface or both the back surface and the front surface. Among these, it is more desirable to provide the recessed part 302 in the back surface of the semiconductor element 142a from a viewpoint of heat dissipation improvement.

なお、半導体素子１４２ａの少なくとも一方の面に形成される凹部３０２に埋め込まれる材料は、金属に限定されず、たとえば半導体素子を用いることができる。半導体素子として、たとえば、ペルチェ素子を用いることにより、凹部３０２内の熱吸収効果がより高まるので、半導体素子１４２ａの放熱性向上に好適である。   Note that the material embedded in the recess 302 formed on at least one surface of the semiconductor element 142a is not limited to metal, and for example, a semiconductor element can be used. By using, for example, a Peltier element as the semiconductor element, the heat absorption effect in the recess 302 is further increased, which is suitable for improving the heat dissipation of the semiconductor element 142a.

図６および図７は、基材１４０に回路素子を実装する手順を示す断面図である。まず、図６（ａ）に示すように、基材１４０上に複数の半導体素子１４２ａ、半導体素子１４２ｂ、受動素子１４４等の回路素子を固定するダイ・チップボンド工程を行う。   6 and 7 are cross-sectional views showing a procedure for mounting a circuit element on the substrate 140. First, as shown in FIG. 6A, a die / chip bonding process for fixing circuit elements such as a plurality of semiconductor elements 142 a, semiconductor elements 142 b, and passive elements 144 on the base material 140 is performed.

半導体素子１４２ａおよび半導体素子１４２ｂは、たとえば、トランジスタ、ダイオード、ＩＣチップ等である。半導体素子１４２ａには、上述のように、裏面に金属が埋め込まれた複数の凹部３０４が形成されている。また、受動素子１４４は、たとえば、チップコンデンサ、チップ抵抗等である。なお、ここで述べた受動素子１４４も、これらの受動素子１４４の一部または全部の材料となる埋込材料を、素子間絶縁膜を含有する膜の凹部内部に埋め込んで埋込部材を形成させる技術により形成することができる。   The semiconductor element 142a and the semiconductor element 142b are, for example, a transistor, a diode, an IC chip, or the like. As described above, the semiconductor element 142a has a plurality of recesses 304 in which metal is embedded on the back surface. The passive element 144 is, for example, a chip capacitor or a chip resistor. Note that the passive element 144 described here also embeds an embedding material, which is a part or all of the material of the passive element 144, into the recess of the film containing the inter-element insulating film to form an embedding member. It can be formed by technology.

本実施形態では、回路素子を搭載する領域に合わせて第１の金属層１５０の表面に溝１５５が形成されているので、基材１４０に半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４をそれぞれに対応する溝１５５にはめ込むことにより、容易かつ正確に載置することができる。   In this embodiment, since the groove 155 is formed on the surface of the first metal layer 150 in accordance with the region where the circuit element is mounted, the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 are respectively formed on the base 140. By fitting into the corresponding groove 155, it can be placed easily and accurately.

続いて、図６（ｂ）に示すように、銅箔付き樹脂膜などの導電性膜付き絶縁樹脂膜を基材１４０上に貼付し、真空プレスにより、半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４を絶縁樹脂膜１２２内に押し込む。   Subsequently, as shown in FIG. 6B, an insulating resin film with a conductive film such as a resin film with a copper foil is pasted on the substrate 140, and the semiconductor element 142a, the semiconductor element 142b, and the passive element are vacuum-pressed. 144 is pushed into the insulating resin film 122.

これにより、半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４が絶縁樹脂膜１２２内に埋め込まれ、半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４が絶縁樹脂膜１２２内に圧着されて接着するとともに、絶縁樹脂膜１２２と基材１４０とが接合する。なお、各回路素子と基材１４０との間には絶縁樹脂膜１２２が存在するが、図６（ｂ）〜図６（ｅ）および図７（ｆ）〜図７（ｉ）では図示を省略する。なお、絶縁樹脂膜１２２内への回路素子の埋め込みをより確実にするために、図６（ａ）において、第１の金属層１５０の表面に絶縁樹脂膜を予め成膜した後、基材１４０に回路素子を載置してもよい。これによれば、基材１４０に載置された回路素子間の絶縁性をさらに高めることができる。   As a result, the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 are embedded in the insulating resin film 122, and the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 are pressure-bonded and bonded to the insulating resin film 122, and are insulated. The resin film 122 and the base material 140 are joined. An insulating resin film 122 exists between each circuit element and the base material 140, but is not shown in FIGS. 6 (b) to 6 (e) and FIGS. 7 (f) to 7 (i). To do. In order to more reliably embed circuit elements in the insulating resin film 122, an insulating resin film is formed in advance on the surface of the first metal layer 150 in FIG. A circuit element may be mounted on. According to this, the insulation between the circuit elements mounted on the base material 140 can be further enhanced.

また、複数の半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４に段差が生じている場合でも、半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４間へ絶縁樹脂膜が入り込むため、基材１４０から導電性膜１２３までの厚さを均一に保つこともできる。これにより、回路装置の寸法精度を高めることができる。   Further, even when there are steps in the plurality of semiconductor elements 142a, 142b, and passive elements 144, the insulating resin film enters between the semiconductor elements 142a, 142b, and passive elements 144. The thickness up to the film 123 can also be kept uniform. Thereby, the dimensional accuracy of a circuit device can be improved.

導電性膜１２３は、たとえば圧延銅箔等の圧延金属である。絶縁樹脂膜１２２としては、加熱することにより軟化する材料であればどのようなものを用いることもできるが、たとえばエポキシ樹脂、ＢＴレジン等のメラミン誘導体、液晶ポリマー、ＰＰＥ樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等を用いることができる。このような材料を用いることにより、回路装置の剛性を高めることができ、回路装置の安定性を向上することができる。   The conductive film 123 is a rolled metal such as a rolled copper foil. As the insulating resin film 122, any material can be used as long as it is softened by heating. For example, epoxy resin, melamine derivatives such as BT resin, liquid crystal polymer, PPE resin, polyimide resin, fluororesin Phenol resin, polyamide bismaleimide, etc. can be used. By using such a material, the rigidity of the circuit device can be increased, and the stability of the circuit device can be improved.

また、絶縁樹脂膜１２２には、フィラーまたは繊維等の充填材を含めることができる。フィラーとしては、たとえば粒子状または繊維状のＳｉＯ2やＳｉＮを用いることができる。絶縁樹脂膜１２２にフィラーや繊維を含めることにより、絶縁樹脂膜１２２を加熱して半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４を熱圧着した後、絶縁樹脂膜１２２をたとえば室温に冷却する際に、絶縁樹脂膜１２２の反りを低減することができ、また熱伝導性も向上する。これにより、半導体素子１４２および受動素子１４４と絶縁樹脂膜１２２との密着性を高めることができる。また、絶縁樹脂膜１２２に繊維を含めた場合、絶縁樹脂膜１２２の剛性を高めることができるため、ハンドリングが容易になる。このような観点からは、絶縁樹脂膜１２２を構成する材料としてアラミド不織布を用いると、繊維よりも樹脂の流動性が高くなるため、加工性を良好にすることができる。 The insulating resin film 122 can include a filler such as a filler or fiber. As the filler, for example, particulate or fibrous SiO 2 or SiN can be used. When the insulating resin film 122 is included in the insulating resin film 122, the insulating resin film 122 is heated and the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 are thermocompression bonded, and then the insulating resin film 122 is cooled to, for example, room temperature. In addition, warping of the insulating resin film 122 can be reduced, and thermal conductivity is also improved. Thereby, the adhesiveness between the semiconductor element 142 and the passive element 144 and the insulating resin film 122 can be improved. In addition, when fibers are included in the insulating resin film 122, the rigidity of the insulating resin film 122 can be increased, so that handling becomes easy. From such a viewpoint, when an aramid nonwoven fabric is used as the material constituting the insulating resin film 122, the fluidity of the resin is higher than that of the fibers, so that the workability can be improved.

導電性膜付き絶縁樹脂膜としては、フィルム状の絶縁樹脂膜１２２上に導電性膜１２３が付着したものを用いることができる。また、導電性膜付き絶縁樹脂膜は、導電性膜１２３上に絶縁樹脂膜１２２を構成する樹脂組成物を塗布・乾燥することにより形成することもできる。本実施の形態において、樹脂組成物は、本発明の目的に反しない範囲において、硬化剤、硬化促進剤、その他の成分を含むことができる。導電性膜付き絶縁樹脂膜は、絶縁樹脂膜１２２がＢステージ化（一次硬化、半硬化あるいは仮硬化した状態を意味する）した状態で基材１４０上に配置される。   As the insulating resin film with a conductive film, a film in which a conductive film 123 is attached to a film-like insulating resin film 122 can be used. The insulating resin film with a conductive film can also be formed by applying and drying a resin composition constituting the insulating resin film 122 on the conductive film 123. In this Embodiment, the resin composition can contain a hardening | curing agent, a hardening accelerator, and another component in the range which is not contrary to the objective of this invention. The insulating resin film with a conductive film is disposed on the substrate 140 in a state where the insulating resin film 122 is B-staged (meaning a state of primary curing, semi-curing, or temporary curing).

このようにすれば、絶縁樹脂膜１２２と半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４との密着性を高めることができる。この後、絶縁樹脂膜１２２を構成する樹脂の種類に応じて絶縁樹脂膜１２２を加熱し、真空下または減圧下で導電性膜付き絶縁樹脂膜１２２と半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４を圧着する。また、他の例において、フィルム状の絶縁樹脂膜１２２をＢステージ化した状態で基材１４０上に配置し、さらにその上に導電性膜１２０を配置して絶縁樹脂膜１２２を半導体素子１４２ａ、半導体素子１４２ｂ、受動素子１４４と熱圧着する際に、導電性膜１２３を絶縁樹脂膜１２２に熱圧着することによっても導電性膜付き絶縁樹脂膜１２２を形成することができる。   In this manner, the adhesion between the insulating resin film 122 and the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 can be improved. Thereafter, the insulating resin film 122 is heated in accordance with the type of resin constituting the insulating resin film 122, and the insulating resin film 122 with the conductive film, the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 are subjected to vacuum or reduced pressure. Crimp the. In another example, the film-shaped insulating resin film 122 is placed on the base material 140 in a B-staged state, and the conductive film 120 is further disposed thereon to form the insulating resin film 122 as a semiconductor element 142a, The insulating resin film 122 with the conductive film can also be formed by thermocompression bonding of the conductive film 123 to the insulating resin film 122 when thermocompression bonding with the semiconductor element 142b and the passive element 144 is performed.

そして、導電性膜１２３を、レーザー直描法（トレパニングアライメント）またはウェット銅エッチングにより配線形成する配線パターニング工程を行う。   Then, a wiring patterning process is performed in which the conductive film 123 is formed by laser direct drawing (trepanning alignment) or wet copper etching.

また、この後、図６（ｃ）に示すように、炭酸ガスレーザー、ＹＡＧレーザー、ドライエッチングを組み合わせて絶縁樹脂膜１２２にビアホール（スルーホール）を形成するビアホール形成工程を行う。   Thereafter, as shown in FIG. 6C, a via hole forming step of forming a via hole (through hole) in the insulating resin film 122 by combining carbon dioxide laser, YAG laser, and dry etching is performed.

続いて、図６（ｄ）に示すように、高アスペクト比対応の無電解銅めっき、電解銅めっきにより、導電性膜１２０を形成するとともに、スルーホール内を導電性材料で埋め込み、ビア１２１を形成するめっき工程を行う。次いで、導電性膜１２０をセミアディティブめっきによりパターニングして高密度配線を形成し、複数の半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４間を電気的に接続する配線形成工程を行う。   Subsequently, as shown in FIG. 6D, a conductive film 120 is formed by electroless copper plating or electrolytic copper plating corresponding to a high aspect ratio, and the through hole is filled with a conductive material, and a via 121 is formed. A plating process to be formed is performed. Next, the conductive film 120 is patterned by semi-additive plating to form a high-density wiring, and a wiring forming process for electrically connecting the plurality of semiconductor elements 142a, the semiconductor elements 142b, and the passive elements 144 is performed.

次いで、図６（ｅ）に示すように、導電性膜付き絶縁樹脂膜の絶縁樹脂膜１２２が第一の絶縁樹脂膜および第二の絶縁樹脂膜により構成されるように、さらに導電性膜１２３付きの第二の絶縁樹脂膜を形成する第二の絶縁樹脂膜形成工程を行う。導電性膜付き絶縁樹脂膜において、第一の絶縁樹脂膜上に第二の絶縁樹脂膜が形成され、第二の絶縁樹脂膜上に導電性膜１２３が形成される。   Next, as shown in FIG. 6E, the conductive film 123 is further formed so that the insulating resin film 122 of the insulating resin film with the conductive film is composed of the first insulating resin film and the second insulating resin film. A second insulating resin film forming step for forming the attached second insulating resin film is performed. In the insulating resin film with the conductive film, the second insulating resin film is formed on the first insulating resin film, and the conductive film 123 is formed on the second insulating resin film.

本実施の形態において、第二の絶縁樹脂膜は、半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４を絶縁樹脂膜１２２内に埋め込み熱圧着する際に、第一の絶縁樹脂膜を構成する材料よりも、剛性の高い材料により構成されてもよい。これにより、熱圧着時に、半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４を第一の絶縁樹脂膜内に埋め込むとともに、絶縁樹脂膜１２２の形状を剛直に保つことができる。   In the present embodiment, the second insulating resin film is made of a material constituting the first insulating resin film when the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 are embedded in the insulating resin film 122 and thermocompression bonded. Alternatively, it may be made of a highly rigid material. Thereby, at the time of thermocompression bonding, the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 can be embedded in the first insulating resin film, and the shape of the insulating resin film 122 can be kept rigid.

第二の絶縁樹脂膜を構成する材料は、第一の絶縁樹脂膜において説明した、たとえばエポキシ樹脂、ＢＴレジン等のメラミン誘導体、液晶ポリマー、ＰＰＥ樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等の中から適宜選択して用いることができる。   The material constituting the second insulating resin film is, for example, an epoxy resin, a melamine derivative such as BT resin, a liquid crystal polymer, a PPE resin, a polyimide resin, a fluororesin, a phenol resin, a polyamide bis described in the first insulating resin film. It can be appropriately selected from maleimide and the like.

第二の絶縁樹脂膜の上部にさらに設けられる導電性膜１２３は、たとえば圧延銅箔等の圧延金属であってもよい。   The conductive film 123 further provided on the upper portion of the second insulating resin film may be a rolled metal such as a rolled copper foil.

ここで、たとえば、第一の絶縁樹脂膜は、第二の絶縁樹脂膜を構成する材料よりも軟化しやすい材料により構成することができる。これにより、熱圧着時に第一の絶縁樹脂膜の方が第二の絶縁樹脂膜よりも変形しやすくなるので、第一の絶縁樹脂膜内に半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４がスムーズに押し込まれるとともに、第二の絶縁樹脂膜が剛直性を保ち、絶縁樹脂膜１２２全体が変形するのを防ぐことができる。   Here, for example, the first insulating resin film can be made of a material that is easier to soften than the material forming the second insulating resin film. As a result, the first insulating resin film is more easily deformed than the second insulating resin film during thermocompression bonding, so that the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 are smoothly in the first insulating resin film. In addition, the second insulating resin film can be kept rigid, and the entire insulating resin film 122 can be prevented from being deformed.

また、たとえば、第一の絶縁樹脂膜は、第二の絶縁樹脂膜を構成する材料よりもガラス転移温度の低い材料により構成することもできる。また、他の例において、第一の絶縁樹脂膜は、第二の絶縁樹脂膜を構成する材料よりも、半導体素子１４２ａ、半導体素子１４２ｂや受動素子１４４との密着性が高い材料により構成することもできる。このようにしても、上述したのと同様の効果を得ることができる。   Further, for example, the first insulating resin film can be made of a material having a glass transition temperature lower than that of the material constituting the second insulating resin film. In another example, the first insulating resin film is made of a material having higher adhesion to the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 than the material constituting the second insulating resin film. You can also. Even if it does in this way, the same effect as mentioned above can be acquired.

さらに、第一の絶縁樹脂膜および第二の絶縁樹脂膜には、フィラーまたは繊維等の充填材を含めることができる。この場合、第一の絶縁樹脂膜における充填材の含有量が、第二の絶縁樹脂膜における充填材の含有量よりも少なくなるように構成してもよい。また、第二の絶縁樹脂膜にのみ充填材を含め、第一の絶縁樹脂膜には充填材を含めない構成とすることもできる。このようにすれば、第一の絶縁樹脂膜の柔軟性を高めて半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４の埋め込みを行いやすくするとともに、第二の絶縁樹脂膜により絶縁樹脂膜１２２の反りを低減することができる。   Further, the first insulating resin film and the second insulating resin film can include a filler or a filler such as fiber. In this case, the content of the filler in the first insulating resin film may be configured to be smaller than the content of the filler in the second insulating resin film. Alternatively, the second insulating resin film may include a filler, and the first insulating resin film may include no filler. In this way, the flexibility of the first insulating resin film is increased to facilitate the embedding of the semiconductor element 142a, the semiconductor element 142b, and the passive element 144, and the warping of the insulating resin film 122 by the second insulating resin film. Can be reduced.

以上のように、第一の絶縁樹脂膜および第二の絶縁樹脂膜をそれぞれ目的に応じて好ましい材料により構成することにより、絶縁樹脂膜１２２への半導体素子１４２ａ、半導体素子１４２ｂおよび受動素子１４４の埋め込みを良好に行うことができるとともに、回路装置の剛性を高め、成型性を向上することができる。   As described above, by configuring the first insulating resin film and the second insulating resin film with preferable materials according to the purpose, the semiconductor element 142a, the semiconductor element 142b, and the passive element 144 on the insulating resin film 122 are formed. The embedding can be performed well, the rigidity of the circuit device can be increased, and the moldability can be improved.

次に、図７（ｆ）に示すように、第二の絶縁樹脂膜およびその上部の導電性膜についても、上記と同様に、配線パターニング工程、ビアホール形成工程、めっき工程、配線形成工程を繰り返して、２層配線形成工程を行う。   Next, as shown in FIG. 7F, the wiring patterning step, the via hole forming step, the plating step, and the wiring forming step are repeated for the second insulating resin film and the conductive film thereabove as well. Then, a two-layer wiring forming process is performed.

なお、後述するように、第二の絶縁樹脂膜の上にさらに積層される積層膜１６０に、配線１２５や導電性膜１２４があらかじめ設けられている場合には、第二の絶縁樹脂膜の表面に別途配線を形成する必要はない。   As will be described later, when the wiring 125 and the conductive film 124 are provided in advance in the laminated film 160 further laminated on the second insulating resin film, the surface of the second insulating resin film There is no need to form a separate wiring.

続いて、図７（ｇ）に示すように、第二の絶縁樹脂膜の上部に、凹部１９０を構成する積層膜１６０を積層する機能層形成第一工程を行う。この積層膜１６０は、あらかじめレーザー加工またはプレス加工などで窪ませた凹部あるいは打ち抜いた貫通部を備えているため、第二の絶縁樹脂膜の上部に圧着などにより接着されると、凹部１９０を構成することになる。この凹部１９０は、底面を有し、積層膜１６０の上方にのみ開口する窪状の凹部であってもよく、積層膜１６０の両面に開口するトンネル状の貫通部と第二の絶縁樹脂膜の上面とで構成される凹部であってもよい。いずれにしても、後述のペースト状の埋込材料を埋め込むことができる点では変わりないからである。   Subsequently, as shown in FIG. 7G, a functional layer forming first step of laminating a laminated film 160 constituting the recess 190 on the second insulating resin film is performed. Since this laminated film 160 has a concave portion or a punched through portion that has been recessed by laser processing or press processing in advance, a concave portion 190 is formed when bonded to the upper portion of the second insulating resin film by pressure bonding or the like. Will do. The concave portion 190 may be a concave concave portion having a bottom surface and opened only above the laminated film 160. The concave portion 190 may be formed of a tunnel-shaped through portion opened on both surfaces of the laminated film 160 and the second insulating resin film. It may be a recess constituted by the upper surface. In any case, this is because the paste-like embedding material described later can be embedded.

このように圧着などにより接着することにより、第一の膜の上部に、凹部や貫通部を備える第二の膜を貼付して凹部を構成すれば、膜を積層した後にパターニングやエッチングなどにより凹部を形成する場合に比べて、製造安定性よく凹部を構成することができる。 すなわち、本実施形態において、凹部１９０を構成するには、絶縁樹脂膜１２２上に積層膜１６０を積層した後にパターニングやエッチングなどにより、凹部１９０を形成してもよい。または、絶縁樹脂膜１２２上に、あらかじめ凹部または貫通部を形成した積層膜１６０を圧着してもよい。   In this way, by adhering by pressure bonding or the like, if a concave portion is formed by attaching a second film having a concave portion or a penetrating portion to the upper portion of the first film, the concave portion is formed by patterning or etching after the films are stacked. Compared to the case of forming the concave portion, the concave portion can be formed with high manufacturing stability. That is, in this embodiment, in order to form the recess 190, the recess 190 may be formed by patterning or etching after the laminated film 160 is laminated on the insulating resin film 122. Alternatively, a laminated film 160 in which a concave portion or a through portion is formed in advance may be pressure-bonded on the insulating resin film 122.

なお、絶縁樹脂膜１２２上に、あらかじめ凹部または貫通部を形成した積層膜１６０を圧着する方が、製造工程が簡便になるため望ましい。   Note that it is preferable to pressure-bond the laminated film 160 in which the concave portion or the through portion is formed in advance on the insulating resin film 122 because the manufacturing process becomes simple.

また、この積層膜１６０は、絶縁樹脂膜であってもよい。積層膜１６０に用いられる絶縁樹脂膜としては、上記の絶縁樹脂膜１２２において説明した、たとえばエポキシ樹脂、ＢＴレジン等のメラミン誘導体、液晶ポリマー、ＰＰＥ樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等の中から適宜選択して用いることができる。このような材料を用いることにより、後述する配線１２５や導電性膜１２４が他の導電性部材と好適に絶縁されるからである。また、このような材料は凹部の加工または真空貼付法による積層が容易だからでもある。   The laminated film 160 may be an insulating resin film. As the insulating resin film used for the laminated film 160, for example, epoxy resin, melamine derivatives such as BT resin, liquid crystal polymer, PPE resin, polyimide resin, fluorine resin, phenol resin, polyamide bis described in the above-mentioned insulating resin film 122. It can be appropriately selected from maleimide and the like. This is because by using such a material, a wiring 125 and a conductive film 124 described later are suitably insulated from other conductive members. This is because such a material can be easily processed by recessing or laminated by a vacuum sticking method.

また、この積層膜１６０は、特に限定されないが、膜強度の観点からは、膜厚が５０ｎｍ以上であってもよく、特に１００ｎｍ以上であってもよい。膜厚がこの範囲にあれば、積層膜１６０の構成する凹部１９０に掻取手段２００により埋込材料を埋め込んだ場合にも、積層膜１６０の破損が生じ難いからである。この積層膜の膜厚には特に上限はないが、埋込部材が回路素子の構成部材としての機能を発揮しうる膜厚であるように構成することができる。   Further, the laminated film 160 is not particularly limited, but from the viewpoint of film strength, the film thickness may be 50 nm or more, and particularly 100 nm or more. This is because, if the film thickness is within this range, the laminated film 160 is hardly damaged even when the embedding material 200 is embedded in the concave portion 190 of the laminated film 160. There is no particular upper limit to the thickness of the laminated film, but the embedded member can be configured to have a thickness that can function as a component of the circuit element.

また、この積層膜１６０には、配線１２５や導電性膜１２４があらかじめ設けられていてもよい。これらの配線１２５や導電性膜１２４としては、たとえば圧延銅箔等の圧延金属を加工して用いることができる。このように配線１２５や導電性膜１２４をあらかじめ設けておくことにより、別途の配線形成工程や導電性膜形成工程が不要となるため、回路装置の製造工程が簡便となり、製造コストおよび製造安定性を向上させることができるからである。   In addition, the laminated film 160 may be provided with the wiring 125 and the conductive film 124 in advance. As these wiring 125 and conductive film 124, for example, a rolled metal such as a rolled copper foil can be processed and used. By providing the wiring 125 and the conductive film 124 in advance as described above, a separate wiring forming process and a conductive film forming process are not required, thereby simplifying the manufacturing process of the circuit device, manufacturing cost, and manufacturing stability. It is because it can improve.

そして、この凹部１９０を構成する積層膜１６０を積層する工程は、この積層膜を真空貼付法または減圧貼付法により積層する工程を含んでもよい。ここで、真空貼付法または減圧雰囲気法とは、真空雰囲気下または減圧雰囲気下において、この積層膜１６０を熱圧着などにより貼り付ける方法を意味する。このように、真空雰囲気法または減圧雰囲気法を用いると、第二の絶縁樹脂膜と積層膜１６０または埋込部材との間に気泡などが混入しにくくなるため、抵抗器１８０やキャパシタ１７５などの埋込部材と他の導電性部材との電気的接触が改善されて高速信号伝送が可能となるか、あるいは回路装置の製造コストおよび製造安定性が改善される。   And the process of laminating | stacking the laminated film 160 which comprises this recessed part 190 may include the process of laminating | stacking this laminated film by the vacuum sticking method or the pressure reduction sticking method. Here, the vacuum attaching method or the reduced pressure atmosphere method means a method of attaching the laminated film 160 by thermocompression bonding or the like in a vacuum atmosphere or a reduced pressure atmosphere. As described above, when the vacuum atmosphere method or the reduced pressure atmosphere method is used, bubbles or the like are hardly mixed between the second insulating resin film and the laminated film 160 or the embedded member. The electrical contact between the embedded member and the other conductive member is improved to enable high-speed signal transmission, or the manufacturing cost and manufacturing stability of the circuit device are improved.

次いで、図７（ｈ）に示すように、ペースト状の埋込材料をこの積層膜１６０の構成する凹部１９０内部に埋め込む工程と、この埋込材料に乾燥などの処理を施して抵抗器１８０や後述するキャパシタ１７５を構成する高誘電率部材１７０などの回路素子の一部または全部を構成する埋込部材を形成する工程と、からなる機能層形成第二工程とを行う。   Next, as shown in FIG. 7 (h), a paste-like embedding material is embedded in the concave portion 190 constituting the laminated film 160, and the embedding material is subjected to a treatment such as drying to form a resistor 180 or A functional layer formation second step is performed, which includes a step of forming an embedded member constituting part or all of a circuit element such as a high dielectric constant member 170 constituting the capacitor 175 described later.

このように、ペースト状の埋込材料を積層膜１６０の構成する凹部１９０内部に埋め込んで処理することにより回路素子の一部または全部を構成する埋込部材を形成すると、埋込部材を形成する工程が簡便となる。このため、抵抗器１８０や後述するキャパシタ１７５を構成する高誘電率部材１７０などを含む回路素子の一部または全部を構成する埋込部材の表面を平坦（バンプレス）にすることができるので、小型化または薄型化された回路装置を製造安定性よく提供することができる。   As described above, when the embedded member constituting part or all of the circuit element is formed by embedding and processing the paste-like embedding material in the recess 190 constituting the laminated film 160, the embedded member is formed. The process becomes simple. For this reason, the surface of the embedded member constituting part or all of the circuit element including the resistor 180 and the high dielectric constant member 170 constituting the capacitor 175 described later can be made flat (bumpless). A circuit device reduced in size or thickness can be provided with high manufacturing stability.

ここで、この回路素子の一部または全部を構成する埋込部材は、受動素子などを構成する部材とすることができる。例えば、この埋込部材は、抵抗器１８０や後述するキャパシタ１７５などの受動素子の一部または全部を構成する部材であってもよい。この埋込部材が抵抗器１８０の一部または全部を構成する部材である場合には、この埋込部材の材料である埋込材料は、高抵抗を有する材料であれば特に限定はないが、例えば、カーボンや、Ｎｉ−Ｃｒ（ニクロム）をはじめとする金属材料を含む材料などを用いることができる。   Here, the embedded member constituting part or all of the circuit element can be a member constituting a passive element or the like. For example, this embedded member may be a member constituting part or all of a passive element such as the resistor 180 and the capacitor 175 described later. When the embedded member is a member constituting part or all of the resistor 180, the embedded material as the material of the embedded member is not particularly limited as long as it is a material having high resistance. For example, carbon or a material containing a metal material such as Ni—Cr (nichrome) can be used.

また、この埋込部材が後述するキャパシタ１７５を構成する高誘電率部材１７０である場合には、この埋込部材の材料は、高誘電率を有する材料であれば特に限定はないが、例えば、大きな比表面積を持つ活性炭などの炭素系材料や、五酸化タンタルなどを含む材料を用いることができる。   Further, when the embedded member is a high dielectric constant member 170 constituting the capacitor 175 described later, the material of the embedded member is not particularly limited as long as it is a material having a high dielectric constant. A carbon-based material such as activated carbon having a large specific surface area or a material containing tantalum pentoxide or the like can be used.

なお、キャパシタの下部電極または上部電極は、導電性を有する金属により形成することができる。例えば、銅、アルミニウムなどからなる薄膜電極などを用いることができる。   Note that the lower electrode or the upper electrode of the capacitor can be formed of a conductive metal. For example, a thin film electrode made of copper, aluminum, or the like can be used.

ここで、回路装置内に、ＣＶＤや、パターニングや、エッチングなどの手法を用いる通常の工程でキャパシタを設ける場合には、キャパシタは、一般に高誘電率部材と、電極部材という異種材料からなる部材を含むため、キャパシタの上面を平坦にすることが難しく、バリなども発生しやすく、また精度よくエッチングをすることが困難であるため製造安定性の面でも改善の余地があった。   Here, when a capacitor is provided in a circuit device by a normal process using a technique such as CVD, patterning, or etching, the capacitor generally includes a member made of different materials such as a high dielectric constant member and an electrode member. Therefore, it is difficult to flatten the upper surface of the capacitor, burrs are easily generated, and it is difficult to perform etching accurately, so there is room for improvement in terms of manufacturing stability.

一方、本実施の形態のように、凹部内部に高誘電率材料を埋め込むことによりキャパシタを形成する場合には、リソグラフィ技術も必要なく、あるいはエッチングを行う必要もないため、製造安定性が向上し、精度よく加工することも容易になり、あるいはバリなどの発生が低減して不純物などによる汚染なども少なくなる。   On the other hand, when the capacitor is formed by embedding a high dielectric constant material in the recess as in this embodiment, the manufacturing stability is improved because there is no need for lithography technology or etching. Therefore, it becomes easy to process with high precision, or the occurrence of burrs and the like is reduced, so that contamination by impurities and the like is reduced.

また、本実施の形態のように、凹部内部に高誘電率材料を埋め込むことによりキャパシタを形成する場合には、キャパシタの下部電極または上部電極と、高誘電率部材との平面形状が完全に一致している必要がないため、目合わせが容易であり、製造の際の設計マージンが大きく、この点でも製造安定性が向上する。   Further, when a capacitor is formed by embedding a high dielectric constant material in the recess as in this embodiment, the planar shape of the lower electrode or upper electrode of the capacitor and the high dielectric constant member is completely the same. Since it is not necessary to make adjustments, alignment is easy and a design margin in manufacturing is large, which also improves manufacturing stability.

また、これらの埋込材料は、粉末状の固形物を溶媒中に懸濁したペースト状の材料であってもよい。このようなペースト状の材料であれば、後述する掻取手段２００により、容易に凹部１９０内部に埋め込むことができる。   Further, these embedding materials may be paste-like materials in which a powdery solid is suspended in a solvent. Such a paste-like material can be easily embedded in the recess 190 by the scraping means 200 described later.

また、この埋め込む工程は、この埋込材料をスキージなどの掻取手段２００により埋め込む工程を含んでもよい。このようにスキージなどの掻取手段２００を用いることにより、凹部１９０内部に隙間なく埋込材料を埋め込むことができ、余った埋込材料は掻取手段２００により排除されるため、埋込部材の製造工程が簡便になり、回路素子の一部または全部を構成する埋込部材の表面が平坦になるので、薄型化または小型化された回路装置を製造安定性よく製造することができる。   The embedding step may include a step of embedding the embedding material with a scraping means 200 such as a squeegee. By using the scraping means 200 such as a squeegee in this way, the embedding material can be embedded without gaps in the recess 190, and the surplus embedding material is eliminated by the scraping means 200. Since the manufacturing process is simplified and the surface of the embedded member constituting part or all of the circuit element is flattened, a thin or miniaturized circuit device can be manufactured with high manufacturing stability.

また、かかる掻取手段により埋込材料を埋め込んだ場合には、出来合の抵抗器やキャパシタなどの受動素子を搭載する場合に発生しがちな、受動素子と、受動素子搭載面との間の隙間が発生する可能性が少ない。掻取手段により埋込材料が搭載面に圧着されるためである。そのため、本実施の形態においては、かかる空隙による回路装置の特性の低下を防ぐことができる。   In addition, when embedding material is embedded by such scraping means, it is likely to occur when mounting passive elements such as ready resistors and capacitors, between the passive element and the passive element mounting surface. There is little possibility of gaps. This is because the embedding material is pressed against the mounting surface by the scraping means. For this reason, in this embodiment, it is possible to prevent deterioration of the characteristics of the circuit device due to the gap.

あるいは、この埋め込む工程は、この埋込材料をスクリーン法により埋め込む工程を含んでもよい。ここで、スクリーン法とは、孔版印刷法の一種で版に絹や、テトロン、ナイロン等の化学繊維、あるいは金属繊維などのスクリーンを利用する印刷法を意味する。   Alternatively, the embedding step may include a step of embedding the embedding material by a screen method. Here, the screen method is a kind of stencil printing method and means a printing method using a screen made of a chemical fiber such as silk, tetron or nylon, or a metal fiber for a plate.

スクリーン法を実施することにより、スクリーン面に接して埋込材料の上面が形成されるため、積層膜の上部の一面とこの構成部材の上部の一面とで容易に平坦な面を形成させることができ、その結果、さらに上部に積層される膜の上面も平坦となるため、小型化または薄型化された回路装置を製造安定性よく提供することができるからである。また、この場合、凹部内にあらかじめ別の部材などが設けられていなければ、この積層膜の下部の一面とこの構成部材の下部の一面とで平坦な面を形成する。   By performing the screen method, since the upper surface of the embedded material is formed in contact with the screen surface, it is possible to easily form a flat surface between the upper surface of the laminated film and the upper surface of the constituent member. As a result, the upper surface of the film laminated on the upper portion is also flattened, so that a circuit device reduced in size or thickness can be provided with high manufacturing stability. In this case, if another member or the like is not provided in advance in the recess, a flat surface is formed by the lower surface of the laminated film and the lower surface of the constituent member.

本実施の形態において、スクリーン法を実施する手順としては、まず、スクリーンを枠に張り、四方を引っ張り緊張させて固定し、その上に機械的または光工学的（写真的）方法で版膜（レジスト）を作って必要な画線以外の目を塞いで版を作る。次に、枠内に埋込材料を入れ、スキージと呼ぶヘラ状のゴム板などからなる掻取手段２００でスクリーンの内面を加圧・移動する。すると、埋込材料は、版膜のない部分のスクリーンを透過して版の下に置かれた被印刷物面である積層膜１６０の凹部１９０内部に押し出されて、凹部内部を隙間ない状態で埋め尽くすこととなる。   In this embodiment, as a procedure for carrying out the screen method, first, the screen is stretched on a frame, and is fixed by pulling and tensioning all sides, and then a plate film (mechanical or optical engineering (photographic) method is used thereon. (Resist) to make a plate with the eyes other than the necessary strokes closed. Next, an embedding material is put into the frame, and the inner surface of the screen is pressurized and moved by scraping means 200 made of a spatula-shaped rubber plate called a squeegee. Then, the embedding material passes through the screen of the portion without the plate film and is pushed out into the concave portion 190 of the laminated film 160 which is the surface of the printed material placed under the plate, and fills the concave portion with no gap. I will do everything.

また、本実施の形態における回路装置の製造方法は、この積層膜１６０の凹部１９０外に残存するこの埋込材料をスキージ等の掻取手段２００などにより除去する工程をさらに備えてもよい。このように、埋込材料を除去する工程を備えることにより、この凹部１９０内部を埋め尽くした状態で余ってしまう埋込材料を積層膜の上から除去することができるため、積層膜の上面を平坦にすることができ、残存した埋込材料の存在による回路装置の特性の低下を防ぐことができる。   In addition, the method of manufacturing the circuit device according to the present embodiment may further include a step of removing the embedded material remaining outside the concave portion 190 of the laminated film 160 with a scraping means 200 such as a squeegee. In this way, by providing the step of removing the embedded material, it is possible to remove the embedded material remaining in the state in which the inside of the recess 190 is completely filled from the top of the laminated film. It can be flattened, and deterioration of the circuit device characteristics due to the presence of the remaining embedding material can be prevented.

このような埋込材料を除去する工程としては、例えば、スキージなどの掻取手段２００により積層膜１６０の上面を掻き取る工程などを設けてもよい。この場合、積層膜１６０の凹部１９０に埋込材料を埋め込む工程と、この埋込材料を除去する工程とが、同一の工程となってもかまわない。同一の工程で行うことにより、回路装置の製造コストおよび製造安定性を改善できる。   As a step of removing such an embedding material, for example, a step of scraping the upper surface of the laminated film 160 by a scraping means 200 such as a squeegee may be provided. In this case, the process of embedding the embedding material in the recess 190 of the laminated film 160 and the process of removing the embedding material may be the same process. By performing in the same process, the manufacturing cost and manufacturing stability of the circuit device can be improved.

また、この埋込材料を乾燥させて抵抗器１８０や後述するキャパシタ１７５を構成する高誘電率部材１７０などの埋込部材を形成する工程は、この埋込材料、この埋込材料を凹部１９０内部に含む積層膜１６０または製造途中の回路装置全体を加熱することによって、この埋込材料を乾燥させる工程を含んでもよい。また、この埋込材料を乾燥させて埋込部材を形成する工程は、絶縁性樹脂膜からなる積層膜１６０を他の部材と熱圧着させる工程と同一の工程であってもよい。同一の工程で行うことにより、回路装置の製造コストおよび製造安定性を改善できる。   Further, the step of drying the embedded material to form an embedded member such as the resistor 180 and the high dielectric constant member 170 constituting the capacitor 175 to be described later, The step of drying the embedding material by heating the laminated film 160 or the entire circuit device being manufactured may be included. Further, the step of drying the embedding material to form the embedding member may be the same step as the step of thermocompression bonding the laminated film 160 made of the insulating resin film with another member. By performing in the same process, the manufacturing cost and manufacturing stability of the circuit device can be improved.

このような製造方法によれば、積層膜と、この積層膜に埋め込まれた埋込部材とを備え、この積層膜の上部の一面とこの埋込部材の上部の一面とで平坦な面を形成するように構成されている回路装置が提供される。また、この場合、凹部内にあらかじめ別の部材などが設けられていなければ、この積層膜の下部の一面とこの埋込部材の下部の一面とで平坦な面を形成する。ここで、上記の積層膜の上部または下部の一面と埋込部材の上部または下部の一面とで形成される平坦な面は、完全に平坦な面である必要はなく、多少の凹凸があっても実質的に平坦な面であればよい。   According to such a manufacturing method, a laminated film and an embedded member embedded in the laminated film are provided, and a flat surface is formed by an upper surface of the laminated film and an upper surface of the embedded member. A circuit device configured to do so is provided. In this case, if another member or the like is not provided in advance in the recess, a flat surface is formed by the lower surface of the laminated film and the lower surface of the embedded member. Here, the flat surface formed by the upper surface or the lower surface of the laminated film and the upper surface or the lower surface of the embedded member does not need to be a completely flat surface, and has some unevenness. As long as the surface is substantially flat.

このような構成を備える回路装置は、この積層膜の上部の一面とこの埋込部材の上部の一面とで平坦な面を形成するように構成されているため、さらに上部に積層される薄膜の上部表面も平坦な面を形成するので、薄型化または小型化された回路装置を製造安定性よく提供することができる。また、この積層膜の下部の一面とこの埋込部材の下部の一面とで平坦な面を形成するように構成されているため、下層膜との層間密着性も良好となる。   Since the circuit device having such a configuration is configured to form a flat surface by one surface of the upper portion of the laminated film and one surface of the upper portion of the embedded member, the thin film to be further laminated on the upper portion is formed. Since the upper surface also forms a flat surface, a thin or miniaturized circuit device can be provided with high manufacturing stability. In addition, since the flat surface is formed by the lower surface of the laminated film and the lower surface of the embedded member, the interlayer adhesion with the lower layer film is improved.

次いで、図７（ｉ）に示すように、積層膜および回路装置の構成部材のさらに上部に、さらなる絶縁樹脂膜およびその上部の導電性膜を形成し、上記と同様に、配線パターニング工程、ビアホール形成工程、めっき工程、配線形成工程を繰り返して、３層配線形成工程を行う。そして、最上層の上部に形成された導電性膜１２６上に、半田印刷法などにより裏面電極として半田電極（ハンダボール）２１０を形成する半田電極形成工程を行う。   Next, as shown in FIG. 7 (i), a further insulating resin film and a conductive film thereabove are formed further on the laminated film and the constituent members of the circuit device. The three-layer wiring forming process is performed by repeating the forming process, the plating process, and the wiring forming process. Then, a solder electrode forming process is performed in which a solder electrode (solder ball) 210 is formed as a back electrode on the conductive film 126 formed on the uppermost layer by a solder printing method or the like.

後述するように、このようにして形成した回路装置は、導電性膜付き絶縁樹脂膜の導電性膜上に別の導電性膜付き絶縁樹脂膜を積み重ねて配線層を形成し、複数の半導体素子１４２ａ、半導体素子１４２ｂや受動素子１４４間を電気的に接続し、他のデバイスと電気的に接続することができる。   As will be described later, the circuit device thus formed has a plurality of semiconductor elements in which a wiring layer is formed by stacking another insulating resin film with a conductive film on the conductive film of the insulating resin film with a conductive film. 142a, the semiconductor element 142b, and the passive element 144 can be electrically connected to each other and electrically connected to other devices.

本実施の形態における回路装置の製造工程によれば、簡易な方法で複数の半導体素子１４２ａ、半導体素子１４２ｂや受動素子１４４を絶縁樹脂膜１２２内に埋め込み封止することができる。また、回路装置の放熱性を良好にすることもできる。また、回路装置を小型化することもできる。また、回路装置の基材１４０と絶縁樹脂膜１２２との密着性を向上させることができる。   According to the manufacturing process of the circuit device in this embodiment, a plurality of semiconductor elements 142a, semiconductor elements 142b, and passive elements 144 can be embedded and sealed in the insulating resin film 122 by a simple method. In addition, the heat dissipation of the circuit device can be improved. In addition, the circuit device can be reduced in size. In addition, the adhesion between the substrate 140 of the circuit device and the insulating resin film 122 can be improved.

本実施の形態によれば、ウェハ工程と、ＩＳＢ（Integrated System in Board；登録商標）の技術、装置を活用した、マルチチップＳｉＰを実現することができる。また、真空貼付法により、複数のＬＳＩ上に絶縁フィルム、銅配線を一括で形成することもできる。そして、バンプレス構造が実現でき、高速信号伝送、薄型パッケージが実現できる。その結果、回路装置内に受動素子を内蔵させることが可能になり、薄型の高機能ＳｉＰを提供することができる。   According to the present embodiment, it is possible to realize a multi-chip SiP using a wafer process, ISB (Integrated System in Board; registered trademark) technology and apparatus. In addition, an insulating film and copper wiring can be collectively formed on a plurality of LSIs by vacuum bonding. A bumpless structure can be realized, and high-speed signal transmission and a thin package can be realized. As a result, a passive element can be built in the circuit device, and a thin high-performance SiP can be provided.

以上、本発明を実施の形態および実施例に基づいて説明した。この実施の形態および実施例はあくまで例示であり、種々の変形例が可能なこと、またそうした変形例も本発明の範囲にあることは当業者に理解されるところである。   The present invention has been described based on the embodiments and examples. It is to be understood by those skilled in the art that the embodiments and examples are merely examples, and various modifications are possible and that such modifications are within the scope of the present invention.

例えば、表面に凹部を備える膜の凹部の内部に埋込材料を埋め込む方法としては、スクリーン法により埋め込む方法に限られず、この膜の上面全面に埋込材料を塗布して、凹部の外部に存在する埋込材料を掻取手段などにより除去する方法を用いてもよい。例えば、ＣＶＤ法などにより埋込材料をこの膜の上面全面に積層させて、この埋込材料のうち凹部からはみ出したものをスキージなどで掻き取って除去してもよい。   For example, the method of embedding the embedding material in the concave portion of the film having the concave portion on the surface is not limited to the method of embedding by the screen method, and the embedding material is applied to the entire upper surface of the film and exists outside the concave portion. A method of removing the embedded material to be removed by a scraping means or the like may be used. For example, an embedding material may be laminated on the entire upper surface of this film by a CVD method or the like, and a portion of the embedding material protruding from the recess may be scraped off with a squeegee or the like.

あるいは、この膜の上面の一部に埋込材料を載置して、この埋込材料を掻取手段で横方向に移動させながら凹部の上を通過させることによって、凹部の内部に埋込材料を埋め込む方法を用いてもよい。例えば、凹部の近くの膜上に炭素材料を含むペーストを塗布して、このペーストをスキージにより引っ掻きながら膜上を移動させて、凹部の上面を移動させることによって、凹部の内部にペーストを埋め込んでもよい。   Alternatively, the embedding material is placed on a part of the upper surface of the film, and the embedding material is passed through the recess while moving the embedding material laterally by the scraping means. You may use the method of embedding. For example, by applying a paste containing a carbon material on a film near the recess, moving the paste on the film while scratching the paste with a squeegee, and moving the upper surface of the recess, the paste is embedded inside the recess. Good.

あるいは、配線層において、層間の電気的接続は、スルーホールを導電性材料で埋め込む方法に限られず、たとえば、ワイヤを介して行うこともできる。この場合ワイヤを封止材により覆ってよい。   Alternatively, in the wiring layer, the electrical connection between the layers is not limited to the method of filling the through hole with a conductive material, and can be performed, for example, via a wire. In this case, the wire may be covered with a sealing material.

なお、半導体素子１４２ｂは、図６乃至図７に示すように、第一の素子上に第二の素子が配置された回路素子を含む構成とすることもできる。第一の素子上に第二の素子の組み合わせとしては、たとえばＳＲＡＭとＦｌａｓｈメモリ、ＳＲＡＭとＰＲＡＭとすることができる。この場合、第一の素子上に第二の素子とはビアにより電気的に接続され得る。   Note that the semiconductor element 142b may include a circuit element in which a second element is arranged on the first element as illustrated in FIGS. As a combination of the second element on the first element, for example, SRAM and Flash memory, SRAM and PRAM can be used. In this case, the first element can be electrically connected to the second element by a via.

また、積層膜１６０の材料は、絶縁樹脂膜に限られず、抵抗器の材料となるカーボン材料やキャパシタの構成部材となる高誘電率材料であってもよい。この場合、積層膜１６０の凹部１９０に埋め込まれる埋込材料は、絶縁性樹脂材料であることができる。積層膜中において、かかる抵抗器やキャパシタの構成部材となる領域が大部分を占め、絶縁性樹脂膜が占める領域が少ない場合には、このような構成が特に有効である。   The material of the laminated film 160 is not limited to the insulating resin film, and may be a carbon material that serves as a resistor material or a high dielectric constant material that serves as a constituent member of a capacitor. In this case, the embedding material embedded in the concave portion 190 of the laminated film 160 can be an insulating resin material. Such a configuration is particularly effective in the case where the regions constituting the resistors and capacitors occupy most of the laminated film and the region occupied by the insulating resin film is small.

そして、上記の埋込材料としては、ペースト状の埋込材料に限定されず、掻取手段により上記の積層膜の凹部内部に埋め込むことができるテクスチャーを有する材料であればよく、例えば、乾燥した粉末状の材料であってもよく、あるいは軟化した樹脂材料などであってもよい。   The above-described embedding material is not limited to a paste-like embedding material, and may be any material having a texture that can be embedded in the concave portion of the laminated film by scraping means, for example, dried It may be a powdered material or a softened resin material.

さらに、キャパシタや抵抗器をはじめとする回路素子の一部または全部を構成する埋込部材を形成するための上記の埋込材料の処理方法としては、乾燥処理に限定されず、例えば、焼成、圧着、圧縮、固化、凝固、成型、架橋、硬化、変性などの様々な処理を、目的とする埋込部材の特性に応じて用いることができる。   Furthermore, the method for treating the embedded material for forming the embedded member constituting part or all of the circuit elements including the capacitor and the resistor is not limited to the drying process, for example, firing, Various treatments such as pressure bonding, compression, solidification, coagulation, molding, crosslinking, curing, and modification can be used according to the characteristics of the target embedded member.

本実施の形態における回路装置に用いられる基材の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the base material used for the circuit device in this Embodiment. 粗化処理前の第１の金属層の表面の電子顕微鏡像である。It is an electron microscope image of the surface of the 1st metal layer before a roughening process. 粗化処理後の第１の金属層の表面の電子顕微鏡像である。It is an electron microscope image of the surface of the 1st metal layer after a roughening process. 第１の金属層の表面の凹凸が異方性を有しない場合の結晶粒および第１の金属層の表面の凹凸が異方性を有する場合の結晶粒をそれぞれ模式的に表す平面図である。It is a top view which represents typically the crystal grain when the unevenness | corrugation of the surface of a 1st metal layer does not have anisotropy, and the crystal grain when the unevenness | corrugation of the surface of a 1st metal layer has anisotropy, respectively . 半導体素子の放熱性を高めるための加工方法を示す断面図である。It is sectional drawing which shows the processing method for improving the heat dissipation of a semiconductor element. 基材に回路素子を実装する手順を示す断面図である。It is sectional drawing which shows the procedure which mounts a circuit element on a base material. 基材に回路素子を実装する手順を示す断面図である。It is sectional drawing which shows the procedure which mounts a circuit element on a base material.

符号の説明Explanation of symbols

１００ ＢＧＡ、１０２ ＬＳＩチップ、１０４ 金属線、１０６ ガラスエポキシ基板、１０８ 接着層、１１０ 封止樹脂、１１２ 半田ボール、１２０ 配線、１２１ ビア、１２２ 絶縁樹脂膜、１２３ 導電性膜、１２４ 導電性膜、１２５ 配線、１２６ 導電性膜、１４０ 基材、１４２ａ 半導体素子、１４２ｂ 半導体素子、１４４ 受動素子、１４６ 引張方向、１４８ 応力緩和方向、１６０ 積層膜、１７０ 高誘電率部材、１７５ キャパシタ、１８０ 抵抗器、１９０ 凹部、２００ 掻取手段、２１０ 半田ボール。   100 BGA, 102 LSI chip, 104 metal wire, 106 glass epoxy substrate, 108 adhesive layer, 110 sealing resin, 112 solder ball, 120 wiring, 121 via, 122 insulating resin film, 123 conductive film, 124 conductive film, 125 wiring, 126 conductive film, 140 base material, 142a semiconductor element, 142b semiconductor element, 144 passive element, 146 tensile direction, 148 stress relaxation direction, 160 laminated film, 170 high dielectric constant member, 175 capacitor, 180 resistor, 190 recess, 200 scraping means, 210 solder ball.

Claims (5)

金属性の基材と、
前記基材の上に設けられた絶縁樹脂膜と、
前記絶縁樹脂膜に埋め込まれた複数の回路素子と、
を備え、
前記基材に、前記複数の回路素子に対応する複数の溝が形成され、
前記基材の前記複数の溝内の表面に凹凸が形成され、
前記複数の回路素子が、それぞれに対応する溝にはめ込まれ、
前記凹凸は、異方性を有して形成され、前記回路素子に起因した前記基材と前記絶縁樹脂膜との界面剥離の生じやすい方向に結晶粒界が多いことを特徴とする回路装置。 A metallic substrate;
An insulating resin film provided on the substrate;
A plurality of circuit elements embedded in the insulating resin film;
With
A plurality of grooves corresponding to the plurality of circuit elements are formed in the base material,
Concavities and convexities are formed on the surfaces in the plurality of grooves of the base material,
The plurality of circuit elements are fitted into corresponding grooves,
The circuit device is characterized in that the unevenness is formed with anisotropy, and there are many crystal grain boundaries in a direction in which interface peeling between the base material and the insulating resin film due to the circuit element is likely to occur. 前記基材と前記絶縁樹脂膜との間に、接着層が設けられたことを特徴とする請求項１に記載の回路装置。   The circuit device according to claim 1, wherein an adhesive layer is provided between the base material and the insulating resin film. 前記基材の表面に絶縁膜が形成されていることを特徴とする請求項１または２に記載の回路装置。   The circuit device according to claim 1, wherein an insulating film is formed on a surface of the base material. 前記絶縁樹脂膜は、前記基材の上に設けられた第一の絶縁樹脂膜と、この第一の絶縁樹脂膜の上に設けられた第二の絶縁樹脂膜とを含み、
前記第二の絶縁樹脂膜は、前記第一の絶縁樹脂膜よりも高い剛性を有していることを特徴とする請求項１〜３のいずれか一項に記載の回路装置。 The insulating resin film includes a first insulating resin film provided on the base material, and a second insulating resin film provided on the first insulating resin film,
The circuit device according to claim 1, wherein the second insulating resin film has higher rigidity than the first insulating resin film. 金属性の基材の表面に複数の回路素子に対応する複数の溝を形成する工程と、
前記基材の表面を粗化し、前記複数の溝内に凹凸を形成する工程と、
前記複数の回路素子を対応する溝にはめ込むとともに、絶縁樹脂膜に埋め込む工程と、
前記絶縁樹脂膜を前記基材に接合する工程と、
を備え、
前記凹凸を形成する工程では、前記回路素子に起因した前記基材と前記絶縁樹脂膜との間で界面剥離の生じやすい方向に結晶粒界が多くなるように、前記凹凸を、異方性を有して形成することを特徴とする回路装置の製造方法。 Forming a plurality of grooves corresponding to a plurality of circuit elements on the surface of the metallic substrate;
Roughening the surface of the substrate and forming irregularities in the plurality of grooves;
Inserting the plurality of circuit elements into corresponding grooves and embedding in an insulating resin film;
Bonding the insulating resin film to the substrate;
With
In the step of forming the irregularities, the irregularities are made anisotropic so that crystal grain boundaries increase in a direction in which interface peeling easily occurs between the base material and the insulating resin film caused by the circuit element. A method of manufacturing a circuit device, comprising:
JP2004191884A 2004-06-29 2004-06-29 Circuit device and manufacturing method thereof Expired - Fee Related JP4425072B2 (en)

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