TWI313924B - High frequency ic package for uniforming bump-bonding height and method for fabricating the same - Google Patents

High frequency ic package for uniforming bump-bonding height and method for fabricating the same Download PDF

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TWI313924B
TWI313924B TW095127401A TW95127401A TWI313924B TW I313924 B TWI313924 B TW I313924B TW 095127401 A TW095127401 A TW 095127401A TW 95127401 A TW95127401 A TW 95127401A TW I313924 B TWI313924 B TW I313924B
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Taiwan
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bump
substrate
bumps
integrated circuit
frequency integrated
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TW095127401A
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Chinese (zh)
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TW200807659A (en
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Kuang Hua Liu
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Chipmos Technologies Inc
Chipmos Technologies Bermuda
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Wire Bonding (AREA)

Description

1313924 九、發明說明： 【發明所屬之技術領域】 及其製造方法 本發明係有關於一種高頻積體電路封裝技術，特別係 有關於一種一致化凸塊接合高度之高頻積體電路封裴構1 【先前技術】1313924 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a high-frequency integrated circuit packaging technology, and more particularly to a high-frequency integrated circuit package with uniform bump bonding height. Structure 1 [Prior Art]

積體電路封裝技術是希望在以更簡化的製程與更低 的封裝成本保護更高頻、運算速度更快的積體電路晶 片。然目前的封裝方法在晶片與基板之間電性連接是 個別採用打線連接或覆晶接合技術，打線連接有電= 傳輸距離，無法供高頻積體電路之使用，覆晶接合則需 要在覆晶晶片之表面形成一重配置線路層 (Redistribution Uyer，RDL)，以使覆晶晶片所需的凸 塊為矩陣排列，但成本高，尤其是不適用於較低腳位 的記憶體封裝。 請參閱第1圖，一種習知積體電路封裝構造丨〇〇主 要包含一基板1 1 0、—晶片1 20、一黏晶層1 3 0、複數 個銲線1 40、一封膠體丨5 〇及複數個外接端子丄。該 基板1 0之第表面1 1 1係作為黏晶表面，該基板1 1 〇 之第二表面U2係作為植球面。通常該基板1 10係為 硬質印刷電路板並具有一槽孔丨13，以供打線通過。 該黏晶層1 3 〇形成在該晶片1 20之主動面i 2丨，以黏 接該晶片120之主動面121。該晶片12〇之該主動面 1 2 1係形成有複數個銲墊1 22。利用打線形成之銲線 5 !313924 % 0電性連接該晶片1 2 〇之該些銲墊丨2 2與該基板 〇並以該封膠體1 5 0密封該晶片1 2 0與該些銲線 40。該些如銲球之外接端子1 6〇係接合於該基板η 〇 之忒第二表面1 1 2，可對外表面接合（s ΜΤ)至一外部印 刷電路板。然而該些銲線1 4〇之長度不利於高頻ic之 訊號傳輸。此外，在高頻積體電路封裝產品中希望能 更薄化與更輕量化。 φ 【發明内容】 本發明之主要目的係在於提供一種一致化凸塊接 σ同度之南頻積體電路封裝構造及其製造方法，能以 非矩陣排列凸塊之低成本晶片進行覆晶接合，達到降 低製程複雜度及增加量產速度’且具有電性傳導路徑 ’ 短、防止沖線以及封裝薄化之功效。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。依據本發明，一種一致化凸塊接合高 φ 度之高頻積體電路封裝構造主要包含一基板、一多階段 黏晶層、一晶片以及複數個外接端子。該基板係具有一第一 表面與一第二表面’其中該第一表面上係形成有複數個凸塊 接墊。該多階段黏晶層係形成於該基板之該第一表面上。該 晶片係具有一主動面以及複數個在'該主動面上之凸塊，該晶 片係覆晶設置於該基板之該第一表面上，以使該些凸塊鍵合 至該些凸塊接墊，並且該多階段黏晶層係黏接該晶片之該主 動面。該些外接端子係設置於該基板之該第二表面。 本發明的目的及解決其技術問題還可採用以下技 6 1313924Integral circuit packaging technology is expected to protect higher frequency, faster computing integrated circuit wafers with a more simplified process and lower package cost. However, the current packaging method is to use a wire bonding or flip chip bonding technology in the electrical connection between the wafer and the substrate. The wire connection has electricity = transmission distance, and cannot be used for the high frequency integrated circuit, and the flip chip bonding needs to be covered. The surface of the crystal wafer forms a Redistribution Uyer (RDL) to make the bumps required for the flip chip are arranged in a matrix, but the cost is high, especially for a memory package of a lower pitch. Referring to FIG. 1 , a conventional integrated circuit package structure mainly includes a substrate 1 10 , a wafer 1 20 , a die layer 1 30 , a plurality of bonding wires 1 40 , and a colloid 丨 5 . 〇 and a plurality of external terminals 丄. The first surface 1 1 1 of the substrate 10 serves as a die-bonding surface, and the second surface U2 of the substrate 1 1 作为 serves as a spherical surface. Typically, the substrate 1 10 is a rigid printed circuit board and has a slot 13 for wire passing. The adhesive layer 13 is formed on the active surface i 2 of the wafer 120 to adhere to the active surface 121 of the wafer 120. The active surface 1 2 1 of the wafer 12 is formed with a plurality of pads 1 22 . The bonding wire 52 2 313924% is electrically connected to the wafer 12 2 and the substrate 〇 and the sealing film 150 is sealed with the sealing material 150 and the bonding wires 40. The solder ball external terminals 16 are bonded to the second surface 112 of the substrate η , to be externally bonded (s ΜΤ) to an external printed circuit board. However, the length of these bonding wires is not conducive to the transmission of high frequency ic signals. In addition, it is desired to be thinner and lighter in high-frequency integrated circuit package products. Φ [Summary of the Invention] The main object of the present invention is to provide a southwest-integrated circuit package structure and a method for fabricating the same bumps and sigma, which can be flip-chip bonded by a low-cost wafer in which non-matrix arrays are arranged. , to reduce the complexity of the process and increase the mass production speed 'and has a short electrical path, to prevent punching and packaging thinning effect. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a high-frequency integrated circuit package structure in which a uniform bump is bonded to a high φ degree mainly comprises a substrate, a multi-stage adhesive layer, a wafer, and a plurality of external terminals. The substrate has a first surface and a second surface, wherein a plurality of bump pads are formed on the first surface. The multi-stage adhesive layer is formed on the first surface of the substrate. The wafer has an active surface and a plurality of bumps on the active surface. The wafer is flip-chip mounted on the first surface of the substrate to bond the bumps to the bumps. a pad, and the multi-stage adhesive layer adheres to the active surface of the wafer. The external terminals are disposed on the second surface of the substrate. The object of the present invention and solving the technical problems thereof can also adopt the following techniques: 6 1313924

術措施進一步實現。 在前述的尚頻積體曾 , 广 電路封裝構造中，每一凸塊接墊 係具有一凹陷區’以增加m # ^ s加對該些凸塊之接合面積。 在前述的南頻積體電 封裝構造中，該些凸塊係為 錫鉛凸塊’且該些凸塊接墊係 _ 你形成有一鎳金層。 在前述的兩頻積體電路 ί裝構造中，該些凸塊係為 金凸塊，且該些凸塊接墊係开彡 成有一鲜料層，以利焊溶該些 凸塊。 —The technical measures are further realized. In the above-mentioned prior art, a wide circuit package structure, each bump pad has a recessed area ′ to increase m #^ s plus the bonding area of the bumps. In the aforementioned south-frequency integrated package structure, the bumps are tin-lead bumps and the bump pads are formed with a nickel-gold layer. In the above two-frequency integrated circuit structure, the bumps are gold bumps, and the bump pads are opened to form a fresh layer to facilitate soldering of the bumps. -

在前述的高頻積體電路封裝構造中 係包含銲球。 在前述的高頻積體電路封裝構造中 DDR3記憶體晶片。 在前述的高頻積體電路私 % &封裝構造中 電路薄膜。 該些外接端子 ’該晶片係為 該基板係為一In the above-described high-frequency integrated circuit package structure, solder balls are included. In the aforementioned high-frequency integrated circuit package structure, a DDR3 memory chip. In the aforementioned high-frequency integrated circuit, the circuit film is in the % & package structure. The external terminals ’ the wafer is the substrate

在前述的高頻積體電路封裝構造中 晶片尺寸。【實施方式】 該基板係接近 請參閱第2圖’在本發明一 — 之第·一具體貫施例中， 種一致化凸塊接合高度之 主要包含一基板210、— 两頻積體電路封裝構造200 多階段黏晶層 2 2 0、 2 3 0以及複數個外接端子2 4 Q。 該基板2 1 0係具有一笛 乐—表面 21 1與 212,其中該第一表面二丨丨上 a曰 片 2 1 3。該基板2 1 0係可為印 ‘第二表面 係形成有複數個凸塊接墊 刷電路板或電路薄膜。較佳 7 1313924 /押乙月日修( <)正^^換頁 '1_____The wafer size in the aforementioned high-frequency integrated circuit package structure. [Embodiment] The substrate is close to the second embodiment of the present invention. In the first embodiment, the uniform bump bonding height mainly includes a substrate 210, and a two-frequency integrated circuit package. A multi-stage adhesive layer 2 2 0, 2 3 0 and a plurality of external terminals 2 4 Q are constructed. The substrate 210 has a dew-surface 21 1 and 212, wherein the first surface has a sheet 2 1 3 . The substrate 210 can be printed with a plurality of bump pads or a circuit film formed on the second surface. Better 7 1313924 / 押乙月日修 ( <) 正^^ 换页 '1_____

地，該基板210係為一例如cOF軟膜之電路薄膜，有利 於封裝薄化、輕量化與降低熱阻。另，在本實施例中’該 基板210係可接近晶片尺寸。該基板210之該第二表 面212係形成有複數個球墊215。該基板210另包含 有一在第一表面211之線路層217與貫通之複數個電 性導通孔2 1 6 ’以電性連接該基板2 1 0之該些凸塊接 墊2 1 3與該些球墊2 1 5。此外，該基板2 1 0之該第一 表面2 1 1係可形成有一防銲層（圖未繪出），以局部覆 蓋該基板210之該線路層，217。 該多階段黏晶層220係形成於該基板210之該第一 表面2 1 1上。該多階段黏晶層220係包含有多階段固 化樹脂，例如該多階段黏晶層220在A階段（A-stage) 可印刷在該基板2 1 0上，烘烤該基板2 1 0以局部熟化 該多階段黏晶層220至B階段（B-stage)，其係具有黏The substrate 210 is a circuit film such as a COF flexible film, which is advantageous for thinning, weight reduction, and thermal resistance reduction. Further, in the present embodiment, the substrate 210 is accessible to the wafer size. The second surface 212 of the substrate 210 is formed with a plurality of ball pads 215. The substrate 210 further includes a circuit layer 217 on the first surface 211 and a plurality of electrical vias 2 1 6 ′ extending through the substrate 211 to electrically connect the bump pads 2 1 3 of the substrate 2 1 0 and the pads Ball pad 2 1 5. In addition, the first surface 211 of the substrate 210 may be formed with a solder resist layer (not shown) to partially cover the circuit layer 217 of the substrate 210. The multi-stage adhesive layer 220 is formed on the first surface 21 of the substrate 210. The multi-stage adhesive layer 220 comprises a multi-stage cured resin. For example, the multi-stage adhesive layer 220 can be printed on the substrate 210 in the A-stage, and the substrate 2 10 is baked to be partially Curing the multi-stage adhesive layer 220 to the B-stage, which has a viscosity

晶特性並以膠膜型態貼附於該基板2 1 0，在最終產品 出貨時’該多階段黏晶層 220將完全熟化至C階段 (C-stage)。另，在不同實施例變化中，B階段的多階 段黏晶層220可進一步細分為更多階變化的局部熟化 狀態，如B1、B2、B3等等。 該晶片230係具有一主動面231，並具有數個在該 主動面23 1上之凸塊233。該晶片230係覆晶設置於 該基板210之該第一表面211上，以使該些凸塊233 金屬鍵合至該些凸塊接墊 2 1 3，並且該多階段黏晶層 220係黏接該晶片23 0之該主動面23 1。利用該多階段 8 '1313924The crystal characteristic is attached to the substrate 210 in a film type, and the multi-stage adhesive layer 220 will be fully cured to the C-stage when the final product is shipped. In addition, in various embodiment variations, the multi-staged polycrystalline layer 220 of the B-stage can be further subdivided into more localized ripening states, such as B1, B2, B3, and the like. The wafer 230 has an active surface 231 and has a plurality of bumps 233 on the active surface 23 1 . The wafer 230 is overlying the first surface 211 of the substrate 210 such that the bumps 233 are metal bonded to the bump pads 2 1 3 , and the multi-stage adhesive layer 220 is adhered. The active surface 23 1 of the wafer 230 is connected. Utilize the multi-stage 8 '1313924

黏晶層220維持覆晶接合間隙與黏貼晶片’該晶片230 可不需要製作重配置線路層（RDL)，該些凸塊233係可直接 設置在該晶片230之原有複數個銲墊232之上方，位於該主 動面231之中央或周邊。在本實施例中，該些凸塊233係 為金凸塊，且該些凸塊接墊213係形成有一銲料層 2 1 4，以利焊熔該些凸塊23 3，達到覆晶接合之電性連 接。因此’ δ玄晶片230與該基板210之電性連接路徑 很短，並使該些凸塊233之接合高度一致化，可不需要打 線形成之金線更省略習知覆晶晶片之重配置線路層 (RDL)，適用於低成本之南頻封裝。較佳地，該晶片 23 0係為DDR3記憶體晶片，其頻率係超過500MHz以 上。此外，該晶片2 3 0之背面較佳為顯露狀或另貼設 一散熱片（圖未繪出），以增加散熱效果。 該些外接端子2 4 0係設置於該基板2丨〇之該第二表 面2 1 2 ’以供對外接合。在本實施例中，該些外接端 子240係包含銲球（solder ball) ’其係設置於該些球墊215 上。在不同實施例中，可利用錫膏、金屬球、金屬栓 或ACF導電膠置換銲球而成該些外接端子240。 藉由在該些凸塊23 3周圍的多階段黏晶層220，當 該些凸塊2 3 3金屬鍵合至該些凸塊接墊2 1 3，該晶片 2 3 0不易傾斜’以維持該些凸塊2 3 3之接合高度一致 化，不需要再填入底部填充膠（underfill material)。此 外，該晶片2 3 0與該基板2 1 0之間的電性連接係省略 以往的打線電性連接步驟，具有製程簡化的方便性。 9 •1313924 :· 配合第3 A至3 C圖，揭示該高頻積體電路封裝構 造2 00之製作過程。首先，如第3A圖所示，首先提供一 基板2 1 0 ’其第一表面2 11上係形成有複數個凸塊接塾2丨3， 其第二表面2 1 2上係形成有複數個球墊2 1 5。利用該線路層 2 1 7與該些電性導通孔21 6，電性連接該些凸塊接墊2丨3與 該些球墊215。接著，如第3B圖所示’可運用鋼板印刷形 成一多階段黏晶層220於該基板210之該第一表面211上， 並在黏晶前預烤成B階，達到適當之支撐效果。 之後’如第3C圖戶斤示，覆晶設置-晶片230於該基板 210之該第一表面211上，該晶片230之凸塊233係鍵合至 該些凸塊接墊2 1 3，並且該多階段黏晶層220係黏接該晶片 230之主動面23 1。最後，將該些外接端子240設置於該些 ' 球墊215，並熟化該多階段黏晶層220並能製作得到如第2 圖所示之高頻積體電路封裝構造2〇〇。 請參閱第4圖，在本發明之第二具體實施例中，揭 ^ 示另種一致化凸塊接合高度之高頻積體電路封裝構 造3 00，主要包含一基板3 1〇、一多階段黏晶層32〇、 一晶片3 3 0以及複數個外接端子3 4 〇。該基板3丨〇係 具有一第一表面311與一第二表面312，其中該第一 表面3 1 1上係形成有複數個凸塊接墊3 1 3，該基板3 1 0 之該第二表面3 1 2係形成有複數個球墊3 1 6。該基板 3 1 〇另包含有複數個電性導通孔3丨7與至少一線路層 3 1 8，以電性連接該些凸塊接墊3丨3與該些球墊3丨6。 在本實施例中，該基板310係可為一印刷電路板或電路 10 •1313924 *· 薄膜’有利於封裝薄化與輕量化。該多階段黏晶層3 2 〇 係形成於該基板3 1 〇之該第一表面3丨丨上。該晶片3 3 〇 係具有一主動面331以及複數個在該主動面331上之 凸塊3 3 3 ’該晶片3 3 〇係覆晶設置於該基板3 1 0之該 第一表面311上’以使該些凸塊333鍵合至該些凸塊 接塾3 1 3 ’並且該多階段黏晶層3 2〇係黏接該晶片3 3 〇 之該主動面3 3 1 °較佳地，該些凸塊333係設置在該晶片 330之鲜塑1 332上方’以省略習知覆晶晶片之重配置線路 層。該些外接端子3 40係設置於該基板之該第二表面 312 °亥些外接&amp;子340係可包含銲球（s〇ider ball)。較 佳地，如第5圖所示，每—凸塊接墊3丨3係具有一凹陷 區3 1 4 ’以增加對該些凸塊3 3 3之接合面積，並防止 «亥些凸塊3 3 3之塌散。在本實施例中，該些凸塊3 3 3 係為錫錯凸塊’且該些凸塊接墊3 1 3係形成有一鎳金 層3 1 5 ’以回焊方式達到金屬鍵合。由於在本實施例 % 中’該晶片3 3 0以回焊取代熱壓合達到覆晶接合作 業’當該多階段黏晶層3 2 0的供給量未能密封該些凸 塊333’該高頻積體電路封裝構造3〇〇可另包含有一 封膠體350’其係形成於該基板31〇之該第一表面311 並可密封該晶片330，更可填入該晶片33〇下方之空 隙處’以防止填膠不實產生爆米花（p〇pc〇rn)現象。 以上所述’僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 施例揭露如上’然而並非用以限定本發明，任何熟悉 11The bonding layer 220 maintains the flip-chip bonding gap and the bonding wafer. The wafer 230 may not need to be fabricated with a reconfigured wiring layer (RDL). The bumps 233 may be directly disposed above the original plurality of pads 232 of the wafer 230. Located at the center or periphery of the active surface 231. In this embodiment, the bumps 233 are gold bumps, and the bump pads 213 are formed with a solder layer 2 1 4 to solder the bumps 23 3 to achieve flip chip bonding. Electrical connection. Therefore, the electrical connection path between the δ sinusoidal wafer 230 and the substrate 210 is short, and the bonding height of the bumps 233 is uniform, and the gold wire formed by the wire can be omitted, and the reconfigured circuit layer of the conventional flip chip is omitted. (RDL) for low cost south frequency packages. Preferably, the wafer 306 is a DDR3 memory chip having a frequency of more than 500 MHz. In addition, the back surface of the wafer 230 is preferably exposed or otherwise provided with a heat sink (not shown) to increase the heat dissipation effect. The external terminals 240 are disposed on the second surface 2 1 2 ' of the substrate 2 for external bonding. In this embodiment, the external terminals 240 comprise solder balls disposed on the ball pads 215. In various embodiments, the solder terminals may be replaced by solder paste, metal balls, metal plugs or ACF conductive paste to form the external terminals 240. By the multi-stage adhesion layer 220 around the bumps 23 3 , when the bumps 2 3 3 are metal-bonded to the bump pads 2 1 3 , the wafers 2 3 0 are not easily tilted to maintain The joint height of the bumps 2 3 3 is uniform, and it is not necessary to refill the underfill material. In addition, the electrical connection between the wafer 230 and the substrate 210 is omitted from the conventional wiring electrical connection step, and the process is simplified. 9 • 1313924 :· In conjunction with Figures 3A to 3 C, the fabrication process of the high-frequency integrated circuit package structure 200 is disclosed. First, as shown in FIG. 3A, a substrate 2 1 0 ' is first provided with a plurality of bump blocks 2丨3 formed on the first surface 2 11 and a plurality of second surfaces 2 1 2 formed thereon. Ball pad 2 1 5. The bump pads 2丨3 and the ball pads 215 are electrically connected to the electrical vias 21, 6 and the electrical vias 21, 6 . Then, as shown in Fig. 3B, a multi-stage adhesive layer 220 can be formed on the first surface 211 of the substrate 210 by using a steel plate, and pre-baked into a B-stage before the bonding, to achieve an appropriate supporting effect. Then, as shown in FIG. 3C, the flip chip is disposed on the first surface 211 of the substrate 210, and the bumps 233 of the wafer 230 are bonded to the bump pads 2 1 3 , and The multi-stage adhesive layer 220 is bonded to the active surface 23 1 of the wafer 230. Finally, the external terminals 240 are placed on the 'ball pads 215, and the multi-stage die layer 220 is cured, and the high-frequency integrated circuit package structure 2 shown in FIG. 2 can be fabricated. Referring to FIG. 4, in a second embodiment of the present invention, a high-frequency integrated circuit package structure 300 of a uniform bump bump height is disclosed, which mainly includes a substrate 3 1 , a multi-stage The die layer 32 is, a wafer 3 30 and a plurality of external terminals 3 4 〇. The substrate 3 has a first surface 311 and a second surface 312. The first surface 31 is formed with a plurality of bump pads 3 1 3 , and the second substrate 3 1 0 The surface 3 1 2 is formed with a plurality of ball pads 3 16 . The substrate 3 1 〇 further includes a plurality of electrical vias 3 丨 7 and at least one wiring layer 3 1 8 to electrically connect the bump pads 3 丨 3 and the ball pads 3 丨 6 . In this embodiment, the substrate 310 can be a printed circuit board or a circuit 10 • 1313924 *· film </ RTI> to facilitate thinning and weight reduction of the package. The multi-stage adhesive layer 3 2 is formed on the first surface 3 of the substrate 3 1 . The wafer 3 3 has an active surface 331 and a plurality of bumps 3 3 3 ′ on the active surface 331. The wafer 3 3 is laminated on the first surface 311 of the substrate 310 . Preferably, the bumps 333 are bonded to the bump pads 3 1 3 ′ and the multi-stage adhesive layer 3 2 is bonded to the active surface 3 3 1 该 of the wafer 3 3 较佳 preferably, The bumps 333 are disposed over the fresh plastic 1 332 of the wafer 330 to omit the reconfigured wiring layer of the conventional flip chip. The external terminals 340 are disposed on the second surface of the substrate, and the circumscribing amps 340 can include a solder ball. Preferably, as shown in FIG. 5, each bump pad 3丨3 has a recessed portion 3 1 4 ′ to increase the joint area of the bumps 3 3 3 and prevent the bumps from being covered. 3 3 3 collapsed. In this embodiment, the bumps 3 3 3 are tin bumps and the bump pads 3 1 3 are formed with a nickel gold layer 3 1 5 ' to achieve metal bonding by reflow. Since in the present embodiment %, the wafer 303 is replaced by thermal recompression by reflow to achieve a flip chip bonding operation, 'the supply amount of the multi-stage viscous layer 3 2 0 fails to seal the bumps 333'. The memory package structure 3 can further include a glue 350' formed on the first surface 311 of the substrate 31 and can seal the wafer 330, and can be filled in the space below the wafer 33 'To prevent the occurrence of popcorn (p〇pc〇rn) phenomenon. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, although the present invention has been described above by way of a preferred embodiment.

·, 1313924 &lt;. * 本項技術者，在不脫離本發明之技術範圍内，所作 任何簡單修改、等效性變化與修飾，均仍屬於本發 的技術範圍内。 【圖式簡單說明】 第1圖：一種習知積體電路封裝構造之截面示意圖 第2圖：依據本發明之第一具體實施例，一種一致 凸塊接合高度之高頻積體電路封裝構造之 面示意圖。 第3 A至3 C圖：依據本發明之第一具體實施例，該 頻積體電路封裝構造在製程中之基板截面 意圖。 第4圖：依據本發明之第二具體實施例，另一種一 化凸塊接合高度之高頻積體電路封裝構造 截面示意圖。 第5圖：依據本發明之第二具體實施例，該高頻積 電路封裝構造之其中一凸塊之局部放大截 示意圖。 【主要元件符號說明】 的 明 化 截 面 示 致 之 體 面 100積體電路封裝構造 110 基板 111 第 113 槽孔 120 晶片 121 主 130 黏晶層 140 銲 160 外接端子 一表面 112 第二表面 動面 122 銲墊 線 150 封膠體 12 1313924And all of the simple modifications, equivalent changes, and modifications made by the present invention are within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional integrated circuit package structure. FIG. 2 is a view showing a high-frequency integrated circuit package structure of a uniform bump bonding height according to a first embodiment of the present invention. Schematic diagram. 3A to 3C: In accordance with a first embodiment of the present invention, the integrator circuit package is constructed with a substrate cross-section in the process. Fig. 4 is a cross-sectional view showing another high-frequency integrated circuit package structure of a bump-joining height according to a second embodiment of the present invention. Figure 5 is a partially enlarged cross-sectional view showing one of the bumps of the high frequency product circuit package structure in accordance with a second embodiment of the present invention. [Main component symbol description] The apparent cross section shows the decent surface 100 integrated circuit package structure 110 substrate 111 113th slot 120 wafer 121 main 130 adhesive layer 140 solder 160 external terminal one surface 112 second surface dynamic surface 122 solder Pad line 150 sealant 12 1313924

200高頻積體電路封裝構造 2 1 0基板 2 1 3凸塊接墊 2 1 6電性導通孔 211第—表面 214銲料層 217線路層 212第二表面 2 1 5球墊 220多階段黏晶層 230晶片 233凸塊 231主動面 232銲墊200 high frequency integrated circuit package structure 2 1 0 substrate 2 1 3 bump pad 2 1 6 electrical via 211 first surface 214 solder layer 217 circuit layer 212 second surface 2 1 5 ball pad 220 multi-stage die Layer 230 wafer 233 bump 231 active surface 232 pad

240外接端子 3 00高頻積體電路封裝構造240 external terminal 3 00 high frequency integrated circuit package structure

3 10基板 3 13凸塊接墊 3 16球墊 320多階段黏晶層 330晶片 333凸塊 3 40外接端子 3 11苐一表面 3 14凹陷區 3 1 7電性導通孔 33 1主動面 3 5 0封膠體 3 12第二表面 3 1 5錄金層 3 1 8線路層 3 3 2鲜塾 133 10 substrate 3 13 bump pad 3 16 ball pad 320 multi-stage adhesive layer 330 wafer 333 bump 3 40 external terminal 3 11 苐 a surface 3 14 recessed area 3 1 7 electrical via 33 1 active surface 3 5 0 sealant 3 12 second surface 3 1 5 gold layer 3 1 8 circuit layer 3 3 2 fresh 塾 13

Claims (1)

•1313924 十、申請專利範圍： 1、 一種一致化凸塊接合高度之高頻積體電路封裝構造， 包含： 一基板，其係具有一第一表面.與一第二表面，其中該第 一表面上係形成有複數個凸塊接墊;• 1313924 X. Patent Application Range: 1. A high-frequency integrated circuit package structure with uniform bump bonding height, comprising: a substrate having a first surface and a second surface, wherein the first surface The upper system is formed with a plurality of bump pads; 一多階段黏晶層，其係形成於該基板之該第一表面上； 一晶片，其係具有一主動面以及複數個在該主動面上之 凸塊，該晶片係覆晶設置於該基板之該第一表面上， 以使該些凸塊鍵合至該些凸塊接墊，並且該多階段黏 晶層係黏接該晶片之該主動面；以及 複數個外接端子，其係設置於該基板之該第二表面； 其中每一凸塊接墊係具有一凹陷區。 2、 如申請專利範圍第1項所述之一致化凸塊接合高度之 高頻積體電路封裴構造，其中該些凸塊係為錫鉛凸 塊’且該些凸塊接墊係形成有一鎳金層。 3、 如申請專利範圍第1項所述之一致化凸塊接合高度之 高頻積體電路封裝構造，其中該些凸塊係為金凸塊， 且該些凸塊接墊係形成有一銲料層。 4、 如申請專利範圍第丨項所述之一致化凸塊接合高度之 高頻積體電路封裳構造，其中該些外接端子係包含鲜 球。 5、 如申請專利範圍第！項所述之一致化凸塊接合高度之 高頻積體電路封裝構造，其中該基板係為—電路薄膜。 6、 如申請專利範圍第】項所述之一致化凸塊接合高度之 14 1313924 高頻積體電路封裝構造，其中該基板係為一印刷電路 板0 ^、一種一致化凸塊接合高度之高頻積體電路封裝方法， 包含： 提供一基板，其係具有一第一表面與一第二表面，其中 該第一表面上係形成有複數個凸塊接墊； 形成一多階段黏晶層於該基板之該第一表面上；a multi-stage adhesive layer formed on the first surface of the substrate; a wafer having an active surface and a plurality of bumps on the active surface, the wafer is flip-chip disposed on the substrate On the first surface, the bumps are bonded to the bump pads, and the multi-stage adhesive layer is bonded to the active surface of the wafer; and a plurality of external terminals are disposed on the first surface The second surface of the substrate; wherein each bump pad has a recessed region. 2. The high frequency integrated circuit sealing structure of the uniform bump height according to claim 1, wherein the bumps are tin-lead bumps and the bump pads are formed Nickel gold layer. 3. The high-frequency integrated circuit package structure of the uniform bump-bonding height according to claim 1, wherein the bumps are gold bumps, and the bump pads are formed with a solder layer. . 4. The high frequency integrated circuit sealing structure of the uniformized bump joint height as described in the scope of the patent application, wherein the external terminals comprise fresh balls. 5, such as the scope of patent application! The high-frequency integrated circuit package structure of the uniformized bump bonding height described in the item, wherein the substrate is a circuit film. 6. The 14 1313924 high-frequency integrated circuit package structure of the uniform bump bonding height as described in the patent application scope, wherein the substrate is a printed circuit board 0 ^, and a uniform bump bonding height is high. The method of packaging a capacitor circuit includes: providing a substrate having a first surface and a second surface, wherein the first surface is formed with a plurality of bump pads; forming a multi-stage adhesive layer On the first surface of the substrate; 覆晶設置一晶片於該基板之該第一表面上，該晶片係具 有一主動面以及複數個在該主動面上之凸塊，該些凸 塊係鍵合至該4b &amp; :i 4f 〇 » ^ —凸塊接墊，並且5亥多階段黏晶層係黏 接。亥日日片之g亥主動面；以及 設置複數個外接端子於該基板之該第二表面。 ^申請專利範圍第7項所述之_致化凸塊接合高度之 兩頻積體電路封裝方法，其中每一凸塊接墊係具有-The flip chip is provided with a wafer on the first surface of the substrate, the wafer has an active surface and a plurality of bumps on the active surface, the bumps are bonded to the 4b &amp; :i 4f 〇 » ^ —Bumping pads, and 5H multi-stage bonding layer bonding. a g Hai active surface of the sunday film; and a plurality of external terminals are disposed on the second surface of the substrate. ^The method of encapsulating a height of a two-integrated body circuit according to the seventh aspect of the patent application, wherein each bump pad has - 9、 如申請專利範圍笛7 ^ 古 項所述之一致化凸塊接合高度之 间頻積體電路封奘古 捸，且H 裝方法，其中該些凸塊係為錫鉛凸 二？些凸塊接墊係形成有一錦金層。 10、 如申δ月專利範圍第 高頻積體電路封裝方本斤述之—致化凸塊接合高度之 且該些凸塊接塾㈣f其中該些凸塊係為金凸塊， &quot;、如申請專利範圍第;：―銲料層。 高頻積體電路封装方、、所述之一致化凸塊接合高度之 球。 法’其中該些外接端子係包含銲 15 1313924 12、 如申請專利範.圍笫7话糾、+、— ^ 固弟7項所述之一致化凸塊 古 高頻積體電路封护方口间度之 封裝方法，其中該基板係為一 13、 如申請專利範圍笫7栢糾、+， 潯膜 第1所述之—致化凸塊接合高度之 高頻積體電路封裝方法，苴 /、甲》哀基板係為一印刷電路 板。 14、 塊接合高度之高頻積體電路封裝構造， 包含： 丞极，共係具有9. If the application of the patent range is the same as that of the unification of the bumps, the inter-frequency block circuit is sealed, and the H-mounting method is that the bumps are tin-lead convex two? The bump pads are formed with a gold layer. 10, such as the application of the δ month patent range of the high-frequency integrated circuit package, the height of the bumps and the bumps (4) f, wherein the bumps are gold bumps, &quot;, Such as the scope of patent application;: "solder layer. The high-frequency integrated circuit package side, the uniformized bump bonding height ball. The method of the external terminal includes welding 15 1313924 12 , such as the patent application model, the 笫 笫 7 纠 、, +, — ^ ^ 固 7 7 item of the uniform bump ancient high-frequency integrated circuit sealing square mouth An inter-package method in which the substrate is a high-frequency integrated circuit package method of a height of a bump of a bumper bump, as described in the patent application, 笫7, ,,,,,,,,, A, the substrate is a printed circuit board. 14. The high-frequency integrated circuit package structure of the block bonding height, comprising: a bungee π W兴 π — π囬 表面上係形成有複數個凸塊接墊； -=階段黏晶層’其係形成於該基板之該[表面上； 一晶片’其係、具有-主動面以及複數個在該主動面上之 凸塊，該晶片係覆晶設置於該基板之該第一表面上， 以使該些凸塊鍵合至該些凸塊接墊，並且該多階段黏 晶層係黏接該W主動面；以及 複數個外接端子，其係設置於該基板之該第二表面； 、中在該二凸塊接墊上係形成有一銲料層，以利焊您該 些凸塊。 ⑴如申請專利範圍第14項所述之一致化凸塊接合高度之 高頻積體電路封裝構造，其中該些外接端子係包2銲 球。 ' Η、如申請專利範圍第14項所述之一致化凸塊接合高度之 尚頻積體電路封裝構造，其中該基板係為—電路薄膜。 17、如申請專利範圍第14項所述之一致化凸塊接合高度之 高頻積體電路封裝構造，其中該基板係為一印刷電路 16 '1313924 Λ *· 板。 1 8、如申請專利範圍第1 4項所述之一致化凸塊接合高度之 高頻積體電路封裝構造，其中該些凸塊係為金凸塊。π W π π — π back surface is formed with a plurality of bump pads; -= stage viscous layer ' is formed on the surface of the substrate [a surface; a wafer's system, with - active surface and plural a bump on the active surface, the wafer is flip-chip disposed on the first surface of the substrate, such that the bumps are bonded to the bump pads, and the multi-stage adhesive layer is Bonding the W active surface; and a plurality of external terminals disposed on the second surface of the substrate; wherein a solder layer is formed on the two bump pads to solder the bumps. (1) A high-frequency integrated circuit package structure of a uniform bump bonding height as described in claim 14, wherein the external terminals are packaged with solder balls. Η 尚 Η Η Η Η Η Η Η 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致17. The high frequency integrated circuit package structure of the uniform bump bonding height as described in claim 14, wherein the substrate is a printed circuit 16 '1313924 Λ *· board. 18. A high frequency integrated circuit package structure having a uniform bump bond height as described in claim 14 wherein the bumps are gold bumps. 17 1313924 七、指定代表圖： (一) 本案指定代表圖為：第（2)圖。 (二) 本代表圖之元件符號簡單說明: 200高頻積體電路封裝構造 212第二表面 215球墊 232銲墊 210基板 211第一表面 213凸塊接墊 214銲料層 2 1 6電性導通孔 21 7線路層17 1313924 VII. Designated representative map: (1) The representative representative of the case is: (2). (2) Brief description of the components of the representative figure: 200 high-frequency integrated circuit package structure 212 second surface 215 ball pad 232 pad 210 substrate 211 first surface 213 bump pad 214 solder layer 2 1 6 electrical conduction Hole 21 7 circuit layer 220多階段黏晶層 230晶片 231主動面 233凸塊 240外接端子 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式：220 multi-stage adhesive layer 230 wafer 231 active surface 233 bump 240 external terminal 8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention:
TW095127401A 2006-07-26 2006-07-26 High frequency ic package for uniforming bump-bonding height and method for fabricating the same TWI313924B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI495065B (en) * 2012-03-28 2015-08-01 Chipbond Technology Corp Semiconductor package structure and the method of making the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI495065B (en) * 2012-03-28 2015-08-01 Chipbond Technology Corp Semiconductor package structure and the method of making the same

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