TW200807659A - High frequency IC package for uniforming bump-bonding height and method for fabricating the same - Google Patents

High frequency IC package for uniforming bump-bonding height and method for fabricating the same Download PDF

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TW200807659A
TW200807659A TW095127401A TW95127401A TW200807659A TW 200807659 A TW200807659 A TW 200807659A TW 095127401 A TW095127401 A TW 095127401A TW 95127401 A TW95127401 A TW 95127401A TW 200807659 A TW200807659 A TW 200807659A
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Taiwan
Prior art keywords
bump
bumps
substrate
wafer
integrated circuit
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TW095127401A
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Chinese (zh)
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TWI313924B (en
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Kuang-Hua Liu
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Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Priority to TW095127401A priority Critical patent/TWI313924B/en
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Publication of TWI313924B publication Critical patent/TWI313924B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Disclosed are a high frequency IC package and a method for fabricating the same. The package mainly includes a substrate, a multi-stage chip attach material, a bumped chip, and a plurality of external terminals. The multi-stage chip attach material is formed on the substrate for fixing the active surface of the chip on which a plurality of bumps are disposed. When the bumps are bonded to the bump pads of the chip, the multi-stage chip attach material adheres to the active surface of the chip at the same time. Accordingly, the bonding heights of the bumps are uniform. The bumps can be primarily located on the bonding pads of the chip without redistribution layer or be formed at a non-array fashion, which provide shorter electrical transmissions to accord with low cost and high frequency IC packages.

Description

200807659 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種高頻積體電路封裝技術，特別係 有關於一種一致化凸塊接合高度之高頻積體電路封裝構造 及其製造方法。 【先前技術】 積體電路封裝技術是希望在以更簡化的製程與更低 的封裝成本保護更高頻、運算速度更快的積體電路晶 片。然目前的封裝方法在晶片與基板之間電性連接是 個別採用打線連接或覆晶接合技術，打線連接有電性 傳輸距離，無法供高頻積體電路之使用，覆晶接合則需 要在覆晶晶片之表面形成一重配置線路層 (Redistribution Uyer，RDL〇，以使覆晶晶片所需的凸 塊為矩陣排列，但成本高，尤其是不適用於較低腳位 的記憶體封裝。 請參閱第1圖，一種習知積體電路封裝構造丨〇〇主200807659 IX. Description of the Invention: [Technical Field] The present invention relates to a high-frequency integrated circuit packaging technology, and more particularly to a high-frequency integrated circuit package structure with uniform bump bonding height and a manufacturing method thereof . [Prior Art] The integrated circuit package technology is intended to protect higher frequency, faster operation integrated circuit wafers in a more simplified process and lower package cost. However, the current packaging method is electrically connected between the wafer and the substrate by a wire bonding or flip chip bonding technology. The wire bonding has an electrical transmission distance and cannot be used by a high frequency integrated circuit. The flip chip bonding needs to be covered. The surface of the crystal wafer forms a redistribution layer (RDL) so that the bumps required for the flip chip are arranged in a matrix, but the cost is high, especially for a memory package with a lower pin. Figure 1, a conventional integrated circuit package structure

要包含一基板110、一 Η μ 1 〇 A L 日日片1 2 0、一黏晶層i 3 〇、複數 個 線 1 4 0、'封膠·體 1 S Π k 7m T修篮1 5 0及複數個外接端子i 6 〇。該 基板1 1 0之第 面1 1 2係作為植球面。通常該基板丨丨〇係為 之第 衣® 1 1 1係作為黏晶表面 硬 、Ί，口么φ低 丄I ν 内、 質印刷電路板並具有—摊 ^ ^ ^ 八’槽孔1 13，以供打線通過 或黏晶層1 3 0形成在該 接該晶片120之主動面 1 2 1係形成有複數個銲 晶片1 2 0之主動面j 2 1，以黏 121。該晶片120之該主動面 塾1 2 2。利用打線形成之銲線 5 200807659 1 4 0電性連接該晶片1 2 〇之兮此 、 71 Αζυ之該些銲墊122與該基板 1 1 0。並以該封膠Μ 1 50密封該晶Μ 1 20與該些銲線 .該些如銲球之外接端子1則接合於該基板110 之吞亥第一表面112，可料从主工上六人 J對外表面接合（SMT)至一外部印 刷電路板。然而該歧銲蝮彳4 n 一杆環140之長度不利於高頻ic之 sfl號傳輸。此外，尤古处5叙 回頻積體電路封裝產品中希望能 更薄化與更輕量化。 【發明内容】To include a substrate 110, a Η μ 1 〇AL day wafer 1 2 0, a viscous layer i 3 〇, a plurality of lines 1 4 0, 'sealing body 1 S Π k 7m T basket 1 5 0 And a plurality of external terminals i 6 〇. The first surface 11 2 of the substrate 110 is used as a ball-forming surface. Usually, the substrate is made of the first coat of clothing. The 1 1 1 series is used as the surface of the die-bonding surface. The surface of the substrate is hard, Ί, φ 丄 low 丄 I ν internal, quality printed circuit board and has - spread ^ ^ 八 八 slot 1 13 The active surface 1 1 1 of the wafer 120 is formed with a plurality of solder wafers 1 2 0 to form an active surface j 2 1 to adhere 121. The active side of the wafer 120 is 塾1 2 2 . A bonding wire formed by wire bonding 5 200807659 1 4 0 electrically connects the wafers 1 2 , 71 该 of the pads 122 and the substrate 1 10 . And sealing the wafer 1 20 and the bonding wires with the sealing material Μ 150. The terminal 1 such as the solder ball is bonded to the first surface 112 of the substrate 110, which can be expected from the main work. The person J is externally surface bonded (SMT) to an external printed circuit board. However, the length of the brazed joint 4 n a rod ring 140 is not conducive to the transmission of the high frequency ic sfl number. In addition, the Yugu Division 5 regenerative integrated circuit package product is expected to be thinner and lighter. [Summary of the Invention]

本毛月之主要目的係在於提供一種一致化凸塊接 合高度之高頻積體電路封裝構造及其製造方法，能以 非矩陣排列凸塊之低成本晶片進行覆晶接合，達到降 低製程複雜度及增加量產速度’I具有電性傳導路徑 短、防止沖線以及封裝薄化之功效。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。依據本發明，一種一致化凸塊接合高 度之高頻積體電路封裝構造主要包含一基板、一多階段 黏晶層、一晶片以及複數個外接端子。該基板係具有一第一 表面與一第二表面，其中該第一表面上係形成有複數個凸塊 接墊。该多階段黏晶層係形成於該基板之該第一表面上。該 晶片係具有一主動面以及複數個在該主動面上之凸塊，該晶 片係覆晶設置於該基板之該第一表面上，以使該些凸塊鍵合 至該些凸塊接墊，並且該多階段黏晶層係黏接該晶片之該主 動面。該些外接端子係設置於該基板之該第二表面。 本發明的目的及解決其技術問題還可採用以下技 6 200807659 術措施進一步實現。 在前述的高頻積體電路封裝構造中，每一凸塊接塾 係具有一凹陷區’以增加對該些凸塊之接合面積。 在前述的高頻積體電路封裝構造中，該些凸塊係為 錫鉛凸塊，且該些凸塊接墊係形成有一鎳金層。 在前述的南頻積體電路封裝構造中，該些凸塊係為 金凸塊，且該些凸塊接墊係形成有一銲料層，以利焊熔該些 凸塊。The main purpose of this month is to provide a high-frequency integrated circuit package structure with uniform bump height and a manufacturing method thereof, which can perform flip-chip bonding with a low-cost wafer in which non-matrix arrays are arranged, thereby reducing process complexity. And increase the mass production speed 'I has the effect of short electrical conduction path, prevention of punching and thinning of package. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a high-frequency integrated circuit package structure of a uniform bump bonding height mainly comprises a substrate, a multi-stage adhesive layer, a wafer, and a plurality of external terminals. The substrate has a first surface and a second surface, wherein the first surface is formed with a plurality of bump pads. The multi-stage adhesive layer is formed on the first surface of the substrate. The wafer has an active surface and a plurality of bumps on the active surface, the wafer is overlying on the first surface of the substrate, so that the bumps are bonded to the bump pads. And the multi-stage adhesive layer adheres to the active surface of the wafer. The external terminals are disposed on the second surface of the substrate. The object of the present invention and solving the technical problems thereof can be further realized by the following technique 6 200807659. In the aforementioned high-frequency integrated circuit package structure, each of the bump contacts has a recessed portion' to increase the joint area of the bumps. In the above high-frequency integrated circuit package structure, the bumps are tin-lead bumps, and the bump pads are formed with a nickel-gold layer. In the foregoing south-frequency integrated circuit package structure, the bumps are gold bumps, and the bump pads are formed with a solder layer to solder the bumps.

在前述的高頻積體電路封裝構造中，該些外接端子 係包含鮮球。 在前述的高頻積體電路封裝構造中，該晶片係為 DDR3記憶體晶片。 a玄基板係為一 在前述的高頻積體電路封裝構造中 電路薄膜。 中，該基板係接近 在前述的高頻積體電路封裝^ $、止 晶片尺寸。 【實施方式】 請參閱第2圖，在本發明 <第一具體實施例中，一 種一致化凸塊接合高度之高頻 積體電路封裝構造200 主要包含一基板2 1 0、一多階i；L ^ n 凡黏日9層2 2 0、一晶片 230以及複數個外接端子24〇。 該基板2 1 0係具有一第— 2i2,其中該第-表面211上面2U與—第二表面 2 1 3。該基板2 1 0係可為印刷、、有複數個凸塊接墊 P刷電路板或電路薄膜。較佳 7 200807659 地，該基板210係為一例如cOF軟膜之電路薄膜，有利 於封裝薄化、輕量化與降低熱阻。另，在本實施例中，該 基板210係可接近晶片尺寸。該基板210之該第二表 面2 1 2係形成有複數個球墊2 1 5。該基板2 1 0另包含 有一在第一表面211之線路層217與貫通之複數個電 性導通孔2 1 6，以電性連接該基板2 1 0之該些凸塊接 墊2 1 3與該些球墊2 1 5。此外，該基板2 1 0之該第一 表面21丨係可形成有一防銲層（圖未繪出），以局部覆 蓋該基板210之該線路層217。 該多階段黏晶層220係形成於該基板2 1 0之該第一 表面2 1 1上。該多階段黏晶層22〇係包含有多階段固 化樹脂，例如該多階段黏晶層220在A階段（A-stage) 可印刷在該基板2 1 0上，烘烤該基板2 1 0以局部熟化 该多階段黏晶層2 2 0至B階段（B - s t a g e)，其係具有黏 晶特性並以膠膜型態貼附於該基板2丨〇，在最終產品 \ ; 出貨時，該多階段黏晶層220將完全熟化至C階段 (C-stage)。另，在不同實施例變化中，b階段的多階 段黏晶層220可進一步細分為更多階變化的局部熟化 狀態，如B1、B 2、B 3等等。 该晶片2 3 0係具有一主動面2 3 1，並具有數個在該 主動面231上之凸塊233。該晶片230係覆晶設置於 該基板2 1 〇之該第一表面2 1 1上，以使該些凸塊2 3 3 金屬鍵合至該些凸塊接墊2 1 3，並且該多階段黏晶層 220係黏接該晶片23〇之該主動面231。利用該多階段 8 200807659 黏晶層220維持覆晶接合間隙與黏貼晶片，該晶片23〇 可不需要製作重配置線路層（RDL)，該些凸塊233係可直接 設置在該晶片230之原有複數個銲墊232之上方，位於該主 勳面231之中央或周邊。在本實施例中，該些凸塊23 3係 為金凸塊，且該些凸塊接墊2 1 3係形成有一銲料層 2 1 4 ’以利焊熔該些凸塊23 3，達到覆晶接合之電性連 接。因此，該晶片23 0與該基板2 1 0之電性連接路徑 很短，並使該些凸塊233之接合高度一致化，可不需要打 / 線形成之金線更省略習知覆晶晶片之重配置線路層 (RDL)，適用於低成本之高頻封裝。較佳地，該晶片 230係為DDR3記憶體晶片’其頻率係超過5〇〇MHz以 上。此外，該晶片2 3 0之背面較佳為顯露狀或另貼設 一散熱片（圖未繪出），以增加散熱效果。 該些外接端子2 4 0係設置於該基板2 1 0之該第二表 面2 12 ’以供對外接合。在本實施例中，該些外接端 子240係包含銲球（solder ball)，其係設置於該些球墊21 5 " 上。在不同實施例中，可利用錫膏、金屬球、金屬栓 或ACF導電膠置換銲球而成該些外接端子24〇。 藉由在該些凸塊23 3周圍的多階段黏晶層220，當 該些凸塊2 3 3金屬鍵合至該些凸塊接墊2 1 3，該晶片 230不易傾斜，以維持該些凸塊23 3之接合高度一致 化，不需要再填入底部填充膠（underfill material)。此 外，該晶片23 0與該基板2 1 0之間的電性連接係省略 以往的打線電性連接步驟，具有製程簡化的方便性。 9 200807659 配合第3A至3C圖，揭示該高頻積體電路封裝構 造200之製作過程。首先，如第3A圖所示，首先提供一 基板2 1 0，其第一表面2 11上係形成有複數個凸塊接墊2丨3， 其第二表面212上係形成有複數個球墊215。利用該線路層 217與該些電性導通孔216，電性連接該些凸塊接墊213與 戎些球塾215。接著，如第3 B圖所示，可運用鋼板印刷形 成一多階段黏晶層220於該基板210之該第一表面211上， 並在黏晶前預烤成B階，達到適當之支撐效果。 之後，如第3C圖所示，覆晶設置一晶片230於該基板 210之該第一表面211上，該晶片230之凸塊233係鍵合至 該些凸塊接墊213，並且該多階段黏晶層22〇係黏接該晶片 230之主動面231。最後，將該些外接端子24〇設置於該些 球墊2 1 5，並熟化該多階段黏晶層22〇並能製作得到如第2 圖所示之高頻積體電路封裝構造2〇〇。 請參閱第4圖，在本發明之第二具體實施例中，揭 示另一種一致化凸塊接合高度之高頻積體電路封裝構 300主要包含一基板310、一多階段黏晶層320、 一晶片33 0以及複數個外接端子34〇。該基板31〇係 具有一第一表面311與一第二表面312，其中該第一 表面3 1 1上係形成有複數個凸塊接墊3 1 3，該基板3 J 〇 之該第二表面3 1 2係形成有複數個球墊3丨6。該基板 3 1 〇另包含有複數個電性導通孔3丨7與至少一線路層 3 1 8 ’以電性連接該些凸塊接墊3丨3與該些球墊3丨6。 在本實施例中，該基板3 i 〇係可為一電路薄膜，有利於 10 200807659 封裝薄化與輕量化。該多階段黏晶層3 2 0係形成於該基 板310之該第一表面311上。該晶片330係具有一主 動面331以及複數個在該主動面331上之凸塊333， 該晶片3 3 0係覆晶設置於該基板3 1 0之該第一表面3 1 1 上’以使該些凸塊333鍵合至該些凸塊接墊313，並 且該多階段黏晶層3 2 0係黏接該晶片3 3 0之該主動面 33 1 °較佳地，該些凸塊333係設置在該晶片330之銲墊 3 32上方，以省略習知覆晶晶片之重配置線路層。該些外接 端子340係設置於該基板之該第二表面3 12，該些外 接端子340係可包含銲球（solder ball)。較佳地，如第5 圖所示，每一凸塊接墊3 1 3係具有一凹陷區3 1 4，以增 加對該些凸塊333之接合面積，並防止該些凸塊333 之塌散。在本實施例中，該些凸塊3 3 3係為錫鉛凸塊， 且該些凸塊接墊3 1 3係形成有一鎳金層3 1 5，以回焊 方式達到金屬鍵合。由於在本實施例中，該晶片330 以回焊取代熱壓合達到覆晶接合作業’當該多階段黏 晶層3 2 0的供給量未能密封該些凸塊3 3 3，該高頻積 體電路封裝構造300可另包含有一封膠體3 5 0，其係 形成於該基板3 1 0之該第一表面3 1 1並可密封該晶片 33〇’更可填入該晶片330下方之空隙處，以防止填膠 不貫產生爆米花（popcorn)現象。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 施例揭露如上，然而並非用以限定本發明，任何熟悉 11 200807659 ，所作的 於本發明 本項技術者，在不脫離本發明之技術範圍内 任何簡單修改、等效性變化與修飾，均仍屬 的技術範圍内。 【圖式簡單說明】 面示意圖。 一種一致化 裳構造之& 第1圖：一種習知積體電路封裝構造之截 第2圖··依據本發明之第一具體實施例， 凸塊接合高度之高頻積體電路封 面示意圖。In the above-described high-frequency integrated circuit package structure, the external terminals comprise fresh balls. In the above-described high-frequency integrated circuit package structure, the wafer is a DDR3 memory chip. The a-base substrate is a circuit film in the above-described high-frequency integrated circuit package structure. In this case, the substrate is close to the above-described high-frequency integrated circuit package. [Embodiment] Referring to FIG. 2, in the first embodiment of the present invention, a high-frequency integrated circuit package structure 200 of uniformized bump bonding height mainly includes a substrate 2 1 0, a multi-step i ; L ^ n where the sticky layer 9 layers 2 2 0, a wafer 230 and a plurality of external terminals 24 〇. The substrate 210 has a second -2i2, wherein the first surface 211 has a 2U and a second surface 2 1 3 . The substrate 210 can be printed, has a plurality of bump pads, a P-brush circuit board or a circuit film. Preferably, the substrate 210 is a circuit film such as a COF flexible film, which is advantageous for thinning, lightweight, and reduced thermal resistance of the package. Further, in the present embodiment, the substrate 210 is accessible to the wafer size. The second surface 2 1 2 of the substrate 210 is formed with a plurality of ball pads 2 15 . The substrate 2 10 further includes a circuit layer 217 on the first surface 211 and a plurality of electrical vias 21 163 extending therethrough for electrically connecting the bump pads 2 1 3 of the substrate 2 1 0 with The ball pads 2 15 . In addition, the first surface 21 of the substrate 210 may be formed with a solder resist layer (not shown) to partially cover the circuit layer 217 of the substrate 210. The multi-stage adhesive layer 220 is formed on the first surface 21 of the substrate 210. The multi-stage adhesive layer 22 includes a multi-stage curing resin. For example, the multi-stage adhesive layer 220 can be printed on the substrate 210 in the A-stage, and the substrate is baked. Locally curing the multi-stage adhesive layer 220 to the B-stage, which has a die-forming property and is attached to the substrate 2 in a film type, at the time of final product shipment; The multi-staged die layer 220 will be fully cured to the C-stage. In addition, in various embodiment variations, the multi-staged polycrystalline layer 220 of the b-stage can be further subdivided into more mature localized states of the order, such as B1, B2, B3, and the like. The wafer 230 has an active surface 231 and has a plurality of bumps 233 on the active surface 231. The wafer 230 is overlying the first surface 21 1 of the substrate 2 1 , so that the bumps 2 3 3 are metal bonded to the bump pads 2 1 3 , and the multi-stage The adhesive layer 220 is bonded to the active surface 231 of the wafer 23 . By using the multi-stage 8 200807659 adhesive layer 220 to maintain the flip-chip bonding gap and the pasting wafer, the wafer 23 〇 does not need to be fabricated with a reconfigured wiring layer (RDL), and the bumps 233 can be directly disposed on the original of the wafer 230 Above the plurality of pads 232, located in the center or periphery of the main surface 231. In this embodiment, the bumps 23 3 are gold bumps, and the bump pads 2 1 3 are formed with a solder layer 2 1 4 ′ to weld the bumps 23 3 to cover the bumps 23 3 . Electrical connection of the crystal bond. Therefore, the electrical connection path between the wafer 230 and the substrate 210 is short, and the bonding height of the bumps 233 is uniform, and the gold wire formed by the wire/wire is not required, and the conventional flip chip is omitted. Reconfigured Line Layer (RDL) for low cost, high frequency packages. Preferably, the wafer 230 is a DDR3 memory chip having a frequency system exceeding 5 〇〇 MHz. In addition, the back surface of the wafer 230 is preferably exposed or otherwise provided with a heat sink (not shown) to increase the heat dissipation effect. The external terminals 240 are disposed on the second surface 2 12 ′ of the substrate 2 10 for external bonding. In this embodiment, the external terminals 240 include solder balls disposed on the ball pads 21 5 ". In various embodiments, the solder balls may be replaced by solder paste, metal balls, metal plugs or ACF conductive paste to form the external terminals 24A. By the multi-stage adhesion layer 220 around the bumps 23 3 , when the bumps 2 3 3 are metal-bonded to the bump pads 2 1 3 , the wafer 230 is not easily tilted to maintain the The joint height of the bumps 23 3 is uniform, and it is not necessary to refill the underfill material. Further, the electrical connection between the wafer 230 and the substrate 210 is omitted from the conventional wiring electrical connection step, and the process is simplified. 9 200807659 In conjunction with Figures 3A through 3C, the fabrication process of the high frequency integrated circuit package structure 200 is disclosed. First, as shown in FIG. 3A, a substrate 2 1 0 is first provided, and a plurality of bump pads 2 丨 3 are formed on the first surface 2 11 , and a plurality of ball pads are formed on the second surface 212 . 215. The bump pads 213 and the ball pads 215 are electrically connected to the circuit pads 217 and the electrical vias 216. Then, as shown in FIG. 3B, a multi-stage adhesive layer 220 may be formed on the first surface 211 of the substrate 210 by using a steel plate, and pre-baked into a B-stage before the bonding, to achieve an appropriate supporting effect. . Then, as shown in FIG. 3C, a wafer 230 is disposed on the first surface 211 of the substrate 210, and the bumps 233 of the wafer 230 are bonded to the bump pads 213, and the multi-stage The bonding layer 22 is adhered to the active surface 231 of the wafer 230. Finally, the external terminals 24 are disposed on the ball pads 2 15 , and the multi-stage adhesive layer 22 is cured, and the high-frequency integrated circuit package structure as shown in FIG. 2 can be fabricated. . Referring to FIG. 4, in a second embodiment of the present invention, another high-frequency integrated circuit package 300 for unifying bump bump height is disclosed. The main assembly 300 includes a substrate 310, a multi-stage adhesive layer 320, and a The wafer 33 0 and a plurality of external terminals 34 are. The substrate 31 has a first surface 311 and a second surface 312. The first surface 31 is formed with a plurality of bump pads 3 1 3 , and the substrate 3 J 〇 the second surface The 3 1 2 system is formed with a plurality of ball pads 3丨6. The substrate 3 1 〇 further includes a plurality of electrical vias 3 丨 7 and at least one wiring layer 3 1 8 ′ to electrically connect the bump pads 3 丨 3 and the ball pads 3 丨 6 . In this embodiment, the substrate 3 i can be a circuit film, which is beneficial to the thinning and light weight of the package 10 200807659. The multi-stage adhesive layer 300 is formed on the first surface 311 of the substrate 310. The wafer 330 has an active surface 331 and a plurality of bumps 333 on the active surface 331. The wafer 310 is over-molded on the first surface 3 1 1 of the substrate 310 to enable The bumps 333 are bonded to the bump pads 313, and the multi-stage adhesive layer 320 is bonded to the active surface 33 1 0 of the wafer 330. Preferably, the bumps 333 The solder pads 3 32 are disposed over the pads 330 of the wafer 330 to omit the reconfigured wiring layers of the conventional flip chip. The external terminals 340 are disposed on the second surface 312 of the substrate, and the external terminals 340 may include solder balls. Preferably, as shown in FIG. 5, each of the bump pads 3 1 3 has a recessed portion 3 1 4 to increase the joint area of the bumps 333 and prevent the bumps 333 from collapsing. Scattered. In this embodiment, the bumps 3 3 3 are tin-lead bumps, and the bump pads 3 1 3 are formed with a nickel-gold layer 3 15 to achieve metal bonding by reflow. In the present embodiment, the wafer 330 is replaced by thermal recompression to achieve the flip chip bonding operation. When the supply amount of the multi-stage adhesive layer 320 is unable to seal the bumps 3 3 3 , the high frequency The integrated circuit package structure 300 may further include a glue body 350 formed on the first surface 31 of the substrate 310 and may seal the wafer 33' to be filled under the wafer 330. In the gap, to prevent the popping of the popcorn phenomenon. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed above by way of preferred embodiments, it is not intended to limit the invention, any familiarity with 11 200807659, It is within the technical scope of the present invention to make any simple modifications, equivalent changes and modifications within the technical scope of the present invention. [Simple description of the diagram] A conforming skirt structure & Fig. 1 is a cross-sectional view showing a conventional integrated circuit package structure. Fig. 2 is a schematic view showing a high-frequency integrated circuit of a bump bonding height according to a first embodiment of the present invention.

第3 A至3 C圖：依據本發明之第一具體實施士 ^ ，该高 頻積體電路封裝構造在製程中之基板截面示 意圖。 第4圖：依據本發明之第二具體實施例，另一種一致 化凸塊接合高度之高頻積體電路封裝構造之 截面示意圖。 第5圖：依據本發明之第二具體實施例，該高頻積體 電路封裝構造之其中一凸塊之局部放大截面 不意圖。 【主要元件符號說明】 100積體電路封裝構造 110 基板 111 第一 表面 112 第二 表面 113 槽孔 120 晶片 121 主動 面 122 銲墊 130 黏晶層 140 銲線 150 封膠 體 160 外接端子 12 200807659 200高頻積體電路封裝構造 210 基板 211 第一表面 212 213 凸塊接墊 214 銲料層 215 216 電性導通孔 217 線路層 220 多階段黏晶層 230 晶片 231 主動面 232 233 凸塊 240 外接端子 300 高頻積體電路封裝構造 310 基板 311 第一表面 312 313 凸塊接墊 314 凹陷區 315 316 球墊 317 電性導通孔 318 320 多階段黏晶層 330 晶片 331 主動面 332 333 凸塊 340 外接端子 350 封膠體 第二表面 球塾 銲塾 第二表面 鎳金層 線路層 鋅墊 133A to 3C: In accordance with a first embodiment of the present invention, the high frequency integrated circuit package is constructed in a cross-sectional view of a substrate in a process. Fig. 4 is a cross-sectional view showing another high-frequency integrated circuit package structure of a uniform bump-bonding height in accordance with a second embodiment of the present invention. Fig. 5 is a partially enlarged cross-sectional view showing one of the bumps of the high-frequency integrated circuit package structure according to the second embodiment of the present invention. [Main component symbol description] 100 integrated circuit package structure 110 substrate 111 first surface 112 second surface 113 slot 120 wafer 121 active surface 122 pad 130 adhesive layer 140 bonding wire 150 sealing body 160 external terminal 12 200807659 200 high Integral circuit package structure 210 substrate 211 first surface 212 213 bump pad 214 solder layer 215 216 electrical via 217 circuit layer 220 multi-stage bonding layer 230 wafer 231 active surface 232 233 bump 240 external terminal 300 high Integral circuit package structure 310 substrate 311 first surface 312 313 bump pad 314 recessed area 315 316 ball pad 317 electrical via 318 320 multi-stage adhesive layer 330 wafer 331 active surface 332 333 bump 340 external terminal 350 Sealant second surface ball 塾 soldering second surface nickel gold layer circuit layer zinc pad 13

Claims (1)

200807659 十、申請專利範圍： 1、一種一致化凸塊接合高度之高頻積體電路封裝構造，包 含： 一基板’其係具有一第一表面與一第二表面，其中該第 一表面上係形成有複數個凸塊接墊；200807659 X. Patent Application Range: 1. A high-frequency integrated circuit package structure having a uniform bump bonding height, comprising: a substrate having a first surface and a second surface, wherein the first surface is Forming a plurality of bump pads; 一多階段黏晶層，其係形成於該基板之該第一表面上； 一晶片，其係具有一主動面以及複數個在該主動面上之 凸塊，該晶片係覆晶設置於該基板之該第一表面上，以 使該些凸塊鍵合至該些凸塊接墊，並且該多階段黏晶層 係黏接該晶片之該主動面；以及 複數個外接端子，其係設置於該基板之該第二表面 如申1專利範圍第1項所述之一致化凸塊接合高度之高 頻積體電路封裝構造，其中每一凸塊接墊係具有一凹陷 區，以增加對該些凸塊之接合面積。 1項所述之一致化凸塊接合高度之高 3、如申請專利範圍第 /貝積體電路封裝構造’其中該些凸塊係為錫雜凸塊，且 / 一凸塊接墊係形成有_鎳金層。 4、 如申請專利範圍第i 頻積體電路封裝構造 些凸塊接墊係形成有 5、 如申請專利範圍第1 頻積體電路封裝構造 6、 如申請專利範圍第1 頻積體電路封裝構造 項所述之一致化凸塊接合高度之高 其中該些凸塊係為金凸塊，且該 一銲料層，以利焊熔該些凸塊。 項所述之一致化凸塊接合高度之高 ’其中該些外接端子係包含銲球。 項所述之一致化凸塊接合高度之高 ’其中該晶片係為DDR3記憶體晶 14 200807659 片。 7、 如申請專利範圍第1項所述之一致化凸塊接合高度之高 頻積體電路封裝構造，其中該基板係為一電路薄膜。 8、 如申請專利範圍第1項所述之一致化凸塊接合高度之高 頻積體電路封裝構造，其中該基板係接近晶片尺寸。 9、 一種一致化凸塊接合高度之高頻積體電路封裝方法，包 含： 提供一基板，其係具有一第一表面與一第二表面，其中 該第一表面上係形成有複數個凸塊接墊； 形成一多階段黏晶層於該基板之該第一表面上； 覆晶設置一晶片於該基板之該第一表面上，該晶片係具 有一主動面以及複數個在該主動面上之凸塊，該些凸塊 係鍵合至該些凸塊接墊，並且該多階段黏晶層係黏接該 晶片之該主動面；以及 設置複數個外接端子於該基板之該第二表面。 . 1〇、如申請專利範圍第9項所述之一致化凸塊接合高度之 高頻積體電路封裝方法，其中每一凸塊接墊係具有一凹 陷區’以增加對該些凸塊之接合面積。 11、 如申請專利範圍第9項所述之一致化凸塊接合高度之 高頻積體電路封裴方法，其中該些凸塊係為錫鉛凸塊， 且該些凸塊接墊係形成有一鎳金層。 12、 如中請專利範圍第9項所述之一致化凸塊接合高度之 高頻積體電路封裝方法，其中該些凸塊係為金凸塊，且 該些凸塊接墊係形成有一銲料層，以利焊熔該些凸塊。 15 200807659 13、 如申請專利範圍第9 高頻積體電路封裝方法 14、 如申睛專利範圍第$ 高頻積體電路封裝方法 晶片。 1 5、如申请專利範圍第$ 高頻積體電路封裝方法 1 6、如申請專利範圍第9 高頻積體電路封裝方法 項所述之一致化凸塊接合高度之 ’其中該些外接端子係包含鲜球。 項所述之一致化凸塊接合高度之 ’其t該晶片係為DDR3記憶體 項所述之一致化凸塊接合高度之 ，其中該基板係為一電路薄膜。 項所述之一致化凸塊接合高度之 ’其中該基板係接近晶片尺寸。 16a multi-stage adhesive layer formed on the first surface of the substrate; a wafer having an active surface and a plurality of bumps on the active surface, the wafer is flip-chip disposed on the substrate On the first surface, the bumps are bonded to the bump pads, and the multi-stage adhesive layer is bonded to the active surface of the wafer; and a plurality of external terminals are disposed on the first surface The second surface of the substrate is a high-frequency integrated circuit package structure of a uniform bump-bonding height as described in claim 1 wherein each bump pad has a recessed region to increase the The joint area of the bumps. The height of the uniformized bump bonding height of the first item is as described in claim 1, wherein the bumps are tin bumps and / a bump pad is formed _ Nickel gold layer. 4. In the patent application scope, the i-th frequency body circuit package structure has some bump pads formed, and the first frequency body circuit package structure 6 as in the patent application scope, such as the patented range first frequency body circuit package structure. The height of the uniform bump bonding height is high, wherein the bumps are gold bumps, and the solder layer is used to solder the bumps. The uniformized bump bonding height described in the item is where the external terminals comprise solder balls. The uniformized bump bonding height described in the item is 'the DDR3 memory crystal 14 200807659 piece. 7. The high-frequency integrated circuit package structure of the uniform bump bonding height as described in claim 1, wherein the substrate is a circuit film. 8. The high frequency integrated circuit package structure of the uniform bump bump height as described in claim 1, wherein the substrate is close to the wafer size. A method for packaging a high-frequency integrated circuit of a bump bump height, comprising: providing a substrate having a first surface and a second surface, wherein the first surface is formed with a plurality of bumps a pad; forming a multi-stage adhesive layer on the first surface of the substrate; flip chip is provided with a wafer on the first surface of the substrate, the wafer has an active surface and a plurality of active surfaces a bump, the bumps are bonded to the bump pads, and the multi-stage adhesive layer is bonded to the active surface of the wafer; and a plurality of external terminals are disposed on the second surface of the substrate . The method of claim 1, wherein each bump pad has a recessed portion to increase the bumps. Joint area. 11. The method of sealing a high-frequency integrated circuit of a uniform bump height according to claim 9, wherein the bumps are tin-lead bumps, and the bump pads are formed Nickel gold layer. 12. The high frequency integrated circuit packaging method of the uniform bump bonding height according to claim 9, wherein the bumps are gold bumps, and the bump pads are formed with a solder. Layers to facilitate the fusion of the bumps. 15 200807659 13, such as the scope of patent application ninth high-frequency integrated circuit packaging method 14, such as the scope of the patent range of the high-frequency integrated circuit packaging method wafer. 1 5, as claimed in the patent range No. 1 high-frequency integrated circuit packaging method 16. The uniformized bump bonding height as described in the ninth high-frequency integrated circuit packaging method of the patent application scope, wherein the external terminal systems Contains fresh balls. The uniformized bump bonding height of the item is 'the wafer is the uniform bump bonding height described in the DDR3 memory item, wherein the substrate is a circuit film. The uniformized bump bond height described in the item wherein the substrate is close to the wafer size. 16
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