TWI311737B

TWI311737B - Structure of display panel

Info

Publication number: TWI311737B
Application number: TW94140407A
Authority: TW
Inventors: Hung-Ju Kuo; Chien-Hsiang Huang; Ming-Chun Tseng
Original assignee: Chi Mei El Corporatio; Chi Mei Optoelectronics Corporatio
Priority date: 2005-11-17
Filing date: 2005-11-17
Publication date: 2009-07-01
Also published as: TW200721071A

Description

1311737 16746twfl .doc/006 96-2-27 九、發明說明：【發明所屬之技術領域】本發明是有關於-種顯示面板的結於-種共用陰極線之顯示面板的結構。且特別疋有關【先前技術】由於多媒體社會的急速進步，的技術也隨之具有飛躍性的進步。就顯示哭而i顯=裂置機發光顯示器具有無視角限制、低製造成:而:庫= 流驅動、工作溫度範圍大以及重量輕且可器的直此，有機電光付時代顯示器的特性要求。因力，可望具魏大的發展潛缺 r世代的新穎平面顯示器。後，；：成：有機電激發光二極體顯示器在長時間工作 ν-ge)隨時ί:::，薄臈二晶體的工作電流下 , 而造成了流财機鱗光二極體亮度表現，這將合，需要更高的操作電虔以得到相同的命。、麵激發光二極體顯示ϋ的使用壽[Technical Field] The present invention relates to a display panel of a display panel having a common cathode line. And especially related to [Prior Art] Thanks to the rapid advancement of the multimedia society, the technology has also made rapid progress. It shows that crying and i display = splicing machine illuminating display has no viewing angle limitation, low manufacturing: and: library = flow drive, operating temperature range and light weight and can be straight, the characteristics of organic electro-optical display . The force is expected to have the development potential of Wei Da. After:: into: organic electroluminescent diode display in the long-term work ν-ge) anytime ί:::, thin 臈 two crystals under the operating current, and caused the lumens of the dioxin brightness performance, this The combination will require a higher operating power to get the same life. , surface excitation light diode shows the use life of ϋ

Daw細)d述的問題，習知由道森(RobinMarkAdrian —種可簡償電晶第6229506號專利中提出器。請參照圖 —| %堊的有機激發光二極體顯示之晝素結構。龙j/、緣示了此種有機激發光二極體顯示器、電阳體101的源極端輕接資料線η， 5 1311737 16746tw] fldoc/〇〇6 96-2-27 電晶體101的閘極端耦接掃描線13，晶體10!的沒極端與電晶體⑽㈣電接電的源極端祕直流電源Vdd，電容c s ’電晶體103 之間極端與其源極端之間；電晶體 ==103 制線15,電晶體105的源極端輕接。=接至控端，而電晶體1〇5的汲極端_接至電= 體〇3的閘極與電晶體107的源極端；電晶體 =—的汲極端 17 ’而電晶體107的汲極端_接至有執接控制線 111的陽極端；此外，有機電 =激發光二極體則接地。極體⑴的陰極端雖然圖1中的書音I m 111的電流不受電晶體阳的機發光二極體在有以下缺點： 1.由於-個畫素内配置有四個線(Layout)上的_度增加，且其Μ會造成佈也會造戍 %示面板之 2.由於-個畫素内的元件太多’二、、會因此增加開口率的低落。【發明内容】因此，本發明的目的電路’可以使得4素電路内Ϊ工作板和書素電壓的影響。作電流不弩略旦京 ,^ 兒晶體之臨界本發明的另一目路，可以崎電路的=供〜種顯、板和畫素電 6 1311737 16746twfl.doc/006 96-2-27 本發明提供-種顯示面板，其方向平行排列的掃描線，以及多數條以排列的資料線。另外，在本發方=平行 t括了千订於㈣線的多數條陰 ^ ”線的交錯處，則配置有—晝素電路在:每晝ί電路，都耦接相同的陰極線。特別的是'在極二壓、'7:條陰極線都透過—開關電路而耦接至-阶開關電路都依據-控制訊號而決定是：將陰極電麼導通至對應的陰極線。义疋古用於提:-種畫素電路，其適 _。其中，外部開陰極電麼導通至晝素電路。而在本發明中r包括、==將，體’其陰極端透過外躺關_接錢陰，- 陽極端則耦接了—第—雕 "電&，而其體的間極端透過—電容第—電晶壓三另外，本發明也包括了第二電晶體%極電四電晶體和第五電晶體。其中，带弟―甩日日體、第掃描線，以接收—掃描訊號，而第二電曰體的、、電晶體之_和二 ^日日-的閘極糕和源極端分別耦接上貢料線，以接收掃描訊號和—資料訊號，=線和-沒極端_接第-電晶體的源極端。除〜普晶體的體的卿嶋1晶體之源極端，而第四電以 1311737 16746twfl.doc/〇〇6 96-2-27 極端和源極端則分別耦接控制訊訊號與掃描訊號為反相。而第五電曰m的电昼，其中控制至第-電晶體之閘極端，其閘極曰：的〆及極端則是耦接接，並轉接至顯示面板中的前-條掃°描=端則彼此互軸以透明二供-種晝素電路，其可 ::據制訊號而決定是否將陰極電== 電路。本發明包括了—發电皂¥通至晝素關而耦接至陰極電壓，—，，、陰極端透過外部開極端，並且第二，極端_接第—電晶體的沒容互相婦同；η::極端還透過-第-電險描雷授从限4 1日日體的源極端則耦接了—大於麵接-資料線和二掃描;:】;:==^極端分別號々，並且第二電晶體的汲極端則是透===婦描訊至第-電晶體的閘極端。而第曰俨厂奋而耦接分別輕接第—電曰㈣—电日曰體的源極端和汲極端 -第二控制訊;間極端和汲極端，其一 ^ 攸本叙明另—觀點來看，本 ::也適用於顯示面板，並且二=一第= 4=:陰極電壓。其中第-外部開關會依據發===壓”。同樣地= 輕接至陰極電^而豆i “極端透過第—外部開關而 _，而其陽極端_接„第—電晶體的汲極 1311737 16746twfl.doc/006 96-2-27 :極:Γ 電ί體的源極端_接-大於陰極電壓的 =ί ’ ί發明也包括了—第二電晶體和第i電曰曰-八中弟一電晶體的間極描線和一資料線，以接收—掃描訊號和 ΐ;:__三電晶體的源極端。：外；二^體之雜端纽極端彼此互相至第-電晶體的閘極端。除此之外，：且、同耦接第-電晶體之源極端的Γ端：:，對於據定是否減至-重置則依據—重置訊號，而決從另-觀點來看，本發明還提供了—種顯示面板，其絲，*錄底上則配置了多_晝素結構，並且各該晝素結構都包括了—薄膜電晶 =上賴了，第'絕緣層，並且在第牛—=二面具有-孔洞。喊-陽極電極，細第二方向延伸而形 i在上：並且藉由細連接至薄膜電晶體。另 Μ在本巾’騎括—第二絕緣層，健蓋住孔洞以及第-絕緣層之曝露部份。而在第二絕緣層上，則配置了至少兩個間隔壁結構。這些間隔壁結構係延伸向第一方向’並配置在4素結構的兩侧。在兩個間隔壁結構之間的 =，還配ί有—有機層，係延伸向第—方向，並且形成在第-、％緣層與&極電極之上，以用來發光1在有機層的上方以及，隔壁結構之間的區域，又覆蓋了—層陰極電極，同樣也是延伸向第—方向。而陰極電極職接了一開 ^311737 Γ5746 6twfl.doc/006 96-2-27 直流觸送據-編號而決定是否將一中，由於具有補償之畫素電路晝素電路内的元件 =曰曰體和電各，因此整個如是有機發光二極體的;先口元:個:容外加-個例晝素電路的元件較少，因於本發明内之口率就可以提升，而B ^ ,嗌月所棱供之顯示面板的開為讓本翻之的元㈣減少辦之消耗。易懂，下文特舉目的、特徵和伽能更明顯明如下。佳心例’並配合所附圖式，作詳細說【實施方式】例。其中該些圖亍，明本發明的較佳實施下所敘述之電晶體的心，月各種較佳實施例。而以明較佳的實施例。然而歹'PM0S電晶體’均為本發況將其改換為其他_ =習此技藝者可以依據實際的狀的精神造成影響。、、电晶體，而並不會對本發明主要於下以所卜敘述的陽極電壓的電壓值’都會大加以解釋。 i，而在以下各段中將不會再特別圖2緣示了依照本發明板的電路圖。妹來听較佳只施例的一種顯示面 u'圖2 ’在本發明所提供的顯示面板200 1311731,,oc/006 96-2-27 中，配置了數條沿第一方向平杆扭^ α ?〇7 . 9〇4, 、，R $十仃排列的掃描線(例如掃描線 202和204)，亚且配置了數條沿第二 = 線(例如資料線212)。其中，第— 丁二= 列。另外，在顯不面板200中還包括 ^ ，線，而這些陰極線與掃描線是彼此; ί 線者!透過一開關而耦接至陰極電壓vss，並且 =開關雜據-㈣職μ定導通至對躺陰轉。 vss ^如，陰極線222透過開關電路232而至 m 開關電路232會依據控制訊紅別而決定i 否將陰極電壓vss導通至陰極線222。疋在每-掃描線和資料線的交會處，都配置有一路。例如，在掃描線202與資料後212 Μ ^ 書辛雷敗*山，、貝行琛212的父會處，配置有 - ^電路242。其巾，同—聽線上的晝素電路會例如，掃描線202上_的所有畫素電路都共冋耦接陰極線222。電路===第一實施例的-種晝素電路之資料電路300麵接了掃描線332和读=34。另外，晝素電路3〇〇還藉由陰極線336，並且化汗關電路35〇而轉接至陰極電壓vss。二，田，332上的掃描訊號Sn—N彼此為反相。 5月繼續參關3，晝素電路3GQ包括了 PMqS電晶體 I3117M 6twfi.doc/006 96-2-27 όΌΖ 中，發x光二:體3Γ和補償電路31G。在本發明的實施例接陰極線336，甘Γ以是有機發光二極體，其陰極端麵極^。、，而，、陽極端則麵接PM〇S電晶體302的汲 PMQS 電晶體312、314、輪雜請 L= 2㈣2的閘極端則透過掃描_而耗电日日體314的閘極端。PM〇s電晶體314 =端輕接資料線334’而其汲極端縣接pM〇s電晶體二 H，並且也柄接至t _观。丨外PM〇S電晶體316的源極端^+ 並且透過電容322而耦接==== 極端和_電晶體312的源極端，而_二:2體：控制訊號CE。另外，_電晶體318 =二源極端，而_S電晶魏的源極 =Sn—則。例如，圖2中的晝素電路244除了接收=; ⑽所傳_掃描訊狀外，還會接所傳輸的掃描訊號。 202 在本實施例中，開關電路350包括PM〇s電 ^ vPs=電晶體352的源極端和開極端分_接陰極电[VSS和控制訊號CE，而其汲極端則透過陰極線说 12 1311737 16746twfl.doc/006 而麵接至發光二極體304的陰極端。圖4繪示圖3之畫素電路的訊號時序圖。請合併參照圖3和圖4 ’在T0時’掃描訊號Sn—N-1和Sn_N都為高準位VH的狀態。而由於控制訊號CE與掃描訊號Sn_N彼此反相，因此在T0時’控制訊號ce為低準位VL的狀態。在T1時’掃描訊號sn_N-l下拉至低準位Vl狀態，因此PMOS電晶體318會導通(Turn On)。同時間，PMOS 电晶體312、314為關閉(Turn 〇ff)狀態，另外，pM〇s電響晶體352、316則是導通的狀態。此時，節點A1的電壓為 VL+Vth，而節點B1的電壓則是VDD。其中，vth為pM〇s 電晶體302的臨界電壓。在T2時，掃描訊號Sn—N-1回復至高準位VH的狀態，而輪到掃描訊號Sn_N下拉至低準位VL的狀態。而由於控制訊號OE和掃描喊Sn—N彼此反相，因此控制訊號 CE g上升至尚準位狀態vh。因此，pM〇s電晶體316、 318和352會關閉，而PM0S電晶體312和314則是導通。 φ晝素資料會從資料線334送入晝素電路_内。也，是說，在資料線上會產生一個資料電壓Vdata，以致於節點B1的電壓準位會等於資料電壓，而使得節點 A1的電壓準位會等於vdata_vth，並且會對電容奶充電。在丁3時，掃描訊號Sn一N會回到高準位VH的狀能， =於控制訊號CE會回到低準位VL的狀態。此時，pM；s 電晶體302和352會導通，並將陰極電壓vss導通至發光二極體304的陰極端’使得PM〇s電晶體3〇2會產生:作 13 Ι31171 fl-doc/006 96-2-27 電流II流經發光二極體304。藉此，被驅動而發光。同時間，PM0S電曰 —^ _ 304就會於電容322所儲存的能量，節點J的電而由 V為：一是咖的t壓心出：眾所皆知的’工作電流11可以用以下的方程式來求Daw fine) The problem described by Dawson (Robin Mark Adrian, a kind of device that can be used in the patent No. 62295506. Please refer to the figure -| %垩's organic excitation light diode shows the structure of the element. j/, the source of the organic excitation light diode display, the source terminal of the electric body 101 is lightly connected to the data line η, 5 1311737 16746tw] fldoc/〇〇6 96-2-27 the gate terminal of the transistor 101 is coupled The scan line 13, the crystal 10! is not extremely connected to the source of the transistor (10) (four), the source of the extreme DC power supply Vdd, the capacitor cs 'the transistor 103 between the extreme and its source terminal; the transistor == 103 line 15, the electricity The source of the crystal 105 is extremely lightly connected. = is connected to the control terminal, and the 汲 terminal of the transistor 1 〇 5 is connected to the gate of the body 与 3 and the source terminal of the transistor 107; the 汲 terminal 17 of the transistor = - 'And the 汲 terminal of the transistor 107 is connected to the anode end of the control line 111; in addition, the organic electric=excitation diode is grounded. The cathode end of the polar body (1) is the book sound I m 111 in Fig. 1. The machine-emitting diodes whose current is not affected by the transistor are defective in the following ways: 1. Since there are four components in the pixel The _ degree on (Layout) is increased, and the Μ will cause the cloth to be 戍戍戍戍示 2 2 2 2 2 2 2 2 2 2 2 2 2 2 由于由于由于由于。。。。。。。。。。。。。。。 Therefore, the object circuit of the present invention can make the influence of the working plate and the pixel voltage in the 4-cell circuit. The current is not a little bit of a nucleus, and the criticality of the crystal of the invention is another path of the invention. ~ Display, board and pixel electricity 6 1311737 16746twfl.doc/006 96-2-27 The present invention provides a display panel in which the scanning lines are arranged in parallel, and a plurality of data lines are arranged in series. The sender=parallel t encloses the intersection of the majority of the 阴^” lines of the (four) line, and is configured with the 昼-电路 circuit: every 昼ί circuit, the same cathode line is coupled. Especially the 'at the pole The second voltage, '7: the cathode line is transmitted through the switch circuit and coupled to the -step switch circuit are determined according to the control signal: the cathode is electrically connected to the corresponding cathode line. Prime circuit, which is suitable for _. Among them, the external open cathode electricity is turned on to 昼In the present invention, r includes, == will, the body 'the cathode end passes through the outer lying off _ the money is yin, the anode end is coupled to the - the first eagle " electric & Between the extreme transmission and the capacitance-electro-optic pressure, in addition, the present invention also includes a second transistor, a nano-electrode, and a fifth transistor, wherein the younger brother, the Japanese body, and the scan line are received. - scanning the signal, and the gate electrode and the source terminal of the second electric body, the transistor, and the second day are respectively coupled to the tributary wire to receive the scanning signal and the data signal, the = line and - There is no extreme _ connected to the source terminal of the transistor. Except for the source of the crystal of the crystal, the fourth source is 1311737 16746twfl.doc/〇〇6 96-2-27. The extreme and source extremes are respectively coupled with the control signal and the scanning signal are inverted. . And the electric 第五 of the fifth electric 曰m, wherein the control is to the gate end of the first transistor, the 〆 and the extreme of the gate 曰: are coupled and transferred to the front-strip scanning in the display panel The = terminal is mutually coaxial with a transparent binary-type halogen circuit, which can: determine whether the cathode is == circuit according to the signal. The invention includes that the power generation soap is connected to the cathode voltage, and the cathode end is transmitted through the external open end, and the second, the terminal is connected to the second crystal; η::Extreme is also transmitted through the -first-electric hazard. The source terminal of the Japanese body is coupled to - the greater than the face-to-wire and the second scan;:];:==^ And the 汲 extreme of the second transistor is through the === female tracing to the gate terminal of the first-transistor. The Dijon factory is coupled to each other and is connected to the first-electron (4)--the source of the electric scorpion and the extremes of the scorpion - the second control message; the extreme and the extreme, the ^ 叙叙另另另Look, this:: also applies to the display panel, and two = one = 4 =: cathode voltage. The first-external switch will be based on the hair===pressure. Similarly, the light is connected to the cathode and the bean is “extremely transmitted through the first-external switch and the anode terminal is connected to the drain of the first transistor”. 1311737 16746twfl.doc/006 96-2-27 : Pole: Γ The source of the ί body is extremely _ connected - greater than the cathode voltage = ί ' ̄ The invention also includes - the second transistor and the ith 曰曰 - eight The inter-electrode trace of a transistor and a data line to receive-scan signals and ΐ;:__ the source terminal of the three-transistor:: outer; the hetero-terminal end of the two-body to each other to the first-transistor The gate is extreme. In addition, the terminal of the source terminal of the first-transistor is coupled to: -, whether it is reduced to - reset, based on - reset signal, and from another point of view It is to be noted that the present invention also provides a display panel, wherein the wire and the bottom of the recording are provided with a multi-cell structure, and each of the pixel structures includes a thin film electrocrystal=the upper insulating layer And on the first cow -= two sides have - holes. Shouting - anode electrode, extending in the second direction and forming i on: and by fine connection to the thin film transistor. The cover is provided with a second insulating layer to cover the exposed portion of the hole and the first insulating layer, and on the second insulating layer, at least two partition walls are disposed. Extending to the first direction 'and arranging on both sides of the four-layer structure. Between the two partition walls, = also with - organic layer, extending to the first direction, and forming at the -, % edge Above the layer and the & pole electrode, for emitting light 1 above the organic layer and between the partition structure, covering the layer of the cathode electrode, also extending to the first direction. The cathode electrode is connected One open ^ 311737 Γ 5746 6twfl.doc / 006 96-2-27 DC touch data - number to determine whether it will be one, because the components in the pixel circuit with compensation pixel circuit = body and electricity, therefore The whole is as an organic light-emitting diode; the first mouth element: one: the externally-added element has fewer components, because the mouth rate in the invention can be improved, and B ^, the display of the moon The opening of the panel is to reduce the consumption of the yuan (4). The purpose, features and gamma energy of the article are more clearly as follows. The example of the present invention is described in detail with reference to the accompanying drawings, which are described in detail in the preferred embodiments of the invention. The heart of the transistor, various preferred embodiments of the month, and the preferred embodiment. However, the 'PM0S transistor' is changed to other conditions in this case. _ = This artist can be based on the actual situation The spirit of the invention, the transistor, and the voltage value of the anode voltage, which is not primarily described in the present invention, will be explained. i, and in the following paragraphs, there will be no special Fig. 2 The circuit diagram of the board in accordance with the present invention is shown. The girl listens to a display surface of the preferred embodiment. FIG. 2 'In the display panel 200 1311731 provided by the present invention, oc/006 96-2-27, a plurality of flat rods are arranged along the first direction. ^ α 〇 7 . 9 〇 4, , , R 仃仃仃仃 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 。。。。。。。。 Among them, the first - D = two = column. In addition, the display panel 200 further includes ^, lines, and the cathode lines and the scan lines are each other; ί line! coupled to the cathode voltage vss through a switch, and = switch impurities - (four) job μ to conduct to Lying on the yin. Vss ^ If the cathode line 222 passes through the switch circuit 232 and the m switch circuit 232 determines whether the cathode voltage vss is conducted to the cathode line 222 according to the control signal.配置 There is one way at the intersection of each scan line and data line. For example, in the parent line of the scan line 202 and the data 212 Μ ^ book Xin Lei defeat * mountain, and Bei Xing 琛 212, - ^ circuit 242 is arranged. For example, all of the pixel circuits on the scan line 202 are coupled to the cathode line 222. Circuit === The data circuit 300 of the pixel device of the first embodiment is connected to the scan line 332 and the read = 34. In addition, the halogen circuit 3 is also switched to the cathode voltage vss by the cathode line 336 and the sweat-off circuit 35A. Second, the scan signals Sn-N on the field 332 are inverted from each other. Continue to participate in 3 in May, the 3GQ of the halogen circuit includes the PMqS transistor I3117M 6twfi.doc/006 96-2-27 όΌΖ, the x-ray 2: body 3 Γ and the compensation circuit 31G. In the embodiment of the present invention, the cathode line 336 is an organic light-emitting diode having a cathode end face. In addition, the anode terminal is connected to the 〇 PMQS transistor 312, 314 of the PM〇S transistor 302, and the gate terminal of the L=2 (4) 2 is transmitted through the scan_ while the gate terminal of the solar body 314 is consumed. The PM 〇s transistor 314 = lightly connected to the data line 334' and the 汲 extreme county is connected to the pM 〇s transistor II H, and is also stalked to t_view. The source terminal of the external PM 〇S transistor 316 is ++ and coupled via the capacitor 322 ==== extreme and the source terminal of the _ transistor 312, and _ 2: 2 body: control signal CE. In addition, _ transistor 318 = two source extremes, while _S electromorphic Wei source = Sn - then. For example, the pixel circuit 244 of Fig. 2 receives the transmitted scan signal in addition to the received signal. 202 In the present embodiment, the switching circuit 350 includes a source terminal and an open terminal of the PM 〇 s ^ pus = transistor 352 _ connected to the cathode [VSS and control signal CE, and the 汲 terminal is transmitted through the cathode line 12 1311737 16746 twfl .doc/006 is connected to the cathode end of the light-emitting diode 304. 4 is a timing diagram of signals of the pixel circuit of FIG. 3. Please refer to Fig. 3 and Fig. 4' at the time of T0. The scanning signals Sn_N-1 and Sn_N are both in the state of the high level VH. Since the control signal CE and the scanning signal Sn_N are inverted from each other, the control signal ce is in the state of the low level VL at T0. At T1, the scan signal sn_N-1 is pulled down to the low level V1 state, so the PMOS transistor 318 is turned "Turn On". At the same time, the PMOS transistors 312, 314 are in the off (Turn 〇 ff) state, and the pM 〇 s motor crystals 352, 316 are in the on state. At this time, the voltage of the node A1 is VL+Vth, and the voltage of the node B1 is VDD. Where vth is the threshold voltage of the pM〇s transistor 302. At T2, the scan signal Sn_N-1 returns to the state of the high level VH, and it is the state that the scan signal Sn_N is pulled down to the low level VL. Since the control signal OE and the scan call Sn-N are inverted from each other, the control signal CE g rises to the still-state vh. Therefore, the pM〇s transistors 316, 318, and 352 are turned off, and the PMOS transistors 312 and 314 are turned on. The φ 昼资料 data will be sent from the data line 334 to the 昼电路 circuit. Also, it means that a data voltage Vdata is generated on the data line, so that the voltage level of the node B1 will be equal to the data voltage, so that the voltage level of the node A1 will be equal to vdata_vth, and the capacitor milk will be charged. At D3, the scan signal Sn-N will return to the high level VH, and the control signal CE will return to the low level VL state. At this time, the pM;s transistors 302 and 352 are turned on, and the cathode voltage vss is conducted to the cathode terminal of the light-emitting diode 304 so that the PM〇s transistor 3〇2 is generated: 13 Ι 31171 fl-doc/006 96-2-27 Current II flows through the light-emitting diode 304. Thereby, it is driven to emit light. At the same time, the PM0S 曰-^ _ 304 will store the energy stored in the capacitor 322, and the power of the node J will be V: one is the t-press of the coffee: the well-known 'operating current 11 can use the following Equation for

Ioled = /?/2(VSg-Vth)2 ⑴ 其中，Ioled為驅動發光二極體3〇4的工例中就是II，而Vsg則是PM〇s /瓜本貫施端之間的電壓，也就是等於節點Ioled = /?/2(VSg-Vth)2 (1) where Ioled is II in the case of driving the LED 3〇4, and Vsg is the voltage between the PM〇s / melon application. Equal to the node

Ai的電壓位準。由於節點A1的電壓咸去節點而節點B1的兩厭a -隹仿早等於Vdata-Vth ’ =第(1)式又可以寫成： = ^/2(VDD-Vdata)2 (2) 大小體：==^工作電流11 提供的*辛雷H 界電壓無關。因此，本發明不會隨_S電晶體302的臨界電 &。#所影響，並且進而增加發光二極體删的使用雖3所提供的畫素電路能夠解決臨界電壓的問法有在晝素電路内具有5個電晶體，因此還是無的-1圭本、開口率。圖5緣示了依照本發明第二實施例 ^路路之放大電路圖。請參照圖5，同樣地，晝素'路500耦接了掃描線532、資料線534和陰極線536。 14 131171, doc/006 96-2-27 較特別的是，畫素電路500還柄接了控制線538，以用來接收控制訊號AZ。在本實施例中，控制線538在例如圖2 的面板上，可以和掃描線平行排列。 +曰請繼續參照圖5,在晝素電路500巾，包括了 PM〇s 電晶體502，其祕端她陽極㈣VDD，其汲極端則 f例如是有機發光二極體之發光二極體元件綱的陽極發光一極體504的陰極端則藉由陰極線536而輕接電路54G。另外，在晝素電路= 了補償電路510。匕枯在，償電路510中，配置有pM〇s電晶體512和514。線糾=^3體2 512 ^源極端和閑極端分_接資料訊號Sn N，而'PMQS收資料電壓_和掃描 _至_s電日曰;^2曰=^及極端則透過電容训 514的源極端係耦接至PMJ ί 電晶體透過電宠SIS 1 电日日體502的閘極端，並且 # 電晶體514的閘極端輕極:接此外，PM〇S Μ，而PM0S電日日^線538，以接收控制訊號 502的沒極端。S —的及極端則輕接PMOS電晶體來實ΐ圖電路54°可以利用PMos電晶體542 訊號cE，而复、、^馬接陰極電壓vss，其間極端輕接控制二、及極知則耦接陰極線530。照圖5和圖6，^ ^之f素電路的訊號時序圖。請合併參The voltage level of Ai. Since the voltage of the node A1 is salty and the node is not the same as the Vdata-Vth of the node B1, the equation (1) can be written as: = ^/2(VDD-Vdata)2 (2) Size body: ==^ Operating current 11 is independent of the * Xinlei H boundary voltage. Therefore, the present invention does not follow the critical electric &#的影响, and further increase the use of light-emitting diodes. Although the pixel circuit provided by 3 can solve the critical voltage, there are five transistors in the pixel circuit, so there is still no -1 Opening ratio. Fig. 5 is a view showing an enlarged circuit diagram of a path in accordance with a second embodiment of the present invention. Referring to FIG. 5, similarly, the pixel 'way 500 is coupled to the scan line 532, the data line 534, and the cathode line 536. 14 131171, doc/006 96-2-27 More specifically, the pixel circuit 500 further handles the control line 538 for receiving the control signal AZ. In the present embodiment, control line 538, for example on the panel of Figure 2, may be arranged in parallel with the scan lines. + 曰Please continue to refer to FIG. 5, in the battery board 500, including the PM〇s transistor 502, the secret end of her anode (four) VDD, and the extreme end f is, for example, the light-emitting diode component of the organic light-emitting diode. The cathode end of the anode light-emitting diode 504 is lightly connected to the circuit 54G by the cathode line 536. In addition, the compensation circuit 510 is replaced by the pixel circuit. In the compensation circuit 510, pM〇s transistors 512 and 514 are disposed. Line correction = ^ 3 body 2 512 ^ source extreme and idle extreme points _ connected to the data signal Sn N, and 'PMQS receive data voltage _ and scan _ to _s electric day 曰; ^ 2 曰 = ^ and extreme through the capacitance training The source terminal of 514 is coupled to the PMJ ί transistor through the gate terminal of the electric pet SIS 1 electric solar body 502, and the gate of the transistor 514 is extremely light: in addition, PM〇S Μ, and PM0S electricity day Line 538, to receive control signal 502, is not extreme. S- and extreme-light PMOS transistors can be used to calculate the circuit 54° can use PMos transistor 542 signal cE, and complex, ^ horse connected to the cathode voltage vss, during which the extreme light control 2, and the know-how coupled Cathode line 530. See Figure 5 and Figure 6, the signal timing diagram of the circuit. Please merge the parameters

在T0蚪，掃描訊號Sn—N、控制訊號AZ 15 13117况_ .doc/006 96-2-27 和CE都為高準位，以致於pM〇s電晶體$ i 2、$ 都是關閉的狀態。 ~ 在ϋ時’掃描訊號Sn—N由高準位 PMOS電晶體512會導通。才At T0蚪, the scanning signal Sn—N, the control signal AZ 15 13117 _ .doc/006 96-2-27 and CE are all high level, so that the pM〇s transistors $ i 2, $ are all closed. status. ~ When the scan signal Sn-N is turned on by the high level PMOS transistor 512. only

Ik P在T2日守’控制訊號Az也由高準位轉為低準位，因此PMOS电晶體514就會導通，使得pM〇s電晶體5〇2 的間極端和沒極端可以看作短路。此時，PMOS電晶體502 ==1一個二極體’而其閘極電壓就可以表示為 VDD-Vth ’在此稱此間極電壓為偏移臨界電壓侧，也可以被^作PMOS電晶體5〇2最新的臨界電壓。以上的步 2疋要對PMOS電晶體5〇2的臨界電壓進行程式化 tg_ming)，崎到所需要的臨界電壓，也就是偏移臨界電壓Vthl。妾著在T3日守，控制訊號az又會回到高準位，使得 PMOS電晶體514關閉。 ^Τ4時’晝素資料會從資料線534送入晝素電路· ± ί疋說在貝料線534上會產生資料電壓vdata。 ¥ ’節點B2和A2的電壓差(^)可以表示為：Ik P is on the T2 day. The control signal Az is also switched from the high level to the low level. Therefore, the PMOS transistor 514 is turned on, so that the extreme and non-extreme of the pM〇s transistor 5〇2 can be regarded as a short circuit. At this time, the PMOS transistor 502 ==1 one diode ' and its gate voltage can be expressed as VDD-Vth 'here, the inter-electrode voltage is referred to as the offset threshold voltage side, and can also be used as the PMOS transistor 5 〇 2 latest threshold voltage. In the above step 2, the threshold voltage of the PMOS transistor 5〇2 is stylized tg_ming), and the required threshold voltage, that is, the offset threshold voltage Vthl. Next to the T3, the control signal az will return to the high level again, causing the PMOS transistor 514 to turn off. ^Τ4 o's data will be sent from the data line 534 to the pixel circuit. ± 疋疋疋在在在在在在在在在 534 534 534 534 534 534 534 534 534 534 534 534 534 534 ¥ ' The voltage difference (^) between nodes B2 and A2 can be expressed as:

Vsg = Vth-(Cl/(ci + l2))Vdata (3) C1為電谷516的電容值，而C2則為電容518的電谷值。料日1★描訊號Sn—N會轉為高準位，並且晝素資 ’、傳迗凡畢，因而使得PMOS電晶體512關閉。而在 16 131171 fl.doc/006 96-2-27 T6時，控制訊號CE會變為低準位，以致於pm〇S電晶體 542導通，而將電壓VSS導通至發光二極體504的陰極端。此時’ PMOS電晶體502會導通，而產生工作電流12來驅動發光二極體504,而工作電流12也就等於第（1)式中的 Ioled。而將第（1)式中的Vsg用第(3)式代入，則工作電流 12就可以表示為：Vsg = Vth - (Cl / (ci + l2)) Vdata (3) C1 is the capacitance of the valley 516, and C2 is the valley of the capacitor 518. The material day 1 ★ tracing signal Sn-N will turn into a high level, and the 昼资、、、、、、、、、、、、、、、、、、、、、、、、、、 At 16 131171 fl.doc/006 96-2-27 T6, the control signal CE becomes a low level, so that the pm〇S transistor 542 is turned on, and the voltage VSS is turned on to the cathode of the light emitting diode 504. extreme. At this time, the PMOS transistor 502 is turned on, and an operating current 12 is generated to drive the light-emitting diode 504, and the operating current 12 is equal to Ioled in the equation (1). When Vsg in the formula (1) is substituted by the formula (3), the operating current 12 can be expressed as:

12 = (/?/2)((Cl/(Cl + C2))Vdata)2 (4) 由第(4)式可知，驅動發光二極體504的工作電流I2 大小與PMOS電晶體502的臨界電壓vth沒有關係。同時，在晝素電路500内也僅有三個電晶體，因此本實施例所提供的畫素電路500能夠有效地提升開口率。 ♦ Θ 7、、、s示了依照本發明第三實施例的一種晝素電路之 ^路圖。4參照圖7，在畫素電路中，同樣還是包括辦電晶體7〇2、例如是有機發光二極體的發光二極12 = (/?/2)((Cl/(Cl + C2))Vdata)2 (4) From the equation (4), the magnitude of the operating current I2 of the driving LED 504 and the critical value of the PMOS transistor 502 are known. The voltage vth does not matter. At the same time, there are only three transistors in the pixel circuit 500, so the pixel circuit 500 provided in this embodiment can effectively increase the aperture ratio. ♦ Θ 7, s, s show a circuit diagram of a pixel circuit in accordance with a third embodiment of the present invention. 4 Referring to FIG. 7, in the pixel circuit, the same also includes the transistor 7, 2, for example, the LED of the organic light-emitting diode.

打绩7^償電路710。另外，晝素電路7〇0也耗接了掃 Μ和陰極線736。其中，陰極線736 疋還過開關電路74〇而耦接至陰極電壓vss。的照圖7,在晝素電路700中，發光二極體观至陰極線736,而陽極端則是_至讀OS 至陽及極端。而PM0S電晶體702的源極爾在補其閘極端則是輕接至補償電路710。其中，曰中’包括7 _S電晶體712和714。 i θθ體712的源極端和間極端分顺接資料 17 I3H737wfld OC/006 96-2-27 線。734和掃描線732，以分別接收資料電壓別她和峨Snjs[。此外，PMOS電晶體川的沒極端則是: mos電晶體714的源極端，而ρ·電晶體714的問極端和汲極端是彼此互相耦接。另外，PM〇s電晶體714 ^極端還輕接至PMOS電晶體搬的閘極端，並且透過带谷716而耦接至PMOS電晶體7〇2的源極端。甩 7Π。在本實施例中，電容716的一端相接至PMOS電晶體〇2的源極端，而另一端除了耦接至PMOS電晶體702的 ==和_電晶體7_及極端之外，還 44而麵接至一重置電壓VR。其中開關電路744會依 —重置訊號RST，而決定是否將重置電壓VR PM〇S電晶體702的閘極端。 1 另外，開關電路740同樣也可以包括pM〇s電晶體 2 ’其源極端_陰極電壓州，閘極端接收控制訊號 it，而汲極端則耦接陰極線736。昭同圖8、曰不了圖7之晝素電路的訊號時序圖。請合併參都::和圖8，在T〇時’掃描訊號Sn-N和重置訊號RST P為咼準位，而控制訊號CE則是低準位。在T1 %•，重置吼號RST會從高準位下拉至低準位， ^制訊號CE岐從低雜上拉至辭位，⑽於PMO S ^體714會導通。反之’ PMOS電晶體712和742則是芦閉的狀恶。此時’節點A3的電壓位準為VR+Vth，B3 位準為VR ’其中’ vth為pM〇s電晶體7i4的臨介電壓。 18 13117^1 746twfl.doc/006 96-2-27 Π在Τ2 1重置訊號RST會回復為高準位，而掃描訊號Sn一N則是被下拉至低準位，以致於pM〇s電晶體712 會導通。同時’晝素資料會從資料線734送至晝素^路7⑻ 内。也就是說，在資料線734上會產生資料電壓。此時，節點A3的電壓位準會，而節點色3的電壓則是Vdata-Vth。其中，Vth為PMOS電晶體714的臨界電壓。在T3時，掃描訊號Sn_N會回復至高準位，並且晝素資料也傳送完畢。此時，控制訊號CE會下拉至低準位，以致於PMOS電晶體702和742會導通，而產生一工作電流13來驅動發光二極體7〇4，其中驅動電壓13就是第（1) 式中的Ioled。此時，由於節點B3的電壓位準為Vdata_Vth，因此PMOS電晶體702的源極端和閘極端之間的電壓差 (Vsg)可以表示為：The performance of the 7 compensation circuit 710. In addition, the halogen circuit 7〇0 also consumes the sweep and cathode lines 736. The cathode line 736 is also coupled to the cathode voltage vss via the switching circuit 74A. Referring to Figure 7, in the pixel circuit 700, the light emitting diode is viewed to the cathode line 736, and the anode terminal is _ to read the OS to the anode and the extreme. The source of the PMOS transistor 702 is connected to the compensation circuit 710 while complementing its gate terminal. Wherein, the ’" includes 7 _S transistors 712 and 714. The source and the extremes of the i θθ body 712 are connected to the data line 17 I3H737wfld OC/006 96-2-27 line. 734 and scan line 732 to receive the data voltage separately from her and 峨Snjs[. Further, the PMOS transistor is not extreme: the source terminal of the MOS transistor 714, and the terminal and the 汲 terminal of the ρ· transistor 714 are coupled to each other. In addition, the PM〇s transistor 714 is also lightly connected to the gate terminal of the PMOS transistor and is coupled to the source terminal of the PMOS transistor 7〇2 through the valley 716.甩 7Π. In this embodiment, one end of the capacitor 716 is connected to the source terminal of the PMOS transistor ,2, and the other end is coupled to the == and _ transistor 7_ and the extreme of the PMOS transistor 702, and 44 The surface is connected to a reset voltage VR. The switch circuit 744 determines whether the gate terminal of the voltage VR PM〇S transistor 702 will be reset according to the reset signal RST. In addition, the switch circuit 740 can also include a pM〇s transistor 2' whose source terminal_cathode voltage state, the gate terminal receives the control signal it, and the drain terminal is coupled to the cathode line 736. Figure 8 shows the signal timing diagram of the pixel circuit of Figure 7. Please merge the parameters:: and Fig. 8. At T〇, the scanning signal Sn-N and the reset signal RST P are at the 咼 level, and the control signal CE is at the low level. At T1 %•, the reset apostrophe RST will be pulled from the high level to the low level, the ^ signal CE 岐 will be pulled from the low noise to the vocabulary, and (10) the PMO S ^ body 714 will be turned on. On the other hand, the PMOS transistors 712 and 742 are in the form of a closed state. At this time, the voltage level of the node A3 is VR+Vth, and the B3 level is VR' where 'vth is the intermediate voltage of the pM〇s transistor 7i4. 18 13117^1 746twfl.doc/006 96-2-27 Π Τ 2 1 reset signal RST will return to high level, and scan signal Sn - N is pulled down to low level, so that pM 〇 s Crystal 712 will conduct. At the same time, the 昼资料 data will be sent from the data line 734 to the 昼素^路7(8). That is, a data voltage is generated on the data line 734. At this time, the voltage level of node A3 will be, and the voltage of node color 3 will be Vdata-Vth. Where Vth is the critical voltage of the PMOS transistor 714. At T3, the scan signal Sn_N will return to the high level and the data of the enamel will be transmitted. At this time, the control signal CE is pulled down to the low level, so that the PMOS transistors 702 and 742 are turned on, and an operating current 13 is generated to drive the light emitting diode 7〇4, wherein the driving voltage 13 is the (1) Ioled in. At this time, since the voltage level of the node B3 is Vdata_Vth, the voltage difference (Vsg) between the source terminal and the gate terminal of the PMOS transistor 702 can be expressed as:

Vsg = VDD - Vdata + Vth (5) 將第（5)式代入第（1)式後，就可以將第（丨）式改寫如下：Vsg = VDD - Vdata + Vth (5) After substituting the formula (5) into the equation (1), the equation (丨) can be rewritten as follows:

Ioled - β/2(ΥΌΌ - Vdata + Vth - Vth)2 = J3/2(VDD-Vdata)2 () 同樣地，從第(6)式中可以很清楚的看到，用來驅動發光二極體704的工作電流i3(I〇led)之大小，會與PMOS電晶體702的臨界電壓無關。另外，將晝素電路700與晝素電路5〇〇相比發現，晝素電路700比晝素電路500少了 — 顆電容，因此其佈線更為簡單。是以，本實施例所提供的 a素電路能夠有效地提升開口率。在本發明的另外一些實施例中，開關電路744和重置 19 1311737 l61^6twf\.doc/006 96-2-27 1、i的力此可以藉由前—條掃描線來實現。也就是節點B3改轉至前—條掃描線。當前—條掃描線的 ^田减被下拉至鱗位時，節點B3的準位就和前一條掃描線的準位相同。如此，_ 7的實施例又可以減少一個開關電路，而使得電路的實現更為簡單。Ioled - β/2(ΥΌΌ - Vdata + Vth - Vth)2 = J3/2(VDD-Vdata)2 () Similarly, it can be clearly seen from equation (6) that it is used to drive the light-emitting diode The magnitude of the operating current i3 (I〇led) of the body 704 is independent of the threshold voltage of the PMOS transistor 702. Further, by comparing the halogen circuit 700 with the halogen circuit 5, it is found that the halogen circuit 700 has a smaller capacitance than the halogen circuit 500, so that the wiring is simpler. Therefore, the a-type circuit provided in this embodiment can effectively increase the aperture ratio. In still other embodiments of the present invention, the switching circuit 744 and the reset 19 1311737 l61^6twf\.doc/006 96-2-27 1, i can be achieved by the front-strip scan line. That is, node B3 changes to the front-strip scan line. When the current field of the scan line is pulled down to the scale position, the level of the node B3 is the same as the level of the previous scan line. Thus, the embodiment of _ 7 can reduce one switching circuit and make the implementation of the circuit simpler.

kμ11二不了依知、本發明之—較佳實施例的一種顯示面、、:才不思圖。請參照圖9 ’顯示面板900可以利用圖2 =示面板2G0的電路來實現。在顯示面板9 各個晝素中包含-陽極電極_，= 丨:式排列在顯示面板900上，用以顯伸。:々一母—陽極電極丨〇19都是朝向γ方向延示），亇歹i上之晝素結構’則共用一條陰極電極（圖未 9〇4減#財素結構贈㈣姉透過陰極接觸端 9〇4耦接至—開關電路 ⑽按觸鈿隔壁結構1〇23區隔開來。彳 * 5電極則藉由間用-條陰極電極，而這條p極’ ^列上之晝素結構共Kμ11 is not known, and a display surface of the preferred embodiment of the present invention is not considered. Referring to Figure 9, the display panel 900 can be implemented using the circuit of Figure 2 = panel 2G0. In the respective elements of the display panel 9, - anode electrodes _, = 丨: are arranged on the display panel 900 for display. : 々 a mother-anode electrode 丨〇19 is extended toward the γ direction), and the 昼i structure on 亇歹i shares a cathode electrode (Fig. 9〇4 minus #财素结构赠(四)姊transmitted through the cathode The terminal 9〇4 is coupled to the switch circuit (10) separated by the touch barrier structure 1〇23 region. The 彳*5 electrode is separated by a strip-cathode electrode, and the p-pole '^ column is a halogen Total structure

_開關電路912。注係透過陰極接觸端904_ Switch circuit 912. Injection through the cathode contact end 904

方向延伸。此外，門捫垂、疋母陰極電極都會朝向X 或任何可糊= 上述之電晶體说路都會依據—控制訊號(，=見:：广峨 VSS導通至對應的陰極電極上。）而叙疋否將直流電壓圖:0繪示了沿圖9之9a_9a，的剖面在基板1011上，配置有每。月々π圖10，電晶體元件聰上开晶體兀件1013。而在薄膜也成有-絕緣層⑻5,益且絕緣層 20 I3H737wfi doc/006 96-2-27 1015的表面具有孔洞]017。所在巴緣層1015上’係开)成一層陽極電極1019，而其以:!銦錫氧化物、銦鋅氧化物及鋁鋅氧化物等。陽 ηηΓπρ係藉由孔洞1〇17連接至薄臈電晶體元件以曰s π陽極電極1019也覆蓋了部分的絕緣層1015, 以在頒不面板上形成晝素結構。用夹電極1〇19的部分上’係形成絕緣層1021，其缘屛^5的^ 1〇17 ’以及沒有被陽極電極1〇19覆蓋之絕心爾1叫_麵可以 1023 5 ^ 向延伸。H + 伸方向的兩端，並且朝向圖5之X方係呈二：的::。10的剖面上來看，間隔壁結構助小分子的有機材料或是高分子的有機括了 ⑽7的上方則形的”材科。而在有機層銀合金等。麟桎电極1029 ’其材質可為紹、甸、鎂The direction extends. In addition, the sag and the mother-electrode cathode electrode will all face X or any of the above-mentioned transistors, and the circuit will be based on the control signal (, = see:: 峨 VSS is turned on to the corresponding cathode electrode). Otherwise, the DC voltage map: 0 is shown along the 9a-9a of FIG. 9, and the cross section is arranged on the substrate 1011. Moon 々 π Figure 10, the transistor element Cong open the crystal element 1013. On the other hand, the film also has an insulating layer (8) 5, and the surface of the insulating layer 20 I3H737wfi doc/006 96-2-27 1015 has a hole 017. The edge layer 1015 is "opened" to form an anode electrode 1019, which is: indium tin oxide, indium zinc oxide, aluminum zinc oxide, and the like. The ηηηΓπρ is connected to the thin transistor element by the hole 1〇17. The 曰s π anode electrode 1019 also covers part of the insulating layer 1015 to form a halogen structure on the panel. The insulating layer 1021 is formed on the portion of the clamping electrode 1〇19, and the ^1〇17' of the edge 屛^5 and the singularity 1 which is not covered by the anode electrode 1〇19 can be extended by 1023 5 ^ . H + extends both ends of the direction, and faces the X of Figure 5 in two:::. In the cross section of 10, the partition structure helps the organic material of the small molecule or the organic polymer to be formed above the (10)7 shape. In the organic layer, the silver alloy, etc. For Shao, Dian, Magnesium

之xtt述：有機層助和陰極電極卿都是朝向圖Q 接對庫的° = ’且陰極電極1029透過陰極接觸蠕90:耦 =,路。由於間隔壁結構1〇23可 = 顯示面板_上各列書^所Γ。错由間隔壁結構1〇23, —素所，儿積之有機層1027和陰極電極 21 •doc/006 96-2-27 1029將可被分隔開來，即每一列均有其相對應之有機層 1〇27與陰極電極1〇29，因此也可以簡化製程步驟。綜上所述，本發明至少有以下優點： 1. 由於單—畫素電路内之元件的減少，因而可以減低佈線的困難度。 2. 由於單—畫素電路内之元件個數較少，因而增加了本發明之顯示面板的開口率。Xtt said that both the organic layer and the cathode electrode are oriented toward the Q of the library Q = ' and the cathode electrode 1029 is transmitted through the cathode contact with the creep 90: coupling =, path. Since the partition structure 1〇23 can be displayed on the display panel _. The fault is caused by the partition structure 1〇23, the element, the organic layer 1027 and the cathode electrode 21 •doc/006 96-2-27 1029, which can be separated, that is, each column has its corresponding The organic layer 1〇27 and the cathode electrode 1〇29 can also simplify the process steps. In summary, the present invention has at least the following advantages: 1. Due to the reduction of components in the single-pixel circuit, the difficulty of wiring can be reduced. 2. Since the number of components in the single-pixel circuit is small, the aperture ratio of the display panel of the present invention is increased.

3. 由於開口率的增加，因此本發明之顯示面板的亮度需求可以降低’進而增加了有機發光二極體元件的壽命。 4. 由於顯示面板的亮度可以降低，因此也減少了電源 5:由於本發明可以使流過發光二極體元件的工作電流維持穩^，g此可簡持顯示面板之晝面的品質。 6. 由於晝素電路内之工作電流敎，因此也可以增加晝素電路的壽命。3. Since the aperture ratio is increased, the brightness requirement of the display panel of the present invention can be lowered', thereby increasing the lifetime of the organic light-emitting diode element. 4. Since the brightness of the display panel can be lowered, the power supply 5 is also reduced: since the operating current flowing through the light-emitting diode element can be kept stable, the quality of the face of the display panel can be simplified. 6. Due to the operating current in the halogen circuit, the life of the pixel circuit can also be increased.

7. 由於上賴電壓Vss可以依據實際情絲設定，因此可以增加本發明的應用性和實用性。 η隔本發明麵*面板結勒制了貞光阻來形成間隔土、纟口構，因此可以簡化製程。限定發明6以較佳實施綱露如上，然其並非用以和i任何_此技藝者’在不獅本發明之精神之f叙* w可將此發日用科同之電路上並可作些許利範者=本發明之保護範圍當視後附之申請專 22 I311737wfLdoc/006 96-2-27 【圖式簡單說明】顯不益之晝素結構的電路較佳實施爿的—種顯示面圖1緣示了一種習知之平面圖。圖2繪示了依照本發明之— 板的電路圖。圖3繪示了依照本發明第電路圖。實施例的一種晝素電路之7. Since the voltage Vss can be set according to the actual situation, the applicability and practicability of the present invention can be increased. The η spacer of the invention has a 贞 photoresist formed to form a spacer soil and a 纟构 structure, thereby simplifying the process. The invention 6 is defined by the preferred embodiment as described above, but it is not intended to be used in conjunction with any of the skilled artisans. Some of the benefits of the invention = the scope of protection of the present invention is attached to the application of the application 22 I311737wfLdoc / 006 96-2-27 [Simple description of the diagram] The circuit of the display of the advantage of the structure of the structure is not a good display of the display surface 1 The edge shows a conventional plan. Figure 2 is a circuit diagram of a board in accordance with the present invention. Figure 3 depicts a circuit diagram in accordance with the present invention. A pixel circuit of an embodiment

=4繪示圖3之畫素電路的訊號時序圖。圖5繪不了依照本發明第二電路圖。仞的—種晝素電路之圖6繪示了圖5之畫素電路的訊號時序圖7 _ 了依照本發明f三實施電路圖。搜晝紊電路之圖8綠示了圖7之晝素電路的訊號時序圖 '種顯斧面圖9繪示了依照本發明之—較佳實施例板的結構示意圖。=4 shows the signal timing diagram of the pixel circuit of FIG. Figure 5 illustrates a second circuit diagram in accordance with the present invention. Fig. 6 shows the signal timing of the pixel circuit of Fig. 5. Fig. 7 is a circuit diagram of the implementation of f according to the present invention. Figure 8 is a diagram showing the signal timing diagram of the pixel circuit of Figure 7. 'Emerging axe surface. Fig. 9 is a block diagram showing the structure of a preferred embodiment according to the present invention.

圖KU會示了沿圖9之9a-9a，的剖面圖。【主要元件符號說明】 U、212 ' 334 ' 534、734 :資料線資料電壓：Vdata U、202、204、332、532、732 :掃描線、Sn_N :掃描訊號 15、17、538 :控制線 ^、CE1、AZ :控制訊號 23 96-2-27 i311737wfl,〇c/006 RST :重置訊號 1(U、103、105、107、302、312、314、316、318、352、 502、512、514、542、702、712、714 :電晶體 111、304、504、704 :有機發光二極體 200、900 :顯示面板 222、336、536、736 :陰極線 232、350、540、740 :開關電路 242、244、300、500、700 ··晝素電路 310、510、710 :補償電路 a、C2、322、516、518、716 :電容 904 :陰極接觸端 912 :開關電路 1011 :基板 1013 :薄膜電晶體元件 1015、1021 :絕緣層 1017 :孔洞 1019 :陽極電極 1023 :間隔壁結構 1027 :有機層 1029 :陰極電極 VDD :陽極電壓 VSS :陰極電壓 24Figure KU shows a cross-sectional view along 9a-9a of Figure 9. [Description of main component symbols] U, 212 ' 334 ' 534, 734 : Data line data voltage: Vdata U, 202, 204, 332, 532, 732: Scan line, Sn_N: Scan signal 15, 17, 538: Control line ^ , CE1, AZ: control signal 23 96-2-27 i311737wfl, 〇c/006 RST: reset signal 1 (U, 103, 105, 107, 302, 312, 314, 316, 318, 352, 502, 512, 514, 542, 702, 712, 714: transistors 111, 304, 504, 704: organic light-emitting diodes 200, 900: display panels 222, 336, 536, 736: cathode lines 232, 350, 540, 740: switching circuits 242, 244, 300, 500, 700 · 昼 circuit 310, 510, 710: compensation circuit a, C2, 322, 516, 518, 716: capacitor 904: cathode contact 912: switch circuit 1011: substrate 1013: film The crystal element 1015, 1021: the insulating layer 1017: the hole 1019: the anode electrode 1023: the partition structure 1027: the organic layer 1029: the cathode electrode VDD: the anode voltage VSS: the cathode voltage 24

Claims

13 1 1 733l40407號專利範圍無劃線替換頁十、申請專利範圍： 1.一種顯示面板，包括：多數個掃描線，係沿一第一方向彼此平行排列夕數個資料線，係沿一第二方向彼此平行排列夕數個陰極線，係沿該弟一方向彼此平行排列，一多數個晝素電路，係分別對應耦接該些掃描線與該些貝料線其中之一，且每一該些掃描線上耦接的所有畫素電路係辆接相同的陰極線，而該晝素電路包括：一第一 PMOS電晶體’其源極端耦接一陽極電壓; —發光二極體，其陽極端耦接該第一 PM〇s電晶體之汲極端，而陰極端則耦接該些陰極線其中之一；山 —第二PMOS電晶體’其第一源/没極端和閘極知，77別輕接對應之資料線和掃描線；· -m —第三™08電晶體’其第一源/沒極端麵接該第 —〇S電晶體之第二源/没極端，而該第三PMOS電曰體之閘極辦帛二細^频此互日曰該第-mos電晶體之閘極端；以及』耦接至一電谷，一端耦接該陽極電壓，一第-觸s電晶體之問極端接該否搞接至一重置電壓；以及據重置訊號而決定是 —多數烟關電路’分別祕該極線之〜，一開關電路分別依據-控制訊號而 _ ’且 2.如申請專利範圍第1項所述之顯示面板，其=電 25 13 1 17i?il40407 號專利範圍無劃線替換頁容透過一重置開關而耦接至該重置電壓據該重置訊號而決定是否將該重置電壓端，而該重置開關依導通至該電容之一 3. ’係耦接至對應之掃描幻曰射如申請專利範圍第1項所述之顯示面扳，其中該電相對於耦接該陽極電壓的另一端線的前一條掃描線。 4.如申請專利範圍第i項所述之 S:電=、—開關電，，其第二源/汲極端耦:: 其閘極端_接::=:輕接該些陰極線其中之-’而夕卜邻素電路，適用於—顯示面板，並透過一第一〜陰極賴，其中該第—外部開關依據號而決定是·該陰極電壓導通至該晝素電路，吻該晝素電路包括：發光二極體，其陰極端透過該第—外部關而輕接王孩陰極電麗；第電晶體，其汲極端輕接至該發光二極體之陽極陰極電=㈣減—陽極賴，其巾該雜電壓大於該和第一電晶體，其閘極端和源極端分別耦接一掃描線 °—資，線’用以接收—掃描訊號和—資料訊號；第j電晶體，其源極端耦接該第二電晶體之汲極而該第二電晶體之閘極端與汲極端彼此互相耦接，且、同轉接至該第-電晶體之閘極端；以及 26 13 1 1 7¾錳140407號專利範圍無劃線頁一電容，其中一端接收該陽極電壓，而另一至該第一電晶體之閘極端，並依據一重置訊梦:端則耦接 ^收-重置電壓，其中該重置訊號的相位係^先 a 6.如申請專鄕圍第5項所述之晝素電路各相對於耦接該陽極電壓的另一端透過一一中該電電壓，其中該第二外部開關的ΐ通= 前一你捃知成朴丄們对"王嘁顯不面板中的重置^ 前—條掃描線上㈣㈣號作為該 C重置電壓的位準等於前-條掃描線上之掃〜電曰辦中Μ專利㈣第5項所述之晝素電路，其中該第 9曰V J第二電晶體和第三電晶體皆為PM〇S電晶體。光二極體1 請專利範圍第5項所述之晝素電路，其中該發耀為—有機發光二極體。 1〇·—種顯示面板，包括·· 一基底；包括多數個晝素結構，形狀該基底上，各該些畫素結構溥膜電晶體元件，配置在該基底上；該第-姑―第―絕緣層’形成在該薄膜電晶體元件上，且絕緣層表面具有一孔洞； 27 13117^7 14_7號專利範圍無劃線難頁㈣爲Γ陽極電極’細—第二方向延伸而形成在該第二=上，並藉由該孔洞連接至該薄膜電晶體元件，且該1W極電極覆蓋該第一絕緣層之部分；曝露部份Γ第二絕緣層，覆蓋住該孔洞與該第一絕緣層之 i少兩㈣隔麵構’分卿成層畫壁結構係以該第-方向延伸配置在- 上，且以^機t形成於該第二絕緣層與該陽極電極之區域，^發光/延伸覆蓋住該兩個間隔壁結構之間的 -陰極電極’形成於該有機向延伸《在該兩個間隔壁結構之間；以及該弟一方訊號而決直f 極電極，用以依據一控制二疋㈣s流·傳送至該陰極電極。第-絕述之顯示面板，其中該些第^述之顯示面板’其中該些陽====述之顯示面板，其中該化物至少其中」錫祕物、銦鋅氧化物及銘鋅氧 14.如申請專利範圍第1()項些有機層的材料包括小分子的有機材料面板’其中該 28 13 1 1 7Α7ΐ40407 號專利範圍無劃線替換頁 15. 如申請專利範圍第10項所述之顯示面板，其中該些有機層的材料包括向分子的有機材料。 16. 如申請專利範圍第10項所述之顯示面板，其中該些陰極電極的材料包括鋁、鈣、鎂銀合金至少其中之一。13 1 1 733l40407 Patent range without scribe line replacement page 10, the scope of patent application: 1. A display panel, comprising: a plurality of scanning lines, arranged in parallel with each other along a first direction, a number of data lines, along the first The two directions are arranged in parallel with each other in a plurality of cathode lines, which are arranged in parallel along the direction of the brother, and a plurality of pixel circuits are respectively coupled to the scan lines and one of the plurality of shell lines, and each All of the pixel circuits coupled to the scan lines are connected to the same cathode line, and the pixel circuit includes: a first PMOS transistor whose source terminal is coupled to an anode voltage; and a light emitting diode having an anode terminal Coupling the first terminal of the first PM〇s transistor, and the cathode end is coupled to one of the cathode lines; the mountain-second PMOS transistor's first source/no terminal and gate know, 77 is light Connect the corresponding data line and scan line; · -m - the third TM08 transistor 'its first source / no extreme face connected to the first - 〇 S transistor second source / no extreme, and the third PMOS曰之之帛细细细细细细 ^ 此此此此互The gate of the os transistor is extreme; and is coupled to a valley, one end is coupled to the anode voltage, and the first terminal is connected to a reset voltage; and the reset signal is The decision is that most of the smoke-off circuits are secreted by the pole line, and a switch circuit is based on the control signal _ 'and 2. The display panel as described in claim 1 of the patent scope, which = 25 13 1 17i The il40407 patent range without a scribe line replacement page is coupled to the reset voltage through a reset switch to determine whether to reset the voltage terminal according to the reset signal, and the reset switch is turned on to the capacitor A 3. The system is coupled to the corresponding scanning illusion as shown in claim 1, wherein the electricity is relative to a previous scan line coupled to the other end line of the anode voltage. 4. For the S: electric =, - switching electric, as described in item i of the patent application, the second source / 汲 extreme coupling:: its gate terminal _ 接 ::: =: lightly connect the cathode lines - ' The illuminating circuit is applicable to the display panel and is passed through a first to a cathode, wherein the first external switch is determined according to the number: the cathode voltage is conducted to the pixel circuit, and the pixel circuit includes : The light-emitting diode has a cathode end that is lightly connected to the cathode of the cathode through the first-outer turn; the second transistor is electrically connected to the anode of the light-emitting diode at the anode of the light-emitting diode = (4) minus-anode, The differential voltage of the towel is greater than the first transistor, and the gate terminal and the source terminal are respectively coupled to a scan line, the line 'for receiving-scanning signal and the data signal; the j-th transistor, the source terminal thereof The gate of the second transistor is coupled to the gate terminal and the drain terminal of the second transistor, and is coupled to the gate terminal of the first transistor; and 26 13 1 1 73⁄4 manganese 140407 No. Patent range without a scribe line, a capacitor, one end receiving the anode voltage, and the other a gate to the first transistor, and according to a reset message: the end is coupled to the reset-reset voltage, wherein the phase of the reset signal is first a 6. If the application is for the fifth item Each of the halogen circuits is transparent to the other end of the anode voltage, and the second external switch is passed through, and the second external switch is =通=前捃你捃成朴丄对"王嘁显The reset in the panel is not the front ^ strip scan line (4) (4) as the level of the C reset voltage is equal to the pixel circuit described in the fifth item of the scan on the scan line. The 9th VJ second transistor and the third transistor are both PM〇S transistors. The photodiode 1 is a halogen circuit as described in the fifth aspect of the patent, wherein the illuminating is an organic light-emitting diode. a display panel comprising: a substrate; comprising a plurality of halogen structures, on the substrate, each of the pixel structure 溥 film transistor elements disposed on the substrate; the first-gu An "insulation layer" is formed on the thin film transistor element, and the surface of the insulating layer has a hole; 27 13117^7 14_7 patent range without a scribe line (4) is formed by the Γ anode electrode 'fine-second direction extension a second=upper and connected to the thin film transistor element by the hole, and the 1W pole electrode covers a portion of the first insulating layer; exposing a portion of the second insulating layer to cover the hole and the first insulation The layer i is less than two (four), and the partition structure is formed by extending in the first direction, and is formed in the region of the second insulating layer and the anode electrode by the machine t, a cathode electrode extending between the two partition walls is formed in the organic extension "between the two partition structures; and the other side of the signal and the straight electrode is used to control Two (four) s stream · transmitted to the yin Electrode. a display panel of the above-mentioned description, wherein the display panel of the first description has a display panel in which the anodes are at least said, wherein the compound has at least a tin-like substance, an indium zinc oxide, and a zinc oxide. The material of the organic layer such as the scope of claim 1 () includes a small-molecular organic material panel, wherein the patent scope of the patent is in the range of the patent application. A display panel, wherein the materials of the organic layers comprise organic materials to molecules. 16. The display panel of claim 10, wherein the material of the cathode electrodes comprises at least one of aluminum, calcium, magnesium silver alloy.

29 13117^2 twfl.doc/006 96-2-27 七、指定代表圖： (一）本案指定代表圖為：圖（2 )。 (二) 本代表圖之元件符號簡單說明： 200 :顯示面板 202、204 :掃描線 212 :資料線 222 :陰極線 232 :開關電路 242、244 :晝素電路 VSS :陰極電壓八、本案若有化學式時，請揭示最能顯示發明特徵的化學式：益29 13117^2 twfl.doc/006 96-2-27 VII. Designated representative map: (1) The representative representative of the case is: Figure (2). (2) A brief description of the components of the representative figure: 200: display panel 202, 204: scan line 212: data line 222: cathode line 232: switch circuit 242, 244: halogen circuit VSS: cathode voltage VIII, if there is a chemical formula When revealing the chemical formula that best shows the characteristics of the invention:

44