TWI310910B - An apparatus and method for address bus power control - Google Patents

An apparatus and method for address bus power control Download PDF

Info

Publication number
TWI310910B
TWI310910B TW092134895A TW92134895A TWI310910B TW I310910 B TWI310910 B TW I310910B TW 092134895 A TW092134895 A TW 092134895A TW 92134895 A TW92134895 A TW 92134895A TW I310910 B TWI310910 B TW I310910B
Authority
TW
Taiwan
Prior art keywords
sense amplifiers
address
data
english
response
Prior art date
Application number
TW092134895A
Other languages
English (en)
Other versions
TW200428279A (en
Inventor
Tsvika Kurts
Doron Orenstien
Marcelo Yuffe
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/317,798 external-priority patent/US7216240B2/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200428279A publication Critical patent/TW200428279A/zh
Application granted granted Critical
Publication of TWI310910B publication Critical patent/TWI310910B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
  • Small-Scale Networks (AREA)
  • Selective Calling Equipment (AREA)
  • Dram (AREA)
  • Amplifiers (AREA)
  • Machine Translation (AREA)
  • Microcomputers (AREA)
  • Electrically Operated Instructional Devices (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Description

1310910 (此處由本局於收 文時黏貼條碼 附件：第92134895號專利申請案中文說明書修正 民國94年12月if曰呈發明專利說明軎 m (本申請斟各式、λ辭及麵字，請雛，※言 〇
842682 riS A ※申請案號：92134895 ※申請臼期：92年12月10日 ※沉分類：如作 ―、發明名稱： (中）位址匯流排電力控制之裝置及方法 (英）An apparatus and method for address bus power control 二、申請人：（共1人)
1.姓名：（中）英特爾股份有限公司 (英）INTEL CORPORATION 代表人：（中）1.大衛賽門 (英）1.SIMON, DAVID 地址：（中）美國加州聖大克拉瑞密遜學院路二二〇〇號
(英）2200 Mission College Blvd.，Santa Clara, CA 95052 USA 國籍：（中英）美國 U.S.A. ’ 三、發明人：（共3人) 1. 姓名：（中）堤斯維卡科茲 (英）KURTS，TSVIKA 國籍：（中）以色列
(英）ISRAEL 2. 姓名：（中）多朗歐倫斯坦
(英）ORENSTEIN，D0R0N 國籍：（中）以色列 (英）ISRAEL 3. 姓名：（中）馬塞羅尤菲
(英）YUFFE, MARCEL0 國籍：（中）以色列 (英）ISRAEL 四、聲明事項： ◎本案申請前已向下列國家（地區）申請專利□主張國際優先權： 1310910 (此處由本局於收 文時黏貼條碼 附件：第92134895號專利申請案中文說明書修正 民國94年12月if曰呈發明專利說明軎 m (本申請斟各式、λ辭及麵字，請雛，※言 〇
842682 riS A ※申請案號：92134895 ※申請臼期：92年12月10日 ※沉分類：如作 ―、發明名稱： (中）位址匯流排電力控制之裝置及方法 (英）An apparatus and method for address bus power control 二、申請人：（共1人)
1.姓名：（中）英特爾股份有限公司 (英）INTEL CORPORATION 代表人：（中）1.大衛賽門 (英）1.SIMON, DAVID 地址：（中）美國加州聖大克拉瑞密遜學院路二二〇〇號
(英）2200 Mission College Blvd.，Santa Clara, CA 95052 USA 國籍：（中英）美國 U.S.A. ’ 三、發明人：（共3人) 1. 姓名：（中）堤斯維卡科茲 (英）KURTS，TSVIKA 國籍：（中）以色列
(英）ISRAEL 2. 姓名：（中）多朗歐倫斯坦
(英）ORENSTEIN，D0R0N 國籍：（中）以色列 (英）ISRAEL 3. 姓名：（中）馬塞羅尤菲
(英）YUFFE, MARCEL0 國籍：（中）以色列 (英）ISRAEL 四、聲明事項： ◎本案申請前已向下列國家（地區）申請專利□主張國際優先權： 1310910 842682 【格式請依 1. 美國 2. 美國 受理國家（地區）；申請日；申請案號數順序註記】 ;2002/12/11 ; 10/317,798 0有主張優先權 ;2003/05/12 ; 10/436,903 0有主張優先權 -2-
TW092134895A 2002-12-11 2003-12-10 An apparatus and method for address bus power control TWI310910B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/317,798 US7216240B2 (en) 2002-12-11 2002-12-11 Apparatus and method for address bus power control
US10/436,903 US20040128416A1 (en) 2002-12-11 2003-05-12 Apparatus and method for address bus power control

Publications (2)

Publication Number Publication Date
TW200428279A TW200428279A (en) 2004-12-16
TWI310910B true TWI310910B (en) 2009-06-11

Family

ID=32511034

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092134895A TWI310910B (en) 2002-12-11 2003-12-10 An apparatus and method for address bus power control

Country Status (11)

Country Link
US (1) US20040128416A1 (zh)
EP (2) EP1570335B1 (zh)
JP (1) JP4813180B2 (zh)
KR (1) KR100737549B1 (zh)
CN (1) CN100422905C (zh)
AT (1) ATE437394T1 (zh)
AU (1) AU2003293030A1 (zh)
DE (1) DE60328520D1 (zh)
HK (1) HK1075949A1 (zh)
TW (1) TWI310910B (zh)
WO (1) WO2004053706A2 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7000065B2 (en) 2002-01-02 2006-02-14 Intel Corporation Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers
US7484016B2 (en) * 2004-06-30 2009-01-27 Intel Corporation Apparatus and method for high performance volatile disk drive memory access using an integrated DMA engine
US7822978B2 (en) * 2005-07-22 2010-10-26 Intel Corporation Quiescing a manageability engine
US7870407B2 (en) * 2007-05-18 2011-01-11 Advanced Micro Devices, Inc. Dynamic processor power management device and method thereof
US7477178B1 (en) * 2007-06-30 2009-01-13 Cirrus Logic, Inc. Power-optimized analog-to-digital converter (ADC) input circuit
US8581756B1 (en) 2012-09-27 2013-11-12 Cirrus Logic, Inc. Signal-characteristic determined digital-to-analog converter (DAC) filter stage configuration
US11138348B2 (en) * 2018-10-09 2021-10-05 Intel Corporation Heterogeneous compute architecture hardware/software co-design for autonomous driving

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4202045A (en) * 1979-03-05 1980-05-06 Motorola, Inc. Write circuit for a read/write memory
US4862348A (en) * 1986-01-20 1989-08-29 Nec Corporation Microcomputer having high-speed and low-speed operation modes for reading a memory
JPH0812756B2 (ja) * 1987-06-22 1996-02-07 松下電子工業株式会社 スタチックｒａｍ回路
US5432944A (en) * 1991-08-05 1995-07-11 Motorola, Inc. Data processing system having a dynamically enabled input synchronizer for selectively minimizing power consumption
US5327394A (en) * 1992-02-04 1994-07-05 Micron Technology, Inc. Timing and control circuit for a static RAM responsive to an address transition pulse
US5430683A (en) * 1994-03-15 1995-07-04 Intel Corporation Method and apparatus for reducing power in on-chip tag SRAM
US5692202A (en) * 1995-12-29 1997-11-25 Intel Corporation System, apparatus, and method for managing power in a computer system
US5911153A (en) * 1996-10-03 1999-06-08 International Business Machines Corporation Memory design which facilitates incremental fetch and store requests off applied base address requests
US5848428A (en) * 1996-12-19 1998-12-08 Compaq Computer Corporation Sense amplifier decoding in a memory device to reduce power consumption
US6141765A (en) * 1997-05-19 2000-10-31 Gigabus, Inc. Low power, high speed communications bus
US6243817B1 (en) * 1997-12-22 2001-06-05 Compaq Computer Corporation Device and method for dynamically reducing power consumption within input buffers of a bus interface unit
US6330679B1 (en) 1997-12-31 2001-12-11 Intel Corporation Input buffer circuit with dual power down functions
JPH11212687A (ja) * 1998-01-26 1999-08-06 Fujitsu Ltd バス制御装置
US6058059A (en) * 1999-08-30 2000-05-02 United Microelectronics Corp. Sense/output circuit for a semiconductor memory device
JP4216415B2 (ja) * 1999-08-31 2009-01-28 株式会社ルネサステクノロジ 半導体装置
JP2001167580A (ja) * 1999-12-07 2001-06-22 Toshiba Corp 半導体記憶装置
US6609171B1 (en) * 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
KR100546184B1 (ko) * 2000-10-20 2006-01-24 주식회사 하이닉스반도체 센스 앰프 회로
US7000065B2 (en) * 2002-01-02 2006-02-14 Intel Corporation Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers
US6961787B2 (en) * 2002-01-07 2005-11-01 Intel Corporation Method and apparatus for updating task files
US7152167B2 (en) * 2002-12-11 2006-12-19 Intel Corporation Apparatus and method for data bus power control

Also Published As

Publication number Publication date
AU2003293030A8 (en) 2004-06-30
US20040128416A1 (en) 2004-07-01
ATE437394T1 (de) 2009-08-15
EP1570335A2 (en) 2005-09-07
JP2006511897A (ja) 2006-04-06
KR20050085590A (ko) 2005-08-29
KR100737549B1 (ko) 2007-07-10
EP1570335B1 (en) 2009-07-22
WO2004053706A3 (en) 2004-11-18
WO2004053706A2 (en) 2004-06-24
EP2109029B1 (en) 2012-12-26
AU2003293030A1 (en) 2004-06-30
CN100422905C (zh) 2008-10-01
DE60328520D1 (de) 2009-09-03
TW200428279A (en) 2004-12-16
JP4813180B2 (ja) 2011-11-09
EP2109029A1 (en) 2009-10-14
HK1075949A1 (en) 2005-12-30
CN1726451A (zh) 2006-01-25

Similar Documents

Publication Publication Date Title
TWI310910B (en) An apparatus and method for address bus power control
Risheg et al. A recurrent mutation in MED12 leading to R961W causes Opitz-Kaveggia syndrome
Grau et al. Detection of African swine fever, classical swine fever, and foot-and-mouth disease viruses in swine oral fluids by multiplex reverse transcription real-time polymerase chain reaction
WO2006013425A8 (en) A data processing system for accurately calculating a policyholder's discount in a medical insurance plan and a method therefor
CA2186598A1 (en) Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge
Lee et al. Encephalomyelitis associated with Akabane virus infection in adult cows
WO2008144179A8 (en) Method and apparatus for cache transactions in a data processing system
Fung et al. Does aging matter? The efficacy of carpal tunnel release in the elderly
WO2004021297A3 (en) Interactive retrofit capable loyalty device
Cao et al. To Zika and destroy: an antimalarial drug protects fetuses from Zika infection
Hågå et al. Pricing and reimbursement of pharmaceuticals in Norway
Wasserman et al. Re-analysis of modeling a switch from a 13-valent to 10-valent pneumococcal conjugate vaccine in Canada: leveraging real-world experience from Belgium
Centers for Disease Control and Prevention Active Bacterial Core Surveillance Report, Emerging Infections Program Network, Legionellosis, 2015
Malik Genomics research: the underpinning of infectious disease prevention and control strategies
Baev et al. The South Caucasus: a challenge for the EU
Ting The potential adverse patient effects of ambulance ramping, a relatively new problem at the interface between prehospital and ED care
Rigo et al. In-brace correction of the Cobb angle with RSC-CAD CAM compared with'hand made'from the original author
WO2003087979A3 (en) A system for processing healthcare claim data
Miroshkina et al. The effectiveness of frozenthawed embryo transfer in patients with different transcriptional gene signatures of endometrial receptivity
Hadid et al. Author Correction: the genetic legacy of continental scale admixture in Indian Austroasiatic speakers
Hurlburt et al. Peanut panallergen Ara h 8 IgE and IgG4 epitopes
Igarashi et al. Response to Feemster KA et al. letter to the editor on Cost-effectiveness analysis for PCV13 in adults 60 years and over with underlying medical conditions which put them at an elevated risk of pneumococcal disease in Japan
Claudio et al. Recurrence and algorithmic information
Mylonas et al. Erratum to: Evidence of inhibin/activin subunit betaC and betaE synthesis in normal human endometrial tissue
Campbell DATA-MINE OPERATORS.

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees