TWI301976B

TWI301976B - Internal voltage generating circuit in semiconductor memory device

Info

Publication number: TWI301976B
Application number: TW093105704A
Authority: TW
Inventors: Chang-Ho Do
Original assignee: Hynix Semiconductor Inc
Priority date: 2003-12-30
Filing date: 2004-03-04
Publication date: 2008-10-11
Also published as: JP4380386B2; JP2005196727A; KR20050070279A; TW200522066A; CN1637946B; CN1637946A; US7068547B2; US20050141292A1; KR100605589B1

Description

1301976 玖、發明說明： (一）發明所屬之技術領域：本發明係有關一種半導體記憶裝置，且更特別的是有關一種半導體記憶裝置中之內電壓產生電路。 (二）先前技術：1301976 发明, DESCRIPTION OF THE INVENTION: (I) Technical Field to Which the Invention pertains: The present invention relates to a semiconductor memory device, and more particularly to an internal voltage generating circuit in a semiconductor memory device. (ii) Prior art:

一般而言，因爲記憶體晶片的高度合倂，使單元尺寸變得更小同時也降低了其操作電壓。大多數記憶體晶片都含有一內電壓產生電路以產生用以操作記憶體晶片之內部電路所需要的內電壓。重要的因素是定常地提供具有穩定之電壓位準的內電壓。第1圖係用以顯示一種半導體記憶裝置中之習知內電壓產生電路的電路圖。In general, because of the high degree of integration of the memory chips, the cell size is made smaller and the operating voltage is also reduced. Most memory chips contain an internal voltage generating circuit to generate the internal voltage required to operate the internal circuitry of the memory chip. An important factor is the constant provision of an internal voltage with a stable voltage level. Fig. 1 is a circuit diagram for showing a conventional internal voltage generating circuit in a semiconductor memory device.

如圖所示，該內電壓產生電路包含：一比較器1 〇，係用於將內電壓 Vint的電壓位準與參考電壓 VREF作比較 ;以及一上拉式PMOS電晶體MP1，係連接在電源供應電壓VDD與輸出端子之間，且其閘極會接收該比較器1 〇的輸出信號d r v _ ο n b。較佳的是該比較器1 〇建造有一電流鏡像型式的標準差分放大器。該比較器1〇係藉由將參考電壓VREF與內電壓Vint作比較而在內電壓Vint低於參考電壓VREF時輸出呈邏輯低位準的輸出信號drvjnb，以致打開了該上拉式PMOS電晶體MP1。因此，增加了該內電壓Vint的電壓位準。另一方面，假如使該內電壓 Vint的電壓位準增加到高於參考電壓VREF的電壓位準，則該比較器10的輸出信 -5- 1301976As shown, the internal voltage generating circuit includes: a comparator 1 〇 for comparing the voltage level of the internal voltage Vint with a reference voltage VREF; and a pull-up PMOS transistor MP1 connected to the power supply The supply voltage VDD is between the output terminal and the gate thereof receives the output signal drv_ ο nb of the comparator 1 。. Preferably, the comparator 1 is constructed with a standard differential amplifier of current mirror type. The comparator 1 outputs an output signal drvjnb having a logic low level when the internal voltage Vint is lower than the reference voltage VREF by comparing the reference voltage VREF with the internal voltage Vint, so that the pull-up PMOS transistor MP1 is turned on. . Therefore, the voltage level of the internal voltage Vint is increased. On the other hand, if the voltage level of the internal voltage Vint is increased to a voltage level higher than the reference voltage VREF, the output signal of the comparator 10 is -5- 1301976

，奢虫J ^ηιΚ-：, -5 ------ ---------------- 號drv_onb會變爲邏輯高位準，以致關閉了該上拉式PMOS 電晶體MP1。因此，停止了該內電壓 Vint之電壓位準的上升。使用由該內電壓產生電路產生的內電壓當作內部電路 100的源隨耦器。在藉由操作該內部電路產生電力消耗之後，重複上述比較程序直到該內電壓 Vint的電壓位準變成等於參考電壓VREF的電壓位準爲止。該內部電路的電力消耗會隨著所製造半導體記憶裝置之操作速率的變高而增加。因此，應該增加該內電壓產生電路內之驅動器亦即該上拉式PMOS電晶體MP1的尺寸以產生穩定的內電壓Vint。同時，隨著操作電壓的減少，一 MOS電晶體的臨限電壓也逐漸地減低。據此，存在的問題是該內電壓Vint會因該上拉式PMOS 電晶體MP 1內所產生的次臨限電流，而產生正比於電源供應電壓VDD之增加而增加。一般而言，係由下列方程式1定義出MOS電晶體內流動的次臨限電流：, luxury insect J ^ ηιΚ-:, -5 ------ ---------------- No. drv_onb will become a logic high level, so that the pull-up PMOS is turned off Transistor MP1. Therefore, the rise of the voltage level of the internal voltage Vint is stopped. The internal voltage generated by the internal voltage generating circuit is used as a source follower of the internal circuit 100. After the power consumption is generated by operating the internal circuit, the above comparison procedure is repeated until the voltage level of the internal voltage Vint becomes equal to the voltage level of the reference voltage VREF. The power consumption of the internal circuit increases as the operating rate of the manufactured semiconductor memory device becomes higher. Therefore, the size of the driver in the internal voltage generating circuit, i.e., the pull-up PMOS transistor MP1, should be increased to produce a stable internal voltage Vint. At the same time, as the operating voltage is reduced, the threshold voltage of a MOS transistor is gradually reduced. Accordingly, there is a problem that the internal voltage Vint is increased in proportion to the increase in the power supply voltage VDD due to the secondary current generated in the pull-up PMOS transistor MP1. In general, the secondary current in the MOS transistor is defined by Equation 1 below:

Isub = I〇 · exp[q · Vgs/nkT] (方程式 1) I〇 = Isub0(W/L) 其中q，Vgs，k和T代表的分別是電子的電荷、閘極源的電壓、溫度常數以及絕對溫度。同時Isuh指的是程序中所得到的電流値，而W和L代表的分別是MOS電晶體的寬度和長度。 -6- 1301976 如方程式1所示，該次臨限電流係線性地正比於MOS 電晶體的寬度且其指數係正比於Vgs。 (三）發明內容：因此，本發明的目的是提供一種半導體記億裝置中之內電壓產生電路，其中該內電壓產生電路可抑制其內電壓肇因於在上拉式驅動器內流動的次臨限電流產生的電位增加Isub = I〇· exp[q · Vgs/nkT] (Equation 1) I〇= Isub0(W/L) where q, Vgs, k and T represent the charge of the electron, the voltage of the gate source, and the temperature constant And absolute temperature. At the same time, Isuh refers to the current 値 obtained in the program, and W and L represent the width and length of the MOS transistor, respectively. -6- 1301976 As shown in Equation 1, the secondary current is linearly proportional to the width of the MOS transistor and its index is proportional to Vgs. (III) SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an internal voltage generating circuit in a semiconductor device, wherein the internal voltage generating circuit can suppress the internal voltage due to the second flow in the pull-up type driver Current increase due to current limit

根據本發明某一槪念提供的一種半導體記憶裝置中之內電壓產生電路包含：一比較單元，係用於將內電壓的電壓位準與參考電壓的電壓位準作比較；一上拉式驅動單元，係用於執行輸出端子的上拉作業以回應該比較單元的輸出信號；以及一放電單元，係在該內電壓之電壓位準高於預定目標之電壓位準的週期內用於使輸出端子放電。An internal voltage generating circuit in a semiconductor memory device according to a certain aspect of the present invention comprises: a comparing unit for comparing a voltage level of an internal voltage with a voltage level of a reference voltage; and a pull-up driving a unit for performing a pull-up operation of the output terminal to return an output signal of the comparison unit; and a discharge unit for making the output during a period in which the voltage level of the internal voltage is higher than a predetermined target voltage level The terminal is discharged.

根據本發明另一槪念提供的一種半導體記憶裝置中之內電壓產生電路包含：一比較單元，係用於將內電壓的電壓位準與參考電壓的電壓位準作比較；一上拉式驅動單元，係用於執行輸出端子的上拉作業以回應該比較單元的輸出信號；以及一第一放電單元，係在該內電壓之電壓位準高於預定目標之電壓位準的週期內用於使輸出端子放電以回應該內電壓。 (四）實施方式：以下將參照各附圖以說明一種半導體記憶裝置中根據本發明之內電壓產生電路。第2圖係用以顯示一種半導體記憶裝置中根據本發明之 -7-According to another aspect of the present invention, an internal voltage generating circuit in a semiconductor memory device includes: a comparing unit for comparing a voltage level of an internal voltage with a voltage level of a reference voltage; and a pull-up driving a unit for performing a pull-up operation of the output terminal to return an output signal of the comparison unit; and a first discharge unit for using a period in which the voltage level of the internal voltage is higher than a predetermined target voltage level Discharge the output terminal to return the internal voltage. (4) Embodiments: An internal voltage generating circuit according to the present invention in a semiconductor memory device will be described below with reference to the accompanying drawings. Figure 2 is a diagram showing a -7- according to the present invention in a semiconductor memory device.

內電壓產生電路的電路圖。該內電壓產生電路包含：一比較器20，係用於將內電壓 Vint的電壓位準與參考電壓 VREF作比較；一上拉式 PMOS電晶體MP2，係連接在電源供應電壓 VDD與輸出端子之間，且其閘極會接收該比較器 20的輸出信號 drv_〇nb ;以及各放電單元30, 40和50，係在該內電壓Vint 之電壓位準高於預定目標之電壓位準的週期內用於使輸出端子放電。此中，較佳的是該比較器20建造有一電流鏡像型式的標準差分放大器。該第一放電單元50係用以在內電壓Vint的電壓位準上使輸出端子放電，而該第二放電單元3 0和40係用以使輸出端子放電以回應該電源供應電壓 VDD的電壓位準。該第一放電單元 5 0包含依串聯方式連接在電源供應電壓 VDD與接地電壓VSS之間的複數個二極體耦合式NMOS 電晶體MN2，MN3和MN4。該第二放電單元包含一分壓器 3〇及一放電驅動器40。該分壓器30係藉由分割該電源供應電壓VDD產生一放電控制信號Va，而該放電驅動器 4〇則用以使輸出端子放電以回應該放電控制信號Va。該分壓器30可建造有依串聯方式連接在電源供應電壓VDD 與接地電壓VSS之間的第一電阻器R1和第二電阻器R2 。該放電驅動器40包含一連接在輸出端子與接地電壓VSS 之間的NMOS電晶體MN1且其閘極會接收該放電控制信號Va。以下將說明一種半導體記憶裝置中根據本發明之內電壓 -8-Circuit diagram of the internal voltage generating circuit. The internal voltage generating circuit comprises: a comparator 20 for comparing the voltage level of the internal voltage Vint with the reference voltage VREF; a pull-up PMOS transistor MP2 connected to the power supply voltage VDD and the output terminal And the gate thereof receives the output signal drv_〇nb of the comparator 20; and each of the discharge cells 30, 40 and 50 is in a period in which the voltage level of the internal voltage Vint is higher than a predetermined target voltage level. Used to discharge the output terminals. Preferably, the comparator 20 is constructed with a standard differential amplifier of current mirror type. The first discharge unit 50 is configured to discharge the output terminal at a voltage level of the internal voltage Vint, and the second discharge unit 30 and 40 are configured to discharge the output terminal to return a voltage level of the power supply voltage VDD. quasi. The first discharge cell 50 includes a plurality of diode-coupled NMOS transistors MN2, MN3 and MN4 connected in series between a power supply voltage VDD and a ground voltage VSS. The second discharge unit includes a voltage divider 3A and a discharge driver 40. The voltage divider 30 generates a discharge control signal Va by dividing the power supply voltage VDD, and the discharge driver 4 is used to discharge the output terminal to respond to the discharge control signal Va. The voltage divider 30 can be constructed with a first resistor R1 and a second resistor R2 connected in series between the power supply voltage VDD and the ground voltage VSS. The discharge driver 40 includes an NMOS transistor MN1 connected between the output terminal and the ground voltage VSS and whose gate receives the discharge control signal Va. The internal voltage -8- according to the present invention in a semiconductor memory device will be described below.

.)正替換頁〇產生電路的作業比較器20係藉由將參考電壓VREF與內電壓Vint作比較而在內電壓 Vint低於參考電壓 VREF時輸出呈邏輯低位準的輸出信號drv_onb，以致打開了該上拉式PMOS電晶體MP2。因此，增加了該內電壓Vint的電壓位準。另一方面，假如使該內電壓Vint的電壓位準增加到高於參考電壓VREF的電壓位準，則該比較器20的輸出信號drv_〇nb會變爲邏輯高位準，以致關閉了該上拉式PMOS 電晶體MP2。因此，停止了該內電壓Vint之電壓位準的上升。不過，該內電壓 Vint的電壓位準實質上會肇因於在該上拉式PMOS電晶體MP2之關閉狀態中流動的次臨限電流而增加。此時，可操作各放電單元30，40和50以致能抑制該內電壓Vint之電壓位準出現不正常的上升。該二極體耦合式NMOS電晶體的特徵爲可在將一高於該 NMOS電晶體之臨限電壓Vtn的電壓加到閘極（或汲極）上時打開諸如二極體之類的NMOS電晶體，且在施加有低於該NMOS電晶體之臨限電壓Vtn的電壓時關閉該NMOS電晶體使之因此具有一對應於該臨限電壓的有效應電阻値。據此，假如該複數個二極體耦合式NMOS電晶體係作串聯連接，則在輸出端子上的電壓位準高於nXVtii時（其中 η 代表的是NMOS電晶體的數目）打開了所有的NMOS電晶體，以致使該輸出端子產生放電。另一方面，假如該內電壓Vint的電壓位準低於η X Vtn則關閉了所有的NMOS電 -9- 汛43分愤孫^)正替換頁The operation comparator 20 that is replacing the page generation circuit outputs an output signal drv_onb which is at a logic low level when the internal voltage Vint is lower than the reference voltage VREF by comparing the reference voltage VREF with the internal voltage Vint, so that the voltage is turned on. The pull-up PMOS transistor MP2. Therefore, the voltage level of the internal voltage Vint is increased. On the other hand, if the voltage level of the internal voltage Vint is increased to a voltage level higher than the reference voltage VREF, the output signal drv_〇nb of the comparator 20 becomes a logic high level, so that the upper side is turned off. Pull PMOS transistor MP2. Therefore, the rise of the voltage level of the internal voltage Vint is stopped. However, the voltage level of the internal voltage Vint is substantially increased due to the secondary current flowing in the off state of the pull-up PMOS transistor MP2. At this time, each of the discharge cells 30, 40 and 50 can be operated to suppress an abnormal rise in the voltage level of the internal voltage Vint. The diode-coupled NMOS transistor is characterized in that an NMOS device such as a diode is turned on when a voltage higher than a threshold voltage Vtn of the NMOS transistor is applied to a gate (or a drain). The crystal, and when a voltage lower than the threshold voltage Vtn of the NMOS transistor is applied, turns off the NMOS transistor so that it has an effective resistance 对应 corresponding to the threshold voltage. Accordingly, if the plurality of diode-coupled NMOS transistor systems are connected in series, when the voltage level on the output terminal is higher than nXVtii (where η represents the number of NMOS transistors), all NMOSs are turned on. The transistor is such that the output terminal is discharged. On the other hand, if the voltage level of the internal voltage Vint is lower than η X Vtn, all the NMOS power is turned off. -9- 汛43 points anger Sun ^) Positive replacement page

-ΊΤΓ^ί*-^^ jMt ΛΉΜΕΙΜβ^δα^^ββ^ββββΒ^βββββ^βιβββ^βίΐΓ filMI J ^J 晶體，以致停止了來自該輸出端子的放電作業。據此，假如調整NMOS電晶體的數目或是NMOS電晶體的臨限電壓使η X Vtn高於該內電壓Vint的電壓位準，則能以一額外的控制電路抑制該內電壓Vint的上升。可藉由下列方程式2定出該放電控制信號Va :-ΊΤΓ^ί*-^^ jMt ΛΉΜΕΙΜβ^δα^^βββββββΒβββββββββββββΐΓ filMI J ^J crystal, so that the discharge operation from the output terminal is stopped. Accordingly, if the number of NMOS transistors or the threshold voltage of the NMOS transistor is adjusted so that η X Vtn is higher than the voltage level of the internal voltage Vint, the rise of the internal voltage Vint can be suppressed by an additional control circuit. The discharge control signal Va can be determined by Equation 2 below:

Va = (R2/(Rl+R2))XVDD(方程式 2) 亦即，該放電控制信號Va係根據該電源供應電壓vdd 之電壓位準的變化作線性改變。可藉由調整電阻器R1和R2 的電阻値以控制該放電控制信號Va的電壓位準。假如係將該放電控制信號Va加到該NMOS電晶體MN1的閘極上，則可藉由於升高該內電壓Vint使之超過一目標電壓位準的週期內打開該NMOS電晶體以執行放電作業。因此，可抑制該內電壓Vint出現不正常的上升。在製造了半導體記憶裝置之後，可在諸如燒入測試之類測試程序中提高該電源供應電壓的電壓位準。此時，可根據該電源供應電壓VDD之電壓位準來提高該內電壓Vint 的電壓位準。假如該NMOS電晶體MN1的設計是可藉由調整該放電控制信號 Va的電壓位準於飽和區域內操作，則可抑制該內電壓Vint的電壓位準出現不正常的上升。同時，當該電源供應電壓VDD之電壓位準未在正常作業中出現改變時，假如係藉由調整該放電控制信號Va以執行和透過測試量測得的次臨限電流一樣的放電作業，則可抑制該內電壓Vint的電壓位準出現不正常的上升。第3圖係用以顯示如第1圖和第2圖所示內電壓產生電Va = (R2 / (Rl + R2)) XVDD (Equation 2) That is, the discharge control signal Va is linearly changed in accordance with the change in the voltage level of the power supply voltage vdd. The voltage level of the discharge control signal Va can be controlled by adjusting the resistance 値 of the resistors R1 and R2. If the discharge control signal Va is applied to the gate of the NMOS transistor MN1, the NMOS transistor can be turned on by a period in which the internal voltage Vint is raised to exceed a target voltage level to perform a discharge operation. Therefore, an abnormal rise of the internal voltage Vint can be suppressed. After the semiconductor memory device is fabricated, the voltage level of the power supply voltage can be increased in a test program such as a burn-in test. At this time, the voltage level of the internal voltage Vint can be increased according to the voltage level of the power supply voltage VDD. If the NMOS transistor MN1 is designed to operate in the saturation region by adjusting the voltage level of the discharge control signal Va, an abnormal rise in the voltage level of the internal voltage Vint can be suppressed. Meanwhile, when the voltage level of the power supply voltage VDD is not changed in normal operation, if the discharge control signal Va is adjusted to perform the same discharge operation as the second limit current measured by the test quantity, An abnormal rise in the voltage level of the internal voltage Vint can be suppressed. Figure 3 is used to display the internal voltage generating electricity as shown in Figures 1 and 2

路之內電壓模如圖所示，擬結果的曲線圖。根據習知設計隨著電源供應電壓的增加升高該內電壓 Vint_old的電壓位準，不過根據本發明該內電壓Vint_new的電壓位準並未隨著電源供應電壓VDD的增加升高到超過目標電壓亦即1 · 6伏特。該第一放電單元50中，即使使用了三個二極體耦合式 NMOS電晶體，也可根據該內電壓Vint的目標電壓位準以及該NMOS電晶體的臨限電壓調整二極體耦合式NMOS電晶體的數目。同時根據本發明的較佳實施例，使用了兩個放電單元。不過，也可只使用該放電單元之一以抑制該內電壓Vint 的電壓位準出現不正常的上升。如上所述，由於可根據本發明抑制其內電壓之電壓位準肇因於在上拉式驅動器內流動的次臨限電流產生的不正常上升，故可改良該半導體記憶裝置的可靠度及操作特徵。雖則已針對各較佳實施例說明了本發明，熟悉習知技術的人應該鑑賞的是可在不偏離本發明所附申請專利範圍之精神及架構下作各種改變和修正。 (五）圖式簡單說明：本發明的上述及其他目的及特性將會因爲以下參照各附圖對較佳實施例的說明而變得更淸楚。第1圖係用以顯示一種半導體記憶裝置中之習知內電壓產生電路的電路圖 1301976 產生電路的電路圖。第2圖係用以顯示一種半導體記憶裝置中根據本發明之內電壓產生電路的電路圖。第3圖係用以顯示如第1圖和第2圖所示內電壓產生電路之內電壓模擬結果的曲線圖。主要部分之代表符號說明： 10 比較器 20 比較器 30 分壓器 40 放電驅動器 50 第一放電單元 100,200 內部電路 MP 1，MP2 上拉式PMOS 電晶體 MN 1 Ν Μ O S電晶體 MN2，MN3，MN4 二極體耦合式 NMOS R1，R2 電阻器 VDD 電源供應電壓 VSS 接地電壓 Va 放電控制信號The voltage mode inside the road is shown in the figure, the graph of the proposed result. According to the conventional design, the voltage level of the internal voltage Vint_old increases as the power supply voltage increases, but the voltage level of the internal voltage Vint_new does not rise above the target voltage as the power supply voltage VDD increases according to the present invention. That is, 1 · 6 volts. In the first discharge unit 50, even if three diode-coupled NMOS transistors are used, the diode-coupled NMOS can be adjusted according to the target voltage level of the internal voltage Vint and the threshold voltage of the NMOS transistor. The number of transistors. Also in accordance with a preferred embodiment of the present invention, two discharge cells are used. However, it is also possible to use only one of the discharge cells to suppress an abnormal rise in the voltage level of the internal voltage Vint. As described above, since the voltage level of the internal voltage can be suppressed according to the present invention due to the abnormal rise of the secondary current flowing in the pull-up type driver, the reliability and operation of the semiconductor memory device can be improved. feature. While the invention has been described with respect to the preferred embodiments of the embodiments of the present invention, it will be appreciated that various changes and modifications can be made without departing from the spirit and scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and features of the present invention will become more apparent from the following description of the preferred embodiments. Fig. 1 is a circuit diagram showing a circuit diagram of a conventional internal voltage generating circuit in a semiconductor memory device 1301976. Fig. 2 is a circuit diagram for showing an internal voltage generating circuit according to the present invention in a semiconductor memory device. Fig. 3 is a graph showing the results of voltage simulations of the internal voltage generating circuits as shown in Figs. 1 and 2. Representative symbols for the main part: 10 Comparator 20 Comparator 30 Voltage divider 40 Discharge driver 50 First discharge unit 100, 200 Internal circuit MP 1, MP2 Pull-up PMOS transistor MN 1 Ν Μ OS transistor MN2, MN3, MN4 Diode-coupled NMOS R1, R2 Resistor VDD Power supply voltage VSS Ground voltage Va Discharge control signal

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Claims

1 i 130197^ 〇nii / u^[灌1^6正本| 第93105704號「半導體記憶裝置中之內電壓產生電路」專利案 (2008年1月修正）拾、申請專利範圍： 1. 一種半導體記憶裝置之內電壓產生電路，包含：一比較手段，係用於將內電壓的電壓位準與參考電壓的電壓位準作比較；1 i 130197^ 〇nii / u^[Irrigation 1^6 original | No. 93105704 "Phase generation circuit in semiconductor memory device" Patent case (revised in January 2008) Pickup, patent application scope: 1. A semiconductor memory a voltage generating circuit in the device, comprising: a comparing means for comparing a voltage level of the internal voltage with a voltage level of the reference voltage;

一上拉式驅動手段，係響應該比較手段的輸出信號來執行輸出端子的上拉作業；一第一放電手段，係當該內電壓之電壓位準高於預定目標之電壓位準的時候，使該輸出端子放電，以響應該內電壓；以及一第二放電手段，係響應一放電控制信號來使該輸出端子放電，而該放電控制信號係與一電源供應電壓之電壓位準變化呈線性變化，a pull-up driving means for performing a pull-up operation of the output terminal in response to an output signal of the comparing means; a first discharging means, when the voltage level of the internal voltage is higher than a predetermined target voltage level, Discharging the output terminal in response to the internal voltage; and a second discharging means for discharging the output terminal in response to a discharge control signal, wherein the discharge control signal is linear with a voltage level change of a power supply voltage Variety,

其中，該第一放電手段包含連接在該輸出端子與該接地電壓之間的複數個二極體耦合式NMOS電晶體。 2 ·如申請專利範圍第1項之內電壓產生電路，其中該第二放電手段包含：一分壓器，係藉由分割該電源供應電壓而產生該放電控制信號；以及一放電驅動器，係響應該放電控制信號來執行該輸出端子之放電作業。 3.如申請專利範圍第2項之內電壓產生電路，其中該分壓 1301976 器包含依串聯方式連接在該電源供應電壓與該接地電壓之間的第一和第二電阻器。 4 ·如申請專利範圍第3項之內電壓產生電路，其中該放電 ’ 驅動器包含一連接在該輸出端子與該接地電壓之間的、 NMOS電晶體，且其閘極會接收該放電控制信號。 5 ·如申請專利範圍第1項之內電壓產生電路，其中該上拉式驅動手段係包含一連接在該電源供應電壓與該輸出端子之間的Ρ Μ Ο S電晶體，且其閘極會接收該比較手段的輸出信號。 0 6. —種半導體記憶裝置中之內電壓產生電路，包含·· 一比較單元，係用於將內電壓的電壓位準與參考電壓的電壓位準作比較；一上拉式驅動單元，係響應該比較裝置的輸出信號來執行輸出端子的上拉作業；以及一放電單元，係用於在該內電壓之電壓位準高於預定目標之電壓位準的週期內使輸出端子放電，且該放電單元包含第一及第二放電元件； Φ 其中，在該第一放電單元、第二放電單元與兩者之組合中的其中之一係包含複數個主動式負載，該等以串聯方式連接在該輸出端子與一接地電壓端子之間。 7. 如申請專利範圍第6項之內電壓產生電路，其中該第一放電元件包含依串聯方式連接在該輸出端子與該接地電壓之間的複數個二極體耦合式NMOS電晶體。 8. 如申請專利範圍第6項之內電壓產生電路，其中該第一放 -2- 1301976 電元件係配置成響應該內部電壓來使該輸出端子放電；且該第二放電元件係配置成響應一放電控制信號來使該輸出端子放電，而該放電控制信號係與一電源供應電壓之電壓位準變化呈線性變化。 9.如申請專利範圍第8項之內電壓產生電路，其中該第二放電元件包含：一分壓器，係藉由分割該電源供應電壓而產生該放電控制信號；以及The first discharge means includes a plurality of diode-coupled NMOS transistors connected between the output terminal and the ground voltage. 2. The voltage generating circuit of claim 1, wherein the second discharging means comprises: a voltage divider that generates the discharge control signal by dividing the power supply voltage; and a discharge driver that sounds The discharge control operation should be performed by discharging the control signal. 3. The voltage generating circuit of claim 2, wherein the voltage dividing 1301976 comprises first and second resistors connected in series between the power supply voltage and the ground voltage. 4. A voltage generating circuit as in claim 3, wherein the discharge' driver comprises an NMOS transistor connected between the output terminal and the ground voltage, and a gate thereof receives the discharge control signal. 5. The voltage generating circuit of claim 1, wherein the pull-up driving means comprises a Ρ Ο 电 transistor connected between the power supply voltage and the output terminal, and the gate thereof The output signal of the comparison means is received. 0 6. A voltage generating circuit in a semiconductor memory device, comprising: a comparison unit for comparing a voltage level of an internal voltage with a voltage level of a reference voltage; a pull-up driving unit And performing a pull-up operation of the output terminal in response to the output signal of the comparison device; and a discharge unit configured to discharge the output terminal during a period in which the voltage level of the internal voltage is higher than a predetermined target voltage level, and the The discharge unit includes first and second discharge elements; Φ wherein one of the first discharge unit, the second discharge unit, and a combination of the two includes a plurality of active loads, which are connected in series The output terminal is between a ground voltage terminal. 7. The voltage generating circuit of claim 6, wherein the first discharging element comprises a plurality of diode-coupled NMOS transistors connected in series between the output terminal and the ground voltage. 8. The voltage generating circuit of claim 6, wherein the first discharge -2-1301976 electrical component is configured to discharge the output terminal in response to the internal voltage; and the second discharge component is configured to respond A discharge control signal is applied to discharge the output terminal, and the discharge control signal changes linearly with a voltage level change of a power supply voltage. 9. The voltage generating circuit of claim 8, wherein the second discharging element comprises: a voltage divider that generates the discharge control signal by dividing the power supply voltage;

一放電驅動器，係響應該放電控制信號來執行該輸出端子之放電作業。 1 〇.如申請專利範圍第9項之內電壓產生電路，其中該分壓器係包含以串聯方式連接在該電源供應電壓端子與該接地電壓端子之間的第一和第二電阻器。 1 1.如申請專利範圍第1 〇項之內電壓產生電路，其中該放電驅動器包含一連接在該輸出端子與該接地電壓端子之間的Ν Μ〇S電晶體，且該Ν Μ〇S電晶體具有一閘極，可接收該放電控制信號。 Φ 12.如申請專利範圍第6項之內電壓產生電路，其中該上拉式驅動單元包含一連接在該電源供應電壓端子與該輸出端子之間的PMOS電晶體，且該PMOS電晶體具有一閘極，可接收該比較單元的該輸出信號。 -3- 1301976 柒、指定代表圖： (一）本案指定代表圖為：第（2 )圖。 (二) 本代表圖之元件代表符號簡單說明: 2 0 比較器 30 分壓器 40 放電驅動器 50 第一放電單元 200 內部電路A discharge driver is responsive to the discharge control signal to perform a discharge operation of the output terminal. 1 . The voltage generating circuit of claim 9, wherein the voltage divider comprises first and second resistors connected in series between the power supply voltage terminal and the ground voltage terminal. 1 1. The voltage generating circuit of claim 1, wherein the discharge driver comprises a Μ〇电 S transistor connected between the output terminal and the ground voltage terminal, and the Ν Μ〇 S electric The crystal has a gate that receives the discharge control signal. Φ 12. The voltage generating circuit of claim 6, wherein the pull-up driving unit comprises a PMOS transistor connected between the power supply voltage terminal and the output terminal, and the PMOS transistor has a a gate that receives the output signal of the comparison unit. -3- 1301976 柒, designated representative map: (1) The representative representative of the case is: (2). (2) The symbol of the representative figure of this representative figure is a brief description: 2 0 Comparator 30 Voltage divider 40 Discharge driver 50 First discharge unit 200 Internal circuit

捌、本案若有化學式時，請揭示最能顯示發明特徵的化學式：捌 If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention:

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