CN101814321B - Memory power gating circuit and method - Google Patents
Memory power gating circuit and method Download PDFInfo
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- CN101814321B CN101814321B CN201010119548.XA CN201010119548A CN101814321B CN 101814321 B CN101814321 B CN 101814321B CN 201010119548 A CN201010119548 A CN 201010119548A CN 101814321 B CN101814321 B CN 101814321B
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Abstract
A kind of memory power gating circuit, be configured to be connected to the memory array with builtin voltage, wherein, this power gating circuit comprises the circuit with output signal, builtin voltage, thus to remain between first threshold voltage and Second Threshold voltage lower than raising the builtin voltage of memory array when first threshold voltage and reducing builtin voltage at builtin voltage higher than when Second Threshold voltage at builtin voltage by this output signal.Present invention also offers a kind of method that maintenance has the data of the memory array of builtin voltage.
Description
The cross reference of related application
This application claims the U. S. application the 61/154th submitted on February 23rd, 2009, the right of priority of No. 744, its application is hereby expressly incorporated by reference.
Technical field
Present invention relates in general to field of semiconductor devices, more specifically, relate to the apparatus and method of the power supply requirement for control store.
Background technology
SIC (semiconductor integrated circuit) (IC) industry experienced by and has developed fast.The technical progress of IC material and design has created many for IC, and wherein, every generation all has circuit than last Dai Geng little and more complicated.IC technology scales is contracted to nm regime and adds power dissipation.The power dissipation increased causes some problem, comprises the battery life shortened in mobile system, expensive encapsulation and cooling scheme, and can cause failure of chip.In the many factors causing power dissipation, the power dissipation caused by leakage or static power dissipation constantly increase, and expection can exceed Dynamic power dissipation in the near future.
Passive Power gating contributes to reducing the power dissipation in storer.Traditional power gating circuit is made up of the head driver being connected to head (header), and this head is made up of multiple transistor.During aggressive mode, the transistor of head driver conducting head, to provide drive current to storer.During deep power down mode, head driver makes the transistor cutoff of head.During keeping data mode, the transistor of head plays the function of diode, and head driver controls transistor to keep lower internal power source voltage level.
Summary of the invention
In at least one embodiment, the memory array with builtin voltage is connected to power gating circuit (power gating circuit, powergatingcircuit).Power gating circuit by builtin voltage lower than raising builtin voltage when first threshold voltage and higher than reducing builtin voltage when Second Threshold voltage, builtin voltage being remained between first threshold voltage and Second Threshold voltage at builtin voltage.
In at least one embodiment, the data holding method with the memory array of builtin voltage comprises: the builtin voltage detecting memory array; And when builtin voltage lower than raising builtin voltage when first threshold voltage at builtin voltage higher than reducing builtin voltage when the Second Threshold voltage different from first threshold voltage, thus builtin voltage to be remained between first threshold voltage and Second Threshold voltage.
Will in conjunction with hereafter and accompanying drawing these and other embodiment and feature thereof are described in further detail.
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, the present invention may be better understood according to the following detailed description.It is emphasized that according to the standard practices in industry, various parts be not drawn to scale and only for illustration of object.In fact, in order to clearly discuss, the quantity of various parts and size can be arbitrarily increased or reduce.
Fig. 1 is the schematic diagram that the exemplary power gating circuit be connected with memory array is shown.
Fig. 2 is the schematic diagram that exemplary comparator circuit is shown.
Fig. 3 illustrates the output signal of comparator circuit and the V of memory array
internalbetween the schematic diagram of delayed (hysteresis) relation.
Fig. 4 is the schematic diagram that another example memory comprising power gating circuit is shown, this power gating circuit has fin multi-gated transistor (FinFET).
Fig. 5 is the schematic diagram that the memory array be connected with the exemplary power gating circuit comprising finite state machine is shown.
Fig. 6 be illustrate with comprise finite state machine the schematic diagram of memory array that is connected of another exemplary power gating circuit.
Fig. 7 is the schematic diagram that the exemplary power gating circuit be connected with memory array is shown.
Fig. 8 illustrates the output signal of comparator circuit and the V of memory array
internalbetween the schematic diagram of lagged relationship.
Fig. 9 is the schematic diagram that another exemplary power gating circuit be connected with memory array is shown.
Embodiment
During the keeping data mode of memory array, the transistor of head plays the function of diode.The diode current of transistor is very little, and therefore, a large amount of transistors in head are for providing the diode current needed for the data message keeping storer.But a large amount of transistors needs very large area, which increases the size of storer.As everyone knows, conventional power gating circuit is flimsy for process-voltage-temperature (PVT) change.
Propose active biased method to reduce the power dissipation of storer.Active biased method uses operational amplifier carry out continuous surveillance and regulate the voltage level of storer.But operational amplifier needs a large amount of memory area and compatible with in-line memory (such as, embedded SRAM).
Should be appreciated that, disclosing below provides many different embodiments or example, for realizing its different parts.The particular instance that parts or layout are described below is of the present invention open to simplify.Certainly, these are only examples, and are not used in and limit.Such as, in the following description, first component is formed in and can comprises the embodiment that first component and second component directly contact formation above second component, and can comprise miscellaneous part and can be formed between first component and second component with the embodiment making first component and second component directly not contact.In addition, the disclosure can in different examples repeat reference numerals and/or letter.This repetition is to simplify and object clearly, and not different embodiment described in perfect representation and/or the relation between configuration.
Embodiment relates to the operation method of power gating circuit and integrated circuit (such as, driver, storer, other circuit comprising memory array and/or their combination).Power gating circuit can be storer and provides stagnant ring (hysteresisloop), for being remained between two threshold voltages by the builtin voltage of storer during keeping data mode.
Fig. 1 shows the schematic diagram of the exemplary power gating circuit being connected to memory array.In FIG, system 100 comprises the power gating circuit 110 being connected to memory array 120.In certain embodiments, system 100 is storer (such as, DRAM, SRAM, embedded DRAM and/or embedded SRAM), driver, other integrated circuit and/or their combination.In certain embodiments, memory array 120 is connected to external power source (such as, ground or VSS).Memory array 120 comprises array matrix 121, and has the builtin voltage (V providing voltage to array matrix 121
internal).In an embodiment, builtin voltage (V
internal) be virtual CVDD (storage core power supply voltage).
In an embodiment, power gating circuit 110 comprises at least one first switch, such as has the head 111 of first end 111a and the second end 111b.In certain embodiments, the first end 111a of head 111 is connected to the V of memory array 120
internal.Second end 111b of head 111 is connected to outer power voltage (such as, the external power source CVDD of memory array 120), thus powers to system 100.In an embodiment, head 111 comprises the transistor of multiple parallel connection, such as P-type mos FET (PMOSFET).Parallel transistor is connected with memory array 120 and working current is supplied to memory array 120.During keeping data mode, the transistor of head 111 is used as diode.
In at least some embodiments, at least one second switch 113 is connected to head 111.The first end 113a of second switch 113 is connected to the first end 111a of head 111.Second end 113b of second switch 113 is connected to the second end 111b of head 111.In an embodiment, switch 113 is digital switch, analog switch, relay, other electronic switch and/or their combination.In other embodiments, switch 113 comprises at least one transistor, such as field effect transistor (FET).In an embodiment, switch 113 comprises at least one PMOSFET.In other embodiments, switch 113 comprises the PMOSFET being connected to NMOSFET.
In certain embodiments, comparator circuit 115 is connected with switch 113.The input end 115a of comparator circuit 115 is connected to the first end 113a of switch 113, and the input end 115b of comparator circuit 115 is connected to switch 113.Comparator circuit 115 detects the V of memory array 120
internal, with generating output signal.Comparator circuit 115 and switch 113 are configured to the V to memory array 120
internalfeedback loop is provided.In an embodiment, switch 113 comprises PMOSFET.
In an embodiment, comparator circuit 115 is other circuit that Schmidt trigger or the positive feedback being provided for switch 113 control.Fig. 2 is the schematic diagram of exemplary comparator circuit.In fig. 2, comparator circuit 115 is Schmidt triggers.Comparator circuit 115 comprises the V being connected to memory array 120
internalinput end 115a (as shown in Figure 1) and be connected to the output terminal 115b (as shown in Figure 1) of switch 113.In an embodiment, comparator circuit 115 comprises PMOSFET211,213,215 and 217 and NMOSFET221,223,225 and 227.Note, the quantity of transistor and the configuration of comparer 115 are only exemplary.Based on embodiment, those of ordinary skill in the art can change comparator circuit 115 and/or use other circuit to provide and control the digital feedback of switch 113.
Description is below about the V keeping memory array 120 during storer Holdover mode
internal.In order to keep the data of memory array 120, power gating circuit 110 provides hysteresis, with at V
internallower than the V raising memory array 120 when first threshold voltage
internaland at V
internalhigher than the V of the situation decline low memory array 120 of Second Threshold voltage
internal.Power gating circuit 110 is by the V of memory array 120
internalremain between first threshold voltage and Second Threshold voltage.
Fig. 3 illustrates the output signal of comparator circuit and the V of memory array
internalbetween the schematic diagram of lagged relationship.With reference to Fig. 1 and Fig. 3, the V of the input end 115a monitoring memory array 120 of comparator circuit 115
internal.During system 100 is transformed into " B " from " A ", comparator circuit 115 is at output terminal 115b generating output signal " 1 ".Output signal " 1 " cut-off switch 113.At " B " place, if determine V
internallower than first threshold voltage (such as, the data of the memory cell of array matrix 121 keep voltage (DRV)), then comparator circuit 115 outputs signal " 0 " at output terminal 115b, thus turn on-switch 113, provide the expectation magnitude of current from CVDD to raise the V of memory array 120
internaland system 100 is transformed into " C " from " B ".If system 100 is transformed into " D " from " C ", then comparator circuit 115 holding signal " 0 ", with turn on-switch 113.At state " D " place, if the V of memory array 120
internalhigher than Second Threshold voltage (such as, DRV+ Δ V), then comparator circuit 115 exports the signal " 1 " of cut-off switch 113, the state of system 100 is changed to " A " from " D ".Δ V is the amount with the voltage difference of DRV, and is any applicable value.Those of ordinary skill in the art can use different Δ V to realize different results.
Note, during keeping data mode, the PMOSFET of switch 113 provides the electric current of high about at least one order of magnitude of the electric current produced than the transistor by head 111.The PMOSFET of switch 113 is configured to the V of memory array 120
internalbecome the transistor being greater than head 111.By using the PMOSFET of switch 113, keep V
internalthe number of transistors of the head 111 needed for state and the area of head 111 decrease.Such as, traditional 32M storer has the conventional head being connected to 32M memory array.Conventional head has 32,768 transistors, for providing working current and keeping the state of the builtin voltage of 32M memory array.In one embodiment, said system 100 comprises the memory array 120 of power gating circuit 110 and 32M.Power gating circuit 110 comprises and has 16 further, the head 111 of 384 transistors and have the switch 113 of 4 PMOSFET.Thus the quantity of transistor is the half of conventional head in head 111, and the area of head 111 is about half of conventional head.In addition, system 100 is even run in design specifications when the poorest process-voltage-temperature (PVT) change (such as FF/SS/0.9V/-40 DEG C).
Fig. 4 is the schematic diagram that another exemplary storage device comprising the power gating circuit with FinFET is shown.In the diagram, system 400 comprises the power gating circuit 410 being connected to memory array 420.Memory array 420 comprises array matrix 421 and has builtin voltage V
internal.Element identical with Fig. 1 in Fig. 4 is represented by identical reference number, and just reference number number adds 300.
Power gating circuit 410 comprises at least one switch, is such as connected to the head 412 of comparator circuit 415.Comparator circuit 415 has the builtin voltage V being connected to memory array 420
internalinput end 415a and be connected to the output terminal 415b of head 412.The builtin voltage V of input end 415a monitoring memory array 420
internal, and output signal is transferred to head 412 to control head by output terminal 415b.
In an embodiment, head 412 comprises the FinFET with front grid 412a and backgate 412b.Front grid 412a receives the control signal (such as data retention signal) of output from driver.Backgate 412b is connected to the output terminal 415b of comparator circuit 415, and controls the electric current of an order of magnitude at least higher than the electric current controlled by front grid 412a, makes the electric current controlled by backgate 412b can raise or reduce the V of memory array 420
internal.
Below the V describing and keep memory array 420 during storer Holdover mode is disclosed
internalan embodiment of apparatus and method.In order to keep the data of memory array 420, power gating circuit 410 provides hysteresis, with at V
internallower than the V raising memory array 420 when first threshold voltage
internaland at V
internalhigher than the V of the situation decline low memory array 420 of Second Threshold voltage
internal.Power gating circuit 410 is by the V of memory array 420
internalremain between first threshold voltage and Second Threshold voltage.
With reference to Fig. 3 and Fig. 4, the input end 415a of comparator circuit 415 detects the V of memory array 420
internal.The running status of supposing the system 400 is transformed into " B " (as shown in Figure 3) from " A ", then, within the time period of A to B, comparator circuit 415 outputs signal " 1 " at output terminal 415b.Output signal " 1 " is applied to the backgate 412b of head 412, to disconnect the current path controlled by backgate 412b.In state " B ", if determine V
internallower than first threshold voltage (such as, DRV), then comparator circuit 415 outputs signal " 0 ", to connect the current path controlled by backgate 412b at output terminal 415b.The current path controlled by backgate 412b is configured to provide the magnitude of current of expectation from CVDD and raise the V of memory array 420
internal.The state of system 400 changes to " C " (as shown in Figure 3) from " B ".If the running status of system 400 changes to " D " from " C ", then comparator circuit 415 keeps output signal " 0 " with conducting backgate 412b.In state " D ", if determine the V of memory array 420
internalhigher than Second Threshold voltage (such as, DRV+ Δ V), then comparator circuit 415 exports the signal " 1 " of cut-off backgate 412b, for turn-off current path.The state of system 400 changes to " A " from " D ".
Note, the system 400 of Fig. 4 comprises power gating circuit 410, and it uses FinFET to provide working current to memory array 420.Compared with the power gating circuit 110 of Fig. 1, power gating circuit 410 does not comprise switch 113, further reduces the area of head 412.In other embodiments, power gating circuit 410 comprises the switch of such as switch 113, to realize feedback compensation or the hysteresis of expectation.
Fig. 5 is the schematic diagram that the memory array being connected to the exemplary power gating circuit comprising finite state machine is shown.Element identical with Fig. 1 in Fig. 5 is represented by identical reference number, and just reference number number adds 400.In Figure 5, power gating circuit 510 comprises the finite state machine 530 be connected between comparator circuit 515 and switch 513.Finite state machine 530 receives output signal from comparator circuit 515 and generates the signal with multiple state (such as, 4,8,16 or more) subsequently.The operation of multimode output signal gauge tap 513, to provide feedback loop or lag compensation.Those of ordinary skill in the art can select the number of states of finite state machine 530, to realize the expectation lag compensation to system 400.
Fig. 6 shows the schematic diagram of the memory array being connected to another exemplary power gating circuit comprising finite state machine.Element identical with Fig. 4 in Fig. 6 is represented by identical reference number, and just reference number number adds 200.In figure 6, finite state machine 630 is connected between the backgate 612b of FinFET and comparator circuit 615.Finite state machine 630 receives output signal from comparator circuit 615 and has the signal of multiple state (such as, 4,8,16 or more) subsequently.The operation of the backgate of multimode output signal control FinFET, to provide feedback loop or lag compensation.Those of ordinary skill in the art can select the number of states of finite state machine 630, to realize the expectation lag compensation to system 600.
Fig. 7 is the schematic diagram that the system 700 comprising the exemplary power gating circuit being connected to memory array is shown.Element identical with Fig. 1 in Fig. 7 is represented by identical reference number, and just reference number number adds 600.System 700 comprises the power gating circuit 710 being connected to memory array 720.In the figure 7, power gating circuit 710 comprises at least one switch, such as has the foot (footer) 712 of first end 712a and the second end 712b.First end 712a is connected to the first end 713a of switch 713, and the second end 712b is connected to the second end of switch 713.In an embodiment, switch 713 is NMOSFET.
Description is below the exemplary operation of system 700 during data retention mode.Fig. 8 illustrates the output signal of comparator circuit and the V of memory array
internalbetween the schematic diagram of lagged relationship.With reference to Fig. 7 and Fig. 8, the V of the input end 715a monitoring memory array 720 of comparator circuit 715
internal.In an embodiment, builtin voltage (V
internal) be virtual VSS (V_VSS).During system 700 is transformed into " F " from " E ", comparator circuit 715 at output terminal 715b generating output signal " 1 ", its turn on-switch 113.In state " F ", if determine V
internallower than first threshold voltage (such as, CVDD-DRV-Δ V), then comparator circuit 715 exports the signal " 0 " of cut-off switch 113, to keep or to raise the V of memory array 720
internal.Subsequently, the state of system 700 is transformed into " G " from " F ".If the running status of system 700 is changed into " H " from " G ", then comparator circuit 715 keeps output signal " 0 ", with cut-off switch 713.In state " H ", if the V of memory array 720
internalhigher than Second Threshold voltage (such as, CVDD-DRV), then comparator circuit 715 exports the signal " 1 " of turn on-switch 713, the state of system 700 is changed to " E " from " H ".In an embodiment, power gating circuit 710 comprises finite state machine 530 as shown in Figure 5.Finite state machine is connected between comparator circuit 715 and switch 712, to generate the multiple states for switch 713, thus provides feedback loop to compensate.
Fig. 9 is the schematic diagram that another exemplary power gating circuit being connected to memory array is shown.Element identical with Fig. 4 in Fig. 9 is represented by identical reference number, and just reference number number adds 500.In fig .9, system 900 comprises the power gating circuit 910 being connected to memory array 920.In an embodiment, power gating circuit 910 comprises at least one switch, is such as connected to the foot 911 of comparator circuit 915.
In an embodiment, foot 911 comprises the N-type FinFET with front grid 911a and backgate 911b.Front grid 911a receives the signal (such as, data retention signal) of output from driver.Backgate 911b is connected to the output terminal 915b of comparator circuit 915, and controls the electric current of at least one order of magnitude higher than the electric current controlled by front grid 911a, makes the electric current controlled by backgate 911b can raise or reduce the V of memory array 920
internal.
With reference to Fig. 8 and Fig. 9, the V of the input end 915a monitoring memory array 920 of comparator circuit 915
internal.When the state of system 900 is transformed into " F " from " E ", comparator circuit 915 generates the output signal " 1 " being applied to the backgate 911b of head 911 during time period E-F at output terminal 915b, to connect the current path controlled by backgate 911b.In state " F ", if determine V
internallower than first threshold voltage (such as, VCDD-DRV-Δ V), then comparator circuit 915 outputs signal " 0 " at output terminal 915b.Output signal " 0 " is applied to backgate 911b to disconnect the current path controlled by backgate 911b, thus raises the V of memory array 920
internal.Then, the state of system 900 changes to " G " from " F ".If the state of system 900 changes to " H " from " G ", then comparator circuit 915 keeps output signal " 0 " to end backgate 911b.In state " H ", if determine the V of memory array 920
internalhigher than Second Threshold voltage (such as, VCDD-DRV), then comparator circuit 915 exports the signal " 1 " of conducting backgate 911b, to reduce the V of memory array 920
internal.The state of system 900 changes to " E " from " H ".In at least one embodiment, power gating circuit 910 comprises finite state machine as shown in Figure 6.Finite state machine is connected between the backgate 713b of comparator circuit 715 and switch 713, to produce the multiple states for switch 713, thus provides feedback loop to compensate.
Note, above the power gating circuit that describes of composition graphs 1 to Fig. 9 and storer be all formed in can physics and be electrically connected to printed wiring board or printed circuit board (PCB) (PCB) to be formed in the system of electronic package.This electronic package can be a part for electronic system (such as, computing machine, Wireless Telecom Equipment, peripherals, amusement equipment etc. that computing machine is relevant).
Discuss the parts of some embodiments above, make the various aspects that the present invention may be better understood for those of ordinary skill in the art.It will be understood by those skilled in the art that to use easily and to design based on the present invention or to change other for the process and the structure that reach the object identical with introduced embodiment here and/or realize same advantage.Those of ordinary skill in the art also it should be appreciated that this equivalent constructions does not deviate from the spirit and scope of the present invention, and when not deviating from the spirit and scope of the present invention, can carry out multiple change, replacement and change.
Claims (22)
1. a power gating circuit, is configured to be connected to the memory array with builtin voltage, and described power gating circuit comprises:
There is the circuit of output signal, during keeping data mode, described builtin voltage, thus to remain between described first threshold voltage and described Second Threshold voltage lower than raising the described builtin voltage of described memory array when first threshold voltage and reducing described builtin voltage at described builtin voltage higher than when Second Threshold voltage at described builtin voltage by described output signal;
Wherein, the circuit described in output signal comprises:
At least one first switch, the first end of at least one the first switch described is connected to described builtin voltage, and the second end of at least one the first switch described is connected to external power voltage;
Second switch, the first end of described second switch is connected to the first end of at least one the first switch described, and the second end of second switch is connected to the second end of at least one the first switch described; And
Comparator circuit, the input end of described comparator circuit is connected to the first end of described second switch, and the output terminal of described comparator circuit is connected to described second switch, wherein, described second switch and described comparator circuit are configured to provide feedback loop to described builtin voltage.
2. power gating circuit according to claim 1, wherein, described in there is output signal circuit hysteresis is provided.
3. power gating circuit according to claim 1, wherein, at least one first switch described is the head comprising at least one P-type mos (PMOS) transistor, and described external power voltage is outer power voltage.
4. power gating circuit according to claim 1, wherein, at least one first switch described is the foot comprising at least one N-type metal-oxide semiconductor (MOS) (NMOS) transistor, and described external power voltage is ground voltage.
5. power gating circuit according to claim 1, wherein, described second switch comprises at least one field effect transistor, and at least one field effect transistor described is configured to regulate described builtin voltage to keep the data message of described memory array.
6. power gating circuit according to claim 1, wherein, described comparator circuit comprises Schmidt trigger, and described Schmidt trigger is configured to detect described builtin voltage to generate the output signal for controlling described second switch.
7. power gating circuit according to claim 1, also comprises finite state machine, is connected between described comparator circuit and described second switch.
8. a power gating circuit, is configured to be connected to the memory array with builtin voltage, and described power gating circuit comprises:
There is the circuit of output signal, during keeping data mode, described builtin voltage, thus to remain between described first threshold voltage and described Second Threshold voltage lower than raising the described builtin voltage of described memory array when first threshold voltage and reducing described builtin voltage at described builtin voltage higher than when Second Threshold voltage at described builtin voltage by described output signal;
Described power gating circuit, also comprises:
At least one first switch, comprise fin formula field effect transistor (FinFET), the first end of described first switch is connected to described builtin voltage and the second end of described first switch is connected to external power voltage, wherein, described fin formula field effect transistor comprises front grid and backgate, and described front grid can receive data retention signal; And
Comparator circuit, the input end of described comparator circuit is connected to described builtin voltage and the output terminal of described comparator circuit is connected to the described backgate of described fin formula field effect transistor, to regulate described builtin voltage, wherein, described fin formula field effect transistor and described comparator circuit are configured to provide feedback loop to described builtin voltage.
9. power gating circuit according to claim 8, wherein, described first switch is the head comprising at least one P type fin formula field effect transistor, and described external power voltage is outer power voltage.
10. power gating circuit according to claim 8, wherein, described first switch is the foot comprising at least one N-type fin formula field effect transistor, and described external power voltage is ground voltage.
11. power gating circuits according to claim 8, are also included in the finite state machine between described comparator circuit and the described backgate of described fin formula field effect transistor.
12. 1 kinds of power gating systems, comprising:
Memory array, has builtin voltage; And
Power gating circuit, be connected to described memory array, wherein, during keeping data mode, described power gating circuit be provided in described builtin voltage lower than raise described builtin voltage when first threshold voltage and at described builtin voltage higher than the function reducing described builtin voltage when Second Threshold voltage, described builtin voltage is remained between described first threshold voltage and described Second Threshold voltage;
Described power gating circuit comprises:
At least one first switch, the first end of at least one the first switch described is connected to described builtin voltage, and the second end of at least one the first switch described is connected to external power voltage;
Second switch, the first end of described second switch is connected to the first end of at least one the first switch described, and the second end of second switch is connected to the second end of at least one the first switch described; And
Comparator circuit, the input end of described comparator circuit is connected to the first end of described second switch, and the output terminal of described comparator circuit is connected to described second switch, wherein, described second switch and described comparator circuit are configured to provide feedback loop to described builtin voltage.
13. power gating systems according to claim 12, wherein, described function is hysteresis.
14. power gating systems according to claim 12, wherein, described second switch comprises at least one field effect transistor, and at least one field effect transistor described is configured to regulate described builtin voltage to keep the data message of described memory array.
15. power gating systems according to claim 12, wherein, described comparator circuit comprises Schmidt trigger, and described Schmidt trigger is configured to detect described builtin voltage to generate the output signal for controlling described second switch.
16. power gating systems according to claim 12, also comprise finite state machine, are connected between described comparator circuit and described second switch.
17. 1 kinds of power gating systems, comprising:
Memory array, has builtin voltage; And
Power gating circuit, be connected to described memory array, wherein, during keeping data mode, described power gating circuit be provided in described builtin voltage lower than raise described builtin voltage when first threshold voltage and at described builtin voltage higher than the function reducing described builtin voltage when Second Threshold voltage, described builtin voltage is remained between described first threshold voltage and described Second Threshold voltage;
Described power gating circuit comprises:
At least one first switch, comprise fin formula field effect transistor (FinFET), the first end of described first switch is connected to described builtin voltage and the second end of described first switch is connected to external power voltage, wherein, described fin formula field effect transistor comprises front grid and backgate, and described front grid can receive data retention signal; And
Comparator circuit, the input end of described comparator circuit is connected to described builtin voltage and the output terminal of described comparator circuit is connected to the backgate of described fin formula field effect transistor, to regulate described builtin voltage, wherein, described fin formula field effect transistor and described comparator circuit are configured to provide feedback loop to described builtin voltage.
18. power gating systems according to claim 17, are also included in the finite state machine between described comparator circuit and the described backgate of described fin formula field effect transistor.
19. 1 kinds for keeping the method for the data of the memory array with builtin voltage, described method comprises:
Detect the described builtin voltage of described memory array; And
During keeping data mode, based on the builtin voltage detected, be provided in described builtin voltage lower than raise described builtin voltage when first threshold voltage and at described builtin voltage higher than the function reducing described builtin voltage when Second Threshold voltage, described builtin voltage is remained between described first threshold voltage and described Second Threshold voltage, wherein, described first threshold voltage is different from described Second Threshold voltage.
20. is according to claim 19 for keeping the method for the data of the memory array with builtin voltage, and wherein, described function is hysteresis.
21. is according to claim 19 for keeping the method for the data of the memory array with builtin voltage, wherein, the described function of the builtin voltage raising or reduce described memory array comprises the current path be switched on or switched off between described builtin voltage and external power source, wherein, described current path can provide the electric current of at least one order of magnitude higher than the transistor current of the head or foot that are connected to described memory array.
22. is according to claim 19 for keeping the method for the data of the memory array with builtin voltage, also comprises: export at least one of four states, to provide described function based on detected builtin voltage.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15474409P | 2009-02-23 | 2009-02-23 | |
| US61/154,744 | 2009-02-23 | ||
| US12/707,788 | 2010-02-18 | ||
| US12/707,788 US8305829B2 (en) | 2009-02-23 | 2010-02-18 | Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same |
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| Publication Number | Publication Date |
|---|---|
| CN101814321A CN101814321A (en) | 2010-08-25 |
| CN101814321B true CN101814321B (en) | 2015-11-25 |
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| CN201010119548.XA Active CN101814321B (en) | 2009-02-23 | 2010-02-23 | Memory power gating circuit and method |
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| CN105393307B (en) * | 2013-05-16 | 2019-05-10 | 英特尔公司 | The low-power transient voltage of memory cell collapses device and method |
| KR20150090418A (en) * | 2014-01-29 | 2015-08-06 | 에스케이하이닉스 주식회사 | System using minimum opertaion power and power supply voltage setting method of memory |
| US10878852B2 (en) * | 2018-06-27 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Latch-up prevention circuit for memory storage system |
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| CN101105974A (en) * | 2006-07-14 | 2008-01-16 | 威刚科技股份有限公司 | Non-volatile memory device and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1761931A4 (en) * | 2004-05-14 | 2008-11-19 | Zmos Technology Inc | Internal voltage generator scheme and power management method |
| KR100693783B1 (en) * | 2004-11-04 | 2007-03-12 | 주식회사 하이닉스반도체 | Generator of internal volatge |
| US20070069808A1 (en) * | 2005-09-29 | 2007-03-29 | Hynix Semiconductor Inc. | Internal voltage generator |
| JP5130792B2 (en) * | 2007-06-08 | 2013-01-30 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit and system |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821808A (en) * | 1995-08-25 | 1998-10-13 | Nec Corporation | Voltage circuit for preventing voltage fluctuation |
| CN1637946A (en) * | 2003-12-30 | 2005-07-13 | 海力士半导体有限公司 | Internal voltage generating circuit in semiconductor memory device |
| CN101105974A (en) * | 2006-07-14 | 2008-01-16 | 威刚科技股份有限公司 | Non-volatile memory device and control method thereof |
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