1300484 (1) 九、發明說明 【發明所屬之技術領域】 本發明乃有關於爲了將半導體元件測試裝置及被測試 半導體元件電性地連接於半導體元件測試裝置之元件介面 板，詳細是有效活用10通道，來增大測試對象半導體元 - .......- . 件_(以下簡稱DUT )的種類或是數量的半導體元件測試裝 置，及元件介面板。 【先前技術】 於曰本專利文獻T 1乃揭示，對一條傳送線路的一端 施加驅動訊號，且在途中2分歧，將2分歧的兩傳送線路 連接於兩個DUT的構成。若根據該構成，因一個1〇通道 能驅動兩個DUT，故可達到1〇通道的有效活用。又，於 該文獻乃揭示’採用在受訊端之受訊波形訊號上，能減低 無用之振動波形的2分歧傳送線路的半導體元件測試裝置 〇 第11圖乃表示一般的半導體元件測試裝置與1C處置 (handler)裝置3 00組合來測試複數個DUT的槪念構成 圖。 半導體元件測試裝置100乃由：裝置本體101，和處 在離開裝置本體之位置而與1C處置裝置3 00經由結合線 路所連結的測試頭200所構成。測試頭200乃具有：由N 個（N爲2以上的整數）10通道所形成的複數個1〇通道 群，和一般通道（圖未示），和具有其他（圖未示）的接 -4 - (2) 1300484 腳電子（pin electronics) PE。 在此，10通道乃爲連接於DUT之10接腳（輸出/輸 入端子），若對DUT施加訊號，具有接受由DUT所輸出 的應答訊號之機能的通道之數量，通常是只設有對應DUT 之1〇接腳（即輸出/輸入端子數）的數量。一般通道是指 ，只連接於DUT之輸入接腳而進行訊號之施加的驅動器 之通道。 DUT與半導體元件測試裝置係，經由與測試頭部200 之接腳電子PE連接的效能板PB，和同軸電纜120，和插 座板16.0，接觸座180而連接。再者，間距圖框（spacing frame) 140乃於效能板PB上安裝插座板160，將該等之 組合稱爲高精度定位系統102。 專利文獻T1 :特開2000— 292491號公報 【發明內容】 〔發明欲解決之課題〕 若根據揭示於日本專利文獻T 1的連接構造，一個10 通道的驅動器之輸出乃經由一條傳送線路，在途中的分歧 點分成兩股，該等分成兩股之線路分別連接於兩個DUT， 藉此同時驅動兩個DUT。 此結果，能以一個10通道群同時測定兩個DUT，雖 能有效利用數量有限的10通道，但對波形品質具困難點 〇1300 484 (1) EMBODIMENT OF THE INVENTION [Technical Field] The present invention relates to a component panel for electrically connecting a semiconductor element test device and a semiconductor element to be tested to a semiconductor device test device, and is effective for use in detail. The channel is used to increase the semiconductor element of the test object--..-. (hereinafter referred to as DUT) type or number of semiconductor element test devices, and component interface panels. [Prior Art] Patent Document T1 discloses a configuration in which a driving signal is applied to one end of a transmission line, and two divergent transmission lines are connected to two DUTs on the way. According to this configuration, since one D channel can drive two DUTs, the effective use of one channel can be achieved. Further, in this document, a semiconductor device test device using a two-differential transmission line capable of reducing unnecessary vibration waveforms on a signal waveform received by a signal receiving terminal is disclosed. FIG. 11 is a view showing a general semiconductor device test apparatus and a 1C. A handler device 300 is combined to test the commemorative composition of a plurality of DUTs. The semiconductor element testing device 100 is composed of a device body 101 and a test head 200 connected to the 1C treatment device 300 via a bonding line at a position away from the device body. The test head 200 has a plurality of 1-channel groups formed by N (N is an integer of 2 or more) 10 channels, and a general channel (not shown), and has other connections (not shown)-4 - (2) 1300484 pin electronics PE. Here, the 10 channels are connected to the 10 pins (output/input terminals) of the DUT. If a signal is applied to the DUT, the number of channels having the function of receiving the response signal output by the DUT is usually only provided with the corresponding DUT. The number of pins (ie, the number of output/input terminals). A general channel is a channel of a driver that is connected to the input pin of the DUT for signal application. The DUT and the semiconductor component test device are connected via a performance board PB connected to the pin electronics PE of the test head 200, and a coaxial cable 120, and a socket board 16.0, a contact holder 180. Further, a spacing frame 140 is a socket board 160 mounted on the performance board PB, and the combination of these is referred to as a high-precision positioning system 102. [Problem to be Solved by the Invention] According to the connection structure disclosed in Japanese Patent Document T1, the output of a 10-channel driver is via a transmission line on the way. The divergence point is divided into two shares, and the two-divided lines are respectively connected to the two DUTs, thereby driving the two DUTs at the same time. As a result, two DUTs can be simultaneously measured in a 10-channel group, and although a limited number of 10 channels can be effectively utilized, the waveform quality is difficult.
又，若該技術，如第12B圖所示，應用於一個DUT (3) 1300484 藉由切換控制訊號而互相錯開時間所動作之具有複數對的 一對輸出/輸入端子的特殊型式之情形下，可使一個10通 道對應兩個端子，將10通道的數量減半減，但這也對波 形品質造成困難點。 亦即，在第12B圖所示的試行電路乃，對應有DUT 之對的兩個輸出/輸入接腳與一個驅動器輸出接腳P而動 作，同軸電纜乃其一端連接於驅動器輸出接腳P，另一端 連接於插座板的端子Q，該端子Q至分歧點R以特性阻抗 5 0 Ω的微小條線而連接，且具有分別連接於該分歧點r至 .2分歧線路爲一對的兩個輸出/輸入端子的構成。 有關該試行電路，於由驅動器IODR施加高速的矩形 波’以DUT之一方的輸出/輸入端子爲觀測點（View)來 觀測波形之例，於第1 2C圖示之。有關該圖所示之波形， b乃爲分歧點R至各個輸出/輸入端子的分歧線路之特性阻 抗爲100Ω時的波形，厂乃爲50Ω時的波形。 再者’爲了比較，將在有關不具第12A圖所示之分歧 線路的習知技術之電路構成的DUT之輸出/輸入端子（ View)的理想上之波形，於第i2c圖以a示之。 由該等之波形的比較，於第12B圖由分歧點R觀看 DUT側’至DUT之端子的分歧線路之阻抗爲（b - : 50Ω 之情形’由分歧點R觀看DUT之阻抗爲50 Ω / 2 = 25 Ω， 而與一直到該分歧點R的線路之特性阻抗（5 〇 Ω )形成非 匹配’存在著隨此而來的波形劣化。又，（b ) : 1 〇〇 Ω時 ’由分歧點R觀看DUT的阻抗乃爲1〇〇Ω/2==5〇Ω形成 (4) 1300484 匹配，但若由從一方之輸出/輸入端子形成全反射的訊號 _ 側觀看分歧點的話，至分歧點爲1 00 Ω，了解自那起前面 、 係，成爲輸入側之5 0 Ω與另一方之分歧線路之1 00 Ω的並 列阻抗成爲3 3 Ω，形成非匹配，存在著隨此而來的波形劣 化。因爲無論哪一個，都無法將50 Ω的終端電阻連接於 DUT側的測試裝置，故並未避免掉隨全反射而來的波形劣 化，此乃2分歧方式的極大難點。 • 因而，克服如第1 2B圖所示之具有試行例的波形品質 之劣化的缺點，要求能有效利用數量有限之10通道的半 導體元件測試裝置。 又’能有效利用數量有限之10通道的半導體元件測 試裝置係，除了上述外，連屬於如第13圖所示的半導體 元件’以同一封裝（package )具備同一端子數與同一端 子排列的半導體元件，也要求爲像是能測定寫入/讀出之 10接腳的資料寬爲x4位元，χ8位元，χ16位元之三種的 ® 元件之測試的半導體元件測試裝置。 • 在第13Α圖中’有關4位元之10接腳DQ0〜DQ4以 _ 外’資料的輸出/輸入乃爲無使用接腳NC4〜NC15，第 13Β圖乃有關8位元之10接腳DQ0〜DQ7以外，資料的 輸入及輸出爲無使用接腳NC8〜NC15，第13C圖乃16位 元之接腳DQ0〜DQ15，全作爲資料之輸入及輸出接腳 使用。以下，在該明細書中，第13Α圖所示之資料寬爲χ4 位元構成的半導體元件稱爲第一型式的半導體元件DUT — 第圖所示之資料寬爲x8位元構成的半導體元件稱 (5) 1300484 爲第二型式的半導體元件DUT - 2，第13C圖所示之資料 寬爲xl6位元構成的半導體元件稱爲第三型式的半導體元 件 DUT— 3 〇 將該等各型式的半導體元件以一個半導體元件測試裝 置進行測試，該測試裝置必須在每一各插座板，準備儘量 對應使用於安裝在插座板之DUT的三種DUT中之動作的 端子數量具最大之値的DUT之數量的1〇通道。在上述之 例中，爲了測試第三型式的DUT— 3，準備十六個10通道 〇 另一方面，對應三品種之DUT的插座板乃爲對應各 型式之DUT的10接腳DQ0〜DQ4、DQ0〜DQ7、DQ0〜 DQ15所專用的連接構成。因此，於第14圖表示各型式之 半導體元件用的插座板之一例。分別於第14A圖表示第一 型式之半導體元件DUT— 1用的插座板160— 1，第14B圖 表示第二型式之半導體元件DUT— 2用的插座板160— 2, 第14C圖表示第三型式之半導體元件DUT - 3用的插座板 160- 3。 於各接觸座1 80乃以相同接腳數，設有相同接腳排列 的接觸部（contact ) CNT，在該等接觸部***DUT的10 接腳，該等各接觸座1 80分別連接於對應的插座板。於插 座板160— 1乃有有以四個端子T1〜T4所形成的外部連接 端子群，並以連接於DUT - 1之四個動作用端子DQ0〜 D Q 3般地形成有圖案配線。於插座板1 6 0 - 2乃有有以八 個端子T 1〜T 8所形成的外部連接端子群’並圖案連接於 -8- (6) 1300484 DUT— 2之八個動作用端子DQ0〜DQ7。同時，於插座板 160— 3乃有有以十六個端子T1〜τ 1 6所形成的外部連 接端子群，並圖案連接於DUT - 3之十六個動作用端子 D Q 0 〜D Q 1 5。 由該等圖即可明白，各插座板的圖案配線設計爲每一 DUT的型式’爲製造所必要的。又，在測試存在於半導體 晶圓上之元件時，也須對每種型式的半導體元件準備探針 〇 如此，在利用者側，爲了對每種DUT之型式準備插 座板或是探針，經濟上的負擔是很大的。 又’像這樣以一個半導體元件測試裝置測試複數型式 之半導體元件時，要求減少10通道群的數量，或是倍增 相當於10通道群之可測試的DUT之數量。 本發明之目的乃欲解決上述習知例的課題，詳細是提 供可有效活有10通道的半導體元件測試裝置，具體上是 對一個DUT所必要的10通道之數量比以往少而能完成的 半導體元件測試裝置，或是可增加能以一個10通道群來 測試的DUT之種類之半導體元件測試裝置。 又，提供用於該等半導體元件測試裝置的元件介面板 〇 更詳細是提供，成對的10接腳彼此以不同的時序， 差動式地切換爲動作模式與非動作模式之型式的DUT時 ，能以較習知還少的數量的1〇通道進行測試，又，DUT 爲相同的端子數，且具有相同的端子排列，連動作所必要 -9 - (7) 1300484 的端子數不同的複數種之DUT時，也可使用同一構造的 _ 元件介面板進行測試的半導體元件測試裝置，且連動作用 乂 10接腳之數量不同的複數種之DUT爲對象時，也可使用 同一構成之元件介面板而能測試的半導體元件測試裝置。 〔用以解決課題的手段〕 爲達成該目的，在第1發明中乃提案一，雖具備第一 # 外部端子群與第二外部端子群，一方面該等之端子數及端 子排列爲相同，但不管使用第一外部端子群之一部分而動 作的第一型式之半導體元件，使用第一外部端子群之全部 而動作的第二型式之半導體元件，以及使用第一外部端子 群與第二外部端子群之全部而動作的第三型式之半導體元 件的哪一個都能連接地，在元件介面板準備配備著具有與 第一外部端子群及第二外部端子群相同之數量及排列的第 一接觸端子群以及第二接觸端子群的第一接觸具以與此相 • 同構成的第二接觸具，該第一接觸具的第一接觸端子群與 ，第二接觸具的第二接觸端子群之各對應的端子彼此以跨越 配線來共通連接，於各跨越配線的一端側，對應第一接觸 具之第一接觸端子群的各接觸端子而設置在接腳電子的第 一 ίο通道群之ίο通道的驅動器輸出接腳，於另一端側連 接該1〇通道的比較器輸入接腳，在第二接觸具的第一接 觸端子群的各接觸端子，分別將與此對應而設置在接腳電 子的第二10通道群之10通道的驅動器輸出接腳及比較器 輸入接腳以個別的配線而連接的半導體元件測試裝置。 -10- (8) 1300484 在第2發明中乃提案一，雖具備第一外部端子群與第 二外部端子群，一方面該等之端子數及端子排列爲相同， 但不管使用第一外部端子群之一部分而動作的第一型式之 半導體元件，使用第一外部端子群之全部而動作的第二型 式之半導體元件，以及使用第一外部端子群與第二外部端 子群之全部而動作的第三型式之半導體元件的哪一個都能 連接地，在元件介面板準備配備具有與第一外部端子群及 第二外部端子群相同數量及排列的第一接觸端子群及第二 接觸端子群的第一接觸具及與此相同構成的第二接觸具， 該第一接觸具的第一接觸端子群與第二接觸具的第二接觸 端子群之各對應的端子彼此以兩條第一分歧線來共通連結 ，於該兩條第一分歧線的共通連接點，連接著對應第一接 觸具之第一接觸端子群的各接觸端子而設置在接腳電子的 第一 10通道群之10通道的各驅動器輸出接腳，第一接觸 具的第一接觸端子群與第二接觸具的第二接觸端子群之各 對應的端子彼此以兩條第二分歧線來共通連接，於該兩條 第二分歧線的共通連接點，連接於第一 10通道群之ΪΟ通 道的比較器輸入接腳，在第二接觸具的第一接觸端子群的 各接觸端子，分別將與此對應而設置在接腳電子的第二 10通道群之10通道的驅動器輸出接腳及比較器輸入接腳 以個別的配線而連接的半導體元件測試裝置。 在第3發明中乃提案，針對用來測定至少具備一組以 不同的時序而動作之成對的輸出/輸入用外部端子的半導 體元件之半導體元件測試裝置，將一組輸出/輸入用外部 -11 - (9) (9)1300484 端子的一方與另一方之間以跨越配線而連接，在跨越配線 的一端側，連接著對應該輸出/輸入用外部端子之組而設 置在接腳電子的10通道的驅動器輸出接腳，於另一端側 連接該10通道的比較器輸入接腳的半導體元件測試裝置 〇 在第4發明中乃，於第1或是第2發明記載的半導體 元件測試裝置的任何一裝置中提案，半導體元件的外部端 子是以導出到封裝之外側的接腳所構成，第一接觸具及第 二接觸具是以第一插座及第二插座所構成，元件介面板是 以插座板所構成，分別於實裝在該插座板的第一插座及第 二插座安裝第一型式的半導體元件或是第二型式的半導體 元件，或是在第二插座安裝第三型式的半導體元件，而進 行測試的半導體元件測試裝置。 在第5發明中乃，於第1或是第2發明記載的半導體 元件測試裝置的任何一裝置中提案，半導體元件的外部端 子乃以形成在半導體晶圓上的銲墊所構成，第一接觸具及 第二接觸具乃以第一探針插座及第二探針插座所構成，元 件介面板乃以探針所構成，且使上述第一型式之半導體元 件或是第二型式之半導體元件的任何一個，分別接觸於安 裝在實裝於該探針的第一探針插座及第二探針插座的探針 ，而進行測試的半導體元件測試裝置。 在第6發明中乃，於第3發明記載的半導體元件測試 裝置中提案，外部端子乃以從封裝被導出的接腳所構成， 跨越配線乃以連接在與接腳電性接觸的插座之端子間的配 -12- (10) 1300484 線所構成，分別將配備在連接著跨越配線之一端側的插座 之端子與接腳電子的10通道的驅動器輸出接腳之間以及 配備在連接著跨越配線之另一端側的插座端子與接腳電子 之10通道的比較器輸入接腳之間，各別以配線而連接的 半導體元件測試裝置。 第7發明乃，於第3發明記載的半導體元件測試裝置 中提案，外部端子乃以半導體晶圓上的銲墊所構成，跨越 配線乃以連接於用來支撐與銲墊接觸的探針之接觸端子的 相互間之配線所構成，分別將配備在連接著跨越配線之一 端側的接觸端子與接腳電子的驅動器輸出接腳之間以及配 備在連接著跨越配線之另一端側的接觸端子與接腳電子的 比較器輸入接腳之間，各別以配線而連接的半導體元件測 試裝置。 第8發明乃，於第4至第7發明記載的半導體元件測 試裝置所使用的元件介面板的任何一面板中提案，將跨越 配線以及該跨越配線之一端側與配備在接腳電子的10通 道之驅動器輸出接腳之間的配線以及將跨越配線之另一端 側與配備在接腳電子的10通道之比較器輸入接腳之間的 配線，分別具備與配備在接腳電子之驅動器的輸出阻抗匹 配的特性阻抗，且該等之配線爲被安裝在基板之構造的元 件介面板。 〔發明效果〕 若藉由第1及第2發明，就能使用同一元件介面板來 -13- (11) 1300484 測試利用接腳數不同的複數種類之半導 至第三型式的三種半導體元件）。只要 體元件及第二型式的半導體元件，就能 行測試，而且雖是限制一個不過也可測 體元件。因而，若根據該發明，能使用 ’來測試品種不同的半導體元件，所以 元件介面板就能測定複數品種的元件， 負擔。進而，於每一變更進行測試的元 元件介面板的緣故，所以也可得到操縱 又，因一般元件介面板不限於一枚 測試頭，所以將藉由該發明的元件介面 試頭，藉此關係到第一型式與第二型式 能倍增爲可一次測試的元件之數量，藉 率 〇 又，若根據第3發明，就能將具有 帶所動作之成對的輸出/輸入接腳的半 腳數之一半的10通道之數量而進行測 著由驅動器至比較器的所有線路保持在 所以就能減少波形的劣化。在這點上， 器中之判定誤差之發生的優點，其效果 貢獻。 【實施方式】 〔用以實施發明之最佳形態〕 體元件（例如第一 是第一型式的半導 一次兩個同時地進 試第三型式的半導 共通的元件介面板 利用者只要準備該 就能減輕經濟上的 件之品種，未變更 也變容易的優點。 ，將複數枚實裝在 板複數枚實裝在測 的半導體元件，就 此就能提昇測試效 在互不相同之時間 導體元件，以其接 試。當然也因連接 特定之阻抗的値， 可得到能抑制比較 對實用上有頗大的 -14- (12) 1300484 採用第1圖說明爲了實施該發明之最佳形態。第1圖 • 所示之PE乃表示接腳電子。於接腳電子PE乃表示在此具 λ 備：每Ν(=8)個通道被分配的第一 10通道群IOCH — 1 與第二10通道群IOCH— 2的場合。260乃表示元件介面 板。該元件介面板260乃DUT之外部端子爲接腳型式時 爲插座板，DUT之外部端子爲晶圓上之銲墊型式時成爲探 針。其實體於後面實施例做說明。 # 在該發明中，於元件介面板260實裝第一接觸具280 一 1與第二接觸具280— 2。該等第一接觸具280— 1與第 二接觸具280 - 2乃，DUT.之外部端子爲接腳型式時爲插 座，DUT之外部端子爲晶圓上之銲墊型式時成爲探針卡。 第一接觸具280 - 1乃具備，由接觸端子VI — 1〜VI 一 Ν (在此Ν=8)所形成的第一接觸端子群281-1與由 接觸端子W1 — 1〜W1 - Ν所形成的第二接觸端子群281 — 2。第二接觸具280 — 2也同樣地具備，由接觸端子V2—1 Φ 〜V2- Ν (在此Ν= 8 )所形成的第一接觸端子群281 - 1 - 與由接觸端子W2- 1〜W2—N所形成的第二接觸端子群 281 — 2。各接觸具乃分別在第一接觸端子群281 — 1與第 二接觸端子群2 8 1 - 2，具備以一對一所對應而連接的接觸 部CNT，使DUT之各接腳接觸於該接觸部CNT，而DUT 、第一接觸端子群281 — 1與第二接觸端子群281 — 2就會 被電性連接。 再者，在該發明中，將第一接觸具280— 1的第一接 觸觸子群281— 1的接觸端子VI— 1〜VI - Ν與第二接觸 -15- (13) 1300484 具2 80 - 2的第二接觸端子群281— 2的接觸端子W2 - 1〜 W2 一 N彼此，以跨越配線1 〇 1 B — 1〜1 0 1 B — N而共通連接 。與此同時，將各跨越配線1 0 1 B — 1〜1 0 1 B — N之一端側 與配備於接腳電子PE的第一 10通道群IOCH - 1的10通 道之驅動器輸出接腳S 1 — 1〜S 1 - N，分別以線路1 0 1 A -1〜101A — N而連接。再者，將跨越配線101B - 1〜101B 一 N之另一端側與第一 1〇通道群l〇CH - 1的10通道之比 較器輸入接腳 R 1 - 1〜R 1 - N，分別以線路 1 0 1 C - 1〜 1 0 1 C — N而連接。 在圖中雖是表示一通道部份，但跨越配線101B乃在 第一接觸具280 — 1與第二接觸具280 - 2之間，連接著有 關資料之輸出/輸入的數N部份接觸端子，也就是在本例 連接著八條。隨此，線路1 〇 1 A與1 0 1 B也對應八通道而平 均設有八條。 線路1 0 1 A及1 0 1 C與跨越配線1 0 1 B乃以全部匹配於 配備在接腳電子PE之10通道的驅動器IODR的輸出阻抗 之例如具有5 0 Ω之特性阻抗的訊號線路所構成。在第1圖 所示的例中乃表示，將接腳電子PE的驅動器輸出接腳S1 一 1與設在元件介面板2 6 0的端子T1 一 1之間，以具備5 0 Ω之特性阻抗的同軸電纜所連接’且分別將端子T 1 一1與 第一接觸具280 — 1之第一接觸端子群281 — 1的接觸端子 VI - 1之間、跨越配線1〇1Β— 1、以及第二接觸具2 80 — 2 的第二接觸端子群281 - 2的接觸端子W2 — 1與端子U1 — 1之間，以具有5 0 Ω之特性阻抗的微小條線所連接，且將 -16- (14) 1300484 端子U1 - 1與比較器輸入接腳R1 - 1之間，以具有50 Ω • 之特性阻抗的同軸電纜所連接的場合。但，線路的構造並 〜 不限於第1圖所示的構造，可形成將全部以同軸電纜而連 接，也可形成將全部以微小條線而連接的構造。在驅動器 的輸出端乃連接有，以從傳送路的遠端返回到全反射波爲 終端的串聯終端電阻Rtr，在比較器10CP的輸入端乃連 接有，阻抗匹配用的終端電阻RTM。 • 另一方面，在第二接觸具280— 2的第一接觸端子群 281-1的端子V2— 1〜V2— N，分別將接腳電子PE的第 二10通道群10 CH - 2的10通道之驅動器輸出接腳S2— 1 〜S2 - N與比較器輸入接腳R2— 1〜R2 - N，各別以線路 102A - 1 〜102A— N 與 102B— 1 〜102B - N 而分別連接。 在第1圖所示的例中乃表示，形成將驅動器輸出接腳S2 一 1與端子T2 一〗之間，以具有5 0 Ω之特性阻抗的同軸電 纜所連接，並將端子T2 — 1與第二接觸具280— 2之第一 • 接觸端子群281 — 1的接觸端子V2 — 1之間，以具有50 Ω .之特性阻抗的微小條線所連接的構造當作線路1 02 A - 1， 進而，線路102B — 1也同樣地，形成將比較器輸入接腳 R2 — 1與端子U2 - 1之間，同軸電纜所連接，且將端子 U2—1與第二接觸具280 - 2的第一接觸端子群281 — 1的 接觸端子W2 — 1之間，以微小條線所連接之構造的場合 。但，不必分開使用同軸電纜與微小條線，將全部以同軸 電纜所構成亦可，而且將全部以微小條線所構成亦可。在 第1圖所示的例子中乃表示，在第二接觸具280— 2的第 -17- (15) (15)1300484 一接觸端子群28 1— 1的端子V2 - 1〜V2- N，以成對而施 行一通道份之配線的狀態，但施行有關該第一接觸端子群 281-1之資料的輸入與輸出的N個（例如8個）之接觸 端子V2 — 1〜V2 — 8N ( 8 )通道份完全同樣的配線。 於上述之構成中，線路101A與101C以及102A與 1 02B乃分別包含同軸電纜及微小條線，並使全長略統一 爲同一長，且訊號之傳送時間統一。但，因以使用跨越配 線1 〇 1 B來授受資料的線路，只有傳送跨越配線1 0 1 B之部 分的時間，資料的傳送時間很慢，所以需要以配備在測試 裝置的相位差調整手段來進行相位差調整。 若根據在第1圖所示的構成，如果在第一接觸具280 一 1與第二接觸端子群281 - 2，分別安裝第13A圖所示的 第一型式的半導體元件DUT— 1一 1與DUT— 1 一 2的話， 有關該第一型式的DUT— 1之資料的各外部端子DQ0〜 DQ3乃分別如第2圖所示，通過第一接觸具280 - 1與第 二接觸具280— 2的各第一接觸端子群281— 1之一部分的 接觸端子VI — 1〜VI - 4以及V2 - 1〜V2 - 4而連接於接 腳電子PE。在該狀態中，因在第二接觸具280 一 2的第二 接觸端子群281—2的接觸端子W2 - 1〜W2 - 4，乃接觸 著安裝在第二接觸具280— 1之DUT— 1 一 2的未使用之外 部端子NC8〜NC11，所以從安裝在第一接觸具280— 1之 DUT - 1 — 1所輸出的應答訊號乃，通過跨越配線101B - 1 〜101B - 4與線路i〇1C— 1〜101C— 4而沒有阻礙的輸入 到第一 10通道群IOCH — 1的比較器i〇CPl — 1〜IOCP1 — -18- (16) (16)1300484 4。此結果，就能將第一型式的DUT — 1以每次兩個來測 試。再者，因各型式之DUT的電源端子及控制端子乃以 全部之型式的元件配置於共通的位置，所以在此有關該等 未特別言及。 進而，如第3圖所示，在第一接觸具280 - 1與第二 接觸端子群281— 2安裝2型式的半導體元件DUT - 2的 場合，有關該第二型式的半導體元件DUT— 2之各資料的 外部端子DQ0〜DQ7亦通過第一接觸具280 - 1與第二接 觸具280 — 2之各個的第一接觸端子群281— 1而連接於接 腳電子 PE。此場合也因未使用端子接觸到以跨越配線 101B所連接的第二接觸具280-2的第二接觸端子群281 一 2，所以第二型式的半導體元件也不會受到阻礙，能每 次雨個的進行測試。 進而，若藉由該發明，如第4圖所示，第一接觸具 280—1爲未安裝，且於第二接觸具280 - 2安裝第三型式 的半導體元件 DUT - 3。有關該第三型式的半導體元件 DUT — 3之資料的所有外部端子DQ0〜DQ15乃分SU，通過 第二接觸具280 - 2的第一接觸端子群281 — 1與第二接觸 端子群281 - 2而連接到接腳電子PE。因而，該第三型式 的半導體元件DUT - 3就能一次測試一個。 如上述，若藉由該發明，於各型式的DUT使用共通 的接觸具2 80，就能測試第一型式的半導體元件DUT — 1 與第二型式的半導體元件DUT- 2以及第三型式的半導體 元件DUT— 3的所有元件。再者，通過線路101 A而連接 -19- (17) 1300484Moreover, if the technique is applied to a special type of a pair of output/input terminals having a complex pair that is operated by shifting the control signals by shifting the control signals as shown in FIG. 12B, One 10 channel can be used to correspond to two terminals, and the number of 10 channels can be reduced by half, but this also causes difficulty in waveform quality. That is, the trial circuit shown in FIG. 12B operates corresponding to the two output/input pins of the pair of DUTs and one driver output pin P, and one end of the coaxial cable is connected to the driver output pin P, The other end is connected to the terminal Q of the socket board, and the terminal Q is connected to the divergence point R by a micro strip having a characteristic impedance of 50 Ω, and has two pairs of bifurcation lines respectively connected to the bifurcation point r to .2 The composition of the output/input terminal. In the pilot circuit, an example in which a high-speed rectangular wave is applied by the driver 101R and an output/input terminal of one of the DUTs is used as an observation point (View) is shown in Fig. 2C. Regarding the waveform shown in the figure, b is the waveform when the characteristic impedance of the branch line R to the respective output/input terminals is 100 Ω, and the factory is a waveform of 50 Ω. Further, for comparison, an ideal waveform of an output/input terminal (View) of a DUT constructed by a circuit of a conventional technique which does not have a branch line shown in Fig. 12A is shown in a in the i2c diagram. From the comparison of the waveforms, the impedance of the branch line of the terminal on the DUT side to the terminal of the DUT viewed from the divergence point R in Fig. 12B is (b - : 50 Ω in case 'the impedance of the DUT viewed from the divergence point R is 50 Ω / 2 = 25 Ω, and there is a non-match with the characteristic impedance (5 〇Ω) of the line up to the divergence point R. There is a waveform deterioration that follows. (b) : 1 〇〇Ω when The impedance of the DUT viewing DUT is 1〇〇Ω/2==5〇Ω to form (4) 1300484 match, but if the divergence point is viewed by the signal_side from the output/input terminal forming a total reflection, The divergence point is 100 Ω. Knowing that the front side is the 50 Ω on the input side and the parallel impedance of 100 Ω on the other side of the line becomes 3 3 Ω, forming a non-match, and there is a possibility The waveform is degraded. Because no one of them can connect the 50 Ω terminating resistor to the test device on the DUT side, the waveform deterioration caused by total reflection is not avoided. This is a great difficulty in the divergence mode. Overcoming the deterioration of the waveform quality with the trial example as shown in Fig. 1 2B Disadvantages, it is required to be able to effectively utilize a limited number of 10-channel semiconductor device test devices. Moreover, it is possible to effectively utilize a limited number of 10-channel semiconductor device test device systems, in addition to the above, belonging to the semiconductor device as shown in FIG. A semiconductor device having the same number of terminals and the same terminal array in the same package is also required to have a data width of x4 bits, χ8 bits, χ16 bits, such as 10 pins capable of measuring write/read. Three types of components for testing semiconductor components. • In Figure 13, the output/input for the 4-bit 10-pin DQ0~DQ4 _outer data is the non-use pin NC4~NC15, 13 Β 乃 乃 乃 乃 乃 乃 乃 乃 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外 以外The output pin is used. Hereinafter, in the detailed book, the semiconductor element having the data width of χ4 bits shown in Fig. 13 is called the first type of semiconductor element DUT - the data width shown in the figure is x8 bits. Structure The semiconductor element is referred to as (5) 1300484 is a second type of semiconductor element DUT-2, and the semiconductor element having a data width of x16 bits as shown in FIG. 13C is referred to as a third type of semiconductor element DUT-3. Each type of semiconductor component is tested with a semiconductor component test device which must have the largest number of terminals in each of the socket boards as far as possible to operate in the three DUTs of the DUT mounted on the socket board. 1 channel of the number of DUTs. In the above example, in order to test the third type of DUT-3, sixteen 10-channels are prepared. On the other hand, the socket boards of the DUTs corresponding to the three types are the 10-pins DQ0 to DQ4 corresponding to the respective types of DUTs, A connection dedicated to DQ0 to DQ7 and DQ0 to DQ15. Therefore, an example of a socket board for each type of semiconductor element is shown in Fig. 14. Fig. 14A shows a socket board 160-1 for a first type of semiconductor element DUT-1, and Fig. 14B shows a socket board 160-2 for a second type of semiconductor element DUT-2, and Fig. 14C shows a third A socket plate 160-3 for a type of semiconductor component DUT-3. Each contact holder 180 is provided with a contact CNT of the same pin arrangement with the same number of pins, and 10 pins of the DUT are inserted into the contact portions, and the contact sockets 1 80 are respectively connected to the corresponding contacts. Socket board. The socket board 160-1 has an external connection terminal group formed by four terminals T1 to T4, and pattern wirings are formed in the same manner as the four operation terminals DQ0 to DQ3 connected to the DUT-1. The socket board 1 6 0 - 2 has an external connection terminal group ' formed by eight terminals T 1 T T 8 and is connected to the eight operation terminals DQ0 of the -8-(6) 1300484 DUT-2 DQ7. At the same time, the socket board 160-3 has an external connection terminal group formed by sixteen terminals T1 to τ 16 and is connected to the sixteen operation terminals D Q 0 to D Q 1 5 of the DUT-3. As can be understood from the figures, the pattern wiring of each socket board is designed such that the pattern of each DUT is necessary for manufacturing. Also, when testing components existing on a semiconductor wafer, it is necessary to prepare a probe for each type of semiconductor component. On the user side, in order to prepare a socket board or a probe for each type of DUT, economical The burden on it is great. Further, when a plurality of semiconductor elements are tested by a semiconductor element test apparatus as described above, it is required to reduce the number of 10-channel groups or to multiply the number of testable DUTs equivalent to 10 channel groups. The object of the present invention is to solve the problems of the above-described conventional examples, and in detail to provide a semiconductor device test apparatus capable of effectively operating 10 channels, specifically, a semiconductor which can be completed in a smaller number of 10 channels required for one DUT than in the past. A component test device, or a semiconductor component test device that can increase the type of DUT that can be tested in a 10-channel group. Further, a component interface panel for providing the semiconductor device test apparatus is provided in more detail. When the paired 10 pins are differentially switched to the DUT of the operation mode and the non-operation mode at different timings, It can be tested with a smaller number of channels than the conventional ones. In addition, the DUTs have the same number of terminals and have the same terminal arrangement. It is necessary for the operation -9 - (7) 1300484 In the case of a DUT, a semiconductor device test device that is tested using a _ component interface panel of the same structure can be used, and when a plurality of DUTs having different numbers of 乂10 pins are used as the object, a component interface of the same configuration can also be used. A semiconductor component test device that can be tested with a board. [Means for Solving the Problem] In order to achieve the object, in the first invention, the first # external terminal group and the second external terminal group are provided, and the number of terminals and the terminal arrangement are the same. However, regardless of the first type of semiconductor element operating using one of the first external terminal groups, the second type of semiconductor element operating using all of the first external terminal group, and using the first external terminal group and the second external terminal Which one of the third type semiconductor elements that operate in the group can be connected, and the element interface panel is prepared to be provided with the same number and arrangement of first contact terminals as the first external terminal group and the second external terminal group The first contact of the group and the second contact terminal group is configured as a second contact member, the first contact terminal group of the first contact device and the second contact terminal group of the second contact device The corresponding terminals are connected in common to each other across the wiring, and are provided on the one end side of each of the crossing wires, corresponding to each contact terminal of the first contact terminal group of the first contact device. The driver output pin of the channel of the first ίο channel group of the pin electron is connected to the comparator input pin of the channel of the one channel at the other end side, and the contact terminal of the first contact terminal group of the second contact tool Corresponding to this, the driver output pin and the comparator input pin of the 10th channel of the second 10 channel group of the pin electronics are respectively connected to each other by a separate wiring. -10- (8) 1300484 In the second invention, the first external terminal group and the second external terminal group are provided, and the number of terminals and the terminal arrangement are the same, but the first external terminal is used. The first type of semiconductor element that operates in one of the groups, the second type of semiconductor element that operates using all of the first external terminal group, and the first operation that uses the first external terminal group and the second external terminal group Which of the three types of semiconductor elements can be connected, and the element interface panel is prepared to be provided with the first contact terminal group and the second contact terminal group having the same number and arrangement as the first external terminal group and the second external terminal group a contact device and a second contact member having the same configuration, wherein the first contact terminal group of the first contact device and the corresponding terminal of the second contact terminal group of the second contact device are separated by two first branch lines a common connection, in which the contact terminals of the first contact terminal group corresponding to the first contact device are connected to the common connection point of the two first branch lines Each of the 10 channel drive output pins of the 10 channel group, the first contact terminal group of the first contact device and the corresponding terminal of the second contact terminal group of the second contact device are common to each other by two second branch lines Connecting, at a common connection point of the two second branch lines, a comparator input pin connected to the channel of the first 10 channel group, and each contact terminal of the first contact terminal group of the second contact device Corresponding to this, a 10-channel driver output pin and a comparator input pin of a second 10-channel group of pin electronics are connected to each other by a separate wiring. In the third aspect of the invention, a semiconductor element test device for measuring a semiconductor element having at least one pair of output/input external terminals that operate at different timings is used, and a set of outputs/inputs are externally- 11 - (9) (9) 1300484 One of the terminals is connected to the other by crossing the wiring, and the one that is connected to the external terminal of the output/input is connected to the one end of the wiring. A semiconductor device test device in which the driver output pin of the channel is connected to the 10-channel comparator input pin on the other end side. In the fourth invention, the semiconductor device test device according to the first or second invention is any In a device, the external terminal of the semiconductor component is formed by a pin that is led out to the outside of the package. The first contact and the second contact are formed by the first socket and the second socket, and the component interface panel is a socket. Forming a board, respectively mounting a first type of semiconductor component or a second type of semiconductor component in the first socket and the second socket of the socket board, or The second socket was mounted with a semiconductor element of the third type, and the semiconductor element testing device was tested. According to a fifth aspect of the invention, in any one of the semiconductor device testing devices according to the first or second aspect of the invention, the external terminal of the semiconductor device is formed by a pad formed on the semiconductor wafer, the first contact The second contact device is composed of a first probe socket and a second probe socket, and the component interface panel is formed by a probe, and the semiconductor component of the first type or the semiconductor component of the second type is used. Any one of the semiconductor element testing devices tested for contact with a probe mounted on the first probe socket and the second probe socket of the probe. According to a sixth aspect of the invention, in the semiconductor device test apparatus of the third aspect of the invention, the external terminal is formed by a pin derived from the package, and the terminal is connected to a terminal of the socket electrically contacting the pin. The -12- (10) 1300484 line consists of a 10-channel driver output pin that is connected to the terminal of the socket that is connected to one end of the wiring and the pin electronics, and is connected to the wiring. A semiconductor element testing device that is connected to each other by a wiring between the socket terminal on the other end side and the 10-channel comparator input pin of the pin electronics. According to a seventh aspect of the invention, in the semiconductor device test apparatus of the third aspect of the invention, the external terminal is formed by a pad on the semiconductor wafer, and the wiring is connected to the probe for supporting the contact with the pad. The wirings of the terminals are formed by connecting the contact terminals connected to one end side of the wiring to the driver output pins of the pin electronics and the contact terminals connected to the other end side of the wiring. A semiconductor component test device in which the comparator pins of the foot electronics are connected to each other by wiring. According to the eighth aspect of the invention, in any of the panel of the component dielectric panel used in the semiconductor device testing device according to the fourth to seventh aspects of the invention, it is proposed to extend the wiring and one end side of the crossing wiring and the 10 channel provided in the pin electron. Wiring between the driver output pins and the wiring between the other end side of the wiring and the 10-channel comparator input pin provided on the pin electronics, respectively, and the output impedance of the driver provided in the pin electronics Matched characteristic impedance, and the wiring is a component interface panel that is mounted on the substrate. [Effect of the Invention] According to the first and second inventions, it is possible to test three types of semiconductor elements using a plurality of types of semiconductors having different numbers of pins to the third type using the same device interface panel -13-(11) 1300484) . As long as the body element and the second type of semiconductor element can be tested, and although it is limited to one, the body element can be measured. Therefore, according to the invention, it is possible to test semiconductor elements having different types by using ', and therefore, the component panel can measure a plurality of types of components and burden. Furthermore, since the meta-component panel is tested for each change, the manipulation can also be obtained. Since the general component interface panel is not limited to one test head, the relationship between the components of the invention is used. The number of components that can be multi-tested to the first type and the second type can be multiplied, and the number of half-legs of the pair of output/input pins with the action can be obtained according to the third invention. Half of the 10 channels are measured to keep all the lines from the driver to the comparator kept, so that the waveform degradation can be reduced. At this point, the advantage of the occurrence of the judgment error in the device contributes to the effect. [Embodiment] [Best Mode for Carrying Out the Invention] A body element (for example, the first type is a first type of semi-conductor, and the second type is simultaneously tested. The third type of semi-conductive common element panel user is prepared as long as it is prepared It is possible to reduce the variety of economical parts, and it is easy to change without changing. It is possible to increase the number of pieces of semiconductor components mounted on the board in a plurality of times, thereby improving the test effect at different time intervals. In order to connect with the specific impedance, it is also possible to obtain a suppression of the comparison. It is practically quite large-14- (12) 1300484. The first figure illustrates the best form for implementing the invention. 1 • The PE shown is the pin electronics. The pin electronics PE indicates that there is a λ device: the first 10 channel group IOCH-1 and the second 10 channel are allocated for each channel (=8) channels. In the case of group IOC-2, reference numeral 260 denotes a component interface panel, which is a socket board when the external terminal of the DUT is a pin type, and a probe when the external terminal of the DUT is a pad type on a wafer. Its entity in the following examples In the invention, the first contact member 280-1 and the second contact member 280-2 are mounted on the component interface panel 260. The first contact member 280-1 and the second contact member 280-2 are The external terminal of DUT. is a socket when the pin type is used, and the external terminal of the DUT is a probe card when it is a pad type on the wafer. The first contact tool 280-1 is provided by the contact terminal VI-1~VI The first contact terminal group 281-1 formed by (Ν 8 = 8) and the second contact terminal group 281 - 2 formed by the contact terminals W1 - 1 to W1 - 。. The second contact 280-2 Similarly, the first contact terminal group 281 - 1 - formed by the contact terminals V2 - 1 Φ - V2 - Ν (here, Ν = 8) and the first contact terminal W2- 1 to W2 - N are formed. Two contact terminal groups 281 to 2. Each contact device has a contact portion CNT connected in a one-to-one correspondence between the first contact terminal group 281-1 and the second contact terminal group 2 8 1 - 2 to make the DUT Each of the pins is in contact with the contact portion CNT, and the DUT, the first contact terminal group 281-1 and the second contact terminal group 281-2 are electrically connected. In the invention, the contact terminals VI-1 to VI-Ν of the first contact contact group 281-1 of the first contact member 280-1 and the second contact -15-(13) 1300484 have 2 80 - The contact terminals W2 - 1 to W2 - N of the second contact terminal group 281-2 of 2 are connected in common to each other across the wiring 1 〇 1 B - 1 to 1 0 1 B - N. At the same time, each of the crossing wirings 1 0 1 B — 1 to 1 0 1 B — N one end side and 10 channel driver output pins S 1 - 1 to S 1 - N of the first 10 channel group IOCH - 1 equipped with the pin electronics PE They are connected by lines 1 0 1 A -1 to 101A - N, respectively. Furthermore, the comparators input pins R 1 - 1 to R 1 - N across the other end sides of the wirings 101B - 1 to 101B - N and the first 1-channel group l 〇 CH - 1 are respectively Line 1 0 1 C - 1~ 1 0 1 C - N is connected. Although a channel portion is shown in the figure, the number of contact terminals of the output/input of the data is connected between the first contact member 280-1 and the second contact member 280-2 across the wiring 101B. That is, in this case, eight are connected. Accordingly, lines 1 〇 1 A and 1 0 1 B also correspond to eight channels and eight are provided on average. The lines 1 0 1 A and 1 0 1 C and the crossing wiring 1 0 1 B are all signal lines having a characteristic impedance of, for example, 50 Ω, which are matched to the output impedance of the driver 10 IO provided in the 10-pin of the pin electronics PE. Composition. In the example shown in Fig. 1, it is shown that the driver output pin S1 - 1 of the pin electronic PE is disposed between the terminal T1 - 1 of the component interface panel 260 to have a characteristic impedance of 50 Ω. The coaxial cable is connected to and between the terminal T 1 -1 and the contact terminal VI - 1 of the first contact terminal group 281-1 of the first contact member 280-1, across the wiring 1〇1Β-1, and The contact terminal W2 - 1 of the second contact terminal group 281 - 2 of the second contact device 2 80 - 2 is connected to the terminal U1 - 1 by a tiny strip having a characteristic impedance of 50 Ω, and the -16- (14) 1300484 When the terminal U1 - 1 and the comparator input pin R1 - 1 are connected by a coaxial cable with a characteristic impedance of 50 Ω •. However, the structure of the line is not limited to the structure shown in Fig. 1, and it is possible to form a structure in which all of them are connected by a coaxial cable, or all of them may be connected by a small line. The output terminal of the driver is connected to return from the distal end of the transmission path to the series termination resistor Rtr whose total reflected wave is the terminal, and the terminal resistance RTM for impedance matching is connected to the input terminal of the comparator 10CP. • On the other hand, at the terminals V2 - 1 to V2 - N of the first contact terminal group 281-1 of the second contact member 280-2, 10 of the second 10 channel group 10 CH - 2 of the pin electronics PE, respectively The driver output pins S2 - 1 - S2 - N of the channel and the comparator input pins R2 - 1 - R2 - N are respectively connected by lines 102A - 1 - 102A - N and 102B - 1 - 102B - N respectively. In the example shown in Fig. 1, it is shown that a driver is connected between the driver output pin S2-1 and the terminal T2, and is connected by a coaxial cable having a characteristic impedance of 50 Ω, and the terminal T2-1 is connected. The first contact of the second contact member 280-2, the contact terminal V2-1 of the contact terminal group 281-1, is connected by a micro-wire having a characteristic impedance of 50 Ω as a line 102 A - 1 Further, the line 102B-1 is similarly formed between the comparator input pin R2-1 and the terminal U2-1, the coaxial cable is connected, and the terminal U2-1 and the second contact 280-2 are formed. A case where the contact terminals W2_1 of the contact terminal group 281-1 are connected by a small line. However, it is not necessary to use a coaxial cable and a small strip separately, and all of them may be constituted by a coaxial cable, and all of them may be formed by a small number of lines. In the example shown in Fig. 1, it is shown that the terminals V2 - 1 to V2-N of the contact terminal group 28 1 - 1 of the -17-(15) (15) 1300484 of the second contact tool 280-2, The state in which the wiring of one channel is performed in pairs, but the N (for example, eight) contact terminals V2 - 1 to V2 - 8N (see, for example, the input and output of the data of the first contact terminal group 281-1) are applied. 8) The channel is completely identical. In the above configuration, the lines 101A and 101C and 102A and 102B respectively include coaxial cables and minute lines, and the overall lengths are slightly uniform to the same length, and the transmission time of the signals is uniform. However, since the line for transmitting and receiving data across the wiring 1 〇1 B is used, only the time of transmitting the portion spanning the wiring 1 0 1 B is slow, so the phase difference adjustment means provided in the test device is required. Perform phase difference adjustment. According to the configuration shown in Fig. 1, when the first contact 280-1 and the second contact terminal group 281-2 are respectively mounted, the first type of semiconductor element DUT-1 -1 shown in Fig. 13A is mounted. In the case of DUT-1 to 2, the external terminals DQ0 to DQ3 of the data of the first type of DUT-1 are respectively shown in FIG. 2 through the first contact member 280-1 and the second contact member 280-2. The contact terminals VI-1 to VI-4 and V2-1 to V2-4 of one of the first contact terminal groups 281-1 are connected to the pin electronics PE. In this state, the contact terminals W2-1 to W2-4 of the second contact terminal group 281-2 of the second contact member 280-2 are in contact with the DUT-1 mounted on the second contact member 280-1. The unused external terminals NC8 to NC11 of one or two, so that the response signal outputted from the DUT-1 - 1 mounted on the first contact member 280-1 passes through the wirings 101B - 1 to 101B - 4 and the line i 1C-1 to 101C-4 without obstruction input to the first 10-channel group IOCH-1 comparator i〇CP1-1~IOCP1 — -18- (16) (16) 1300484 4. With this result, the first type of DUT-1 can be tested with two at a time. Further, since the power terminals and the control terminals of the DUTs of the respective types are arranged in common positions by all the types of elements, these are not particularly mentioned herein. Further, as shown in FIG. 3, when the second contact type group 280-1 and the second contact terminal group 281-2 are mounted with the two-type semiconductor element DUT-2, the second type of semiconductor element DUT-2 is The external terminals DQ0 to DQ7 of the respective materials are also connected to the pin electronic PE through the first contact terminal group 281-1 of each of the first contact tool 280-1 and the second contact device 280-2. Also in this case, since the unused terminal contacts the second contact terminal group 281-2 of the second contact 280-2 connected across the wiring 101B, the second type of semiconductor element is not hindered and can be rained every time. Tested. Further, according to the invention, as shown in Fig. 4, the first contact 280-1 is not mounted, and the third type of semiconductor element DUT-3 is mounted on the second contact 280-2. All of the external terminals DQ0 to DQ15 relating to the data of the third type of semiconductor element DUT-3 are sub-SUs, passing through the first contact terminal group 281-1 and the second contact terminal group 281-2 of the second contact 280-2. And connected to the pin electronic PE. Thus, the third type of semiconductor element DUT-3 can be tested one at a time. As described above, according to the invention, the first type of semiconductor element DUT-1 and the second type of semiconductor element DUT-2 and the third type semiconductor can be tested using the common contact device 280 for each type of DUT. All components of component DUT-3. Furthermore, it is connected by line 101 A -19- (17) 1300484
到驅動器輸出接腳S1的第一接觸具2 80 - 1的第一 ‘ 子群2 8 1 — 1與通過線路1 0 1 A以及跨越配線1 0 1 B 、 到驅動器輸出接腳S 1的第一接觸具2 8 0 - 2的第二 子群281-2，由驅動器側（S1)觀察到的傳送延 差異，同樣地由比較器側（R1)觀察到的傳送延遲 差異。因此，半導體元件測試裝置必須考量事先求 之相位差的不同，對應前述相位差之不同的測試圖 0 生條件5以及在比較器側的時序判定條件。再者， 越配線1 0 1 B的線路長，爲儘可能短的配線長。 第5圖於表示在第2發明所提案的半導體元件 置之構成。雖然連第2發明，在元件介面板260安 接觸具280—1與第二接觸具280— 2的構造都是與 明相同，但第一接觸具280 — 1的第一接觸端子群 與第二接觸具280-2的第二接觸端子群281— 2與 子PE的連接構造則是與第1發明相異。 • 也就是，在第2發明中，分別在實裝於元件 . 260的第一接觸具280 — 1與第一接觸端子群281 — 二接觸具280 - 2的第二接觸端子群281 - 2之對應 例如V 1 - 1和W2 - 1，連接兩條第一分歧線1 2 1 A 1 3 1 A — 1的各一端，且將該兩條第一分歧線1 2 1 A 131A— 1之另一端以端子T1—1而共通連接，並 T1 — 1通過線路120A - 1而連接到配備在接腳電子 第一 10通道群I〇CH_l的10通道之驅動器輸出_ 一 1。進而，其特特徵爲在第一接觸具280 — 1的第 接觸端 而連接 接觸端 遲量有 量也有 得兩者 案之發 希望跨 測試裝 裝第一 第〗發 281-1 接腳電 介面板 1與第 的端子 一 1和 一 1和 將端子 ΡΕ的 I腳S1 一接觸 -20- (18) 1300484 端子群281 - 1與第二接觸具280 — 2的第二接觸端子群 • 281 - 2之互相對應的接觸端子例如VI — 1和W2 - 1，連 *· 接兩條第二分歧線1 2 1 B - 1和1 3 1 B — 1的各一端，且將兩 條弟—*分歧線121B — 1和131B - 1之各另一端，連接到設 置在元件介面板260的端子Ul— 1，並將該端子Ul— 1通 過線路130B - 1而連接到設置在比較器輸入接腳R1一 1的 構成。 Φ 再者，於該第2發明中，與針對第二接觸具280 — 2 的第一接觸端子群281 — 1之第二1〇通道群l〇CH — 2的 連接乃與第1發明的連接相同。 在第5圖中，雖然有關各連接構造只舉例表示一通道 份，但在第一接觸具280 - 1的第一接觸端子群28 1 - 1與 第二接觸具280— 2的第一接觸端子群281—1與第二接觸 端子群28 1 - 2，乃針對所有的通道施以同樣的配線。 於第5圖所示的連接構造中，第一分歧線121A和 ® 1 3 1 A以及第二分歧線1 2 1 B和1 3 1 B，乃同時匹配爲線路 . 120A和130A之兩倍的特性阻抗。也就是，由端子T1和 U1觀看各接觸具280 - 1和280 - 2的話，分別連接著兩 條分歧線1 2 1 A、1 3 1 A及1 2 1 B、1 3 1 B，且由該等兩條分歧 線被並聯所觀看到的，該等之各分歧線1 2 1 A和1 3 1 A及 1 2 1 B和；m B乃爲一倍之例如1 00 Ω的特性阻抗，藉此由 端子T1及端子U1觀看各接觸具280 - 1和280 - 2的特性 阻抗即爲5 0 Ω。 連第5圖所示的連接構造，都與第2圖、第3圖、第 -21 - (19) 1300484 4圖所說明的同樣地’能測試第一型式的半導體元件DUT - 1與第二型式的半導體元件DUT— 2以及第三型式的半 導體元件DUT— 3。 實施例1 於第6圖表示該發明之具體的實施例。在該第6圖所 示的實施例中，乃表示測試DUT之外部端子的構造從封 • 裝突出接腳之型式的半導體元件之場合的實施例。以從封 裝突出接腳之型式的半導體元件作爲連接到接腳電子PE 的接觸具，乃如第14圖所說明地，當作一般插座使用。 因而，第1圖至第5圖所示的第一接觸具280 - 1與第二 接觸具280— 2的部分，乃置換爲插座180。隨此，元件介 面板260即爲插座板160。雖然在第6圖中舉例表示在第 1發明所提案的連接構造，但也同樣地適用於第2發明所 提案的連接構造。 _ 實施例2 第7圖乃表示半導體元件爲在存在於半導體晶圓上之 型式的場合，應用該發明的實施例。存在於半導體晶圓上 的半導體元件乃採用在形成有半導體晶圓之元件的領域內 ，配置著稱爲銲墊的外部端子，將稱爲探針之針狀的接觸 子之前端押抵於該銲墊，通過該探針而將半導體元件之各 端子電性連接於接腳電子PE的方法。 第7圖所示的2 90 - 1乃表示當作第一接觸具而動作 -22- (20) (20)1300484 的第一探針插座，290 — 2乃表示當作第二接觸具而動作的 第二探針插座。在此，3 00乃表示探針卡，具有與晶圓之 整面相對面的大基板。第一 /第二探針插座乃構成探針卡 的一部分，用以保持探針291，該等之針乃分別可安裝/ 卸下地連接到探針卡3 00。各探針插座乃相對向於屬於晶 圓上之各1C晶片的半導體元件所配設。該等之探針插座 之一例’ 一般乃在構成探針卡的基板形成具有比晶圓上之 半導體元件的形成區域還大之面積的開口孔，在該開口孔 的周邊排列有第一接觸端子群281 - 1與第二接觸端子群 281 — 2，且在該等之第一接觸端子群281—1與第二接觸 端子群28 1 - 2，以電性式及機械式地連絡並突出於孔之中 空部分而支持著探針29 1。再者，也有未形成開口孔之形 態的探針卡。 第一探針插座290 - 1與第二探針插座290 — 2乃安裝 在探針卡300，且探針卡3 00沿著晶圓之板面而於X-Y 方向及Z方向（上下方向）移動，並使探針291的前端接 觸到晶圓上的半導體元件的銲墊。第一探針插座290 — 1 與第二探針插座290 — 2乃分別與晶圓上之個別的半導體 元件相對向而接觸。 將在第一探針插座2 90 - 1與第二探針插座290-2應 用第1發明之構成，乃與第1圖之場合同樣地，將第一探 針插座290 - 1的第一接觸端子群281 - 1與第二探針插座 290 - 2的第二接觸端子群281 - 2之分別對應的端子彼此 以跨越配線1 0 1 B連接，且將跨越配線1 0 1 B的一端側從端 -23- (21) 1300484 子T 1通過線路1 0 1 A而連接到配備在接腳電子PE的驅動 器輸出接腳S 1，並將跨越配線1 〇〗B的另一端側從端子 U1通過線路101C而連接到配備在接腳電子PE的比較器 輸入接腳R1的構成，於第一探針插座290 - 1的第一接觸 端子群281 — 1與第二探針插座2 90 — 2的第二接觸端子群 2 8 1 - 2之所有接觸端子的範圍施行，並且將在第二探針插 座290 - 2的第一接觸端子群281 - 1，乃分別通過線路 102A和102B而連接到驅動器輸出接腳S2與比較器、輸入 接腳R2的構成，於第二探針插座290 - 2的第一接觸端子 群28 1 — 1之所有端子的範圍施行即可。 藉由如此所構成，即可將存在於晶圓上之狀態的第一 型式的半導體元件及第二型式的半導體元件以每次兩個來 測試。 但，該場合，第三型式的半導體元件，必須是在未安 裝第一探針插座2 9 0 — 1之探針2 9 1的條件來進行測試。 因而，希望探針291是種具備可安裝/卸下的構造。又， 如果第三型式的半導體元件，在晶圓上，只形成在第二探 針插座290— 2之位置，而未形成在第一探針插座290 - 1 之位置的話，就能以該第7圖所示的構成’ 一次一個的進 行測試。在此，存在於晶圓上的第一型式的半導體元件與 第二型式的半導體元件和第三型式的半導體元件，必須是 在同一位置關係形成各個銲墊。 實施例3 • 24- (22) (22)1300484 第8圖乃表示於探針卡應用第2發明之連接構成之場 合的實施例。連該實施例，也能藉由第一探針插座290 - 1 與第二探針插座290 - 2，以每次兩個來測試半導體晶圓上 之第一型式的半導體元件與第二型式的半導體元件◊其理 由因與第2圖及第3圖的說明重複，所以在此省略該以上 的說明。但，在該實施例中，以形成未安裝第一探針插座 290—1之探針291的條件，就會g藉由第二探針插座290-2來測試第三型式的半導體元件。 實施例4 於第9圖表示在第3發明所提案的連接構成。在此所 提案的連接構成乃爲應用於DUT之資料輸出/輸入端子爲 成對的端子彼此以不同的時序而差動式地切換到動作模式 與非動作模式之型式的場合的連接構成。呈現此種特性的 半導體元件乃存在於視訊圖形用的元件，以往是以在每一 端子將第1圖至第5圖所示的第二接觸具280 — 2的第一 接觸端子群28 1 - 1連接到接腳電子PE，或是分別將第5 圖所示的第一接觸具280-1的第一接觸端子群281-1與 第二接觸具280 - 2的第二接觸端子群281 — 2連接到接腳 電子PE的連接構造來進行測試。特別是，採用將第1圖 至第5圖所示的第二接觸具2 80 — 2的第一接觸端子群連 接到接腳電子PE之連接構造的場合，驅動器和比較器必 需爲與DUT之資料輸出/輸入用接腳的數量所對應的數量 -25- (23) 1300484 對此，採用第5圖所示的分歧構造之連接構造的場合 ，乃由驅動器與比較器所形成的各組，爲DUT之資料輸 出/輸入用接腳的數量之約一半的數量即可。 但是，採用第5圖所示的分歧構造之連接的場合，就連第 5圖都如說明般地，線路1 2 1 A、1 2 1 B及1 3 1 A、1 3 1 B必須 匹配爲另一線路120A、130A之特性阻抗的約一倍的特性 阻抗。也就是，線路120A和130B的特性阻抗爲50Ω的 場合，線路1 2 1 A、1 2 1 B和1 3 1 A、1 3 1 B的特性阻抗必須 約1 00 Ω。像這樣於分歧點中，將特性阻抗由50 Ω轉換爲 1 00 Ω的並聯電路的話，訊號會發生反射，產生使波形品 質惡化的不當。 爲了解決該不當，在第3發明中乃請求，將藉由切換 控制訊號而互相錯開時間所動作的端子彼此以跨越配線連 接，且將一方的端子連接到配備在接腳電子的驅動器輸出 接腳，並將另一方的端子連接到配備在接腳電子的比較器 輸入接腳，可將兩個端子以共通的線路進行測試的這點。 第9圖乃表示該實施例。於第9圖所示的2 80乃表示 接觸具。於該接觸具排列有接觸部CNT而設置，使DUT (未特別圖示）之例如接腳型的外部端子接觸到該接觸部 CNT，藉此使DUT的各外部端子電性連接到接觸端子群 281的各接觸端子。 在此乃表示，接觸端子群2 8〗的接觸端子V 1 - 1和 VI - 2、V2 - 1 和 V2 — 2.....VN - 1 和 VN - 2、以及 W1 —1 和 W1 - 2、W2 — 1 和 W2 — 2、…、WN — 1 和 W N — 2 -26- (24) (24)1300484 乃分別，接觸到互相成對而動作的接腳的接觸端子。該等 成對的接觸端子乃，互相以跨越配線101 Bl — 1〜101 B1-N及101B2—1〜101B2- N而共通連接，且將各跨越配線 101B例如101B1— 1之一端側，通過端子T1 一 1和線路 101A - 1而連接到配備在接腳電子PE的第一10通道 IOCH_l的驅動器輸出接腳S1— 1，並將跨越配線101B1 — 1的另一端側，通過端子U 1 - 1和線路1 0 1 C - 1而連接到 配備在比較器輸入接腳R1 - 1。在第9圖中雖是表示兩通 道份的連接（亦即就連第二10通道I0CH - 2也具有同樣 的連接），但卻將DUT之成對而動作的輸入及輸出接腳 全部像這樣地加以連接。 若藉由該構成，在不會發生同時輸出之條件的特異 DUT中，將DUT之共通連接的接腳之一方控制爲動作狀 態，且從驅動器通過線路1 0 1 A而施加測試圖案訊號，並 將該應答訊號通過線路1 0 1 C而取入到比較器側，就能進 行其中一方之接腳的測試。 一方之接腳爲休止狀態中，將另一方之接腳切換爲動 作狀態。在該狀態測試另一方的接腳。而且，與利用 IOCH - 1的一對端子（例如V 1 一 1和V 1 - 2 )的測試一倂 進行利用IOCH — 2之的另一對端子（例如W1 - 1和W1 -2 )的測試。因而，就能利用1 6通道份的10通道來測定 32接腳的1〇接腳之DUT。再者，因一方的接腳與另一方 的接腳作爲跨越配線所形成，與上述同樣地，由驅動器側 觀察到的傳送延遲量有差異，同樣地由比較器側觀察到的 -27- (25) (25)1300484 傳送延遲量就有差異。因此，半導體元件測試裝置必須考 量事先求得兩者之相位差的不同，對應前述相位差之不同 的測試圖案之發生條件，以及在比較器側的時序判定條件 〇 若藉由在第3發明所提案的連接構造，線路1 0 1 A及 1 0 1 C和跨越配線1 〇 1 B，會全部統一爲5 0 Ω的特性阻抗。 此結果，在線路的途中，由於並不存在特性阻抗爲不連續 的部分，故沒有使波形品質劣化之虞。 於第1 0圖表示波形之測定例。 第10A圖乃於有關第1或是第2發明的第1圖至第8 圖的構成中，表示第二接觸具280 — 2的第一接觸端子的 連接構造。第10B圖乃表示在第3發明所提案的連接構造 。第1 0C圖乃表示比較該等兩連接構造的波形觀例。第 10C圖所示的波形a、b、c乃由驅動器IODR施加矩形波 ，且表現在第10A圖和第10B圖所示的各觀測點（a)、 (b) 、（ c )所觀測的波形。由該波形即可明白，了解到 由於在第3發明所提案的連接構造乃連續匹配阻抗的緣故 ，所以波形之劣化少。 〔產業上的可利用性〕 藉由該發明的半導體元件測試裝置及元件介面板乃被 活用在半導體元件製造部門或是半導體元件開發部門'等。 【圖式簡單說明】 -28 - (26) 1300484 〔第1圖〕爲說明對應該發明之請求項1的實 方塊圖。 〔第2圖〕爲說明第1圖所示的實施例之作用 方塊圖。 〔第3圖〕與第2圖同樣的方塊圖。 〔第4圖〕與第2圖同樣的方塊圖。 〔第5圖〕爲說明對應該發明之請求項2的實 方塊圖。 〔第6圖〕爲表示以第1圖所示的實施例爲具 子而說明的方塊圖。 〔第7圖〕與第2圖同樣地，爲表示以第1圖 實施例爲具體的例子而說明的方塊圖。 〔第8圖〕爲表示以第5圖所示的實施例爲更 例子而說明的方塊圖。 〔第9圖〕爲說明對應該發明之請求項3的實 方塊圖。 〔第10圖〕第10A圖乃有關第1或第2發明 體元件測試裝置之驅動訊號傳送線路的連接構成 1 0B圖乃有關第3發明的半導體元件測試裝置之驅 傳送線路的連接構成圖，第10C圖乃第10A圖與 圖之構成中的觀測波形圖。 〔第11圖〕說明半導體元件測試裝置與1C處 之連接構成的圖。 〔第1 2圖〕第1 2 A圖乃習知例的半導體元件 施例之 效果的 施例之 體的例 所示的 具體的 施例之 的半導 圖，第 動訊號 第1 0B 置裝置 測試裝 -29- (27) 1300484 置之驅動訊號傳送線路的連接構成圖，第1 2B圖乃非公知 ^ 之試行例的半導體元件測試裝置之驅動訊號傳送線路的連 % 接構成圖，第12C圖乃第12A圖與第12B圖之構成中的 觀測波形圖。 〔第13圖〕爲了說明第13A圖、第13B圖、第13C 圖所使用之接腳數不同的三種型式之半導體元件的例子的 圖。 # 〔第14圖〕第14A圖、第14B圖、第14C圖乃爲爲 了說明供測試第1 3 A圖、第1 3 B圖、第1 3 C圖所示之三 種類型之半導體元件使用習知之插座板的例子的圖。 【主要元件符號說明】 PE :接腳電子 IOCH— 1 :第一 10通道群 IOCH- 2 :第二10通道群 • 101 A - 1 〜101 A - N、101C - 1 〜101C - N、102A - 1 〜102A — N、102B - 1 〜102B - N:線路 1 0 1 B — 1〜1 0 1 B - N :跨越配線 1 2 1 A — 1、1 3 1 A - 1 :第一分歧線 1 2 1 B - 1、1 3 1 B — 1 :第二分歧線 180 :插座 1 2 0 A、130B ：線路 1 6 0 :插座板 260 :元件介面板 -30- (28) 1300484 2 8 0 :接觸具 • 280— 1:第一接觸具 \ 280 — 2:第二接觸具 2 8 1 :接觸端子群 2 8 1 — 1 :第一接觸端子群 2 8 1 — 2 :第二接觸端子群 290 - 1 :第一探針插座 φ 290 — 2 :第二探針插座 2 9 1 :探針 3 00 :探針卡 CNT :接觸部 DQ0〜DQ15 :外部端子 DUT—1〜DUT— 3:半導體元件 S1 — 1〜SI — N、S2—1〜S2 — N:驅動器輸出接腳 R1 — 1〜Rl — N、R2—1〜R2— N:比較器輸入接腳 • VI - 1 〜VI- N、V2-1 〜V2-N、W1-1 〜W1 - N、 W2 — 1〜W2 — N :接觸端子 IODR:驅動器 IOCP :比較器 Rtr :串聯終端電阻 Rtm :終端電阻 U 1 — 1 ··端子 -31 -The first 'subgroup 2 8 1 - 1 of the first contact 2 80-1 to the driver output pin S1 and the first through the line 1 0 1 A and across the wiring 1 0 1 B to the driver output pin S 1 The second sub-group 281-2 of the contact 2 8 0 - 2 has the difference in propagation delay observed by the driver side (S1), and the difference in transmission delay observed by the comparator side (R1). Therefore, the semiconductor element test apparatus must take into consideration the difference in phase difference obtained in advance, and the test pattern generation condition 5 corresponding to the phase difference and the timing determination condition on the comparator side. Furthermore, the wiring length of the wiring 1 0 1 B is as long as possible, and the wiring length is as short as possible. Fig. 5 is a view showing the configuration of a semiconductor element proposed in the second invention. Although the second invention is the same as the configuration of the contact member 280-1 and the second contact member 280-2 of the component dielectric panel 260, the first contact terminal group and the second contact of the first contact member 280-1. The connection structure of the second contact terminal group 281-2 of the contact tool 280-2 and the sub-PE is different from that of the first invention. • In the second invention, the first contact piece 280-1 and the first contact terminal group 281 are respectively mounted on the element 260, and the second contact terminal group 281-2 of the contact 280-2 is respectively Corresponding to, for example, V 1 -1 and W2 - 1, connecting each end of two first branch lines 1 2 1 A 1 3 1 A-1, and the two first branch lines 1 2 1 A 131A-1 One end is commonly connected by terminal T1-1, and T1_1 is connected to the 10-channel driver output__1 of the first electronic channel 10 group I〇CH_1 via the line 120A-1. Further, it is characterized in that the contact end of the first contact member 280-1 is connected to the contact end by a delay amount, and there is a case in which it is desired to cross the test to install the first first hair 281-1 pin interface. The board 1 is in contact with the first terminals 1 and 1 and the first leg S1 of the terminal -20- (18) 1300484 terminal group 281-1 and the second contact terminal group of the second contact 280-2. The corresponding contact terminals of 2, for example, VI-1 and W2 - 1, are connected to each end of the two second branch lines 1 2 1 B - 1 and 1 3 1 B - 1, and the two brothers - * The other ends of the branch lines 121B-1 and 131B-1 are connected to the terminal Ul-1 disposed on the component panel 260, and the terminal Ul-1 is connected to the comparator input pin through the line 130B-1. The composition of R1 - 1. Further, in the second invention, the connection to the second one-way channel group l〇CH-2 of the first contact terminal group 281-1 for the second contact tool 280-2 is the connection with the first invention. the same. In Fig. 5, although the respective connection structures are only exemplified as one channel portion, the first contact terminal group 28 1 - 1 of the first contact member 280-1 and the first contact terminal of the second contact member 280-2 The group 281-1 and the second contact terminal group 28 1 - 2 are applied with the same wiring for all the channels. In the connection configuration shown in Fig. 5, the first branch line 121A and the ® 1 3 1 A and the second branch line 1 2 1 B and 1 3 1 B are simultaneously matched to twice the line 120A and 130A. Characteristic impedance. That is, when the contacts 280-1 and 280-2 are viewed by the terminals T1 and U1, two branch lines 1 2 1 A, 1 3 1 A and 1 2 1 B, 1 3 1 B are respectively connected, and The two branch lines are viewed in parallel, and the respective branch lines 1 2 1 A and 1 3 1 A and 1 2 1 B and ; m B are twice the characteristic impedance of, for example, 100 Ω, Thereby, the characteristic impedance of each of the contacts 280-1 and 280-2 viewed from the terminal T1 and the terminal U1 is 50 Ω. Even in the connection structure shown in Fig. 5, the first type of semiconductor element DUT-1 and the second can be tested in the same manner as described in Figs. 2, 3, and 21 - (19) 1300484 4 A type of semiconductor element DUT-2 and a third type of semiconductor element DUT-3. Embodiment 1 A specific embodiment of the invention is shown in Fig. 6. In the embodiment shown in Fig. 6, the embodiment of the case where the external terminal of the test DUT is constructed from the semiconductor element of the type in which the pin is protruded is mounted. A semiconductor device of a type that protrudes from the package as a contact for connecting to the pin electronics PE is used as a general socket as explained in Fig. 14. Therefore, the portions of the first contact member 280-1 and the second contact member 280-2 shown in Figs. 1 to 5 are replaced with the socket 180. Accordingly, the component panel 260 is the socket board 160. In the sixth embodiment, the connection structure proposed in the first invention is exemplified, but the connection structure proposed in the second invention is similarly applied. EMBODIMENT 2 Fig. 7 is a view showing an embodiment in which the semiconductor device is a pattern existing on a semiconductor wafer. The semiconductor element existing on the semiconductor wafer is disposed in the field of the element in which the semiconductor wafer is formed, and is disposed with an external terminal called a solder pad, and the front end of the needle-shaped contact called the probe is pressed against the solder. A pad, a method of electrically connecting each terminal of a semiconductor element to a pin electronic PE by the probe. 2 90 - 1 shown in Fig. 7 indicates the first probe socket of -22-(20) (20) 1300484 as the first contact, and 290-2 indicates the action as the second contact. The second probe socket. Here, 300 denotes a probe card having a large substrate facing the entire surface of the wafer. The first/second probe sockets form part of the probe card for holding the probes 291 which are respectively attachably/detachably attached to the probe card 300. Each probe socket is disposed with respect to a semiconductor element belonging to each 1C wafer on the wafer. One example of such probe sockets is generally an open hole having a larger area than a formation region of a semiconductor element on a wafer, and a first contact terminal is arranged around the open hole. The group 281 - 1 and the second contact terminal group 281 - 2, and the first contact terminal group 281-1 and the second contact terminal group 28 1 - 2 are electrically and mechanically connected and protruded The hollow portion of the hole supports the probe 29 1 . Further, there are also probe cards in which the shape of the open hole is not formed. The first probe socket 290-1 and the second probe socket 290-2 are mounted on the probe card 300, and the probe card 00 moves along the plane of the wafer in the XY direction and the Z direction (up and down direction). And the front end of the probe 291 is brought into contact with the pads of the semiconductor elements on the wafer. The first probe receptacle 290-1 and the second probe receptacle 290-2 are in opposing contact with individual semiconductor components on the wafer, respectively. The first invention is applied to the first probe socket 2 90-1 and the second probe socket 290-2, and the first contact of the first probe socket 290-1 is the same as in the case of Fig. 1 The terminals corresponding to the second contact terminal group 281-2 of the terminal group 281-1 and the second probe socket 290-2 are connected to each other across the wiring 1 0 1 B, and will cross the one end side of the wiring 1 0 1 B Terminal -23- (21) 1300484 Sub T 1 is connected to the driver output pin S 1 provided on the pin electronics PE via the line 1 0 1 A and passes the other end side of the wiring 1 〇 B through the terminal U1 The line 101C is connected to the comparator input pin R1 provided on the pin electronic PE, and the first contact terminal group 281-1 and the second probe socket 2 90-2 of the first probe socket 290-1 The range of all contact terminals of the second contact terminal group 2 8 1 - 2 is applied, and the first contact terminal group 281-1 of the second probe socket 290-2 is connected to the driver via lines 102A and 102B, respectively. The output pin S2 and the comparator and the input pin R2 are formed, and the first contact terminal of the second probe socket 290-2 281-- range for all of the terminals 1 can be performed. According to this configuration, the first type semiconductor element and the second type semiconductor element which are present on the wafer can be tested for two at a time. However, in this case, the semiconductor element of the third type must be tested under the condition that the probe 2 9 1 of the first probe socket 2 901 is not mounted. Therefore, it is desirable that the probe 291 is of a configuration that can be attached/detached. Moreover, if the semiconductor element of the third type is formed only on the wafer at the position of the second probe socket 290-2, and is not formed at the position of the first probe socket 290-1, The composition shown in Figure 7 is tested one at a time. Here, the first type of semiconductor element and the second type of semiconductor element and the third type of semiconductor element which are present on the wafer must form the respective pads in the same positional relationship. Embodiment 3 • 24- (22) (22) 1300484 Fig. 8 is a view showing an embodiment in which the probe card is applied to the connection configuration of the second invention. In this embodiment, the first type of semiconductor component and the second type on the semiconductor wafer can be tested by the first probe socket 290-1 and the second probe socket 290-2, respectively. The reason for the semiconductor element is repeated with the description of FIGS. 2 and 3, and thus the above description is omitted here. However, in this embodiment, the third type of semiconductor element is tested by the second probe socket 290-2 under the condition that the probe 291 of the first probe socket 290-1 is not mounted. Fourth Embodiment A connection configuration proposed in the third invention is shown in Fig. 9. The connection configuration proposed here is a connection configuration in which the data output/input terminal applied to the DUT is a mode in which the paired terminals are differentially switched to the operation mode and the non-operation mode at different timings. A semiconductor element exhibiting such characteristics is an element for a video pattern, and the first contact terminal group 28 1 of the second contact 280-2 shown in FIGS. 1 to 5 is conventionally used at each terminal. 1 is connected to the pin electronic PE, or the first contact terminal group 281-1 of the first contact device 280-1 and the second contact terminal group 281 of the second contact device 280-2 are respectively shown in FIG. 2 Connect to the connection structure of the pin electronics PE for testing. In particular, when the first contact terminal group of the second contact 280-2 shown in FIGS. 1 to 5 is connected to the connection structure of the pin electronic PE, the driver and the comparator must be connected to the DUT. The number of data output/input pins corresponds to the number -25 - (23) 1300484. In the case of the connection structure of the divergent structure shown in Fig. 5, the groups formed by the driver and the comparator are It is only about half of the number of pins for data output/input of the DUT. However, in the case of the connection of the divergent structure shown in Fig. 5, even as shown in Fig. 5, the lines 1 2 1 A, 1 2 1 B and 1 3 1 A, 1 3 1 B must be matched as The characteristic impedance of about another one of the characteristic impedance of the other line 120A, 130A. That is, in the case where the characteristic impedance of the lines 120A and 130B is 50 Ω, the characteristic impedance of the lines 1 2 1 A, 1 2 1 B and 1 3 1 A, 1 3 1 B must be about 100 Ω. In this way, in a bifurcation circuit in which the characteristic impedance is converted from 50 Ω to 100 Ω, the signal is reflected, resulting in an improper deterioration of the waveform quality. In order to solve this problem, in the third invention, it is requested that the terminals that are operated by shifting the control signals by the switching time are connected to each other across the wiring, and one of the terminals is connected to the driver output pin provided in the pin electronics. And connect the other terminal to the comparator input pin provided on the pin electronics to test the two terminals on a common line. Fig. 9 shows this embodiment. The 2 80 shown in Figure 9 indicates the contact. The contact member is provided with a contact portion CNT, and a external terminal such as a pin type of a DUT (not shown) is brought into contact with the contact portion CNT, thereby electrically connecting each external terminal of the DUT to the contact terminal group. Each contact terminal of 281. Here, it is shown that the contact terminals V 1 - 1 and VI - 2, V2 - 1 and V2 - 2.....VN - 1 and VN - 2, and W1 -1 and W1 - are in contact with the terminal group 28 2. W2 — 1 and W2 — 2, ..., WN — 1 and WN — 2 -26- (24) (24) 1300484 are contact terminals that contact the pins that act in pairs. The pair of contact terminals are commonly connected to each other across the wirings 101 Bl-1 to 101B1-N and 101B2-1 to 101B2-N, and each of the crossing wires 101B, for example, one end side of 101B1_1, passes through the terminals. T1 - 1 and line 101A - 1 are connected to the driver output pin S1 - 1 of the first 10 channel IOCH_1 provided in the pin electronics PE and will cross the other end side of the wiring 101B1 - 1 through the terminal U 1 - 1 And the line 1 0 1 C - 1 is connected to the comparator input pin R1 - 1. In Fig. 9, although the connection of two channels is shown (that is, even the second 10-channel I0CH-2 has the same connection), the input and output pins of the DUT are operated like this. Connect to the ground. According to this configuration, in the specific DUT in which the condition of simultaneous output does not occur, one of the pins of the common connection of the DUT is controlled to the operating state, and the test pattern signal is applied from the driver through the line 1 0 1 A, and The response signal is taken to the comparator side through the line 1 0 1 C, and the test of one of the pins can be performed. When one of the pins is in the rest state, the other pin is switched to the active state. Test the other's pins in this state. Moreover, testing with another pair of terminals of the IOCH-2 (for example, W1 - 1 and W1 - 2) is performed with a test using a pair of terminals of the IOCH-1 (for example, V 1 -1 and V 1 - 2 ) . Therefore, it is possible to measure the DUT of the 1-pin pin of the 32-pin by using 10 channels of 16 channels. Further, since one of the pins and the other of the pins are formed as crossing wires, the amount of transmission delay observed by the driver side is different as described above, and similarly, the -27- (observed by the comparator side) 25) (25) 1300484 There is a difference in the amount of transmission delay. Therefore, the semiconductor element test apparatus must determine the difference in phase difference between the two in advance, and the conditions for generating the test pattern corresponding to the phase difference and the timing determination condition on the comparator side are obtained by the third invention. The proposed connection structure, line 1 0 1 A and 1 0 1 C, and across wiring 1 〇1 B, will all be unified to a characteristic impedance of 50 Ω. As a result, in the middle of the line, since there is no portion where the characteristic impedance is discontinuous, the waveform quality is not deteriorated. The measurement example of the waveform is shown in Fig. 10 . Fig. 10A is a view showing the connection structure of the first contact terminals of the second contact tool 280-2 in the configuration of the first to eighth drawings of the first or second invention. Fig. 10B is a view showing the connection structure proposed in the third invention. The 10Cth diagram shows an example of a waveform in which the two connection structures are compared. The waveforms a, b, and c shown in Fig. 10C are rectangular waves applied by the driver 10DR, and are observed in the observation points (a), (b), and (c) shown in Figs. 10A and 10B. Waveform. As is apparent from the waveform, it is understood that the connection structure proposed in the third invention has a continuous matching impedance, so that the deterioration of the waveform is small. [Industrial Applicability] The semiconductor element test apparatus and the component dielectric panel of the present invention are used in the semiconductor element manufacturing department or the semiconductor element development department. [Simple description of the drawing] -28 - (26) 1300484 [Fig. 1] is a real block diagram showing the request item 1 corresponding to the invention. Fig. 2 is a block diagram showing the action of the embodiment shown in Fig. 1. [Fig. 3] The same block diagram as Fig. 2. [Fig. 4] The same block diagram as Fig. 2. [Fig. 5] is a real block diagram showing the request item 2 corresponding to the invention. [Fig. 6] is a block diagram showing the embodiment shown in Fig. 1 as a tool. [Fig. 7] Similarly to Fig. 2, a block diagram showing a specific example of the first embodiment is shown. [Fig. 8] is a block diagram showing a further example of the embodiment shown in Fig. 5. [Fig. 9] is a real block diagram showing the request item 3 corresponding to the invention. [Fig. 10] FIG. 10A is a diagram showing a connection configuration of a drive signal transmission line of a semiconductor device test apparatus according to a third aspect of the present invention, and a connection configuration of a drive signal transmission line of the first or second invention component test device. Fig. 10C is an observation waveform diagram in the configuration of Fig. 10A and the figure. [Fig. 11] A view showing a configuration of a connection between a semiconductor element test device and a 1C. [Fig. 1 2] Fig. 1 2A is a semi-conductive diagram of a specific example shown by an example of the effect of the embodiment of the semiconductor device of the conventional example, and the first signal of the first signal is set. Test device -29-(27) 1300484 The connection structure of the drive signal transmission line is set. The 1st and 2nd drawings are the connection diagram of the drive signal transmission line of the semiconductor component test device of the test example, the 12C. The figure is an observation waveform diagram in the configuration of Figs. 12A and 12B. [Fig. 13] Fig. 13 is a view for explaining an example of three types of semiconductor elements having different numbers of pins used in Figs. 13A, 13B, and 13C. # [14] Figure 14A, Figure 14B, and Figure 14C are for the purpose of illustrating the use of the three types of semiconductor components shown in Figures 1 3 A, 1 3 B, and 1 3 C. A diagram of an example of a conventional socket board. [Main component symbol description] PE: Pin electronics IOCH-1: First 10-channel group IOCH- 2: Second 10-channel group • 101 A - 1 to 101 A - N, 101C - 1 to 101C - N, 102A - 1 to 102A — N, 102B - 1 to 102B - N: Line 1 0 1 B — 1 to 1 0 1 B - N : Cross wiring 1 2 1 A — 1, 1 3 1 A - 1 : First divergence line 1 2 1 B - 1, 1 3 1 B — 1 : Second branch line 180 : Socket 1 2 0 A, 130B : Line 1 6 0 : Socket plate 260 : Component panel -30- (28) 1300484 2 8 0 : Contactor • 280— 1: First contact tool \ 280 — 2: Second contact 2 8 1 : Contact terminal group 2 8 1 — 1 : First contact terminal group 2 8 1 — 2 : Second contact terminal group 290 - 1 : First probe socket φ 290 — 2 : Second probe socket 2 9 1 : Probe 3 00 : Probe card CNT : Contact portion DQ0 to DQ15 : External terminal DUT-1 to DUT — 3: Semiconductor component S1 — 1 to SI — N, S2—1 to S2 — N: Driver output pin R1 — 1 to Rl — N, R2—1 to R2 — N: Comparator input pin • VI - 1 to VI- N, V2-1 to V2-N, W1-1 to W1 - N, W2 — 1 to W2 — N : Contact terminal IODR: Driver IOCP : Comparator Rtr : Series termination resistor Rtm : Terminating resistor U 1 — 1 ·· Terminal -31 -