96.12.20第94138375專利說明書及申請專利範圍修正本 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電路板導通孔之製造方法，特別是 關於一銅箔基板藉由一通孔本身之位置分別在二側精確定 義二光阻層之二窗口位置，以便進行後續電鑛該通孔之電 路板導通孔電鍍。 【先前技術】 請參照第1A至1F圖所示，其揭示習用電路板導通孔 電鍍方法，其步驟如下：〔1〕、如第1A圖所示，其係在一 絕緣基板90之上、下表面分別形成一導電層91 ;〔2〕、如 弟1B圖所示，對該絕緣基板9〇及二導電層91鑽孔，以 形成一通孔92，且該通孔92之孔壁形成一鍍層〔未標示 〕；〔3〕、如第1C圖所示，在該二導電層91表面分別壓合 形成一光阻層93，该光阻層93係覆蓋該通孔92 ;〔 4〕、如 第1D圖所示，在該二光阻層93對應於該通孔92之部位 分別利用光罩〔未繪示〕進行曝光及利用顯影液進行顯影 ，而形成一曝光窗口 94，該曝光窗口 94之孔徑係大於該 通孔92之孔徑；〔5〕、如第1E圖所示，對該通孔92進行 電鍍，以形成一連通導電層95，因而組成一導通孔構造； 及〔6〕、如第1F圖所示，除去該光阻層93，藉此該導零 層91、連通導電層95導通該絕緣基板9〇之上、下表面的 電路佈局。 雖然上述電路板導通孔電鍍方法係一般業界習用之 電鍍方法，但是在實際製程中，由於上述電路板導通孔電 1298008 96.12.20第94138375專利說明書及申請專利範圍修正本 鍍方法係先形成該通孔92’再後續利用光罩對該光阻層％ 進行曝光，使其對應於該通孔92之部位曝光顯影形成該窗 口 94，因此若光罩定位不正確，該窗口 94與通孔將容 易形成對位誤差〔如第1G圖所示，對應於第m圖〕，嚴 重時甚至造成後續電鍍僅形成未導通之該連通導電層％ ，進而相對降低電路板製造良率及可靠度。此外，如第出 圖所示’業界通常利用增加該光阻層93之曝光窗口 94的 孔徑尺寸’以避免產生上述對位誤差之情形。然而，如第 1F圖所示，當該連通導電層95形成之後，該連通導電声 %延伸出該通孔％之部位亦相對增加。同時，由於該】 通導電層95之可撓錄低，因此若該電路板選自軟性^路 板’則該連通導電層95延伸出該通孔95之部位則容易因 為该電路板之彎折而發生脆裂之情形。因此，其確實有必 要進一步改良上述電路板導通孔電鍍方法。 、 利用相同方法在另一 窗口；藉此，該第一 成一連通導電層。由 有鑑於此’本發明改良上述之缺點，其係在一銅落基 ，貝穿形成-通孔；先由該銅錄板—側之—導電層」士人 Τ光阻層」再由該銅箱基板之另一側將一溶劑注入該通I 、便在4光阻層對應於該通孔之部㈣彡成—第一窗口； 側形成一弟二光阻層，其亦具一第二96.12.20 Patent No. 94138375 and the scope of the patent application. The present invention relates to a method for manufacturing a via hole of a circuit board, and more particularly to a copper foil substrate by a through hole itself. The positions of the two photoresist layers are precisely defined on the two sides to perform the electroplating of the through-holes of the circuit board of the through-hole. [Prior Art] Referring to FIGS. 1A to 1F, a method of plating a via hole of a conventional circuit board is disclosed. The steps are as follows: [1] As shown in FIG. 1A, it is placed on and below an insulating substrate 90. A conductive layer 91 is formed on the surface; [2], as shown in FIG. 1B, the insulating substrate 9 and the two conductive layers 91 are drilled to form a through hole 92, and a hole is formed in the hole wall of the through hole 92. [3], as shown in FIG. 1C, a photoresist layer 93 is formed on the surface of the two conductive layers 91, and the photoresist layer 93 covers the through hole 92; [4] As shown in FIG. 1D, portions of the two photoresist layers 93 corresponding to the through holes 92 are exposed by a photomask (not shown) and developed by a developing solution to form an exposure window 94. The exposure window 94 is formed. The aperture is larger than the aperture of the through hole 92; [5], as shown in FIG. 1E, the through hole 92 is plated to form a conductive layer 95, thereby forming a via structure; and [6], As shown in FIG. 1F, the photoresist layer 93 is removed, whereby the zero-conducting layer 91 and the conductive layer 95 are electrically connected to the insulating layer. The circuit layout above and below the board. Although the above-mentioned circuit board via plating method is a commonly used electroplating method in the industry, in the actual process, the above-mentioned circuit board via hole 129808 96.12.20 No. 94138375 patent specification and the patent scope correction plate plating method form the pass first. The hole 92' is subsequently exposed to the photoresist layer by a mask to expose the portion corresponding to the through hole 92 to form the window 94. Therefore, if the mask is not positioned correctly, the window 94 and the through hole will be easy. The alignment error is formed (as shown in FIG. 1G, corresponding to the mth image). In severe cases, even the subsequent electroplating only forms the non-conducting conductive layer %, which in turn reduces the board manufacturing yield and reliability. Further, as shown in the figure, the industry generally utilizes an increase in the aperture size of the exposure window 94 of the photoresist layer 93 to avoid the above-described alignment error. However, as shown in Fig. 1F, when the connected conductive layer 95 is formed, the portion of the connected conductive sound % extending out of the through hole % is relatively increased. At the same time, since the flexible recording layer 95 has a low flexible recording, if the circuit board is selected from a flexible circuit board, the portion of the conductive conductive layer 95 extending out of the through hole 95 is easily bent by the circuit board. The situation of brittle fracture occurs. Therefore, it is indeed necessary to further improve the above-mentioned circuit board via plating method. Using the same method in another window; thereby, the first one is connected to the conductive layer. In view of the above, the present invention improves the above-mentioned disadvantages, which are formed by a copper drop base, which is formed by a through hole, and is formed by the copper recording board - the side conductive layer "Shenzhen Τ photoresist layer" The other side of the copper box substrate injects a solvent into the pass I, and the fourth photoresist layer corresponding to the through hole (four) is formed into a first window; the side forms a second light resist layer, which also has a first two
1298008 96.12· 20第94138375專利說明書及申請專利範圍修正本 ，因而可避免該連通導電層發生脆裂之情形。 【發明内容】 本發明主要目的係提供一種電路板導通孔之製造方 法，其係一銅箔基板藉由一通孔本身之位置分別定義二光 阻層之二窗口位置，以便在該通孔内電鍍形成一連通導電 層，使得本發明具有提升對位精確性及製程便利性之功效 〇 本發明次要目的係提供一種電路板導通孔之製造方 法，其係在一絕緣基板二侧分別形成一導電層，且該導電 層係依序結合—光阻層及—保護層，及光線通過該 保護層’叫光硬化該光阻層，轉該絲層先前形成之 窗口形狀，使得本發明具有提升導通孔成形良率之功效。 3根據本發明之祕板導通孔之肢紐，其包含下歹4 步驟：在一電路基板之二侧分別形成一第一導電層及一第 =導電層’該絕緣基板、第—導電層及第二導電層共同貫 穿形f—通孔；將—第—光阻層及—第-保護層依序結合 於該第-導電層上；將—第—溶劑注人該通孔，以洗除$ 第-光阻層對應於該通孔之部位，進而形成—第—窗口、了 利用光線It輕帛-賴相曝光硬化 =:該第-保護層;將-第二先阻層及-第二= 序結合於該第二導電層上；相同製造方法在該第二杏 阻層形成-第二窗口；_—光線通過該第二 =化該第二光阻層，再除去該第二保護層；及在料2 鍍形成-連通導電層，再去除該第—及第二光阻層。 1298008 96.12.20第94138375專利說明書及申請專利範圍修正本 【實施方式】 為讓本發明之上述及其他目的、特徵、優點能更明顯 易懂’下文特舉本發明之較佳實施例，並配合所附圖式， 作詳細說明如下： 請參照第3A及3B圖所示，其揭示本發明較佳實施例 之電路板導通孔之製造方法之第一步驟，其係在-絕緣基 板10之二侧分別形成一第—導電層^及-第二導電層η， ’該絕緣基板1G、第—導電層11及第二導電層11,共同貫 穿形成-通孔12。更詳言之，該第—及第二導電層 較佳可選自銅〔〇〇導電層，且該第一及第二導電層n 、、11係選私船自之以形成於舰絲板10表面。該 』通2 12車乂隹^可、自雷射鑽孔或機械鑽孔之方式貫穿該絕 緣基板10、第一及第二導雷 、 Μ辟r π 寬層1、11 °此外，該通孔12 之孔土〔未私不〕可選擇形成-鍍層〔未標示〕。1298008 96.12. 20 Patent specification 94138375 and the scope of the patent application, so that the bridging of the connected conductive layer can be avoided. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a via hole of a circuit board, wherein a copper foil substrate defines two window positions of the two photoresist layers by a position of a through hole itself, so as to be plated in the through hole. Forming a connected conductive layer, so that the present invention has the effect of improving alignment accuracy and process convenience. The secondary object of the present invention is to provide a method for manufacturing a via hole of a circuit board, which is formed by electrically conducting on both sides of an insulating substrate. a layer, and the conductive layer is sequentially bonded to the photoresist layer and the protective layer, and the light passes through the protective layer, which is called photohardening the photoresist layer, and the previously formed window shape of the silk layer is used to improve the conduction of the present invention. The effect of hole forming yield. 3 according to the present invention, the body of the via hole of the secret plate includes a lower jaw 4 step: forming a first conductive layer and a first conductive layer on both sides of a circuit substrate, the insulating substrate, the first conductive layer and The second conductive layer penetrates through the f-via; the first-photo-resist layer and the first-protective layer are sequentially bonded to the first conductive layer; the first solvent is injected into the through hole to wash away The first-photoresist layer corresponds to the portion of the through-hole, thereby forming a -first window, using light ray It is light--phase exposure hardening =: the first protective layer; the - second first resist layer and - the first a second order is bonded to the second conductive layer; the same manufacturing method forms a second window in the second apricot layer; _-light passes through the second=the second photoresist layer, and then the second protection is removed And forming a conductive layer on the material 2 and removing the first and second photoresist layers. The above and other objects, features and advantages of the present invention will become more apparent and understood <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The drawings are described in detail below. Referring to FIGS. 3A and 3B, the first step of the method for manufacturing the via hole of the circuit board according to the preferred embodiment of the present invention is disclosed. A first conductive layer and a second conductive layer η are formed on the side, and the insulating substrate 1G, the first conductive layer 11 and the second conductive layer 11 are formed in common through the via hole 12. More specifically, the first and second conductive layers are preferably selected from the group consisting of copper and germanium conductive layers, and the first and second conductive layers n and 11 are selected from the private ship to be formed on the shipboard. 10 surface. The "pass" 2 12 car 乂隹 ^, from the laser drilling or mechanical drilling through the insulating substrate 10, the first and second guide lightning, r r r π wide layer 1, 11 ° in addition, the pass The hole soil of the hole 12 [not private] can be formed into a plating layer (not shown).
請參照第3C圖所示 — J 路板導通孔之製造方法之/揭不本發明較佳實施例之電 π及-第-保護層入步驟，其係將一第一光阻層 詳言之，該第-光阻層^以於該第一導電層U上。更 於該第-導電層11上。談侧可選擇以壓合之方式結合 光阻層13之另一侧，^弟一保護層14係結合於該第一 第-導電層U及第-保2第一光阻層13夾設固定於該 撐保護該第-光阻層13 6 14之間’ 5亥第—保護層14支 層Π意外發生剝離。該^而避免後續製程中該第一光阻 〔polyester〕等透明材質保護層14較佳可選自聚_ 、 以供光線通過。 Ι298·2。第94咖專咖書及中_範圍修正本 、明、乡知第3D圖所不，其揭示本發明較佳實施例之電 路"^通孔之製造方法之第三步驟，其係將一第一溶劑〔 未標不〕注入該通孔12，以洗除該第-光阻層13對應於 該通孔12之部位，進而形成—第―窗口 13卜更詳言之: 該第一溶劑可依該第—光阻層13之材質選擇適當之^ 。該第—溶劑係由該通孔12之—侧〔亦即遠離該第一光阻 層13之-側〕注入該通孔12内，且該第一溶劑洗除該第 一光阻層13對應於該通孔12及其周圍區域之部位，以妒 成該第一窗口 m。該第一窗口 131之口徑較佳係控制至 相對大於該通孔12之孔徑。除了將該第-溶劑注入該通孔 12内之方法’本翁較佳實施例亦可選擇賴電路板完全 浸泡至該第-溶射，其同樣料錢除職機通孔色 之戎第一光阻層13之暴露部位。 』請參照第3E及3F圖所示，其揭示本發明較佳實施例 之電路板導通孔之製造方法之第四步驟，其係利用一光線 通過，第-保護層14以曝光硬化該第一光阻層13，再除 去該第-保護層14。更詳言之，在曝光步驟後，使得該第 -光阻層13獲得;^夠結構強度，同時該第 成 開放狀。 乂 明參&第3F至31圖所不，其揭示本發雜佳實施例 ,電路板導通孔之製造方法之第五至七步驟，其係將一第 -光阻層13及—第二保護層14，依序結合於該第二導電層 ij，上；利用相同製造方法在該第二光阻層13，形成—第二 窗口 131，；利用—光線通過該第二保護層14，曝光硬化該 ——10—— !298〇〇8 9δ· 12· 20第94138375專利說明書及申請專利範圍修正本 第二光阻層13’ ’再除去該第二保護層14，。更詳言之，本 發明係利用該第一溶劑〔未標示〕由該第一窗^ Υ3ΐ注入 麵孔12内’以形成該第二窗口 131，。藉此，該通孔u '第-及第二窗口 13卜131，係共同貫穿該絕緣基板1〇、 第-及第二導電層U、u，、第—及第二光阻層η、a。 請參照第3J及3K圖所示，本發明較佳實施例之 板導通孔之製造方法之“步驟，其係在科通孔12電聲 形成-連通導電層15，再去除該第—及第二光阻層13 。更之’該連通導電層15較佳可選擇以電鑛銅之 式形成於該通孔12，如此即組成一導通孔構造。該連通 電層15係電性導通該第一及第二導電層uu，，以供恭 性導通該第一及第二導電層11、11，之電路佈局。电 如上所述’相較於第1G圖之龍電路板導通孔電聲 :二形成該通孔92 ’再後續利用光罩曝光、顯影液顯‘ 方式形成該窗口 94’容易因光罩相對定位 窗 對位誤差等缺點，第2圖； _ ^ 本身之位置分別在二側定義該第-及第 一阻層13、13’之第-及第二窗口 13卜131，的位置，以 便後續電鍍形成該通孔12之連通導電層15，1確實可 對提升對位精確度及電路板製造良率。 雖然本發明已利用上述較佳實施例揭示，然其並非 此技藝者’在不脫離本發明之精 ==當可作各種更動與修改，因此本發明之保 濩耗圍虽視後附之申請專利範圍所界定者為準。 /29¾38 •12· 20第94138375專利說明書及f請專利範圍修正本 【圖式簡單說明】 第1A至1F圖·習用電路板導通孔電鑛方法製造導通孔 步驟之剖視圖。 第1G圖·習用電路板導通孔電鍍方法產生對位誤差之 剖視圖。 第2圖·本發明較佳實施例之電路板導通孔之製造方法 之流程方塊圖。 第3A至3K圖：本發明較佳實施例之電路板導通孔之 製造方法製造導通孔步驟之剖視圖。 【主要元件符號說明】 11第一導電層 12通孔 13，第二光阻層 131’第二窗口 14弟-一保護層 90絕緣基板 92 通孔 94 窗口 10 絕緣基板 11’第二導電層 13第一光阻層 131第一窗口 14第一保護層 15連通導電層 91導電層 93 光阻層 95 連通導電層 —12 —Please refer to FIG. 3C for the manufacturing method of the J-channel via hole, or the electrical π and - first-protective layer-in step of the preferred embodiment of the present invention, which is a first photoresist layer. The first photoresist layer is on the first conductive layer U. More on the first conductive layer 11. The other side of the photoresist layer 13 may be bonded in a press-fit manner, and the protective layer 14 is bonded to the first first conductive layer U and the first protective layer 1 to be fixed. During the protection of the first photoresist layer 13 6 14 , the 5 第 - protective layer 14 support layer is accidentally peeled off. The transparent material protective layer 14 such as the first photoresist in the subsequent process is preferably selected from poly _ for light to pass through. Ι298·2. The third step of the manufacturing method of the circuit of the preferred embodiment of the present invention is to disclose the third step of the method for manufacturing the circuit of the preferred embodiment of the present invention. The first solvent (not labeled) is injected into the through hole 12 to wash away the portion of the first photoresist layer 13 corresponding to the through hole 12, thereby forming a - window 13 in more detail: the first solvent can be The material of the first photoresist layer 13 is selected as appropriate. The first solvent is injected into the through hole 12 from the side of the through hole 12 (that is, the side away from the first photoresist layer 13), and the first solvent is washed away from the first photoresist layer 13 The first window m is formed in the portion of the through hole 12 and its surrounding area. The aperture of the first window 131 is preferably controlled to be relatively larger than the aperture of the through hole 12. In addition to the method of injecting the first solvent into the through hole 12, the preferred embodiment of the present invention can also choose to completely immerse the circuit board in the first-solubilization, which is also the first light of the pass-through color of the de-carrying machine. The exposed portion of the resist layer 13. Referring to FIGS. 3E and 3F, a fourth step of a method for manufacturing a via hole of a circuit board according to a preferred embodiment of the present invention is disclosed. The first step is to pass a light, and the first protective layer 14 is hardened by exposure. The photoresist layer 13 is further removed from the first protective layer 14. More specifically, after the exposure step, the first photoresist layer 13 is obtained with sufficient structural strength while the first opening is open.乂明参& 3F to 31, which discloses a fifth embodiment of the present invention, a fifth to seventh step of the method for manufacturing a via hole of a circuit board, which is a first photoresist layer 13 and a second a protective layer 14 is sequentially bonded to the second conductive layer ij; a second window 131 is formed on the second photoresist layer 13 by the same manufacturing method; and the light is passed through the second protective layer 14 to expose Hardening the -10 - 298 〇〇 8 9 δ · 12 · 20 94138375 patent specification and the patent scope modification of the second photoresist layer 13 ′′ to remove the second protective layer 14 . More specifically, the present invention utilizes the first solvent [not labeled] to be injected into the face 12 by the first window 以3ΐ to form the second window 131. Thereby, the through holes u 'the first and second windows 13 131 are commonly penetrated through the insulating substrate 1 , the first and second conductive layers U, u, and the first and second photoresist layers η, a . Referring to FIGS. 3J and 3K, in the preferred embodiment of the present invention, a method for fabricating a via hole of a board is performed by electroacoustic forming a conductive via layer 15 in the via hole 12, and then removing the first and the third The second photoresist layer 13. The conductive layer 15 is preferably formed in the via hole 12 in the form of electro-mineral copper, thus forming a via structure. The via layer 15 is electrically conductive. The first and second conductive layers uu are arranged to electrically conduct the first and second conductive layers 11, 11. The electrical layout of the first and second conductive layers 11, 11 is as described above. 2. Forming the through hole 92' and then forming the window 94' by means of ret exposure and developer display, which is easy to be misaligned by the relative positioning window of the reticle, and the second figure; _ ^ itself is located on both sides Defining the positions of the first and second resistive layers 13, 13' of the first and second resistive layers 13, 13' for subsequent electroplating to form the via conductive layer 15 of the via 12, 1 can indeed improve the alignment accuracy And board manufacturing yield. Although the invention has been disclosed using the preferred embodiment described above, it is not The skilled artisan of the present invention can make various changes and modifications without departing from the invention. Therefore, the warranty of the present invention is defined by the scope of the appended claims. / 293⁄438 • 12· 20 94138375 Patent Specification and f. Patent Scope Correction [Simplified Drawing] 1A to 1F. Fig. 1 is a cross-sectional view showing a step of manufacturing a via hole by a conventional circuit board via hole electroporation method. FIG. 2 is a block diagram showing a method of manufacturing a via hole of a circuit board according to a preferred embodiment of the present invention. FIGS. 3A to 3K are diagrams showing a method of manufacturing a via hole of a circuit board according to a preferred embodiment of the present invention. Cross-sectional view of the hole step. [Main element symbol description] 11 first conductive layer 12 through hole 13, second photoresist layer 131' second window 14-a protective layer 90 insulating substrate 92 through hole 94 window 10 insulating substrate 11' Second conductive layer 13 first photoresist layer 131 first window 14 first protective layer 15 connected to conductive layer 91 conductive layer 93 photoresist layer 95 connected conductive layer - 12 -