1295909 五、發明說明α) 【發明所屬之技術領域】 本發明係有關於一種形成於電路板中之電容結構，尤 指一種在電路板結構中整合有電容元件，藉以提升電子產 品之電性品質。 【先前技術】 電子產品在南功能及南速化的趨勢下’漸需在半導體 裝置上整合有例如電阻器（Resistors)、電容器（ Capacitors)及電感器（Inductors)等被動元件（Passive component)，以提昇或穩定電子產品的電性功能。 如第1圖所示，多數之被動元件1 2 (如電容元件）係 安置於電路板1之表面，然為避免該等被動元先1 2阻礙電 路板上例如半導體晶片1 1之主動元件與多數鲜接塾（ Β ο n d i ng f i ng e r s)間之電性連結，傳統上多將該等被動 元件1 2安置於電路板1之角端位置或半導體晶片1 1接置區 域外之電路板額外佈局面積上。惟限定被動元件1 2安設位 置將縮小電路板1表面線路佈局（R 〇 u t a b i 1 i t y )之靈活性； 同時需考量銲接墊位置，導致該等被動元件1 2佈設數量受 到侷限，不利半導體裝置高度集積化之發展趨勢；甚者， 被動元件1 2佈設數量隨者半導體裝置南性能之要求而相對 地遽增，如採習知方法該基板1表面必須同時容納多數半 導體晶片1 1以及大量被動元件1 2，而迫使封裝件體積增大 ，亦不符合半導體裝置輕薄短小之發展潮流。 此外，隨著電子產品朝向高功能性與小型尺寸之發展 趨勢，電路板的疊層（L a m i n a t i ο η )技術也就必須具備厚度1295909 V. INSTRUCTION DESCRIPTION α) Technical Field of the Invention The present invention relates to a capacitor structure formed in a circuit board, and more particularly to a capacitor element integrated in a circuit board structure, thereby improving the electrical quality of the electronic product. . [Prior Art] Under the trend of south-function and south-speed, electronic products are increasingly required to integrate passive components such as resistors, capacitors (capacitors) and inductors (Inductors) on semiconductor devices. To enhance or stabilize the electrical function of electronic products. As shown in FIG. 1, a plurality of passive components 12 (such as capacitive components) are disposed on the surface of the circuit board 1, but to prevent the passive components from blocking the active components such as the semiconductor wafer 11 on the circuit board. The electrical connection between most of the fresh 塾 n di di di , , , 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统Additional layout area. However, limiting the position of the passive component 1 2 will reduce the flexibility of the surface layout of the circuit board 1 (R 〇 utabi 1 ity ); at the same time, the position of the solder pad needs to be considered, resulting in the limitation of the number of such passive components 12 , which is disadvantageous for the semiconductor device. The trend of high-accumulation; in other words, the number of passive components 12 is relatively increased with the requirements of the south performance of semiconductor devices. As is known, the surface of the substrate 1 must accommodate most semiconductor wafers 1 and a large number of passives. Element 1 2, forcing the package to increase in volume, does not meet the trend of thin and light semiconductor devices. In addition, as electronic products are moving toward higher functionality and small size, the laminate (L a m i a t i ο η ) technology must have a thickness.
17753 全懋.ptd 第7頁 129590917753 Full 懋.ptd Page 7 1295909
五、發明說明（2) 薄、多層數與高密度之特點。因此，為更進〜 板空間需求，於是發展出鑲埋有被動元件之多=纟侣小電路 其中該些被動元件均係以膜狀方式堆疊於多屛$電路板， 層間。 9笔路板之疊 而整合製成多種膜狀被動元件於一多層曹 數種不同之方式，如铉9冃％ ^ ^ ^ 略板係具有 」之方式如弟2圖所不，將一電容膜2 方二一夕層電路板2中時，該電容膜22係選自介=^鑲埋 ::::子其：由如高分子材料、陶瓷材料、“二之填 •同刀子及其相似物等，其材料可例如為鈦酸鋇（ Barlum-tltanate)、鈦酸鍅鉛（^以―zirc〇nate一 te) 癌疋形氫化碳（Amorphous hydrpgenated Ca^bC^丄或其粉末散佈於黏結劑（Binder )中，如樹脂、 ^，氣末等’亦可利用濺鍍、印刷（Pr int ing)產滾輪旋 二式^Ql leF c〇ating)等方式成形，再藉由諸如曝光、蝕 兩〆=ίί &整（L a S 6 Γ 11 r 1 mm i n g)等圖案化製程而形成所 电:膜22。而後於該電容膜2 2之相對兩表面形成有圖 I電金屬層21，該圖案化之導電金屬層21包含有若 ^ ^ ^ 下馬0系包谷兀件2 2 a之平行板電極2 1 b，俾在該 惟卞此0構之$層間完成鑲埋有電容元件。 厶®，破動元件之鑲埋結構係以整層被動元件材料與 仏制 > 丄 兔路板甲 再經由例如蝕刻、電射等繁雜圖案 化衣牙王力口以形占，你π 古#丄 〃成 便奸電路板之整體結構及其所需製程具 雜度而不符合成本效益。 【發明内容】V. Description of invention (2) Characteristics of thin, multi-layer and high density. Therefore, in order to further increase the space requirement of the board, a large number of embedded passive components are developed. The passive components are stacked in a film-like manner on multiple circuit boards. 9 sets of road plates are stacked and integrated into a variety of film-like passive components in a multi-layered Cao several different ways, such as 铉9冃% ^ ^ ^ slightly board has a way like the brother 2 map does not, will one When the capacitor film 2 is in the square circuit board 2, the capacitor film 22 is selected from the group consisting of: =::::: such as polymer materials, ceramic materials, "two fills with the same knife and The similar substance or the like may be, for example, barium titanate or barium titanate (^-zirc〇nate-te) cancerous hydrogenated carbon (Amorphous hydrpgenated Ca^bC^丄 or its powder dispersion) In the binder, such as resin, ^, gas, etc., can also be formed by sputtering, printing (Pr int ing), and by means of exposure, such as exposure , etching two 〆 = ίί & integer (L a S 6 Γ 11 r 1 mm ing) and other patterning processes to form electricity: film 22. Then the opposite surface of the capacitor film 22 is formed with the metal of Figure I The layer 21, the patterned conductive metal layer 21 comprises a parallel plate electrode 2 1 b of the 0 ^ ^ ^ 包 兀 2 2 2 a, 俾 间 该 卞 0 0 0 Inlaid with capacitive components. 厶®, the embedded structure of the broken component is made of the entire passive component material and the &制&兔板板, and then through the complicated patterning such as etching, electric radiation, etc. In the form of the shape, you π ancient #丄〃成便奸电路板's overall structure and the required process complexity are not cost-effective.
]7753全懋.ptd 第8頁 1295909 五、發明說明（3) 鑒於上述習知技術之缺點，本發明之主要目的係提供 一種形成於電路板中之電容結構，俾提昇半導體裝置内被 動元件之佈設數量，並增加線路佈局的靈活性。 本發明之另一目的係提供一種形成於電路板中之電容 結構，俾縮減電路板使用面積，以達半導體裝置輕薄短小 之目標。 本發明之又一目的係提供一種形成於電路板中之電容 結構，主要係可於電路板内鑲埋有電容結構，以提昇半導 體裝置之電性品質，同時不致影響電路板線路佈局靈活性 〇 本發明之形成於電路板中之電容結構係包#有一對平 @ 行之導電元件，係相互間隔一間隙而呈螺旋折曲狀以鑲埋 於電路"Ϊ反中；以及一介電層，係充填於該對導電先件間之 間隙。 亦即，本發明之形成於電路板中之電容結構係可在電 路板之絕緣層中鑲埋有一對相互間隔之平行導電元件，俾 利用該對相互平行之導電元件作為電容元件之平行板電極 以在該對導電元件之間隙中填充有介電材料而形成電容元 件，同時，本發明之電容結構係呈螺旋折曲狀，俾可在電 路板中欲佈設有被動元件之單位面積下，具有較多之空間 φ 可供充分利用以形成電容元件，同時藉由本發明之該螺旋 折曲狀電容結構之彎折長度與次數以及充填於該導電元件 間之介電材料與尺寸，即可因應各種需求加以決定所需電 性設計之電容值。In the light of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a capacitor structure formed in a circuit board to improve passive components in a semiconductor device. Layout the number and increase the flexibility of the line layout. Another object of the present invention is to provide a capacitor structure formed in a circuit board, which reduces the use area of the board to achieve the goal of slimness and shortness of the semiconductor device. Another object of the present invention is to provide a capacitor structure formed in a circuit board, mainly by embedding a capacitor structure in the circuit board to improve the electrical quality of the semiconductor device without affecting circuit board layout flexibility. The capacitor structure package # formed in the circuit board of the present invention has a pair of conductive elements of a flat row, which are spirally bent at intervals with each other to be embedded in the circuit "Ϊ反; and a dielectric layer , filling the gap between the pair of conductive components. That is, the capacitor structure formed in the circuit board of the present invention may have a pair of mutually spaced parallel conductive elements embedded in the insulating layer of the circuit board, and the pair of mutually parallel conductive elements are used as parallel plate electrodes of the capacitor elements. Forming the capacitor element by filling a gap between the pair of conductive elements to form a capacitor element, and at the same time, the capacitor structure of the present invention is spirally bent, and the crucible can be disposed in a unit area of the circuit board where the passive component is to be disposed. A large amount of space φ can be fully utilized to form a capacitor element, and at the same time, by the bending length and the number of times of the spiral-folded capacitor structure of the present invention and the dielectric material and size filled between the conductive elements, various kinds of conditions can be met. The demand determines the capacitance value of the required electrical design.
17753 全懋.ptd 第9頁 1295909 五、發明說明（4) 因此，本發明所提供之呈螺旋折曲狀之電容結構係可 鑲埋至電路板中，以提昇半導體裝置内被動元件之佈設數 量與電性功能，並得以增加電路板線路佈局靈活性，藉以 縮減使用面積，以達半導體裝置輕薄短小之目標，同時， 藉由簡單之製程即可加以組合完成電性設計所需之電容值 【實施方式 為使本 與認同，茲 說明如后。 係為本發明 合先敘明。 請參閱 容結構之示 件3 1以及充 對導電元件 埋於一多層 於該對導電 屬結構，且 (An) 、！巴 容結構3 0之 層3 2係可選 陶瓷材料、 容結構3 0之 發明之目的、特徵及功效，能更進一步的瞭解 提供下述實施方式，配合詳細揭露及圖示詳加 當然，本發明可以多種形式實施之，以下所述 之較佳實施例，而非用以限制本發男之範圍， 第3圖，係顯示本發明之形成於電路板> 之電 意圖，該電容結構3 0包括有一對平行之導電元 填於該對導電元件3 1間之介電層3 2，其中，該 3 1係相互間隔一間隙31 0而呈螺旋折曲狀以鑲 電路板3之内層結構中，且該介電層3 2係充填 元件3 1間之間隙3 1 0。該導電元件3 1係為一金 該金屬結構係可選自銅（Cu)、鎳（Ni) /金 (Pd)及銀（Ag)之其中一者，藉以作為該電 平行板電極，而充填於該導電元件3 1間之介電 用南介電常數之介電材料’例如南分子材料、 陶瓷粉末填充之高分子及其相似物等，而該電 電容值大小，則可依所使用之介電層3 2材料、17753 懋.ptd Page 9 1295909 V. Description of the Invention (4) Therefore, the spiral-shaped capacitor structure provided by the present invention can be embedded in a circuit board to increase the number of passive components disposed in the semiconductor device. And the electrical function, and can increase the flexibility of the circuit board layout, so as to reduce the use area, in order to achieve the goal of thin and short semiconductor devices, and at the same time, the capacitance value required for the electrical design can be combined by a simple process [ The implementation is to make this and the approval, as explained later. This is a description of the invention. Please refer to the description of the structure 3 1 and the pair of conductive elements buried in a layer of the conductive structure, and (An),! The purpose, characteristics and effects of the invention of the 30-layer 3 2 series of optional ceramic materials and volumetric structures of the Barong structure can be further understood. The following embodiments are provided, with detailed disclosure and illustrations, of course, this The invention may be embodied in a variety of forms, the preferred embodiments described below, rather than limiting the scope of the present invention, and FIG. 3 is an electrical intent to form the circuit board of the present invention. 0 includes a pair of parallel conductive elements filled in the dielectric layer 32 between the pair of conductive elements 31, wherein the 3 1 is spirally bent to be spaced apart from each other by a gap 31 0 to encapsulate the inner structure of the circuit board 3. The dielectric layer 32 is filled with a gap 3 1 0 between the elements 31. The conductive element 31 is a gold metal structure which may be selected from one of copper (Cu), nickel (Ni) / gold (Pd) and silver (Ag), thereby filling the electrode as the parallel plate electrode The dielectric material between the conductive elements 31 is a dielectric material of a south dielectric constant, such as a south molecular material, a ceramic powder filled polymer, and the like, and the capacitance value can be used according to the use. Dielectric layer 3 2 material,
17753 全懋.ptd 第10頁 1295909 五、發明說明（5) 形成於該對導電元件3 1間之介電層3 2尺寸、以及該電容結 構3 0中螺旋折曲狀之彎折長度與次數加以決定。 請參閱第4A及4B圖所示，係為鑲埋有應用本發明之螺 旋折曲狀之電容結構之電路板示意圖。該電容結構3 0係鑲 埋於該多層電路板3之内層結構中，該電容結構3 0中之該 對導電元件3 1係包含有第一導電元件3 1 a以及與該第一導 電元件3 1 a相間隔且對應該第一導電元件3 1 a呈平行配置之 第二導電元件31b，俾於該第一導電元件31 a與該第二導電 元件31b間充填有介電層32，其中，該第一導電元件31 a與 第二導電元件3 1 b係呈螺旋折曲狀以配置於該電路板3之内 u 層結構中，俾可在電路板3中欲佈設有被動元先之單位面 積下，利用該螺旋結構之向中心多次折曲形態以提供較多 之空間，以供充分利用形成電容元件。如此，即苛使該電 路板3具有更多剩餘空間可供線路佈局使用，且該電容結 構3 0係可依線路設計與電性需求加以選擇配置於該電路板 3之内層結構中，藉以提昇線路佈局靈活性。而為使形成 於該電路板3中之線路結構3 3得以電性導接至該電容結構 3 0，係可在該電容結構3 0之第一導電元件3 1 a之一端透過 導電盲孔3 4以與該線路結構3 3電性連接’且在該電容結構 3 〇之第二導電元件3 1 b相對於該第一導電元件3 1 a接置有導 | 電盲孔3 4之另一端，另透過一導電盲孔3 5以與該電路板3 之線路結構3 3完成電性連接。 因此，本發明所提供之呈螺旋折曲狀之電容結構係可 鑲埋至電路板中，以提昇半導體裝置内被動元件之佈設數17753 懋.ptd Page 10 1295909 V. Description of the invention (5) Dimensions of the dielectric layer 32 formed between the pair of conductive elements 31, and the length and number of times of the spiral bending of the capacitor structure 30 Decide. Referring to Figures 4A and 4B, there is shown a schematic diagram of a circuit board in which a spiral-shaped capacitor structure to which the present invention is applied is embedded. The capacitor structure 30 is embedded in the inner layer structure of the multilayer circuit board 3. The pair of conductive elements 31 in the capacitor structure 30 includes a first conductive element 31a and a first conductive element 3. a second conductive element 31b which is spaced apart from each other and which is disposed in parallel with the first conductive element 31a, and a dielectric layer 32 is filled between the first conductive element 31a and the second conductive element 31b, wherein The first conductive element 31 a and the second conductive element 3 1 b are spirally bent to be disposed in the u layer structure of the circuit board 3, and the unit of the passive element can be disposed in the circuit board 3 Under the area, the shape of the spiral structure is bent a plurality of times toward the center to provide more space for making full use of the capacitor element. In this way, the circuit board 3 has more remaining space for the line layout, and the capacitor structure 30 can be selectively disposed in the inner layer structure of the circuit board 3 according to the circuit design and electrical requirements, thereby improving Line layout flexibility. In order to electrically connect the line structure 33 formed in the circuit board 3 to the capacitor structure 30, one of the first conductive elements 31a of the capacitor structure 30 can pass through the conductive blind hole 3. 4 is electrically connected to the line structure 33 and the second conductive element 3 1 b of the capacitor structure 3 接 is connected to the other end of the conductive hole 34 4 with respect to the first conductive element 3 1 a And electrically connected to the circuit structure 3 3 of the circuit board 3 through a conductive blind hole 35. Therefore, the spirally-shaped capacitor structure provided by the present invention can be embedded in a circuit board to increase the number of passive components in the semiconductor device.
17753 全懋.ptd 第11頁 1295909 五、發明說明（6) 量與電性功能，並增加電路板線路佈局靈活性，俾可縮減 使用面積，以達半導體裝置輕薄短小之目標，同時，藉由 簡單之製程即可加以組合完成電性設計所需之電容值。 惟以上所述僅為本發明之較佳實施方式而已，並非用 以限定本發明之實質技術内容之範圍。本發明之實質技術 内容係廣義地定義於下述之申請專利範圍中，任何他人所 完成之技術實體或方法，若是與下述之申請專利範圍所定 義者完全相同，或是為同一等效之變更，均將被視為涵蓋 於此專利範圍之中。17753 懋.ptd Page 11 1295909 V. Description of invention (6) Quantitative and electrical functions, and increase circuit board layout flexibility, can reduce the use of area, in order to achieve the goal of thin and short semiconductor devices, at the same time, by A simple process can be combined to achieve the capacitance values required for electrical design. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the technical scope of the present invention. The technical contents of the present invention are broadly defined in the following claims, and any technical entity or method performed by another person is identical to the one defined in the following claims, or is equivalent. Changes will be considered to be covered by this patent.
]7753 全懋.ptd 第12頁 1295909 圖式簡單說明 【圖式簡單說明】 第1圖係習知將被動元件安置於半導體晶片接置區域 外之電路板額外佈局面積上之示意圖； 第2圖係習知整合膜狀被動元件於多層電路板之示意 圖， 第3圖係顯示本發明之形成於電路板中之電容結構之 示意圖；以及 第4 A及4 B圖係為鑲埋有應用本發明之螺旋折曲狀之電 容結構之電路板示意圖。 (元件符號說明） 1 電 路 板 11 半 導 體 晶 12 被 動 元 件 2 電 路 板 21 % 電 金 屬 層 21b 平 行 板 電 極 22 電 容 膜 22a 電 容 元 件 3 電 路 板 30 電 容 結 構 31 導 電 元 件 31a 第 一 導 元件 31b 第 二 導 電 元件 310 間 隙 32 介 電 層 33 線 路 結 構 34, 35 導 電 盲 孔]7753 全懋.ptd Page 12 1295909 Brief Description of the Drawings [Simple Description of the Drawings] Figure 1 is a schematic diagram showing the placement of passive components on the additional layout area of the circuit board outside the semiconductor wafer mounting area; A schematic diagram of a conventional integrated film-like passive component on a multi-layer circuit board, FIG. 3 is a schematic view showing a capacitor structure formed in a circuit board of the present invention; and FIGS. 4A and 4B are embedded with an application of the present invention Schematic diagram of a circuit board with a spiral-shaped capacitor structure. (Description of component symbols) 1 circuit board 11 semiconductor crystal 12 passive component 2 circuit board 21% electric metal layer 21b parallel plate electrode 22 capacitor film 22a capacitive element 3 circuit board 30 capacitor structure 31 conductive element 31a first conductive element 31b second conductive Element 310 Gap 32 Dielectric Layer 33 Line Structure 34, 35 Conductive Blind
17753 全懋.ptd 第13頁17753 懋.ptd第13页