1288598 九、發明說明： 【發明所眉之技術領域】 本發明係關於一種於外層線路層上形成防銲底層，尤指形成厚度均勻的防 鲜底層。 【先前技術】 由於電子產品«則、之趨勢，雖基板要求的厚度越來_，尺寸也越 來越小，且由於電子產品的魏增加，也造成㈤触速增加。這此種情 況下，封I的方式，已由表面黏著（SMT)、打線式球狀陣列㈣），演進 至覆晶(Fhp Qnp)封裝。因此，對於導電迴路的佈線也隨之越來越密。 在高密度化與_化的要求下，封裝基板本身的厚度變異要求越來越高。 雖然’傳統的製作方法在防焊外層的製作，以印刷方式單次❹次塗佈， 可達到最後的要求的防焊層厚度，但是，厚度控制上的變異仍大。 明參閱第1A〜1B圖’第1A〜1B圖為習知晶片封裝基板製作之示意圖。如第 所示之外層線路㈣，乃依據設計上的需要，具有不_數量的開 3、i孔般而吕，為了後續晶片封裝的需要，在外層線路層之 亡以一般的傳統網印、滾輪塗佈方法塗佈一層防鲜底層a，如第_斤 然而，如第1B圖所示， 通孔，使得防銲底層12 由於外層線路層1〇上具有定數量的開口或是 的填覆效果不佳、不夠均勻，而導致防銲底層12 1288598 塗佈在外層_層10之他魏照_起_躲。觀如插卡記憶體 (Memory stlck)等對於外觀要求較為嚴格的產品，以傳統的塗佈很難:到 防銲底層12外觀平整的要求。 若防銲底層12外觀不辭整時，極容易導致後續晶片封裝製程時的破裂 與錫球麟的著密度補高，進轉響晶肢作的穩定度。 【發明内容】 本發明之主要目的在提供—種戦顧均⑽防職層之製造方法，紹 兩段式方法，形成厚度均勻的防銲底層。 基於上述目的，本發明提1288598 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a solder resist underlayer formed on an outer layer of a wiring layer, and more particularly to an anti-friction underlayer having a uniform thickness. [Prior Art] Due to the trend of electronic products, the thickness of the substrate is increasing, and the size is getting smaller and smaller, and the increase in the speed of the electronic product also causes (5) an increase in the speed of contact. In this case, the way of sealing I has evolved from surface mount (SMT), wire-type ball array (4), to flip chip (Fhp Qnp) package. Therefore, the wiring for the conductive loop is also becoming denser. Under the requirements of high density and _, the thickness variation of the package substrate itself is getting higher and higher. Although the 'traditional manufacturing method' is used in the production of the solder-proof outer layer and is applied in a single pass by printing, the final required solder mask thickness can be achieved, but the variation in thickness control is still large. 1A to 1B are shown in the drawings. Figs. 1A to 1B are schematic views showing the fabrication of a conventional chip package substrate. As shown in the figure, the outer layer circuit (4) is based on the design requirements, and has a number of openings 3 and i holes. For the subsequent chip packaging, the conventional circuit screen is used in the outer circuit layer. The roller coating method applies a layer of anti-frying primer layer a, such as the first sheet, however, as shown in FIG. 1B, the through-holes are such that the solder resist layer 12 has a predetermined number of openings or fillings on the outer layer layer 1 The effect is not good, not uniform enough, and the solder resist bottom layer 12 1288598 is coated on the outer layer _ layer 10. For products such as Memory Stlck, which are more demanding on the appearance, it is difficult to apply conventional coatings to the requirements of the appearance of the solder-proof underlayer 12. If the appearance of the solder resist underlayer 12 is not negligible, it will easily lead to the rupture of the subsequent chip packaging process and the density of the tin ball lining, and the stability of the spinner. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a protective layer of the protective layer (10), and a two-stage method to form a solder resist underlayer having a uniform thickness. Based on the above object, the present invention provides
捉供種形成厚度均勻的防銲底J 之製造方法，其特徵在於 ^防鲜底層乃於塗佈第一防錄底>| 於外層線路層上且填滿绩π 鲜一A method for manufacturing a solder-proof soldering J having a uniform thickness, wherein the anti-frying primer layer is coated with the first anti-recording bottom layer on the outer layer layer and filled with π fresh
、爲線路層開口後，先經磨刷第一防銲JAfter opening the circuit layer, first brush the first solder resist J
層，使曝露出外層線路屉，ιν Ώ A 9 以及使於線路層開口中的第一 p 銲底層齊平於外層線路 使再塗佈第二防銲底層於已被d 平的第一防銲底層之上。 匕板」 關於本發明之優點與精神可以藉由 的瞭解。 以下的發明詳述及所附圖式得到進一步 【實施方式】 圖為本發明晶片封裝基板製作之示意圖。如 厚度均勻_銲底層之製造方法，如同第 睛參閱第2A〜2D圖，第2A〜2d 第2A〜2D圖所示之本發明形成 1288598 1A 1B圖所不之方法，主要是在如第2a _示之外層線路⑺上形成防鲜底 層。只是，為了克服傳統上會因外層線路10具有開口或通口的緣故，使得 形成後的防銲底層有触的聽，因此，本發明的方法與習知技術在做法 的差異，主在於先消除外層線路1G不平整的表面，再形成設計上所需的防 銲底層的厚度。 關於先消除外層線路10不平整的表面，本發明方法乃藉著如第沈圖所示， 塗佈第防銲底層20於外層線路層1〇上且填滿外層線路層開口。須注 意的是，若外層線路10具有通孔時，可在塗佈第一防銲底層2〇於外層線 路層10上之別，以通孔塞膠用途之環氧樹脂將通孔充填。 在塗佈第-防輝底層2Q於外層線路層1G上之後，第_防銲底㈣可能會 像習知技術中具有起伏的現象。不過，經如帶式磨刷㈣t咖齡）、陶竟 滾輪磨刷或不織布滾輪磨刷的磨刷方法磨刷第一防銲底層20將可消除不平 整的情況。 關於磨刷第-防銲底層20的要求，主要在於使部分原本已被第一防鲜底層 20覆蓋住的外層線路層1〇再度被曝露出來，不過，外層線路層w開口或 L孔中的帛防輝底層2〇(或其他相似的材質），須齊平於外層線路層， 如第2C圖所示。如此，即可達到消除外層線路1〇不平整的表面之本發明 第一個製程目標。 緊接著，為了能使本發明的防銲底層的厚度能符合設計上的要求，因此， 如第2D圖所示，再度塗佈另一層防銲底層（亦即第二防銲底層2幻於已被整 平的第一防銲底層20和部分外層線路層2〇之上。由於，形成第二防銲底 1288598 層22時，是在由第—防銲底層20和外層線路層ι〇共同所提供的平整表面 上形成的，因此，鱗可_與習知綱財式，«地戦具有均勾厚 度的防銲底層。 由於第-防銲底層20和第二防銲底層22均屬防銲底層，因此在材質的選 可同樣k至防鮮用途之壤氧樹脂㈤齡贴故）、乾膜式綠漆(s〇i齡 mask dry fUm)、不含玻纖之環氧樹脂、通孔塞膠用途之環氧樹脂和其他 相似材質其中之一。同時，形成第一防銲底層20和第二防銲底層22的方 法，也可同樣地選至網板印刷(screen printing)、滾輪塗佈㈣打 coating)、喷灑塗佈(spray printing)和其他相似方法其中之一。 紅上所述’本發明藉著以上所述的兩段式方法，亦即先消除外層線路μ不 平整的表面’再形成設計上所需的防銲底層的厚度，如此形成厚度均句的 防銲底層。不過，須特別注意的是’在本發明實施例中，形成第一防鲜底 層20和外層線路層10所共同提供的平整表面，僅是一種範例，不盡然限 制在第-防銲底層2〇或外層線路層1〇，只要是在具有開口或通口的載板 上’採用類似於本發明的兩段式方法’均包含在本發明所揭露的特徵與精 神之中。 猎由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與 精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限 制。相反地’其目的是希望能涵蓋各種改變及具相等性的安排於本發明所 欲申請之專利範圍的範疇内。 1288598 【圖式簡單說明】 第1A〜1B圖為習知晶片封裝基板製作之示意圖。 第2 A〜2D圖為本發明晶片封裝基板製作之示意圖。 【主要元件符號說明】 10外層線路層 12防銲底層 20第一防鲜底層 22第二防銲底層a layer for exposing the outer wiring drawer, ιν Ώ A 9 and the first p-welding underlayer in the opening of the circuit layer to be flush with the outer layer to recoat the second solder resist to the first solder resist which has been flattened Above the ground floor. The advantages and spirit of the present invention can be understood. The following detailed description of the invention and the accompanying drawings are further drawn. [Embodiment] FIG. If the thickness is uniform _ the manufacturing method of the underlayer, as in the second embodiment, the 2A to 2D, the 2A to 2d, 2A to 2D, the method of the present invention forms the method of 1288598 1A 1B, mainly in the second method. _ shows the anti-frying bottom layer on the outer layer line (7). However, in order to overcome the conventional reason that the outer layer 10 has an opening or a through opening, the formed solder resist underlayer is touched. Therefore, the difference between the method of the present invention and the conventional technique is mainly eliminated. The surface of the outer layer 1G is not flat, and the thickness of the solder resist underlayer required for the design is formed. With respect to the surface which first eliminates the unevenness of the outer layer 10, the method of the present invention coats the first solder resist layer 20 on the outer wiring layer 1 and fills the outer wiring layer opening, as shown in the first sink diagram. It should be noted that if the outer layer 10 has a through hole, the through hole may be filled with the epoxy resin for the via plug application while the first solder resist 2 is applied to the outer layer 10. After coating the first anti-glare underlayer 2Q on the outer wiring layer 1G, the first solder resist (four) may have an undulation phenomenon as in the prior art. However, the first solder resistive underlayer 20 can be removed by a brushing method such as a belt brush (four) t-age, a ceramic roller or a non-woven roller brush to eliminate unevenness. The requirement for the brush-pre-soldering underlayer 20 is mainly to expose a portion of the outer layer layer 1 that has been covered by the first anti-friction substrate 20, but the outer layer layer w is open or in the L-hole. The anti-corrosion underlayer 2〇 (or other similar material) shall be flush with the outer wiring layer as shown in Figure 2C. Thus, the first process target of the present invention which eliminates the uneven surface of the outer layer line can be achieved. Then, in order to enable the thickness of the solder resist layer of the present invention to meet the design requirements, as shown in FIG. 2D, another layer of solder resist is applied again (ie, the second solder resist layer 2 is already The first solder resist bottom layer 20 and a portion of the outer layer circuit layer 2 are flattened. Since the second solder resist 1288598 layer 22 is formed, it is formed by the first solder resist bottom layer 20 and the outer layer layer Provided on the flat surface provided, therefore, the scale can be _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Therefore, the choice of materials can be the same as the anti-fresh use of the oxy-resin (five) age paste, dry film green paint (s〇i age mask dry fUm), glass fiber-free epoxy resin, through-hole glue One of the epoxy resins and other similar materials used. Meanwhile, the method of forming the first solder resist underlayer 20 and the second solder resist underlayer 22 can also be selected to screen printing, roller coating (coating), spray printing, and the like. One of the other similar methods. In the red, the invention achieves the thickness of the solder resist underlayer by the two-stage method described above, that is, the surface of the outer layer μ unevenness is first removed, so that the thickness uniformity is formed. Solder the bottom layer. However, it should be particularly noted that 'in the embodiment of the present invention, forming the flat surface jointly provided by the first fresh-keeping underlayer 20 and the outer wiring layer 10 is merely an example, and is not limited to the first-pre-solder layer 2 or The outer layer layer 1 〇 is included in the features and spirits disclosed in the present invention as long as it is a two-stage method similar to the present invention on a carrier having an opening or a port. The scope of the present invention is limited by the preferred embodiments disclosed above, which are intended to provide a more detailed description of the present invention. To the contrary, it is intended to cover various modifications and equivalents within the scope of the invention as claimed. 1288598 [Simple Description of the Drawings] FIGS. 1A to 1B are schematic views showing the fabrication of a conventional chip package substrate. 2A to 2D are schematic views showing the fabrication of the chip package substrate of the present invention. [Main component symbol description] 10 outer circuit layer 12 solder resist bottom layer 20 first anti-frying bottom layer 22 second solder resist bottom layer