TWI284401B - Chip embedded packaging structure - Google Patents

Chip embedded packaging structure Download PDF

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TWI284401B
TWI284401B TW094126556A TW94126556A TWI284401B TW I284401 B TWI284401 B TW I284401B TW 094126556 A TW094126556 A TW 094126556A TW 94126556 A TW94126556 A TW 94126556A TW I284401 B TWI284401 B TW I284401B
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Taiwan
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layer
metal plate
chip
metal
package structure
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TW094126556A
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TW200707683A (en
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Shih-Ping Hsu
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Phoenix Prec Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

An embedded packaging structure includes a first metal board, a second metal board including at least a through cavity and disposed on a portion of the first metal board upper surface to form a heat dissipating substrate, at least a semiconductor chip and a chip type capacitor device embedded on the first metal board and embraced in the second metal board, a passive layer disposed on a portion of the second metal board upper surface, and at least a build-up circuit layer covering the semiconductor chip, the chip type capacitor device and the passive device layer on the heat dissipating substrate.

Description

1284401 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種埋入式電子封裝結構，尤指一種將主動及 被動元件接著於線路增層結構與散熱基板之間的埋入式電子封裝 結構。 又 【先前技術】 Φ 近年來，隨著資訊家電產品以及通訊產品的蓬勃發展，資訊 傳輸的容量大為擴增，訊號傳輸的速度要求也大幅提高，同時在 多功能手持式電子產品的驅動下，半導體製程發展無可避免朝高 谷篁、窄線寬的高密度化、高頻、低耗能、多功能整合方向演進。 因此在1C封裝技術方面，為配合高j/〇數、高散熱以及封裝 鲁CSP)、覆晶(FlipChip，Fc)等高階封裝型態需求持續升高。另外， 電路板的疊層(lamination)技術也就必須朝 输度的特靖，並為了更進—步能縮小電路板 求’而發展出表面接著有覆晶晶片以及如電阻器、電容器 器等之被動元件的多層電路板。 一 ^ 、然而’覆晶晶片與接著於多層電路板表面之被動元件仍需透 過多層電路板中之線路層紐連接，故往往因為連線距離太長， 而影響電性的表現。因此，多層電路板内部空間之運用以達到縮 1284401 :積以=τ散熱效率以及縮短與半導體晶㈣ 心料 抓^、磁能的封裝結構，皆是急需克服與發 展的方向。 ^ 【發明内容】 有鑑於此，本發明之主要目的在提供一種埋入主動及被動元 件之埋入式電子封裝結構，以改善_之缺點。 人為達上述目的，根據本發明之較佳實施例，本發明之結構係 包含有·—第一金屬板；一第二金屬板，設於該第一金屬板之上 表面々’該第二金屬㈣形成有至少—貫賴口，且該第二金屬板 與該第一金屬板係構成一散熱基板；至少一半導體晶片及至少一 曰曰片式電谷元件分別接置於該第一金屬板表面，而收納於該第二 金屬板所形成之該貫穿開口中；一被動元件層，設置於該第二金 屬板之部分上表面；以及至少一線路增層結構，設於該散熱基板 表面並覆蓋該半導體晶片、該晶片式電容元件與該被動元件層。 其中本發明結構中之該線路增層結構係包含有：一介電層;至少一 形成於介電層上之線路層;以及至少一穿過介電層以導接至線路層 之導電盲孔，以使該線路增層結構得以透過該導電盲孔電性連接 至該晶片式電容元件、半導體晶片及被動元件層;且該線路增層結 構之外緣表面形成有一防焊層，且該防焊層係形成有複數個開孔 以顯露出部分該線路層作為複數個電性連接墊。 1284401 由於本發明係將主動元件與被動元件設置於一散熱基板表 面，因此具有以下優點：（ι)可以提昇電子元件的散熱效果。 因佈線距離的縮短’可以提昇產品的性能。（3)因佈線空間應用 更佳，可以縮小產品的體積。（4)本發明之被動元件層形成一金 屬-絕緣層·金屬間隔結構之電容。 為了使貴審查委員能更近-步瞭解本發明之特徵及技術内 谷’凊參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與辅助說明用，並非用來對本發明加以限制者。 【實施方式】 ❿ 請參考第1圖’第i圖為本發明之較佳實施例中的埋入主動 及被動元件之埋人式電子封裝結構概圖。如第i騎示，此結 構之底部為-第-金屬板10，接著一第二金屬板12設於第一金屬 板10之上表面且與第-金屬板10構成一散熱基板14。其中第二 金屬板12係形成有至少-貫穿開口，例如：貫穿和16及17。 本發明之第一金屬板1〇與第二金屬板的由相同或不同之金屬 =所構成。例如働卜金屬板，崎此金屬板形成具有一預定 =之凹口，進而構成具有貫穿開口之第二金屬板12以及第一金 全屬Γ。或者疋直接於—金屬板表面形成—具有貫穿開口之另一 層’以構成第二金屬板12具有貫穿開口並形成於第一金屬板 ^表面之賴練14結構。❹卜，本發料 板1〇亦可為單—金屬層、多層之金屬金屬或金屬'絕緣材料^ 1284401 之堆疊結構，而且凡具有良好的導熱功能之金屬材料皆為本發明 應用涵蓋之範壽。 隨後將至少-半導體晶片18及—晶片式電容元件19以黏著 材（圖未不)分別接置於第一金屬板1〇而收納於第二金屬板I?所 形成之貫穿開口 16及Π中。其中，半導體晶片18之主動面係包 含有複數個電極墊181，而半導體晶片18可為主動元件，例如： 記憶體、發光元件或積體電路晶片等，而晶片式電容元件19亦類 似半導體晶#般，其主細包含有複數個電極墊191。本發明之半 導體晶片18係應用-黏著材(圖未示)固定於第一金屬板1〇之上表 面；同理，晶片式電容元件19亦應用-黏紐固定於第一金屬板 ίο之上表面，如此不但可使半導體晶片18與晶片式電容元件19 之向外電性連接的距離驗，進而提昇電性效能；而接著於金屬 板表面更能有效提4各電子元件的散熱效率，而錄㈣電性表 現01284401 IX. Description of the Invention: [Technical Field] The present invention relates to a buried electronic package structure, and more particularly to a buried electronic package in which active and passive components are connected between a line build-up structure and a heat sink substrate. structure. [Prior Art] Φ In recent years, with the vigorous development of information appliance products and communication products, the capacity of information transmission has been greatly expanded, and the speed of signal transmission has been greatly increased, and driven by multifunctional handheld electronic products. The development of semiconductor manufacturing process is inevitable to high-density, high-density, high-frequency, low-energy, and multi-functional integration. Therefore, in the 1C packaging technology, the demand for high-order package types such as high j/turns, high heat dissipation, and packaged CSP) and flip chip (FlipChip, Fc) continues to increase. In addition, the lamination technology of the circuit board must also be in the direction of the transmission, and in order to further reduce the circuit board, the surface is developed with flip chip and such as resistors, capacitors, etc. A multilayer circuit board of passive components. However, the flip chip and the passive components following the surface of the multilayer circuit board still need to be connected through the circuit layer in the multilayer circuit board, so the connection performance is often affected because the connection distance is too long. Therefore, the use of the internal space of the multi-layer circuit board to achieve the shrinkage of 1284401: the thermal efficiency of the product = τ and the shortening of the package structure of the semiconductor crystal (four), the magnetic material is urgently needed to overcome and develop. SUMMARY OF THE INVENTION In view of the above, it is a primary object of the present invention to provide a buried electronic package structure embedding active and passive components to improve the disadvantages. In order to achieve the above object, according to a preferred embodiment of the present invention, the structure of the present invention comprises a first metal plate, and a second metal plate disposed on the upper surface of the first metal plate. (4) forming at least a pass-through port, and the second metal plate and the first metal plate form a heat dissipation substrate; at least one semiconductor chip and at least one chip-type electric valley element are respectively disposed on the first metal plate a surface of the through hole formed in the second metal plate; a passive component layer disposed on a portion of the upper surface of the second metal plate; and at least one line build-up structure disposed on the surface of the heat dissipation substrate The semiconductor wafer, the chip capacitive element, and the passive element layer are covered. The circuit build-up structure in the structure of the present invention comprises: a dielectric layer; at least one circuit layer formed on the dielectric layer; and at least one conductive via hole passing through the dielectric layer to be connected to the circuit layer So that the line build-up structure is electrically connected to the chip capacitor element, the semiconductor chip and the passive component layer through the conductive via hole; and a solder resist layer is formed on the outer edge surface of the line build-up structure, and the anti-solder layer is formed The solder layer is formed with a plurality of openings to expose a portion of the circuit layer as a plurality of electrical connection pads. 1284401 Since the active component and the passive component are disposed on a surface of a heat dissipation substrate, the invention has the following advantages: (1) The heat dissipation effect of the electronic component can be improved. The performance of the product can be improved due to the shortened wiring distance. (3) Because the wiring space is better applied, the size of the product can be reduced. (4) The passive element layer of the present invention forms a capacitor of a metal-insulating layer and a metal spacer structure. In order to enable the reviewing committee to be closer to the features and techniques of the present invention, reference is made to the following detailed description of the invention and the accompanying drawings. The drawings are to be considered in all respects as illustrative and not restrictive. [Embodiment] Please refer to Fig. 1 'i' for an overview of a buried electronic package structure embedding active and passive components in a preferred embodiment of the present invention. The bottom of the structure is a -th metal plate 10, and a second metal plate 12 is disposed on the upper surface of the first metal plate 10 and forms a heat dissipation substrate 14 with the first metal plate 10. The second metal plate 12 is formed with at least a through opening such as a through and 16 and 17. The first metal plate 1 of the present invention is composed of the same or different metal = of the second metal plate. For example, a metal plate is formed, and the metal plate is formed to have a predetermined recess, thereby forming a second metal plate 12 having a through opening and a first metal. Alternatively, the crucible is formed directly on the surface of the metal sheet - another layer having a through opening to constitute a structure in which the second metal sheet 12 has a through opening and is formed on the surface of the first metal sheet. ❹布, the hairboard 1〇 can also be a single-metal layer, a multi-layer metal metal or a metal 'insulation material ^ 1284401 stack structure, and all metal materials with good thermal conductivity are covered by the application of the invention. life. Then, at least the semiconductor wafer 18 and the chip capacitor element 19 are respectively placed on the first metal plate 1 by the adhesive material (not shown), and are accommodated in the through opening 16 and the cymbal formed by the second metal plate I. . The active surface of the semiconductor wafer 18 includes a plurality of electrode pads 181, and the semiconductor wafer 18 can be an active device, such as a memory, a light emitting device, or an integrated circuit chip, and the chip capacitor 19 is similar to a semiconductor crystal. #般, its main thin contains a plurality of electrode pads 191. The semiconductor wafer 18 of the present invention is applied to an upper surface of the first metal plate 1 by an adhesive material (not shown). Similarly, the chip capacitive element 19 is also applied to the first metal plate ίο. The surface can not only improve the electrical performance of the semiconductor chip 18 and the external capacitive connection of the chip capacitor element 19, but also improve the electrical performance; and then effectively improve the heat dissipation efficiency of each electronic component on the surface of the metal plate. (4) Electrical performance 0

然後於第二金屬板12之部分上表面設置一被動元件層20。被 動兀件層20可為一具有高介電常數之介電材料層，且此介電材料 層表面設置有至少一由一金屬層所構成之線路層22，其中線路層 22、介電材料層及第二金屬板12係形成一金屬'絕緣層_金屬 (Metal_Insulator»Metal，MIM)間隔結構之電容。接著形成一線路增 層結構3及一線路增層結構4於散熱基板14表面並覆蓋於晶片式 電谷元件19、半導體晶片is與被動元件層2〇上方。其中，線路 1284401 增層結構3,4係分別包含有介電層31，4卜形成於介電層3i，4i上 之線路層32,42，以及穿過介電層31，41 1乂導接至線路層兑犯之 導電盲孔33,43，以使線路增層結構3,4得以透過導電盲孔33,43 1：性連接至半導體晶片18及晶片型電容元件19各主動面上之複 數個電極塾m，m、被動元件層2G上之線路層22與第二金屬板 12表面’用轉通半導體晶片18、晶片型電容元件㊇及被動元 件層20上之線路層22,並可視實際產品設計之需求而選擇性的電 • 性連接散熱基板14以製作成具有接地的功能。，且線路增層結構 4之外緣表面形成有-防焊層5，防焊層5係形成有複數個開孔34 以顯露出部分祕層42作域脑電錢缝36。如此即完成本 發明之埋入主動及被動元件之埋入式電子封裝結構。 值得注意的是，完成本發明之較佳實施例之後，如第2圖所 不，本發明更可結合覆晶封裝技術，而於線路增層結構4外緣表 面形成有-防焊層5，且防焊層5係形成有複數個開孔％以顯露 # ⑽分線路層42作為電性連接塾36，並接置有複數個錫球6與至 少-覆晶元件7，而覆晶元件7可例如記憶體、發光元件或積體電 路晶片等；且覆晶元件7係以複數個焊料凸塊71電性連接部分之 電性連接墊36，使覆晶元件7與封裝結構内部之半導體晶片18、 晶片型電容元件19與被動元件層2〇作電性導接。其中覆晶元件7 更可藉由線路增賴構3,4轉散絲板M雜連接以達成接地 功能。 9 1284401 另外值得注意的是，如第3圖所示，本發明亦可於電性連接 墊36上接置至少一被動元件8，其中被動元件8係可例如為電容、 電感、電阻等；而被動元件8係利用複數個焊料凸塊81電性連接 部分之電性連接塾36，使被動元件8與封裝結構内部之半導體晶 片18、晶片型電容元件19與被動元件層2〇作電性導接。 此外，本發明之散熱基板14未與線路增層結構相接合之表面 φ 另可β又置有至少一散熱結構(圖未式），例如粗糙表面、凹槽、刻痕 或是鰭狀之立體散齡構，_增加散熱基板14之散熱面積。 s上述，本發明埋入主動及被動元件之埋入式電子封裝結 構相較習知技藝至少包括以下之優點： !·散熱基板可以提昇埋入電子元件的散熱效果。 2·主動與被動元件係連接到散熱基板進行接地，故可大幅提升電 性表現與減少雜訊。 » 3.整合絲树及被航件紅基油且被航件層形成一金 屬、、、邑緣層-金屬間隔結構之電容。縮短佈線的距離，可有效提 昇產印雜# ’並制高魏及高性能的目的並使佈線空間應 用更佳，可以縮小產品的體積。 4·埋入之絲树及鶴播與_顧結魏面之覆晶元件 及被動元件可以達到模組化與多功能化的目的。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 1284401 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為本發明之較佳實施例中的埋入主動及被動元件之埋入式 電子封裝結構剖視圖。 第2圖為本發明之第1圖上設置覆晶元件之結構剖視圖。 第3圖為本發明之第2圖上設置被動元件之結構剖視圖。 丨 【主要元件符號說明】 3 線路增層結構 4 線路增層結構 5 防焊層 6 錫球 7 覆晶元件 8 被動元件 10 第一金屬板 12 第二金屬板 14 散熱基板 16 貫穿開口 17 貫穿開口 18 半導體晶片 19 晶片式電容元件 20 被動元件層 22 線路層 31 介電層 32 線路層 33 導電盲孔 34 開口 36 電性連接墊 41 介電層 42 線路層 43 導電盲孔 71 焊料凸塊 81 焊料凸塊 181 電極墊 191 電極墊 11A passive component layer 20 is then disposed on a portion of the upper surface of the second metal plate 12. The passive element layer 20 can be a dielectric material layer having a high dielectric constant, and the surface of the dielectric material layer is provided with at least one circuit layer 22 composed of a metal layer, wherein the circuit layer 22 and the dielectric material layer And the second metal plate 12 forms a capacitor of a metal-insulator-metal (MIM) spacer structure. Next, a line build-up structure 3 and a line build-up structure 4 are formed on the surface of the heat dissipation substrate 14 and over the wafer-type electric valley element 19, the semiconductor wafer is and the passive element layer 2A. Wherein, the line 1284401 build-up structure 3, 4 includes dielectric layers 31, 4 formed on the dielectric layers 3i, 4i on the circuit layers 32, 42 and through the dielectric layer 31, 41 1 乂Conductive blind holes 33, 43 to the circuit layer constituting so that the line build-up structures 3, 4 are transparently connected to the plurality of active faces of the semiconductor wafer 18 and the chip-type capacitive element 19 through the conductive blind holes 33, 43 The electrodes 塾m, m, the circuit layer 22 on the passive component layer 2G and the surface of the second metal plate 12 are turned on by the semiconductor wafer 18, the chip-type capacitive component VIII, and the circuit layer 22 on the passive component layer 20, and can be visually observed. The heat-dissipating substrate 14 is selectively electrically connected to the needs of the product design to be made to have a grounding function. And the outer edge surface of the line build-up structure 4 is formed with a solder resist layer 5, and the solder resist layer 5 is formed with a plurality of openings 34 to expose a portion of the secret layer 42 as a domain EEG. Thus, the buried electronic package structure embedding active and passive components of the present invention is completed. It should be noted that, after the preferred embodiment of the present invention is completed, as shown in FIG. 2, the present invention can be combined with a flip chip packaging technology, and a solder resist layer 5 is formed on the outer edge surface of the line build-up structure 4, And the solder resist layer 5 is formed with a plurality of open holes % to expose the # (10) sub-line layer 42 as an electrical connection port 36, and is connected with a plurality of solder balls 6 and at least a flip chip element 7, and the flip chip element 7 For example, the memory device, the light-emitting element or the integrated circuit chip, etc.; and the flip-chip element 7 is electrically connected to the electrical connection pad 36 of the plurality of solder bumps 71 to make the flip-chip element 7 and the semiconductor wafer inside the package structure. 18. The chip type capacitive element 19 is electrically connected to the passive element layer 2. The flip-chip element 7 can be connected to the 3, 4-turn bulk board M to achieve the grounding function. 9 1284401 It is also noted that, as shown in FIG. 3, the present invention can also connect at least one passive component 8 to the electrical connection pad 36, wherein the passive component 8 can be, for example, a capacitor, an inductor, a resistor, etc.; The passive component 8 electrically connects the electrical connection portion 36 of the plurality of solder bumps 81 to electrically connect the passive component 8 to the semiconductor wafer 18, the chip-type capacitive component 19 and the passive component layer 2 inside the package structure. Pick up. In addition, the surface φ of the heat dissipation substrate 14 of the present invention that is not bonded to the line build-up structure may be further provided with at least one heat dissipation structure (not shown), such as a rough surface, a groove, a nick, or a fin-shaped solid. The scatter structure, _ increases the heat dissipation area of the heat dissipation substrate 14. As described above, the buried electronic package structure embedding active and passive components of the present invention includes at least the following advantages over the prior art: • The heat dissipation substrate can enhance the heat dissipation effect of the embedded electronic component. 2. The active and passive components are connected to the heat sink substrate for grounding, which can greatly improve the electrical performance and reduce noise. » 3. Integrate the silk tree and the red base oil of the aircraft and form a metal, and 邑 edge layer-metal spacer structure capacitor by the carrier layer. By shortening the wiring distance, it is possible to effectively increase the production and printing of the #' and to achieve high-performance and high-performance purposes, and to make the wiring space application better, which can reduce the volume of the product. 4. Buried silk tree and crane sowing and _ Gu Jie Wei surface of the flip chip and passive components can achieve the purpose of modularization and multi-functionality. The above is only the preferred embodiment of the present invention, and all changes and modifications made in accordance with the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a buried electronic package structure in which active and passive components are embedded in a preferred embodiment of the present invention. Fig. 2 is a cross-sectional view showing the structure of a flip chip device provided in Fig. 1 of the present invention. Fig. 3 is a cross-sectional view showing the structure of a passive element provided in Fig. 2 of the present invention.丨【Main component symbol description】 3 Line build-up structure 4 Line build-up structure 5 Solder mask 6 Tin ball 7 Flip-chip component 8 Passive component 10 First metal plate 12 Second metal plate 14 Heat-dissipating substrate 16 Through-opening 17 Through-opening 18 Semiconductor wafer 19 Chip capacitive element 20 Passive element layer 22 Line layer 31 Dielectric layer 32 Line layer 33 Conductive blind hole 34 Opening 36 Electrical connection pad 41 Dielectric layer 42 Line layer 43 Conductive blind hole 71 Solder bump 81 Solder Bump 181 electrode pad 191 electrode pad 11

Claims (1)

1284401 十、申請專利範園： h 一種埋入式電子封裝結構，包含有·· 一第一金屬板； -第二金屬板，設於鄉-金屬板之上表面，該第 =一貫穿開口，且該第二金屬與該第-金屬板係構成 鲁—s少-半導體晶片及至少一晶片式電容元件分別接置於該第 一金屬板表面，而收納於該第二金屬板所形成之該貫穿開口中； -被動元件層，設置於該第二金屬板之部分上表面；以， 及 至少-線路增層結構，設於該散熱基板表面並覆蓋該半導體 晶片、該晶片式電容元件與該被動元件層。 2·如申請專利範圍第i項之埋入式電子封裝結構，其中該半導體 ® μ#與該晶#式電谷it件另分別包含有複數個電極墊形成於一 主動面。 3.如申請專利範圍第i項之埋入式電子封裝結構，其中該半導體 晶片係為一主動元件，且該主動元件包含記憶體、發光元件及 積體電路晶片之其中一者。 4·如申請專利範圍第1項之埋入式電子封裝結構，其中該線路增 12 1284401 層結構係包含有： 一第一介電層； 至少一形成於該第一介電層上之第一線路層;以及 至少一穿過該第一介電層以導接至該第一線路層之導電盲 孔，以使該線路增層結構得以透過該導電盲孔電性連接至該晶片 式電容元件、半導體晶片及被動元件層。 5·如申請專利範圍第4項之埋入式電子封裝結構，另包含有一防 焊層，且該防焊層係形成於該線路增層結構之外緣表面，並形 成有複數個開似麟丨部分該帛-線路層作為複數個電性連 接墊。 6.如申請專概_ 4項之埋人式電子封裝結構，其中該線路增 層結構係可電性連接該散熱基板以達成接地功能。 S1284401 X. Patent application garden: h A buried electronic package structure comprising a first metal plate; a second metal plate disposed on the upper surface of the town-metal plate, the first through-opening, And the second metal and the first metal plate form a Lu-s-semiconductor chip and the at least one chip-type capacitor element is respectively disposed on the surface of the first metal plate, and is formed by the second metal plate a through-opening; a passive component layer disposed on a portion of the upper surface of the second metal plate; and at least a line build-up structure disposed on the surface of the heat dissipation substrate and covering the semiconductor wafer, the chip capacitive element and the Passive component layer. 2. The buried electronic package structure of claim i, wherein the semiconductor ® μ# and the crystal-type electric cell are respectively formed with a plurality of electrode pads formed on an active surface. 3. The embedded electronic package structure of claim i, wherein the semiconductor wafer is an active component, and the active component comprises one of a memory, a light emitting component, and an integrated circuit chip. 4. The buried electronic package structure of claim 1, wherein the circuit further comprises: a first dielectric layer; at least one first formed on the first dielectric layer a circuit layer; and at least one conductive via hole passing through the first dielectric layer to be electrically connected to the first circuit layer, so that the circuit build-up structure is electrically connected to the chip capacitive element through the conductive via hole , semiconductor wafer and passive component layers. 5. The buried electronic package structure of claim 4, further comprising a solder mask layer, wherein the solder resist layer is formed on the outer edge surface of the line build-up structure, and a plurality of open-like layers are formed The 丨 part of the 帛-circuit layer acts as a plurality of electrical connection pads. 6. The application of the _ 4 embedded electronic packaging structure, wherein the wiring enhancement structure is electrically connected to the heat dissipation substrate to achieve a grounding function. S 7. 如申請專娜圍第5項之埋人式f子封裝結構，另包含有至* -覆晶树(Flipaiip，FC)，設雜路結歡/ 面，並電性連接部分之該等電性連接墊。 另包含有至少 ，並電性連接 8.如申請專利細第5項之埋人式電子封裝結構， -被動元件，設置於該魏結構之外緣表面 部分之該等電性連接墊。 13 1284401 9. 如申請專利範圍第i項之埋入式電子封裝結構，其中該被動元 件層係為一高介電常數之介電材料層且該介電材料層表面設置 有至少一由一金屬層所構成之線路層。 10. 如申請專利範㈣9項之埋人式電子封裝結構，其中該金屬 層、該介電材料層及該第二金屬板係形成一金屬_絕緣層_金屬 (Metal_Insulator-Metal，MIM)間隔結構之電容。 11·如申請專利範圍第1項之埋入式電子封裝結構，其中該散熱基 板未與該線路增層結構相接合之表面另設置有至少一散熱蜂 構。 一" 12·如申請專利範圍第1項之埋入式電子封裝結構，其中該半導體 晶片及該晶片式電容元件係可藉由線路增層結構電性連接該散 熱基板以達成接地功能。 十一、圖式： 147. If you apply for the buried-f-sub-package structure of the fifth item of the Nina, and include the *--Flipaiip (FC), the miscellaneous road knots/faces, and the electrical connection parts. Electrical connection pad. In addition, at least, and electrically connected. 8. The buried electronic package structure of the fifth application example, the passive component, and the electrical connection pads disposed on the outer surface portion of the Wei structure. 13 1284401 9. The embedded electronic package structure of claim i, wherein the passive component layer is a high dielectric constant dielectric material layer and the dielectric material layer surface is provided with at least one metal The layer of circuitry formed by the layers. 10. The buried electronic packaging structure of claim 9 (4), wherein the metal layer, the dielectric material layer and the second metal plate form a metal_insulator-Metal (MIM) spacer structure Capacitance. 11. The buried electronic package structure of claim 1, wherein the surface of the heat dissipation substrate that is not bonded to the line build-up structure is further provided with at least one heat dissipation structure. The embedded electronic package structure of claim 1, wherein the semiconductor wafer and the chip capacitor element are electrically connected to the heat dissipation substrate by a line build-up structure to achieve a grounding function. XI. Schema: 14
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