CN211208440U - Three-dimensional packaging structure integrating chip and antenna - Google Patents
Three-dimensional packaging structure integrating chip and antenna Download PDFInfo
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- CN211208440U CN211208440U CN201922427259.5U CN201922427259U CN211208440U CN 211208440 U CN211208440 U CN 211208440U CN 201922427259 U CN201922427259 U CN 201922427259U CN 211208440 U CN211208440 U CN 211208440U
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Abstract
A chip and antenna integrated three-dimensional packaging structure comprises at least one chip, a glass substrate and a chip, wherein the chip is provided with a first surface and a second surface, the first surface is provided with a functional area and an electrode, the glass substrate is provided with at least one through groove and at least one through hole, and metal conductive materials are respectively deposited on the inner walls of the through groove and the through hole; the chip and a heat dissipation metal block are embedded in the through groove through the bonding structure, and the heat dissipation metal block is positioned on the second surface of the chip; the bonding structure is filled into the through hole, a first wiring surface is formed on the first surface of the chip and one surface of the glass substrate, and a second wiring surface is formed on the surface of the heat dissipation metal block and the other surface of the glass substrate; the first wiring surface is provided with at least one metal circuit to be electrically connected with the electrode of the chip; at least one grounding layer and at least one antenna layer are arranged on the second wiring surface, and the antenna layer is electrically connected with the metal conductive material on the through hole. The utility model discloses compact structure, encapsulation thickness is thin, and transmission signal circuit is short, the loss is low, and electrical property is high.
Description
Technical Field
The utility model relates to a semiconductor package field especially indicates a three-dimensional packaging structure of chip and antenna integration.
Background
With the development of high-frequency electronic products toward high speed and miniaturization, the industry brings vertical stack packaging schemes for mainstream applications such as portable devices, entertainment, and automobiles.
The traditional antenna is usually assembled with a millimeter wave chip on a PCB in a two-dimensional plane mode, so that the packaging volume is large, the area is large, the integration is poor, and the loss is large under millimeter wave transmission.
Therefore, in order to reduce the circuit board area occupied by the antenna, to arrange the package structure reasonably, and to improve the whole antenna packaging efficiency and antenna performance, a high-performance, compact, and fully integrated antenna packaging scheme is required.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a main aim at overcomes the above-mentioned defect among the prior art, provides a chip and antenna integrated three-dimensional packaging structure that compact structure, transmission signal circuit are short, the loss is low, the area is little.
The utility model adopts the following technical scheme:
the utility model provides a three-dimensional packaging structure of chip and antenna integration, includes at least a chip, and the chip is equipped with first surface and second surface, and this first surface is equipped with functional area and electrode, its characterized in that: the glass substrate is provided with at least one through groove and at least one through hole, and metal conductive materials are respectively deposited on the inner walls of the through groove and the through hole; the chip and a heat dissipation metal block are embedded in the through groove through the bonding structure, and the heat dissipation metal block is positioned on the second surface of the chip; the bonding structure is filled into the through hole, a first wiring surface is formed on the first surface of the chip and one surface of the glass substrate, and a second wiring surface is formed on the surface of the heat dissipation metal block and the other surface of the glass substrate; the first wiring surface is provided with at least one metal circuit to be electrically connected with the electrode of the chip; at least one grounding layer and at least one antenna layer are arranged on the second wiring surface, and the antenna layer is electrically connected with the metal conductive material on the through hole.
Preferably, an insulating layer is further disposed between the ground layer and the antenna layer, and the insulating layer is made of polymer glue, glass, ceramic or silicon.
Preferably, the ground layer is located on the surface of the first wiring surface and has an opening, and the antenna layer extends into the opening to be electrically connected with the metal conductive material at the through hole.
Preferably, a passivation layer is further included and is disposed on the surface of the antenna layer and the exposed surface of the insulating layer.
Preferably, the metal line includes a metal wiring layer and a metal bump; the metal wiring layer is positioned on the surface of the first wiring surface and is electrically connected with the electrode of the chip; the metal bump is electrically connected with the external connection area of the metal wiring layer.
Preferably, the chip is a millimeter wave chip.
From the above description of the present invention, compared with the prior art, the present invention has the following advantages:
1. the utility model discloses an encapsulation structure, with the metal conducting material electric connection of antenna layer and through-hole department, and the logical groove at through-hole and chip place is located same one deck, compact structure, and encapsulation thickness is thin, and transmission signal circuit is short, the loss is low, electrical property is high.
2. The utility model discloses an encapsulation structure, shared circuit board area is little, and antenna encapsulation structure integration performance is high.
3. The utility model discloses an encapsulation structure only adopts one deck glass substrate, need not the glass bonding, simple process, simple structure, and the dielectric property of glass base plate is good, the dielectric constant is low, and is with low costs.
4. The utility model discloses a structure is done through-hole and logical groove through the method of laser induction sculpture on glass substrate, leads to the groove and is used for placing the chip, and the through-hole is used for perpendicular interconnection, and processing technology is simple, low cost.
5. The utility model discloses a structure increases heat dissipation metal block at the chip back, improves packaging structure's heat dispersion.
6. The utility model discloses a structure, the dielectric layer among its antenna structure adopts single medium promptly for the insulating layer, does benefit to the stability of antenna performance.
Drawings
Fig. 1 is a cross-sectional view of a structure according to an embodiment of the present invention;
FIG. 2 is a schematic view of through holes and through grooves formed in a glass substrate;
FIG. 3 is a schematic diagram of depositing a metal conductive material on the inner walls of the through holes and the through grooves;
FIG. 4 is a schematic view of a chip and a heat-dissipating metal block embedded in a through-groove by a bonding structure;
FIG. 5 is a schematic diagram of a metal line formed on a first wiring surface;
FIG. 6 is a schematic diagram of an antenna layer and a ground layer formed on the second wiring layer;
FIG. 7 is a schematic view illustrating the fabrication of a metal bump;
fig. 8 is a structural diagram of a second embodiment of the present invention;
wherein:
10. chip, 11, electrode, 20, glass substrate, 21, through groove, 22, through hole, 23, metal conducting material, 30, bonding structure, 31, first wiring surface, 32, second wiring surface, 40, heat dissipation metal block, 50, metal wiring layer, 51, metal bump, 52, ground layer, 53, antenna layer, 54, insulating layer, 55, passivation layer.
The present invention will be described in further detail with reference to the following drawings and specific examples.
Detailed Description
The present invention will be further described with reference to the following detailed description.
Example one
Referring to fig. 1, a three-dimensional package structure with integrated chip and antenna includes at least a chip 10 and a glass substrate 20. The chip 10 is provided with a first surface provided with the functional region and the electrode 11, and a second surface opposite to the first surface. The chip 10 of the present invention is mainly a millimeter wave chip, which includes gallium arsenide (GaAs), InP (indium phosphide) millimeter wave chips, gallium nitride (GaN) millimeter wave chips, etc.
At least one through groove 21 and at least one through hole 22 are arranged on the glass substrate 20, a distance is arranged between the through groove 21 and the through hole 22, the number of the through grooves 21 can be one, two or more, and the number of the through holes 22 can be one, two, three or more.
The inner walls of the through-groove 21 and the through-hole 22 are deposited with the metal conductive material 23, respectively, and the metal conductive material 23 of the inner wall of the through-hole 22 may extend to the first surface and the second surface of the glass substrate 20 along the top end and the bottom end of the through-hole 22. The metal conductive material 23 of the inner wall of the through-groove 21 may or may not extend along the top and bottom ends of the inner wall of the through-groove 21 to the first and second surfaces of the glass substrate 20, which also serves as an electrical connection for metal wiring.
The chip 10 and a heat dissipation metal block 40 are embedded in the through groove 21 through the bonding structure 30, the first surface of the chip 10 is flush with or not flush with the first surface of the glass substrate 20, and the heat dissipation metal block 40 is located on the second surface of the chip 10. The surface of the heat dissipation metal block 40 may be flush with or not flush with the second surface of the glass substrate 20, and the cross-sectional area thereof may be larger than, smaller than or equal to the second surface area of the chip 10, preferably equal to the second surface area, and the heat dissipation metal block 40 may be made of metal with good heat conductivity, such as silver, copper, aluminum, and the like. The number of chips 10 embedded in one through groove 21 may be one, two or more, and the number of heat dissipation metal blocks 40 may also be two or more, preferably one.
The bonding structure 30 is further filled in the through hole 22, and extends to the first surface of the chip 10 and the first surface of the glass substrate 20 to form a first wiring surface 31, and extends to the surface of the heat-dissipating metal block 40 and the second surface of the glass substrate 20 to form a second wiring surface 32. The bonding structure 30 of the present invention can be a bonding material with heat dissipation effect, such as polymer glue or plastic package material.
The first wiring surface 31 is provided with at least one metal line to electrically connect with the electrode 11 of the chip 10, and the first wiring surface 31 is provided with an opening at the electrode 11 of the chip 10. The metal lines include a metal wiring layer 50 and metal bumps 51, which may be made of one or more metals such as copper, aluminum, nickel, gold, silver, and titanium. The metal wiring layer 50 is located on the surface of the first wiring surface 31 and extends into the opening to be electrically connected to the electrode 11 of the chip 10. The metal wiring layer 50 is further provided with an external connection region, and the metal bump 51 is electrically connected with the external connection region of the metal wiring layer 50. The metal bump 51 may be ni-pd-au, ni-au, ti-cu pad, or BGA solder ball.
Further, in order to protect the metal wiring layer 50 on the first wiring surface 31, a passivation layer 55 may be further provided on the surface of the metal wiring layer 50 and the exposed surface of the first wiring surface 31. The passivation layer 55 may be a polymer paste and may be provided with openings in the interconnect region of the metal wiring layer 50.
The second wiring surface 32 is provided with at least one ground layer 52 and at least one antenna layer 53. The antenna layer 53 is electrically connected to the metal conductive material 23 on the via 22. An insulating layer 54 is further disposed between the ground layer 52 and the antenna layer 53, the insulating layer 54 may be one or more of polymer adhesive, glass, ceramic or silicon, the thickness of the insulating layer is 10-1000um, preferably 20um or 400um, different thicknesses may be used for different materials (for example, some polymer adhesives may only be tens of um, if glass materials are used for bonding, several hundreds um. of conductive metals may be used for the ground layer 52 and the antenna layer 53).
Specifically, the ground layer 52 is located on the surface of the first wiring surface 31 and has an opening at the position of the metal conductive material 23 at the through hole 22, and the insulating layer 54 is located on the surface of the ground layer 52 and extends into the opening of the first wiring surface 31. An opening is further formed at the opening of the ground layer 52 of the insulating layer 54 and the second wiring surface 32, and the antenna layer 53 is located on the surface of the insulating layer 54 and extends into the opening of the insulating layer 54 and the second wiring surface 32 to electrically connect with the metal conductive material 23 at the via 22.
Furthermore, the present invention further provides a passivation layer 55 on the side of the second wiring surface 32, which is located on the surface of the antenna layer 53 and the exposed surface of the insulating layer 54 for protecting the antenna layer 53, wherein the passivation layer 55 may be the same as or different from the passivation layer 55 on the side of the first wiring surface 31. In the present invention, the number of the ground layer 52 may be one layer or two layers or more, preferably one layer, and the number of the antenna layer 53 may be one layer or two layers or more, preferably one layer.
The utility model discloses in, metal conducting material 23, metal wiring layer 50, heat dissipation metal block 60, antenna layer 53, ground plane 52 can adopt same kind of conductive metal material, for example copper, and metal bump can adopt another kind of conductive material, for example tin.
Referring to fig. 2-7, the structure of the present invention, its packaging method, includes the following steps:
1) through grooves 21 and through holes 22 are formed in the glass substrate 20, the size of the through grooves 21 may be determined according to the number and size of the chips 10, and the inner diameter of the through holes 22 may be smaller than the inner diameter of the through grooves 21. The step can be realized by laser-induced etching and the like, and the cost is low.
2) The metal conductive material 23 is deposited on the inner walls of the through holes 22 and the through grooves 21, respectively, and the metal conductive material 23 on the inner walls of the through grooves 21 may extend to the first surface and the second surface of the glass substrate 20 by a small distance.
3) Stacking the chip 10 and the heat dissipation metal block 40 in the through groove 21 by pick-and-place so that the first surface of the chip 10 is flush with the first surface of the glass substrate 20; the heat dissipation metal block 40 is attached to the second surface of the chip 10, and the surface of the heat dissipation metal block is flush with the second surface of the glass substrate 20.
4) The bonding structure 30 is prepared by plastic packaging, film pressing or glue brushing to fix the chip 10 and the heat dissipation metal block 40, the bonding structure 30 also extends into the through hole 22, a first wiring surface 31 is formed on the first surface of the chip 10 and the first surface of the glass substrate 20, and a second wiring surface 32 is formed on the surface of the heat dissipation metal block 40 and the second surface of the glass substrate 20.
5) At least one metal line is formed on the first wiring surface 31 and electrically connected to the electrode 11 of the chip 10. Specifically, a hole is opened at the position of the electrode 11 on the first wiring surface 31, and then a metal wiring is formed, where the metal wiring includes a metal wiring layer 50 and a metal bump 51. A passivation layer 55 may be further formed on the surface of the metal wiring and the exposed surface of the first wiring surface 31.
6) At least one ground layer 52 and at least one antenna layer 53 are formed on the second wiring surface 32, and the antenna layer 53 is electrically connected to the metal conductive material 23 on the via hole 22. Specifically, the method includes forming a ground layer 52 on the surface of the second wiring surface 32, forming an insulating layer 54 on the surface of the ground layer 52, and forming an antenna layer 53 on the surface of the insulating layer 54.
Step 6), a passivation layer 55 may be formed on the surface of the antenna layer 53 and the exposed surface of the insulating layer 54. The hole opening in the steps 5) and 6) can be realized by adopting processes such as exposure or laser drilling treatment.
Example two
Referring to fig. 8, a three-dimensional package structure integrating a chip and an antenna has the same main features as the first embodiment except that no passivation layer is disposed on the surface of the antenna layer 53 and the exposed surface of the insulating layer 54. The corresponding manufacturing method does not include the step of forming a passivation layer on the surface of the antenna layer 53 and the exposed surface of the insulating layer 54.
The above-mentioned be the utility model discloses a concrete implementation way, nevertheless the utility model discloses a design concept is not limited to this, and the ordinary use of this design is right the utility model discloses carry out immaterial change, all should belong to the act of infringement the protection scope of the utility model.
Claims (6)
1. The utility model provides a three-dimensional packaging structure of chip and antenna integration, includes at least a chip, and the chip is equipped with first surface and second surface, and this first surface is equipped with functional area and electrode, its characterized in that: the glass substrate is provided with at least one through groove and at least one through hole, and metal conductive materials are respectively deposited on the inner walls of the through groove and the through hole; the chip and a heat dissipation metal block are embedded in the through groove through the bonding structure, and the heat dissipation metal block is positioned on the second surface of the chip; the bonding structure is filled into the through hole, a first wiring surface is formed on the first surface of the chip and one surface of the glass substrate, and a second wiring surface is formed on the surface of the heat dissipation metal block and the other surface of the glass substrate; the first wiring surface is provided with at least one metal circuit to be electrically connected with the electrode of the chip; at least one grounding layer and at least one antenna layer are arranged on the second wiring surface, and the antenna layer is electrically connected with the metal conductive material on the through hole.
2. The integrated three-dimensional chip and antenna package structure of claim 1, wherein: an insulating layer is arranged between the grounding layer and the antenna layer and is made of polymer glue, glass, ceramic or silicon.
3. The integrated three-dimensional chip and antenna package structure of claim 1, wherein: the grounding layer is positioned on the surface of the first wiring surface and is provided with an opening, and the antenna layer extends into the opening to be electrically connected with the metal conductive material at the through hole.
4. The chip and antenna integrated three-dimensional package structure of claim 2, wherein: and the passivation layer is positioned on the surface of the antenna layer and the exposed surface of the insulating layer.
5. The integrated three-dimensional chip and antenna package structure of claim 1, wherein: the metal circuit comprises a metal wiring layer and a metal bump; the metal wiring layer is positioned on the surface of the first wiring surface and is electrically connected with the electrode of the chip; the metal bump is electrically connected with the external connection area of the metal wiring layer.
6. The integrated three-dimensional chip and antenna package structure of claim 1, wherein: the chip is a millimeter wave chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922427259.5U CN211208440U (en) | 2019-12-30 | 2019-12-30 | Three-dimensional packaging structure integrating chip and antenna |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922427259.5U CN211208440U (en) | 2019-12-30 | 2019-12-30 | Three-dimensional packaging structure integrating chip and antenna |
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| Publication Number | Publication Date |
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| CN211208440U true CN211208440U (en) | 2020-08-07 |
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| CN201922427259.5U Active CN211208440U (en) | 2019-12-30 | 2019-12-30 | Three-dimensional packaging structure integrating chip and antenna |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024114183A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Heterogeneous package substrate and module |
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- 2019-12-30 CN CN201922427259.5U patent/CN211208440U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024114183A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Heterogeneous package substrate and module |
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