1283447 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種覆晶薄膜封裝構造，特別係有關 於一種散熱型覆晶薄膜封裝構造。 【先前技術】 現今之電子產業中，會將高效能之晶片覆晶設置於可 撓性基板上，達到覆晶薄膜（Chip on Film)之封裝型態，能 運用於體積輕薄短小之電子產品中，例如驅動1C晶片， 但在產品之運作過程中，晶片會產生熱能，不易逸散，且 在封裝與使用過程，因封裝件之整體結構強度不足，隨著 該可撓性基板之彎折而造成晶片之損傷，導致產品之使用 哥命縮短。 請參閱第1圖，一種習知覆晶薄膜封裝構造1〇〇主要 包含有一可撓性基板110、一覆晶晶片12〇以及一密封膠 130 ’該覆晶晶片12〇係具有一主動面ι21以及一背面 122 ’複數個凸塊123形成於該覆晶晶片12〇之該主動面 121 ’另’該可撓性基板11〇在其上表面m係形成有一 引線層112。當覆晶接合後，該些凸塊123係接合至該引 線層112，該密封膠130係形成於該覆晶晶片12〇與該可 撓性基板110之間。 在上述覆晶薄膜封裝構造100中，該覆晶晶片12〇於 運作時會產生熱能’而熱能係僅由該覆晶晶片12〇之一背’ 面122逸散，因此無法達到最佳散熱效果。此外，該可撓 性基板11不足以支撐在其上方之該覆晶晶片12〇,而在封 1283447 裝與使用過程時，會造成該覆晶晶片120之碰撞損傷。 【發明内容】 本發明之主要目的在於提供一種散熱型覆晶薄膜封 裝構造，一散熱片係設置於一可撓性基板之一下表面，一 覆晶晶片係對應該散熱片並設置於該可撓性基板之一上 表面’以藉由該散熱片支撲已設於該可挽性基板上之該覆 晶晶片，並可利用該散熱片散逸該覆晶晶片於運作時所產 生之熱能。 本發明之次一目的係在於提供一種散熱型覆晶薄膜 封裝構造，一可撓性基板之一下表面係設置有一散熱片， 一覆晶晶片係對應該散熱片並設置於該可撓性基板之一 上表面’且該可撓性基板係包含有至少一連接至該散熱片 之導熱通孔（thermal hole)，以藉由該導熱通孔傳導復晶晶 片運作時所產生之熱能至該散熱片，加速整艘之散熱速 率〇 依據本發明，一種散熱型覆晶薄膜封裝構造係主要包 含一可撓性基板、一散熱片、一覆晶晶片以及一密封膠， 該可撓性基板係具有一上表面以及一下表面並包含有一 在該上表面之引線層，該散熱片係設置於該可撓性基板之 該下表面，該覆晶晶片係對應於該散熱片並設置於該可撓 性基板之該上表面，以電性連接至該引線層，該密封膠係 形成於該覆晶晶片與該可撓性基板之間。 【實施方式】 在本發明之第一具體實施例中，請參閱第2及3圓， 1283447 該散熱型覆晶薄膜封裝構造200係主要包含有一可撓性基 板210、一第一散熱片220、一覆晶晶片230以及一密封 膠240，該可撓性基板210係具有一上表面211以及一下 表面212,該可撓性基板210係包含一形成於該上表面211 之引線層213，該引線層213係包含複數個覆晶接墊、複 數個引線以及複數個往外延伸之外接墊（圖未繪出）。在本 實施例中，藉由一黏膠層221之結合，該第一散熱片220 係以黏貼方式設置於該可撓性基板21〇之該下表面212。 鲁 該覆晶晶片23〇係對應於該第一散熱片220且設置於該可 撓性基板210之該上表面211，該覆晶晶片230係具有一 主動面231以及一背面232並包含複數個形成於該主動面 231之凸塊233,該些凸塊233係電性連接該覆晶晶片23〇 與遠可挽性基板210之該引線層213，其中，該些凸塊233 係可為金凸塊，可利用超音波鍵合、熱壓合或異方性導電 方式達到該些凸塊233與該引線層213之電性連接。較佳 I 地’該第一散熱片220係可略大於該覆晶晶片23〇 ,藉由 較大面積增加導熱效果，可加速整體之散熱速率。 該密封膠240係形成於該覆晶晶片230與該可撓性基 板210之間。該密封膠240係可為底部填充膠（UnderfilHng material)、樹脂、異方性導電膠（Anisotropic conductive paste，ACP)或異方性導電膠膜（Anisotropic c〇nductive film, ACF)。在本實施例中，該可撓性基板21〇係可為一 聚亞醯胺（polyimide，PI)基板。較佳地，該可撓性基板21〇 包含有至少一導熱通孔214(thermal hole)，該導熱通孔214 7 1283447 係貫穿該可撓性基板210之該上表面211與該下表面212 並連接至該散熱片220,該導熱通孔214係熱耦合於該引 線層213。較佳地，該覆晶晶片23〇之該主動面231係另 形成有至少一不具有電性傳遞功能之虛凸塊234 (dummy bump) ’該些虛凸塊234係經由該導熱通孔214而熱耦合 連接至該第一散熱片220。當該覆晶晶片230於運作時， 可藉由該虛凸塊234與該導熱通孔214將該覆晶晶片230 所產生之熱能傳導至該第一散熱片22〇進行散熱。較佳 地，一第二散熱片250係形成於該覆晶晶片23〇之一背面 232’以加速該散熱型覆晶薄膜封裝構造2〇〇整體之散熱 效率。 在本發明之第二具體實施例中，請參閱第4囷，一種 散熱型覆晶薄膜封裝構造300係主要包含有一可撓性基板 310、一散熱片320、一覆晶晶片330以及一密封膠340， 該可撓性基板310係具有一上表面311以及一下表面 312。在本實施例中，該散熱片32〇係為高導熱金屬，例 如銅、鋁或其合金，以濺鍍方式設置於該可撓性基板31〇 之該下表面312，其中該散熱片320係可略大於該覆晶晶 片330。較佳地，該可撓性基板310係包含有至少一導熱 通孔314，該導熱通孔314係貫穿該可撓性基板之該上表 面311與該下表面312並連接至該散熱片320。 該覆晶晶片330係對應於該散熱片320且設置於該可’ 撓性基板310之該上表面311，該覆晶晶片330係以複數 個凸塊332電性連接至該可撓性基板310之該引線層 1283447 313，此外，該引線層313係熱耦合於該導熱通孔314。該 密封膠340係形成於該覆晶晶片330與該可撓性基板31〇 之間。該密封膠340係為填充樹脂或異方性導電膠。在本 實施例中’該覆晶晶片330之該主動面331係形成有至少 一虛凸塊333，其係經由該導熱通孔314熱耦合連接至該 散熱片320，以利該覆晶晶片330之散熱。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和1283447 IX. Description of the Invention: [Technical Field] The present invention relates to a flip chip package structure, and more particularly to a heat sink type flip chip package structure. [Prior Art] In today's electronics industry, high-performance wafer flip-chips are placed on flexible substrates to achieve a chip-on-film package type, which can be used in small and thin electronic products. For example, driving a 1C wafer, but during the operation of the product, the wafer generates thermal energy, is not easy to escape, and during packaging and use, the overall structural strength of the package is insufficient, and the flexible substrate is bent. Damage to the wafer is caused, resulting in shortened use of the product. Referring to FIG. 1 , a conventional flip chip package structure 1 〇〇 mainly includes a flexible substrate 110 , a flip chip 12 〇 and a sealant 130 ′. The flip chip 12 has an active surface ι 21 And a back surface 122' of the plurality of bumps 123 formed on the active surface 121 of the flip chip 12'. The flexible substrate 11 has a lead layer 112 formed on the upper surface m thereof. After the flip chip bonding, the bumps 123 are bonded to the wiring layer 112, and the sealant 130 is formed between the flip chip 12 and the flexible substrate 110. In the above flip chip package structure 100, the flip chip 12 generates thermal energy when it is in operation, and the thermal energy system is only dissipated by the back surface 122 of the flip chip 12, so that the optimal heat dissipation effect cannot be achieved. . In addition, the flexible substrate 11 is insufficient to support the flip chip 12A above it, and the damage of the flip chip 120 may be caused when the package 1283447 is installed and used. SUMMARY OF THE INVENTION The main object of the present invention is to provide a heat-dissipating flip-chip package structure. A heat sink is disposed on a lower surface of a flexible substrate, and a flip chip is disposed on the heat sink and disposed on the flexible substrate. The upper surface of one of the substrates is used to support the flip chip which has been disposed on the flexible substrate by the heat sink, and the heat dissipation sheet can be used to dissipate the thermal energy generated by the flip chip during operation. A second object of the present invention is to provide a heat dissipating flip chip package structure. A heat dissipating sheet is disposed on a lower surface of a flexible substrate, and a flip chip is disposed on the flexible substrate and disposed on the flexible substrate. An upper surface ′ and the flexible substrate includes at least one thermal via connected to the heat sink to conduct thermal energy generated by operation of the polycrystalline wafer through the thermally conductive via to the heat sink The heat dissipation type flip chip package structure mainly comprises a flexible substrate, a heat sink, a flip chip and a sealant, and the flexible substrate has a heat dissipation rate. The upper surface and the lower surface further comprise a lead layer on the upper surface, the heat sink is disposed on the lower surface of the flexible substrate, and the flip chip corresponds to the heat sink and is disposed on the flexible substrate The upper surface is electrically connected to the lead layer, and the sealant is formed between the flip chip and the flexible substrate. [Embodiment] In the first embodiment of the present invention, please refer to the second and third circles, 1283447. The heat-dissipating flip chip package structure 200 mainly includes a flexible substrate 210 and a first heat sink 220. A flip chip 230 and a sealant 240 having an upper surface 211 and a lower surface 212, the flexible substrate 210 including a lead layer 213 formed on the upper surface 211, the lead Layer 213 includes a plurality of flip-chip pads, a plurality of leads, and a plurality of externally extending pads (not shown). In the embodiment, the first heat sink 220 is adhesively disposed on the lower surface 212 of the flexible substrate 21 by a combination of an adhesive layer 221 . The flip chip 23 is corresponding to the first heat sink 220 and disposed on the upper surface 211 of the flexible substrate 210. The flip chip 230 has an active surface 231 and a back surface 232 and includes a plurality of The bumps 233 are formed on the active surface 231. The bumps 233 are electrically connected to the flip chip 23 and the lead layer 213 of the far-receivable substrate 210. The bumps 233 can be gold. The bumps can be electrically connected to the lead layer 213 by ultrasonic bonding, thermocompression bonding or anisotropic conduction. Preferably, the first heat sink 220 is slightly larger than the flip chip 23A, and the heat dissipation effect is increased by a larger area to accelerate the overall heat dissipation rate. The sealant 240 is formed between the flip chip 230 and the flexible substrate 210. The sealant 240 can be an underfill material, a resin, an anisotropic conductive paste (ACP) or an anisotropic conductive film (ACF). In this embodiment, the flexible substrate 21 can be a polyimide (PI) substrate. Preferably, the flexible substrate 21 includes at least one thermal via 214, which extends through the upper surface 211 and the lower surface 212 of the flexible substrate 210. Connected to the heat sink 220, the thermally conductive via 214 is thermally coupled to the lead layer 213. Preferably, the active surface 231 of the flip chip 23 is formed with at least one dummy bump 234 that does not have an electrical transfer function. The dummy bumps 234 pass through the heat conduction vias 214. And thermally coupled to the first heat sink 220. When the flip chip 230 is in operation, the thermal energy generated by the flip chip 230 can be conducted to the first heat sink 22 by the dummy bump 234 and the thermal via 214 to dissipate heat. Preferably, a second heat sink 250 is formed on one of the back faces 232' of the flip chip 23 to accelerate the heat dissipation efficiency of the heat sink type flip chip package structure 2 as a whole. In a second embodiment of the present invention, referring to FIG. 4, a heat-dissipating flip chip package structure 300 mainly includes a flexible substrate 310, a heat sink 320, a flip chip 330, and a sealant. 340. The flexible substrate 310 has an upper surface 311 and a lower surface 312. In this embodiment, the heat sink 32 is made of a highly thermally conductive metal, such as copper, aluminum or an alloy thereof, and is disposed on the lower surface 312 of the flexible substrate 31 by sputtering, wherein the heat sink 320 is It may be slightly larger than the flip chip 330. Preferably, the flexible substrate 310 includes at least one thermal via 314 extending through the upper surface 311 and the lower surface 312 of the flexible substrate and connected to the heat sink 320. The flip chip 330 is corresponding to the heat sink 320 and disposed on the upper surface 311 of the flexible substrate 310. The flip chip 330 is electrically connected to the flexible substrate 310 by a plurality of bumps 332. The lead layer 1283447 313 is further thermally coupled to the thermally conductive via 314. The sealant 340 is formed between the flip chip 330 and the flexible substrate 31A. The sealant 340 is a filled resin or an anisotropic conductive paste. In the present embodiment, the active surface 331 of the flip chip 330 is formed with at least one dummy bump 333 that is thermally coupled to the heat sink 320 via the thermally conductive via 314 to facilitate the flip chip 330. Cooling. The scope of the present invention is defined by the scope of the appended claims, and anyone skilled in the art, without departing from the spirit of the invention.
範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 第1圖··習知覆晶薄膜封裝構造之截面示意圖； 第2圖：依據本發明之第一具體實施例，一種散熱型覆晶 薄膜封裝構造之截面示意圖； 第3圖：依據本發明之第一具體實施例，該散熱型覆晶薄 膜封裝構造之上視圖；及 第4圖：依據本發明之第二具體實施例，一種散熱型覆晶 薄膜封裝構造之截面示意圖。 【主要元件符號說明】 100覆晶薄膜封裝構造 110可撓性基板 111上表面 112弓丨線層 120覆晶晶片 121主動面 122背面 123凸塊 130密封膠 1283447 200 覆 晶薄膜封裝構造 210 可撓性基板 211 上 表面 213 引 線層 214 導熱通孔 220 第 一散熱片 221 黏 膠層 230 覆 晶晶片 231 主 動面 233 凸 塊 234 虛 凸塊 240 密 封膠 250 第 二散熱片 300 覆 晶薄膜封裝構造 310 可撓性基板 311 上 表面 313 引 線層 314 導熱通孔 320 散熱片 330 覆 晶晶片 331 主 動面 333 虛 凸塊 340 密 封膠 212下表面 232背面 312下表面 332凸塊Any changes and modifications made within the scope are within the scope of protection of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional flip chip package structure; FIG. 2 is a cross-sectional view showing a heat dissipating flip chip package structure according to a first embodiment of the present invention; FIG. 4 is a top view of the heat dissipating flip chip structure according to the first embodiment of the present invention; and FIG. 4 is a cross-sectional view showing a heat dissipating flip chip package structure according to a second embodiment of the present invention. . [Main component symbol description] 100 flip-chip film package structure 110 flexible substrate 111 upper surface 112 bow line layer 120 flip chip 121 active surface 122 back surface 123 bump 130 sealant 1283447 200 flip chip package structure 210 flexible Substrate 211 Upper surface 213 Lead layer 214 Thermal conduction via 220 First heat sink 221 Adhesive layer 230 Flip chip 231 Active surface 233 Bump 234 Virtual bump 240 Sealant 250 Second heat sink 300 Flip chip package structure 310 Flexible substrate 311 upper surface 313 lead layer 314 thermal vias 320 heat sink 330 flip chip 331 active surface 333 dummy bump 340 sealant 212 lower surface 232 back 312 lower surface 332 bump
1010