c/e I281787?5wf.do 九、發明說明： 【發明所屬之技術領域】 •本毛明疋關於一種時脈回復電路㈦〇ck rec〇very ，且特別是關於一種包含延遲閃鎖迴路(DLL: delay locked loop)的時脈回復電路。 【先前技術】 番由在Ϊ極驅動器⑻咖加霄)串接架構的液晶顯示裝 ’貧料與時脈(cl〇ck)的信號從時序控制器__ :ιό ei〇輸出後’會依序地從第—獅極驅動器至最後一 顆源極驅動器做串接傳遞。 ^而資料與日才脈的信號在經過源極驅動器裡的邏輯 ΐ對稱的t在”€路中之信號上升緣與下降緣之速度 护、芦糸、，使得原本責任週期(duty Cyde)為50%的輸 5在經過一級一級的源極驅動器後，責任週期改變， ，力口上貝料與犧信_遞的路㈣法完全對稱，因此越 告/-=!!源極驅動器接收到前一級輸出信號相較於時序控 的輪出，¥料的設定日_setuptlme)與保持時間(鐘 Γ _改變，因此可能產生資料晴data latch)的錯 决，而且越多顆源極驅動器串接就越明顯。 極驅Hi此問題，翻專利第咖15號提出了在源 裡增加相位_迴路(PLL: P^e locked loop)或 ㈣脈回復電路’調整責任週期後，再將資 到號同步後輸出’使每—顆源極驅動器接收 。琥s為耵一級源極驅動器同步過後的信號，因此源 6 J281^^wfdoc/e 極驅動器串接的數目將不受限。 然而即使解決上述問題，此種時脈回復電路仍然面臨 如美國專利第5663665號所描述的蓃波閂鎖(harm〇nic 〗〇ck) 問題。 【發明内容】 本發明的目的是在提供一種時脈回復電路，其主要是 要解決在傳鱗脈回復電路巾！發生的諧波_問題。 ，達成上述及其他目白勺’本發明提出一種時脈回復電 ’匕括延制鎖迴路、初始延遲選擇電路、以及時脈合 、 ι遲&5虎以及多個單元延遲信號。其中，第 遲信號的延遲時間是根據—計數值 每元- ^信時間皆大於前—個單元延遲信號 i值:二擇電路根據上述多個單元延遲信號提供初 J ^ 、、:迴路，做為最初的計數值。時脈合成+路 此輸出時難號號產生輸出時脈信號。 輸出時脈信號的責信號大約相同’而且此 依照本發明的較:=;預設值。 括初始時序產生哭、貝轭例所述，初始延遲選擇電路包 (―tiplexer)。初始時序=電路以及第-多工器 號產生初始信號、取择^生°。根據致能信號與輸入時脈信 號，其中延遲問鎖、時脈選擇信號、以及測試信 初始值產生電路絲^在贿信親糾_初始值。 机^號致能時，根據上述多個單元延 ;2817877§Wf.doc/e 遲信號產生初始值。第-多工_根據時脈選 測試信號與輸入時脈信號其中之一，至乜唬輪出 輸入信號。 —鎖迴路做為 依照本發明的較佳實施例所述，初始值產生 比較态及編碼器。比較器在取樣信號致能時，柜栌路包括 個單元延遲信號產生多個比較信號。苴中，若:豕上述多 號不等於第n+1個單元延遲信號，則第 •弟-狀態’否則第⑽比較信號為第二狀態， 整數。編碼器則根據上述的比較信號產生初始值。n為正 依照本發明的較佳實施例所述，延遲問鎖避 遲鏈(delay chain)、相位偵測器、計數器、以 ^延 延遲鏈提供將輸人錢延遲絲㈣—延靜路。 =號、以及單元延遲信號。其中第—延遲^的二；； 間疋根據多個第-延遲選擇信號蚊，第二延遲信狂 遲時間是«乡㈣二稍麟錢決 ^哭 號與第二延遲信號的相位差，提供== 口 ^遞減^日：^號。計數器輸出上述的計數值，在初始 延遲選擇電路提供的彳讀信號致能時擷取初始值做為計數 ^ JL且根據遞姑示錢減減指示信號遞增或遞減計 數值。解碼電路則根據計數值產生第—延遲 二延遲選擇信號。 士依…、本电明的較佳實施例所述，第一延遲信號的延遲 日:間大約為輸人信號的半個週期，而且上述的預設值大約 為 50%。 1281¾¾ twf.doc/e 依照本發明的較佳實施_述 -除頻器、第二除頻器、以 、“成電路包括第 -延遲信號的頻率除以二之後輪=:=:將第 脈信號的頻率除以二之後輸 除頻益將輪入時 ，、弟：：頻，出信號，產生輪 … =發明之_實施例所述’本發明^採 產生屯路以及延遲閃鎖迴路來將輪 、初口值 第—延遲信號、延遲-週期:第ΐϊϊΐί 值:以做延遲_之起始計婁： t號為一個週期以外的週期信號)發生。延遲=== 準地控制第一延遲作缺、楚-X玍之遲閂鎖迴路則精 間的相位差，並且日;：人：：延遲信號與輸入時脈信號之 延遲信號而產=:==依據輸入時脈信叫 是輸入時脈信號二出，信號。因此若 將失真的!^時脈伴任騎㈣復電路會 源極弓區動哭向 亚利用此輸出時脈信號同步 輪出至下一級源極驅動器，故 產生電路可提供適當的初始;;：:;== 避免4:::接近輸入時脈信號的一個週期，因此可 :、、、""本fx月之上述和其他目的、特徵和優點能更明顯 9 I2817874wf.doc/e 作詳細本發明之較佳實施例’並配合所附圖式， 【實施方式】 狀三為依照本發明較佳實施例所繪示之時脈回復電路 士 — Q 兵圖3為依照本發明較佳實施例所繪示 日了脈回復電路之信號時序圖，請隨著之實施方式合 併參照圖1、圖2與圖3。 μ —，1，括初始時序產生器102、初始值產生電路1〇4、 ^夕工器110、時脈合成電路124、以及由延遲鏈112、 f电路114、相位偵測器12〇與計數器122所組成的延 盘绝鎖迴路。其中初始值產生電路刚更包括比較器ι〇6 …广馬器，解碼電路114更包括第—解碼器116與第 Γ解碼器m，時脈合成電路124更包括第—除頻器126、 弟一除頻為128與互斥或閘(XQR gate) 13〇。 初始時序鼓！ 1()2接收致能錢en錢輸入時脈 ^虎clkin，並產生初始信號ini、取樣錢_、時脈選擇 ^sdc與測試信號論。第-多工器11〇接收時脈選擇 =旎selc、輸入時脈信號clkin與測試信號setn，而初始值 ，生電路1〇4巾之比較器106則接收取樣錢細盥致能 ^唬en。當初始值產生電路104被致能信號如致能，且 時脈選擇㈣sele為低電位，此料脈回復電路進入初始 週期(如圖2,示之202與圖3所示之3叫並且/匕 才弗—多工益110 4擇接收測試信號setn，並將測 setn輪出至延遲鏈112做信號延遲以產生多個單元延 12817為 twf.doc/e 號^^圖！所示之cp7、•抓 入訏脈#唬clkm的一個遇缃，并。 電位轉至低電位時(如圖2在取樣，dsel由高 剛好對應-個週躺延遲級數# ^) ’比^ 1G6取出 設-個週期的延遲恰好落在 ,n . 0ax A. ^ k 號 uds 之 cpl5 與 cpl7之間），然後將每個單元 產生多個比較信號(其中，若第,個=:= 態為邏輯i :邏:°〇:3:，：ϊ正整數。並且第-狀 輯0其巾不同於第—狀態者），並=^^邏輯1或邏 做編碼之後產生-個初始值，出至編碼器108 數狀態。此初始值在初始信號12;之初始計 b祝mi為向電位的時候 ^至計數器122内（此時時脈回復電路進 哭ς :如二:示淺與旧所示之聊接著;;】： 擇㈣―由低電位轉至高電位後，第—多工哭 或 ，供輸入時脈信號dkm至延遲鏈112，時脈“文為 由計數器重置週期轉換到正常週期(如圖2所示之高2 3.所示之3%，即延遲_路開始動作)，然後時脈回； ^•路由初始計數狀態開始逐步地逼近鎖住狀態。 如上所述，圖3所示之各信號之時序，其中測試 setn改變狀態於致能信號en致能之後，取樣信號如 : 於測試信號seta改變狀態之後，初始信號加致能於取= 11 128職 :wf.doc/e 信號dsel致能之後，而且時脈選擇信號selc改變狀態於初 始信號ini致能之後。 圖4為依照本發明較佳實施例所繪示之時脈回復電路 之信號時序圖，圖5為依照本發明較佳實施例所繪示之時 脈回復電路在鎖住狀態下之信號時序圖。請隨著以下之實 施方式合併參照圖1、圖4與圖5。 、c/e I281787?5wf.do IX. Description of the invention: [Technical field to which the invention pertains] • The present invention relates to a clock recovery circuit (7) 〇ck rec〇very, and in particular to a delay-containing flash lock loop (DLL) : delay locked loop) clock recovery circuit. [Prior Art] The liquid crystal display in the tandem structure of the bungee driver (8) is connected with the 'lean material and clock (cl〇ck) signal from the timing controller __ : ιό ei〇 after the output The serial transmission is performed from the first lion drive to the last source drive. ^ And the signal of the data and the chronological pulse is in the symmetry of the logic ΐ in the source driver. The signal rises and falls on the rising edge and the falling edge of the signal in the road, so that the original duty cycle (duty Cyde) is 50% of the input 5 after the first level of the source driver, the duty cycle changes, the force on the shell material and the sacrifice letter _ handed the road (four) method is completely symmetrical, so the more /-=!! source driver received before The first-level output signal is compared with the timing control, the set time of the material is set to _setuptlme), and the hold time (the clock _ change, so it may generate a data latch), and the more source drives are connected in series. The more obvious. The problem of the extreme drive Hi, the patent No. 15 proposed to increase the phase in the source _ loop (PLL: P^e locked loop) or (four) pulse recovery circuit 'adjust the responsibility cycle, then the capital number After synchronization, the output 'sends every source driver. A's s is the signal after the primary source driver is synchronized, so the number of source 6 J281^^wfdoc/e pole drivers will not be limited. Problem, this clock recovery circuit still faces The problem of the chopper latch (harm 〇 〇 ck) described in U.S. Patent No. 5,663,665. SUMMARY OF THE INVENTION The object of the present invention is to provide a clock recovery circuit, which is mainly intended to solve the problem in the scaly pulse recovery circuit. The harmonics _ problem that occurred. The above and other objectives have been achieved. 'The present invention proposes a clock recovery circuit', including a delay lock loop, an initial delay selection circuit, and a clock, a mouse, and a tiger. a plurality of unit delay signals, wherein the delay time of the late signal is based on - the count value per unit - the signal time is greater than the previous unit delay signal i value: the second selection circuit provides the initial J ^ according to the plurality of unit delay signals , , : loop, as the initial count value. Clock synthesis + way this output is difficult to generate the output clock signal. The signal of the output clock signal is about the same 'and this according to the invention: =; Set the initial timing to generate the crying, the yoke example, the initial delay selection circuit package ("tiplexer". The initial timing = circuit and the multiplexer number generate the initial signal, the selection ^ ° °. According to the enable signal Input clock signal, wherein delay error lock, clock selection signal, and test signal initial value generating circuit wire ^ in the bribe letter correction _ initial value. When the machine number is enabled, according to the above multiple unit extension; 2817877 § Wf. The doc/e late signal produces an initial value. The first-multiplexer _ selects one of the test signal and the input clock signal according to the clock pulse, and turns the input signal to the wheel. - The lock loop is taken as a preferred embodiment in accordance with the present invention. The initial value generates a comparison state and an encoder. When the sample signal is enabled, the comparator circuit includes a unit delay signal to generate a plurality of comparison signals. If: 豕, the plurality of numbers are not equal to the n+1th The unit delay signal, then the di-state - otherwise the (10) comparison signal is the second state, an integer. The encoder then generates an initial value based on the comparison signal described above. n is positive In accordance with a preferred embodiment of the present invention, a delay chain, a phase detector, a counter, and a delayed delay chain are provided to delay the input of the money (4) - the delay path. = number, and unit delay signal. Wherein the first delay + two;; between the plurality of first-delay selection signal mosquitoes, the second delay letter madness delay time is « township (four) two slightly lining money decision ^ crying number and the second delay signal phase difference, provide == mouth ^ decrement ^ day: ^ number. The counter outputs the above-mentioned count value, and takes the initial value as the count ^ JL when the read signal provided by the initial delay selection circuit is enabled, and increments or decrements the count value according to the decrement indication signal. The decoding circuit generates a first-delay two-delay selection signal based on the count value. According to a preferred embodiment of the present invention, the delay time of the first delayed signal is approximately half a cycle of the input signal, and the predetermined value is approximately 50%. 12813⁄43⁄4 twf.doc/e in accordance with a preferred embodiment of the present invention - the frequency divider, the second frequency divider, and the "the frequency of the circuit including the first delay signal divided by two after the wheel =:=: will be the pulse After the frequency of the signal is divided by two, the frequency is lost, and the frequency is: the frequency is generated, the signal is generated, and the wheel is generated... The invention is described in the embodiment. The invention generates a loop and a delay flash lock loop. The wheel, the initial value, the delay signal, the delay period, the delay value, the delay value, the delay value, the delay value, the delay value, the delay value, the delay value, the delay value, the delay value, the delay value, the delay value, the delay value Delayed deficiency, Chu-X玍's late latching loop is the phase difference between the fine, and day;: person:: delayed signal and delayed signal of input clock signal produced =:== according to the input clock signal is Input clock signal two out, signal. Therefore, if the distortion of the ^^ clock is accompanied by riding (four) complex circuit, the source bow zone will cry to the sub-source to use the output clock signal to rotate out to the next-level source driver. The generation circuit can provide an appropriate initial;;::;== avoid 4::: close to one cycle of the input clock signal, The above and other objects, features and advantages of the present invention can be more apparent. 9 I2817874wf.doc/e is a detailed description of the preferred embodiment of the present invention and cooperates with the drawings. Mode 3 is a clock recovery circuit in accordance with a preferred embodiment of the present invention. FIG. 3 is a timing diagram of a signal of a pulse recovery circuit according to a preferred embodiment of the present invention. Embodiments are combined with reference to Figures 1, 2 and 3. μ - 1, 1 includes an initial timing generator 102, an initial value generating circuit 1〇4, an instant processor 110, a clock synthesis circuit 124, and a delay chain. 112, the f circuit 114, the phase detector 12 〇 and the counter 122 comprise a stalling lock loop, wherein the initial value generating circuit has just included a comparator ι〇6 ... wide-horse, the decoding circuit 114 further includes a first decoding The processor 116 and the second decoder m, the clock synthesizing circuit 124 further includes a first frequency divider 126, a frequency division of 128 and a mutual exclusion or gate (XQR gate) 13 〇. Initial timing drum! 1 () 2 reception Enable money to enter the clock ^ tiger clkin, and generate the initial signal ini, sampling money _, clock Select ^sdc and test signal theory. The first multiplexer 11 receives the clock selection = 旎selc, the input clock signal clkin and the test signal setn, and the initial value, the comparator 106 of the raw circuit 1 receives the sampling When the initial value generating circuit 104 is enabled, such as enabling, and the clock selection (4) sele is low, the pulse recovery circuit enters the initial period (as shown in FIG. 2, showing 202 and FIG. 3 is called 3 and / / 匕 — 多 多 110 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 110 4 110 110 110 110 110 110 110 110 110 110 110 接收 110 接收 110 接收 110 ^^图! The cp7 shown, • caught a encounter with 訏 pulse#唬clkm, and. When the potential is turned to a low potential (as shown in Figure 2, dsel is high-corresponding to - a weekly delay delay number # ^) 'The delay from ^ 1G6 is set to - the period just falls, n . 0ax A. ^ k No. uds between cpl5 and cpl7), and then each unit produces multiple comparison signals (where, if the first, === state is logical i: logic: °〇: 3:,: ϊ positive integer. and - The series 0 is different from the first state, and =^^ logic 1 or the logic is encoded to generate an initial value, which is output to the encoder 108 number state. The initial value is at the initial signal 12; the initial count b is when the mi is at the potential ^ to the counter 122 (when the clock recovery circuit is crying: as shown in the second: the shallow and the old ones are displayed;;) : Select (four) - after switching from low to high, the first - multiplexed crying, for input clock signal dkm to delay chain 112, the clock "text is converted from the counter reset period to the normal cycle (as shown in Figure 2 The high level 2 3. The 3% shown, that is, the delay _ road starts to move, and then the clock back; ^ The route initial count state begins to gradually approach the lock state. As described above, the signals shown in Figure 3 Timing, in which the test setn changes state after the enable signal en is enabled, the sampling signal is as follows: After the test signal seta changes state, the initial signal is added to enable = 11 128 positions: wf.doc/e signal dsel is enabled And the clock selection signal selc changes state after the initial signal ini is enabled. FIG. 4 is a signal timing diagram of a clock recovery circuit according to a preferred embodiment of the present invention, and FIG. 5 is a preferred embodiment of the present invention. The signal timing of the clock recovery circuit in the locked state is shown Fig. 1, Fig. 4 and Fig. 5 are combined with the following embodiments.
圖1中，當時脈選擇信號selc為高電位時，第一多工 态110遥擇將輸入時脈信號clkin輸入至延遲鏈Η〕，並透 過延遲鏈112將輸入時脈信號clkin做信號延遲而產生第 一延遲信號dsl、第二延遲信號ds2與多個單元延遲信號 Ms(CP7、cP9、cpll〜cp29、cp31、cp32)。其中第_^遲二 信號dsl的延遲時間為輸入時脈信號dkin的半個週期，而 第二延遲信號ds2白勺延遲時間為輸入時脈信號dkin的 週期。 U 初始值產生電路104接收多個單元延遲信號Uds而產 生初始值，並且相位偵測器120根據輸入時脈信號 與第二延遲信號ds2之相位差而產生遞增指示信號仏n 減指示信號dis。當計數器122餘始信號如致二 數器122以經過第二除頻器128將時脈頻率除以 二 時脈信號dkm作為操作解，並以初始值魅電路I 所產生的初錄做初料數狀態，織再域遞增 號⑽與遞減指示信號dls依序向上或向下計數而產&數 第一解碼器116接收計數器122所輸出之計數值，並 12 :wf.doc/e 掉最巧效位元的結果而產生多個第-延遲 之計數:第：解碼器118根據計數器122所輸出 112° , . ^ 乡個第二延遲選擇錄dss2。接著延遲鍵 112根據夕個第_延遲選擇信號 ^ 〜S⑺與多個第二延遲選擇信號(=之= 〜D25)分別產生第-延遲信號ds〗二二 並且根據^第二延遲錢龙似， 號ds2在延遲鏈112之延遲級數(印二延遲信 過之延遲單元總數），當延遲級數在某二°個級數門斤通 交=ί=時即達到鎖住狀態(如同圖以 並且假設時脈回復電路在鎖住的狀態之下， ''在騎輸入-個責任週期不為· 心至時脈回復電路，此時就會發生如圖*與圖== 信號ds2時而超前輸入時脈信號clkm，時而落後 的-信號·之延遲時間為第二延遲信號似 ;乐—延遲信號也2的延遲時間幾 輪入時脈信號c—的時間，因此第 圖1所示之第一除頻器126與第二除頻器 除以-（Λ Γ延遲信號dsl與輸入時脈信號clkm之頻率 (如圖5之0P1與〇p2之波形），然後再經過互斥或 =130之後，即可得到責任週期為5〇%白勺時脈 為 «回復電路nlkGut，如圖5所示之dk⑽波g為 13 12817為 twf.doc/e 圖、6為依照本發明較佳實施例所緣示之時脈回復電路 中之延遲鏈112的内部裳置方塊圖，請合併參照圖i鱼圖 =圖t括多個延遲單元6G2，並且所有的延遲單元_ 二:ί，ik· 一個延遲單元6〇2的輸入端接收輸入 _Wdkln’賴其他的延遲單元皆依序接收來自上一 信號clkin，並且在將輸入時脈信祕 做^虎延遲之後再依序串接傳遞至下-個延遲單元602。 崎元602開始的每一個延遲單元602，皆 延遲選擇信號dssl中的其中-個，依序從 602^^f㈣人軸线咖之後㈣_延遲單元 H的母-個㈣單元搬，轉衫 中，依序從D°〜至肪。而= 單元延遲；，五個延遲單元602相耗接處提供多個 广UU S的其中—個，並且每隔二個延遲單元602 3輸出夕個單元延遲信號_的其中另一個，且每 _ ί f 1依序為卬7、卬9、_.』Ρ29、 卬32。，、中cP32由最末個延遲單 單元2之=_^2讀目的多寡與延遲 使用如 圖“;:十。在本發明範圍中，延遲鏈並不侷限於 每一 Γι]是’所有延遲單元6 一 中的母一個延遲單元6〇2根據 就dssl(如圖1之s〇,所示)其中之-的指= 14 128 im :wf.doc/e 一延遲彳§號dsl。所有延遲單元6〇2的一個第二子集合中 的每一個延遲單it 602根據多個第二延遲選擇信號㈣(如 ，1之D0〜D25所示)其中之一的指示而輸出第二延遲信 號ds2。而所有延遲單元6〇2的一個第三子集合中的每一 個延遲單元6G2之輪出組合成多個料延遲信號—，以 提供至初始值產生電路1〇4以產生初始計數值。 圖7為依知本發明較佳實施例所緣示之時脈回復電路 中之延遲單元的内部電路圖，請合併參照圖6與圖7。圖7 —延遲鏈112當中-個典型的延遲單元術，包括多個 反相器7〇2、第一開關704與第二開關706。其中多個反相 此相互串接，並且於其中一個反相器7〇2的輸出 ^摩禺接弟一開關704盘第-閱gf ^ 第-延遲義… 弟一開關704依據 沪罝-決定是否導通’並於導通時使延 第-二、nj出第一延遲信號dsl。而第二開關706依據 而決定是否導通，並於她^ 遲早=602輪出弟二延遲信號似。在本實 遲單元_皆包含第-關7〇4與第二開關 m延遲單元不需輸出第-延遲信號dS卜則不需包 二· 7〇4。同理，若此延遲單元不需輸出第二延遲 仏唬d 2，則不需包含第二開關7〇6。 中之：發明較佳實施例騎示之時脈回復電路 t括: 2的内部電路圖。請參照圖8，豆 及反或_OR㈣814。其中〇型正反器8()2之輸 15 12817¾ twf.d〇c/e 入端din耦接電源電壓Vdd，輸出端〇p耦接D型正反器 =4之輪入端din，而反相輪出端/叩則不耦接。d型正反 器804之輸出端op耦接D型正反器8〇6之輸入端，而 反相輪出端/〇P則提供測試信號setnc3D型正反器8〇6之輪 出端〇P耦接D型正反器808之輸入端din，而反相輸出端 /oP則提供取樣信號dsebD型正反器808之輸出端叩耦 接D型正反器81〇之輸入端出打，而反相輸出端/叩則耦 反或閘814之其中一個輸入端。 • D型正反器810之輸出端op耦接反或閘814之另一個 輸入端，以及柄接至D型正反器812之時脈端c，以提供 D ^正反态812之操作時脈，而反相輸出端/叩則不耦接。 D型正反器812之輸入端din耦接電源電壓Vdd，輪出 叩則提伽夺脈選擇信號selc，而反相輸出端％不輕接。而 母们D型正反态皆以其重置端r接收致能信號如。 味η型正反器802〜81〇皆以其時脈端0接收輸入時脈信 亏泥 clkin 〇 ° 移位狀雜錢en，其實是雜驅動器的 曰存(shlft renter)所產生的閂鎖信號(t〇ken) 查=信號做為致能信號en有二個好處，第一是由於每個 的每—觸會有關錢，因此利 ^乍為時脈回復電路的初始設定信號 、’、: S在二-列都會重新初始化。而當時脈=二== 面錯路在下—赋會正麵鎖住，Μ少晝 生的¥間。第二是可以同時利用適當的問鎖信 16 1281^ twf.doc/e 號，在源極驅動器需要輸出時脈時， 以減少功率消耗。 化脈回復電路， 圖9為依照本發明較佳實施例所 電路之源極驅動器之致能信號波形9姓▲米用時脈回復 tknl〜tknn 與 dkoutl〜clk〇mn 二兔^參照® 8，其中 9〇n的致能信號(即問鎖信號)en以及輪出、$動器902〜 %脈回復電路，因此在源極驅動器9〇 j^來啟動 號產生後，祕驅動H 9G2_時脈回==鎖信 初始設定·(㈣9所故insp) 始進入 延遲閃鎖迴路開始動作，如圖9所示之正巧期（即 出時脈信號(即輸出時脈信號clk〇m)，而接下)即輸 器之動作則依此類推。 0源極驅動 再接下來則視狀況來停住所有的^ ^ ;:，一在源極驅動器再往：=二輪= 7路而輪出時脈信號dk⑽’以達到減低功率消耗的= 改圖，習=種時脈回復電路之技藝者，還可依照需要而修 回之4脈回復電路，例如在圖1中多增加一個多工器， 所^。圖1G為依照本發明另—較佳實施例所^示 Λ回设電路裝置方塊圖，請合併參照圖i與圖⑺。 圖 10 中 1002、1004、1006、1〇08、1〇10、1〇12、1〇14、 1016、1018、1020、1022、1024、1026、1028 與 103〇 分 17 1281¾ wf.doc/e 別相當於圖1中之1〇2、1〇4、106、簡、 116 ^118 ^120. 122 > 124 W26W28^I3〇,^^； 係與動作原理皆不再贅述。而圖1〇與圖 是=關 了第二多工器U)32，並且輸入時脈信號冒加 器；。T初咖 擇決找供以時脈錢elkin或預 位(如㈣屬或是接地電M Gnd)至^-、 除頻器1028。 ’乐— 之1032在時脈回復電路不需要動作的狀能 鎖、口牧f延朗鎖迴路的輸人接定電位，而在延遲γΪ 鎖將輸罐信號clkm輪入至延遲閃 、 更進一步地減少時脈回復電路的功率消耗。 信號施例，圖1中之輸入時脈 遲鏈U2將^f、/ 進入延遲鏈112，並經過延 堤信號ds2，°ΓΪ第^^與第一延遲信號如與第二延 時間的一半，故實際上在第一延遲信號 時，第二唬clkm皆輪入到時脈合成電路124的同 出半二號Μ會比原先所預期之延遲時間還要多 間。而在脈信號ClkH1經過多工器、110而延遲之時 入至時脈合成4Τ=施例中，輸人時脈錄dkm在輸 兒路1024時，同樣也經過第二多工器1032 沒，若假設輸入時脈信號clkin經過第一多工器 18 12817¾ twf.doc/e 成的延遲時間為 的延遲時間—樣，那麼 乐少-麗所以成 所預期之延遲時間，遲信號dsl將會維持在原先 鄉，輸出時脈信號他。；；==進而減少責任週期為 熟習此種時脈回復電 改圖10之時脈回復雷 文^ ^依…而要而修 器以及一個除頻哭Λ 圖10中多增加二個多工 -較佳每施协二°圖11所示。圖11為依照本發明另 八別 W 1122、聰、1126、1128、1130 與 1132 m 101? 10 ^1〇〇2' 1004 '^^1〇〇8.101〇. 、1〇14、1〇16、1〇18、1〇2〇、1〇22、1〇24、1〇26、職、 11 ^32,故其輕接關係與動作原理皆不再贅述。而圖 哭;;圖的區別是多增加了第三多工器ιΐ34、第四多工 二±二及，二除頻器1138 ’並且第二除頻器1128之輸 透過第三多工器u34而提供’ 當f 之操作頻率則改由輸人時脈信號elkm透過 將於1136猶做信號延遲，並再透過第三除頻器1138 ，輪入日仙m elkm之時_ψ除以二 與第四多工器1136的一個輸入端相接固二 是否=二所輸出之時脈選擇信號seic而分別決定 疋否美ί、輸入%脈信號cikm至第二除頻器m8盥第三除 19 1281獅 twf.doc/e 頻器1138。 ”中之所以要增加第三多工 分開在圖10之實施例中 夕°° 1134的原因，疋為了 徑，以改善輪入時脈^ dk. /守脈合成電路1024之路 第二多工器_時過第一多工器_與 :=1，而產生之延遲不匹配的問題。而第四多 S i是爲了改善在圖ig之實施例中，第4 不匹配的_。…刪因為負載不_產生之延遲 j所述’本㈣為制初始值產生電路以及延遲阿 脈信 =極駆動器内之資料信號後輸出至n==同 =解除源極驅動器的串接級數限制。此外，上述的初始 生電路可提供適當的初始計數值，使第二延 ^ 延遲時間-卩箱就很接近輪人時脈錢的—個週期 可，免5皆波閃鎖問題。並且在源極驅動電路内採用本發明 之日t脈回復電路還可以達到節省電源之功效。 雖然本發明已以較佳實施例揭露如上，然其並非用以 本發明，任何熟習此技藝者，在不脫離本發明之精神 ^耗圍内’當可作些許之更動與潤飾，因此本發明之保護 I巳圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 20 I2817s75 twf.doc/e 裝置依照本發明較佳實施例崎示之時脈回復電路 復電路之信Ξ二::照本發明較佳實施例所繪示之時脈回 圖4為依照本發明較佳實施例 之信號時序圖。 斤、、日不之日可脈回復電路 圖5為依照本發明較佳實施例 卜 在鎖住狀態下之信號時序圖。 '、，…之樣回復電路 圖6為依照本發明較佳實施例 卜 中之延遲鏈的内部裝置方塊圖。θ Μ回復電路 圖7為依照本發明較佳實施例 中之延遲單元的内部電路圖。冰日不之《回復電路 圖8為依照本發明較佳實施例所給 中之初始時序產生器的内部電路圖。…回復電路 圖9為依照本發明較佳實_崎 電路之源__、之致能錢波形圖。_日视回復 圖10為依照本發明另一較佳實施 復電路裝置方塊圖。 斤、、、曰不之日寸脈回 圖11為依照本發明另—較佳實施 復電路裝置方塊圖。 π、、、日不之日守脈回 【主要元件符號說明】 初始時序產生器 初始值產生電路 比較器 102 、 1002 、 1102 104 、 1〇〇4 、 11〇4 106 、 1〇〇6 、 11〇6 21 I2817b74 wf.doc/e 108、1008、1108 :編碼器 110、1010、1110 :第一多工器 112、1012、1112 :延遲鏈In FIG. 1, when the current pulse selection signal selc is at a high potential, the first multi-mode 110 remotely inputs the input clock signal clkin to the delay chain, and delays the input clock signal clkin through the delay chain 112. A first delay signal ds1, a second delay signal ds2, and a plurality of unit delay signals Ms (CP7, cP9, cpll~cp29, cp31, cp32) are generated. The delay time of the first signal s1 is the half cycle of the input clock signal dkin, and the delay time of the second delay signal ds2 is the period of the input clock signal dkin. The U initial value generating circuit 104 receives the plurality of unit delay signals Uds to generate an initial value, and the phase detector 120 generates an increment indicating signal 仏n minus the indicating signal dis based on the phase difference between the input clock signal and the second delayed signal ds2. When the counter 122 has a residual signal, the second frequency divider 122 divides the clock frequency by the second frequency divider 128 by the second clock signal dkm as an operational solution, and uses the initial recording generated by the initial value of the magic circuit I as a preliminary material. The number state, the woven re-field increment number (10) and the decrement indication signal dls are sequentially counted up or down, and the first decoder 116 receives the count value output by the counter 122, and 12: wf.doc/e falls the most A plurality of first-delay counts are generated as a result of the effector bit: the decoder 118 selects dss2 according to the output of the counter 122 by 112°, . Then, the delay key 112 generates a first delay signal ds and a second delay selection signal (===D25) according to the first _delay selection signal ^~S(7) and the second delay, respectively. No. ds2 delay series in the delay chain 112 (the total number of delay units after the delay of the second delay), when the delay level reaches a locked state in a certain two-level number of gates = ί = (as shown in the figure And assuming that the clock recovery circuit is in the locked state, ''in the riding input-one duty cycle is not the heart-to-clock recovery circuit, then the figure* and the figure== the signal ds2 will appear ahead of time. The input clock signal clkm, sometimes the delay time of the -signal is the second delay signal; the delay time of the music-delay signal is also the time of the clock signal c-, which is shown in FIG. The first frequency divider 126 and the second frequency divider are divided by - (Λ Γ delay signal dsl and the frequency of the input clock signal clkm (such as the waveforms of 0P1 and 〇p2 of FIG. 5), and then mutually exclusive or =130 After that, the clock with a duty cycle of 5〇% can be obtained as «return circuit nlkGut, as shown in Figure 5, dk(10) g is 13 12817 is a twf.doc/e diagram, and 6 is an internal skirting block diagram of the delay chain 112 in the clock recovery circuit according to the preferred embodiment of the present invention, please refer to FIG. Include a plurality of delay units 6G2, and all delay units _ 2: ί, ik · an input terminal of a delay unit 6 〇 2 receives input _Wdkln 'the other delay units are sequentially received from the previous signal clkin, and After the input clock signal is delayed, it is serially transmitted to the next delay unit 602. Each delay unit 602 starting from the first element 602 delays one of the selection signals dssl, in order from 602^^f (4) After the human axis coffee (4) _ delay unit H mother-one (four) unit moving, in the shirt, sequentially from D ° ~ to fat. And = unit delay;, five delay units 602 phase loss One of a plurality of wide UUs is provided, and every other two delay units 602 3 outputs the other one of the unit delay signals _, and each _ ί f 1 is sequentially 卬7, 卬9, _. Ρ29, 卬32.,, and cP32 are read by the last delay single unit 2 = _^2 Figure ";: Ten. In the scope of the present invention, the delay chain is not limited to each ] ι] is 'the delay unit 6 ' 2 of all the delay units 6 one according to dssl (as shown in Figure 1 Indicates where - the finger = 14 128 im : wf.doc / e a delay 彳 § § ds. Each of the second subset of all delay units 6 〇 2 delays the single it 602 according to a plurality of second delays The second delayed signal ds2 is outputted by the indication of one of the selection signals (4) (e.g., D0 to D25 of 1). And the rounding out of each of the delay units 6G2 in a third subset of all delay units 6〇2 is combined into a plurality of material delay signals—to be supplied to the initial value generating circuit 1〇4 to generate an initial count value. FIG. 7 is an internal circuit diagram of a delay unit in a clock recovery circuit according to a preferred embodiment of the present invention. Please refer to FIG. 6 and FIG. 7 in combination. Figure 7 - A typical delay unit in the delay chain 112, comprising a plurality of inverters 7, 2, a first switch 704 and a second switch 706. The plurality of inversions are connected in series with each other, and the output of one of the inverters 7〇2 is connected to a switch 704. The first reading is read by gf ^ first-delay meaning... the first switch 704 is determined according to the Shanghai-based Whether to conduct 'and make the first delay signal dsl when the second is turned on. The second switch 706 decides whether to turn on, and it is similar to the delay signal of the second generation. In the present real-time unit _ all include the first-off 7〇4 and the second switch, the delay unit does not need to output the first-delay signal dS, and does not need to include the second. Similarly, if the delay unit does not need to output the second delay 仏唬d 2, the second switch 7〇6 is not required to be included. In the preferred embodiment of the invention, the clock recovery circuit of the rider includes: 2 internal circuit diagram. Please refer to Figure 8, Bean and _OR (4) 814. The input type 正p is coupled to the power supply voltage Vdd, and the output terminal 〇p is coupled to the D-type flip-flop = 4 round-in terminal din, and the input of the 正-type flip-flop 8 () 2 is 15 128173⁄4 twf.d〇c/e The reverse wheel end/叩 is not coupled. The output end of the d-type flip-flop 804 is coupled to the input end of the D-type flip-flop 8〇6, and the reverse-stage wheel output/〇P provides the test signal setnc3D type flip-flop 8〇6 round-out 〇 P is coupled to the input terminal din of the D-type flip-flop 808, and the inverted output terminal /oP provides the sampling signal. The output end of the dsebD-type flip-flop 808 is coupled to the input end of the D-type flip-flop 81〇. The inverting output / / is coupled to one of the inputs of the gate 814. • The output op of the D-type flip-flop 810 is coupled to the other input of the inverse OR gate 814, and the handle is connected to the clock terminal c of the D-type flip-flop 812 to provide operation of the D^ forward and reverse 812. Pulse, while the inverting output / 叩 is not coupled. The input terminal din of the D-type flip-flop 812 is coupled to the power supply voltage Vdd, and the turn-up 提 is used to pick up the pulse selection signal selc, and the inverting output terminal % is not lightly connected. The female D-type positive and negative states all receive the enable signal such as the reset terminal r. The η-type flip-flops 802~81〇 receive the input clock with the clock terminal 0, and the shifting miscellaneous money is actually the latch generated by the shelt renter of the miscellaneous drive. Signal (t〇ken) Check = signal as the enable signal en has two advantages, the first is that each of the touch-related money, so the profit is the initial setting signal of the clock recovery circuit, ', : S will be reinitialized in the second column. At that time, the pulse = two == The wrong way is in the lower part - the front will be locked, and the less ¥. The second is to use the appropriate lock letter 16 1281^ twf.doc / e at the same time, when the source driver needs to output the clock to reduce power consumption. FIG. 9 is a schematic diagram of an enable signal waveform of a source driver of a circuit according to a preferred embodiment of the present invention. 9 ▲ meters with clock recovery tknl~tknn and dkoutl~clk〇mn two rabbits ^ reference® 8, Among them, the enable signal of 9〇n (ie, the lock signal) en and the wheel, the actuator 902~% pulse recovery circuit, so after the source driver 9〇j^ to start the number generation, the secret drive H 9G2_ Pulse return == lock initial setting · ((4) 9 reason insp) Start to enter the delay flash lock loop to start the action, as shown in Figure 9 is the coincidence period (that is, the output clock signal (ie output clock signal clk 〇 m), and Next, the action of the transmitter is the same. 0 source drive then next to the situation to stop all ^ ^ ;:, one in the source driver to: = two rounds = 7 ways and turn out the clock signal dk (10) 'to achieve reduced power consumption = change The student of the clock recovery circuit can also repair the 4-pulse recovery circuit as needed, for example, adding one more multiplexer in FIG. 1G is a block diagram of a circuit arrangement of a circuit according to another preferred embodiment of the present invention. Please refer to FIG. 1 and FIG. 7 (7). In Figure 10, 1002, 1004, 1006, 1〇08, 1〇10, 1〇12, 1〇14, 1016, 1018, 1020, 1022, 1024, 1026, 1028 and 103 are divided into 17 12813⁄4 wf.doc/e Corresponding to 1〇2, 1〇4, 106, Jane, 116^118^120.122 > 124 W26W28^I3〇, ^^; in Figure 1, the system and the principle of operation are not repeated. And Fig. 1 and Fig. = = the second multiplexer U) 32 is turned off, and the clock signal is input to the regulator; The first coffee chooses to supply the clock elkin or pre-position (such as (four) or grounding M Gnd) to ^-, frequency divider 1028. 'Le- 1032 in the clock recovery circuit does not need to operate the lock, the grazing f delays the lock circuit of the input potential, and delays the γ 锁 lock to turn the tank signal clkm into the delay flash, further Ground reduces the power consumption of the clock recovery circuit. In the signal embodiment, the input clock delay chain U2 in FIG. 1 enters the delay chain 112 and passes through the delay signal ds2, and the first delay signal and the first delay signal are half of the second delay time. Therefore, in the first delay signal, the second 唬clkm is rounded up to the same half of the clock synthesis circuit 124, which is more than the expected delay time. When the pulse signal ClkH1 passes through the multiplexer and is delayed by 110, it enters the clock synthesis 4Τ=in the example, when the input time record dkm is at 1024, the same time passes through the second multiplexer 1032. If it is assumed that the input clock signal clkin passes the delay time of the first multiplexer 18 128173⁄4 twf.doc/e, then the delay time ds will be maintained. In the original hometown, the output clock signals him. ;;==In turn, reduce the duty cycle to familiarize with the clock recovery. The clock of Figure 10 is replied to Lei Wen ^ ^ Depending on... and the repair and a frequency of crying Λ Figure 10 adds two more multiplexes - Preferably, each application is shown in Figure 11. Figure 11 shows another eight 112, Cong, 1126, 1128, 1130 and 1132 m 101? 10 ^1〇〇2' 1004 '^^1〇〇8.101〇., 1〇14, 1〇16, in accordance with the present invention. 1〇18,1〇2〇,1〇22,1〇24,1〇26, job, 11^32, so the light connection relationship and the principle of action are not repeated. And the picture is crying; the difference between the pictures is that the third multiplexer ιΐ34, the fourth multiplexer two±2 and the second frequency divider 1138' are added, and the second frequency divider 1128 is transmitted through the third multiplexer u34. And provide 'when the operating frequency of f is changed by the input clock signal elkm through the signal will be delayed in 1136, and then through the third frequency divider 1138, when the round of the immortal m elkm _ ψ divided by two One input end of the fourth multiplexer 1136 is connected to the second clock = whether the output pulse selection signal seic of the two outputs is determined separately, and the input of the % pulse signal cikm to the second frequency divider m8 盥 the third division 19 1281 lion twf.doc/e frequency 1138. The reason why the third multiplex is to be separated in the embodiment of Fig. 10 is °° 1134, for the purpose of improving the wheeled clock ^ dk. / 守脉合成电路1024, the second multiplex _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Because the load does not generate a delay j, the 'this (4) is the initial value generation circuit and the delay of the data signal in the A-Min = pole actuator is output to n== the same = the number of cascade stages of the source driver is removed. In addition, the above-mentioned initial generation circuit can provide an appropriate initial count value, so that the second delay delay time - the box is very close to the cycle of the person's clock money, free of the 5 wave flash lock problem. The use of the t-pulse recovery circuit of the present invention in the source driving circuit can also achieve the power saving effect. Although the present invention has been disclosed in the preferred embodiment as above, it is not used in the present invention, and anyone skilled in the art is not Leaving the spirit of the present invention, it can be used to make some changes and Therefore, the protection of the present invention is defined by the scope of the appended patent application. [Simple Description of the Drawings] 20 I2817s75 twf.doc/e Apparatus According to the preferred embodiment of the present invention, the clock response is shown. Circuit Circuit 2: The clock diagram shown in the preferred embodiment of the present invention is shown in FIG. 4 as a signal timing diagram in accordance with a preferred embodiment of the present invention. FIG. 6 is a block diagram of an internal device of a delay chain in accordance with a preferred embodiment of the present invention. FIG. 6 is a block diagram of a signal in a locked state in accordance with a preferred embodiment of the present invention. FIG. 7 is an internal circuit diagram of a delay unit in accordance with a preferred embodiment of the present invention. FIG. 8 is an internal circuit diagram of an initial timing generator according to a preferred embodiment of the present invention. FIG. 10 is a block diagram of a complex circuit device according to another preferred embodiment of the present invention. FIG. 10 is a block diagram of a circuit device according to another preferred embodiment of the present invention. Day inch pulse back to Figure 11 According to the present invention, a block diagram of a complex circuit device is preferably implemented. π, ,, 日日日日脉脉回 [Main component symbol description] Initial timing generator initial value generating circuit comparator 102, 1002, 1102 104, 1〇 〇4, 11〇4 106, 1〇〇6, 11〇6 21 I2817b74 wf.doc/e 108, 1008, 1108: encoders 110, 1010, 1110: first multiplexer 112, 1012, 1112: delay chain
解碼電路 第一解碼器 第二解碼器 相位偵測器 計數器 時脈合成電路 第一除頻器 第二除頻器 互斥或閘 114 、 1014 、 1114 : 116 、 1016 、 1116 : 118 、 1018 、 1118 : 120 、 1020 、 1120 : 122 、 1022 、 1122 : 124 、 1024 、 1124 : 126 、 1026 、 1126 : 128 、 1028 、 1128 : 130 、 1030 、 1130 :Decoding circuit first decoder second decoder phase detector counter clock synthesis circuit first frequency divider second frequency divider mutually exclusive or gate 114, 1014, 1114: 116, 1016, 1116: 118, 1018, 1118 : 120 , 1020 , 1120 : 122 , 1022 , 1122 : 124 , 1024 , 1124 : 126 , 1026 , 1126 : 128 , 1028 , 1128 : 130 , 1030 , 1130 :
202、302、insp :初始級設定週期 204、304 :計數器重置週期 206、306、norp :正常週期 208 :測試信號之轉態點 210 :取樣信號之轉態點 402 :鎖住狀態 602 :延遲單元 702 :反相器 704 :第一開關 706 :第二開關 802、804、806、808、810、812 : D 型正反器 814 :反或閘 22 f.doc/e 1281¾ 902、904、906〜90η :源極驅動器 1032、1132 :第二多工器 1134 :第三多工器 1136 ··第四多工器 1138 ··第三除頻器 c :時脈端 clkin :輸入時脈信號 clkout、clkoutl 〜clkoutn :輸出時脈信號 cp7、cp9、cpll、Cpl3、cpi5、cpl7、cpl9、cp21、 cp23、cp25、cp27、cp29、cp31、Cp32 ··單元延遲信號 dsl :第一延遲信號 ds2 :第二延遲信號 dsel :取樣信號 dis :遞減指示信號 din :輸入端 D0〜D25、dss2 :第二延遲選擇信號 en、tknl〜tkrni :致能信號202, 302, insp: initial stage setting period 204, 304: counter reset period 206, 306, norp: normal period 208: transition point of test signal 210: transition point of sampling signal 402: locked state 602: delay Unit 702: Inverter 704: First switch 706: Second switch 802, 804, 806, 808, 810, 812: D-type flip-flop 814: Reverse or gate 22 f.doc/e 12813⁄4 902, 904, 906 ~90η: source driver 1032, 1132: second multiplexer 1134: third multiplexer 1136 · fourth multiplexer 1138 · third frequency divider c: clock end clkin: input clock signal clkout , clkoutl ~ clkoutn: output clock signal cp7, cp9, cpll, Cpl3, cpi5, cpl7, cpl9, cp21, cp23, cp25, cp27, cp29, cp31, Cp32 · unit delay signal dsl: first delay signal ds2: Two delay signal dsel: sampling signal dis: decrement indication signal din: input terminals D0 to D25, dss2: second delay selection signal en, tknl~tkrni: enable signal
Gnd :接地電壓 ini :初始信號 iis :遞增指示信號 〇pl :第一除頻器之輸出 叩2 :第二除頻器之輸出 〇p :輸出端 /op :反相輸出端 r :重置端 23 1281¾ wf.doc/e 1281¾ wf.doc/e 延遲選擇信號 selc :時脈選擇信號 setn :測試信號 SO〜S12、dssl :第-uds :單元延遲信號 Vdd :電源電壓Gnd : ground voltage ini : initial signal iis : incremental indication signal 〇 pl : output of the first frequency divider 叩 2 : output of the second frequency divider 〇 p : output / op : inverting output r : reset 23 12813⁄4 wf.doc/e 12813⁄4 wf.doc/e Delay selection signal selc: clock selection signal setn: test signal SO~S12, dssl: first-uds: unit delay signal Vdd: supply voltage
24twenty four