TWI382301B - Control circuit for power-on-reset and its operating method - Google Patents
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Description
本發明為一種電源開啟重置控制電路及其操作方法，特別是用於電子系統的重置。The present invention is a power-on reset control circuit and method of operation thereof, particularly for resetting of an electronic system.
一般而言，電子產品在一開始接電時，都要對其內部的電子電路系統重置才能開始正常工作。電源開啟重置(Power on Reset)的方法一般為類比式的RC電路產生一重置訊號以對電子系統重置，但該重置訊號有可能不會產生。In general, when an electronic product is initially powered up, its internal electronic circuitry must be reset to begin normal operation. The power on reset method generally generates an reset signal for the analog RC circuit to reset the electronic system, but the reset signal may not be generated.
以晶片(IC)來說，在一t1時間時，外接電源開始下降到晶片(IC)無法工作時，但又沒有降到0V經一段時間，電源回復到VDD，電源的變化如第一圖，這種情況下電源開啟重置(Power on Reset)不良的現象會常常發生，如此一來晶片(IC)未經過初始狀態後的工作可能會不正常甚至完全無法工作。In the case of a chip (IC), at a time t1, the external power supply begins to drop until the chip (IC) fails to operate, but does not fall to 0 V over a period of time, the power supply returns to VDD, and the power supply changes as shown in the first figure. In this case, a poor power on reset phenomenon often occurs, so that the work after the wafer (IC) has not passed the initial state may be abnormal or not working at all.
根據習知技術案號為095117862，此篇專利在於以數值比較的方式來決定是否重置，電路架構的實現方式在文中提及當數值比較結果需重置的話，再利用判定計數器的值決定產生重置的週期，但計數器的值有可能一開始就是預定的值，會有重置訊號沒有產生的疑慮。According to the conventional technical case number 095117862, this patent is to determine whether to reset by numerical comparison. The implementation of the circuit architecture mentions in the text that when the numerical comparison result needs to be reset, the value of the determination counter is used to determine the generation. The period of the reset, but the value of the counter may be the predetermined value at the beginning, there is no doubt that the reset signal is not generated.
鑑於上述問題，本案發明人經密集試驗與研究，最後終於開發出一種電源開啟重置控制電路及其操作方法，以克服習知技術的缺陷，並具產業利用性。In view of the above problems, the inventors of the present invention finally developed a power-on reset control circuit and its operation method through intensive experiment and research to overcome the defects of the prior art and have industrial applicability.
鑑於上述，本發明內容即在於提出一種電源開啟重置控制電路，包括一除頻器及一移位暫存器，該移位暫存器的時脈輸入端電連接於該除頻器的輸出端，其中當該電源開啟重置控制電路被施加一第一電壓時，該除頻器因應一與該電壓相關的起始振盪訊號而在該除頻器的該輸出端產生一除頻訊號。該移位暫存器的資料輸入端接收一預設準位，且以一順進順出的操作，輸出一第一電源開啟重置訊號。In view of the above, the present invention provides a power-on reset control circuit including a frequency divider and a shift register, the clock input of the shift register being electrically connected to the output of the frequency divider. And wherein when the power-on reset control circuit is applied with a first voltage, the frequency divider generates a frequency-dividing signal at the output of the frequency divider according to an initial oscillation signal related to the voltage. The data input end of the shift register receives a predetermined level, and outputs a first power-on reset signal in a forward-and-forward operation.
該電源開啟重置控制電路，更包括：一數位式電源開啟重置產生電路，包括該除頻器與該移位暫存器；一類比式電源開啟重置產生電路，產生一第二電源開啟重置訊號，其中在一預設時段中，該第二電源開啟重置訊號具有一重置準位；一旗標暫存器，其時脈輸入端接收該第一電源開啟重置訊號，其資料輸入端接收該預設準位，其輸出端產生一旗標訊號，且具有一預設端與一清除端的至少其中之一；及一組合邏輯電路，因應該第一電源開啟重置訊號與該第二電源開啟重置訊號而產生一第三電源開啟重置訊號，其中：當該預設準位為一高準位時，該旗標暫存器的該清除端接收該第二電源開啟重置訊號；當該預設準位為一第一低準位時，該旗標暫存器的該預設端接收該第二電源開啟重置訊號；該旗標訊號與該第三電源開啟重置訊號被提供至一電子電路；該旗標訊號的一第一狀態與該第一電源開啟重置訊號出現一特定準位為相關；及該旗標訊號的一第二狀態與該第二 電源開啟重置訊號出現該重置準位為相關。The power-on reset control circuit further includes: a digital power-on reset generation circuit including the frequency divider and the shift register; and a analog power-on reset generation circuit to generate a second power-on And resetting the signal, wherein the second power-on reset signal has a reset level in a preset period; a flag register receives the first power-on reset signal, and the clock input terminal thereof The data input terminal receives the preset level, the output end generates a flag signal, and has at least one of a preset end and a clear end; and a combination logic circuit, the first power source is turned on to reset the signal and The second power-on reset signal generates a third power-on reset signal, wherein: when the preset level is a high level, the clear end of the flag register receives the second power-on Resetting the signal; when the preset level is a first low level, the preset end of the flag register receives the second power-on reset signal; the flag signal and the third power are turned on The reset signal is provided to an electronic circuit; A first open state of the flag signal to the first power-on reset signal occurs is related to a specific level; and a second state of the flag signal and the second The power-on reset signal appears to be related to the reset level.
本發明內容還包含一種電源開啟重置控制電路的操作方法，包括下列步驟：步驟一，施加該第一電壓於該電源開啟重置控制電路；步驟二，因應與該第一電壓相關的該振盪訊號而產生該除頻訊號；步驟三，因應該除頻訊號而移位一未確定儲存數位值，以產生該第一電源開啟重置訊號。The present invention also includes a method for operating a power-on reset control circuit, comprising the steps of: step one, applying the first voltage to the power-on reset control circuit; and step two, responsive to the oscillation associated with the first voltage The signal is generated by the signal; in step 3, an undetermined stored digit value is shifted due to the frequency signal to generate the first power-on reset signal.
本發明的目的主要在於當主要的電源開啟重置訊號未能重置電子系統時，產生輔助的電源開啟重置訊號以重置電子系統，且能克服先前技術的缺點。其他目的，特徵及功效，可參閱過後文的實施方式後便能得到更進一步的了解。The main purpose of the present invention is to generate an auxiliary power-on reset signal to reset the electronic system when the main power-on reset signal fails to reset the electronic system, and overcome the disadvantages of the prior art. Other purposes, features and effects can be further understood by reference to the embodiments described hereinafter.
電路設計概念是將晶片(IC)工作的必要條件為時脈必須要起振的想法，利用RC振盪器或是晶體(Crystal)振盪器開始起振一與電壓相關的起始振盪信號，經過除頻器發出穩定的一移位時脈的訊號給移位暫存器，開始位移暫存器的該準位以順進順出的方式依序移位遞補，藉由移位暫存器的最後一級之輸出來當做電源開啟重置訊號。The circuit design concept is that the necessary condition for the operation of the chip (IC) is that the clock must be oscillated. The RC oscillator or the crystal oscillator is used to start the oscillation-related initial oscillation signal. The frequency converter sends a stable shifting pulse signal to the shift register, and the shift register is started to shift the replenishment in the order of the forward and backward, by shifting the last of the register. The output of the first level is used as a power on reset signal.
請參閱第二圖(a)，其圖為一數位式電源開啟重置產生電路2之架構圖，該數位式電源開啟重置產生電路2包含一除頻器21以及一第一移位暫存器22。當一第一電壓上升到一起振電壓時，該振盪器(未顯示)開始產生一振盪訊號 P_CLK，該除頻器21接收該振盪信號P_CLK，輸出一除頻訊號S_CLK，該第一移位暫存器22接收該除頻訊號S_CLK，輸出一第一電源開啟重置訊號Rst1。Please refer to FIG. 2( a ), which is a block diagram of a digital power-on reset generation circuit 2 including a frequency divider 21 and a first shift register. Device 22. When a first voltage rises to a voltage, the oscillator (not shown) begins to generate an oscillation signal. P_CLK, the frequency divider 21 receives the oscillating signal P_CLK, and outputs a frequency-divided signal S_CLK. The first shift register 22 receives the frequency-divided signal S_CLK and outputs a first power-on reset signal Rst1.
請參閱第二圖(b)，其圖為該除頻器21的內部元件圖，該除頻器21包含複數依序的T型正反器T1 ~TN ，該複數依序的T型正反器T1 ~TN 的一輸入級正反器T1 的時脈輸入端接收該振盪訊號P_CLK，對於該複數依序的T型正反器T1 ~TN 中相鄰的一前級正反器TN-1 與一後級正反器TN ，該前級正反器TN-1 的輸出端電連接於該後級正反器TN 的時脈輸入端。對於除頻器21的構成而言，亦可使用計數器(Counter)與邏輯閘組成，或是其他有除頻功能的電路所構成，皆不在此限。該除頻器21的作用在確保振盪器的起振是穩定且可靠，且該除頻器21調整該第一電源開啟重置訊號Rst1的一特定準位的一脈波時間長度，以使一電子電路藉由該第一電源開啟重置訊號Rst1完成重置。Please refer to the second figure (b), which is an internal component diagram of the frequency divider 21, the frequency divider 21 includes a plurality of sequential T-type flip-flops T 1 ~T N , the complex sequential T-type when the flip-flop clock input terminal T 1 ~ T N input stage of a flip-flop for receiving the T 1 as the oscillation signal P_CLK, adjacent to the 1 ~ T N of the plurality of T flip-flop T sequentially to a front The step flip-flop T N-1 and a post-stage flip-flop T N , the output of the pre-stage flip-flop T N-1 is electrically connected to the clock input terminal of the post-stage flip-flop T N . For the configuration of the frequency divider 21, a counter (Counter) and a logic gate may be used, or other circuits having a frequency removal function may be used. The function of the frequency divider 21 is to ensure that the start-up of the oscillator is stable and reliable, and the frequency divider 21 adjusts a pulse duration of a certain level of the first power-on reset signal Rst1 to make a pulse The electronic circuit completes the reset by the first power-on reset signal Rst1.
請參閱第二圖(c)，其圖為該第一移位暫存器22的內部元件圖，該第一移位暫存器22包含複數依序的記憶單元A1 ~AN ，組成該第一移位暫存器22。該複數依序的記憶單元A1 ~AN 的一輸入級記憶單元A1 的資料輸入端接收一預設準位Level，該複數依序的記憶單元A1 ~AN 的該每一記憶單元的時脈輸入端接收該除頻訊號S_CLK，對於該複數依序的記憶單元中相鄰的一前級記憶單元AN-1 與一後級記憶單元AN ，該前級記憶單元AN-1 的輸出端電連接於該後級記憶單元AN 的資料輸入端，該複數依序的記憶單元A1 ~AN 的該每一記憶單元的一 第一預設端SET接收一第二電源開啟重置訊號Rst2，該複數依序的記憶單元A1 ~AN 的一輸出級記憶單元AN 的輸出端產生該第一電源開啟重置訊號Rst1。該電源開啟重置控制電路被施加該第一電壓的一初始狀態，該複數依序的記憶單元A1 ~AN 的每一記憶單元儲存一第一未確定位元，以使該第一移位暫存器22共有複數未確定位元。較佳的實施例為一第一D型正反器或Latch A1 ~AN 。該複數未確定位元中包含一特定位元，該特定位元對應於一與該預設準位Level相反的一特定準位，該特定準位用以重置一電子電路。Please refer to the second figure (c), which is an internal component diagram of the first shift register 22, the first shift register 22 includes a plurality of sequential memory cells A 1 -A N , which constitute the The first shift register 22. A data input terminal of the input stage A 1 memory cell of the plurality of sequential memory cell A 1 ~ A N receives a predetermined level Level, the plurality of sequential memory cell A 1 ~ A N of each of the memory cell The clock input terminal receives the frequency-divided signal S_CLK, and the adjacent one-stage memory unit A N-1 and the latter-level memory unit A N in the plurality of sequential memory units, the front-level memory unit A N- the output terminal of each memory connected to a data input of the succeeding a N of the memory unit, the memory unit of the plurality of sequential a 1 ~ a N predetermined unit a first end receiving a second power supply SET The reset signal Rst2 is turned on, and the output terminal of an output stage memory unit A N of the plurality of sequential memory cells A 1 -A N generates the first power-on reset signal Rst1. The power-on reset control circuit is applied with an initial state of the first voltage, and each memory unit of the plurality of sequential memory cells A 1 -A N stores a first undetermined bit to make the first shift Bit register 22 has a plurality of undetermined bits. A preferred embodiment is a first D-type flip-flop or Latch A 1 ~A N . The plurality of undetermined bits includes a specific bit corresponding to a specific level opposite the preset level, the specific level being used to reset an electronic circuit.
請參閱第二圖(d)，其圖為該第一電源開啟重置訊號Rst1的應用之圖，包含該數位式電源開啟重置產生電路2與一第一旗標暫存器31，較佳的實施例為一第二D型正反器或Latch。該第一旗標暫存器31的時脈輸入端接收該數位式電源開啟重置產生電路2的該第一重置訊號Rst1作為一第一觸發時脈，該第一旗標暫存器31的資料輸入端接收該預設準位Level，該第一旗標暫存器31的一第二清除端CLR接收該第二電源開啟重置訊號Rst2，該第一旗標暫存器31的輸出端產生一第一旗標訊號Flag1，提供軟體重置(Software Reset)的應用。Please refer to the second figure (d), which is a diagram of the application of the first power-on reset signal Rst1, including the digital power-on reset generation circuit 2 and a first flag register 31, preferably An embodiment is a second D-type flip-flop or Latch. The clock input end of the first flag register 31 receives the first reset signal Rst1 of the digital power-on reset generation circuit 2 as a first trigger clock, and the first flag register 31 The data input terminal receives the preset level, and a second clearing terminal CLR of the first flag register 31 receives the second power-on reset signal Rst2, and the output of the first flag register 31 The terminal generates a first flag signal Flag1 to provide an application for software reset.
請參閱第二圖(e)，其圖為該第二重置訊號Rst2未重置而該第一重置訊號Rst1發生重置時，該第一移位暫存器22、該第一旗標暫存器31的時序圖。請參閱第二圖(c)、第二圖(d)、第二圖(e)，其中一第一實施例為當該複數依序的記憶單元A1 ~AN 的N=4時，假設在該初始狀態的該複數依序 的記憶單元A1 ~A4 所儲存的該複數未確定位元為0111，且該複數依序的記憶單元A1 ~A4 的一輸入級記憶單元A1 的資料輸入端接收該預設準位Level若為由該第一電壓所建立的一高準位，當該複數依序的記憶單元A1 ~A4 的該每一記憶單元的時脈輸入端接收該除頻訊號S_CLK為一低準位到該高準位變化時，便會將該複數依序的記憶單元A1 ~A4 的位元往下一級記憶單元做移位的動作，即第一次該低準位到該高準位變化時，該複數依序的記憶單元A1 ~A4 所儲存的位元為0111；第二次該低準位到該高準位變化時，該複數依序的記憶單元A1 ~A4 所儲存的位元為1011；第三次該低準位到該高準位變化時，該複數依序的記憶單元A1 ~A4 所儲存的位元為1101；第四次該低準位到該高準位變化時，該複數依序的記憶單元A1 ~A4 所儲存的位元為1110；第五次該低準位到該高準位變化時，該複數依序的記憶單元A1 ~A4 所儲存的位元為1111；該複數依序的記憶單元A1 ~A4 的最後一級記憶單元A4 所儲存的位元不再產生變化，此時該第一移位暫存器22的最後一級記憶單元A4 輸出該第一電源開啟重置訊號Rst1的該特定準位不再產生，因此無法產生重置的動作。Referring to FIG. 2( e ), the first shift register 22 and the first flag are displayed when the second reset signal Rst2 is not reset and the first reset signal Rst1 is reset. A timing diagram of the register 31. Please refer to the second figure (c), the second figure (d), and the second figure (e). One of the first embodiments is that when the complex sequential memory cells A 1 ~A N have N=4, the hypothesis is assumed. The complex undetermined bit stored in the complex sequential memory cells A 1 -A 4 in the initial state is 0111, and an input level memory cell A 1 of the complex sequential memory cells A 1 -A 4 Receiving the preset level Level as a high level established by the first voltage, when the clock input terminal of each of the memory units A 1 -A 4 of the plurality of sequential memory units Receiving the frequency-divided signal S_CLK to a low level to the high-level change, the bit-ordered memory cells A 1 -A 4 are shifted to the next-level memory unit, that is, When the low level changes to the high level, the bits stored in the plurality of sequential memory units A 1 -A 4 are 0111; when the low level changes to the high level, the The bits stored in the plurality of sequential memory cells A 1 -A 4 are 1011; the third time the low level changes to the high level, the bits stored in the memory cells A 1 -A 4 in sequence yuan 1101; fourth time of the low level to the high level changes, the plurality of sequential memory cell A 1 ~ A 4 bit is stored 1110; fifth of the low level to the high level changes The bits stored in the plurality of sequential memory cells A 1 -A 4 are 1111; the bits stored in the last-level memory cells A 4 of the plurality of sequential memory cells A 1 -A 4 no longer change. At this time, the specific level of the first-stage memory unit A 4 of the first shift register 22 outputting the first power-on reset signal Rst1 is no longer generated, and thus the resetting operation cannot be generated.
當該複數依序的記憶單元A1 ~A4 的最後一級記憶單元A4 所儲存的位元為0到1的變化時，且該第一旗標暫存器31的資料輸入端接收該預設準位Level為該第一電壓所建立的該高準位時，該第一旗標訊號Flag1的準位為該高準位。該第一實施例為該第二電源開啟重置訊號Rst2未發生重置的狀況，如果是該第二電源開啟重置訊號Rst2發生重置 的狀況，請參閱第二圖(f)，其圖為該第二重置訊號Rst2發生重置時，該第一移位暫存器22、該第一旗標暫存器31的時序圖。When the bit element stored in the last-level memory unit A 4 of the plurality of sequential memory cells A 1 -A 4 is a change of 0 to 1, and the data input end of the first flag register 31 receives the pre- When the level is set to the high level established by the first voltage, the level of the first flag signal Flag1 is the high level. In the first embodiment, the second power-on reset signal Rst2 is not reset. If the second power-on reset signal Rst2 is reset, please refer to the second figure (f). A timing diagram of the first shift register 22 and the first flag register 31 when the second reset signal Rst2 is reset.
請參閱第二圖(c)、第二圖(d)、第二圖(f)，該第二電源開啟重置訊號Rst2同時對該複數依序的記憶單元A1~A4的每一個記憶單元的準位預設(SET)成該高準位，並且因為不再產生該特定準位而不再產生重置動作，同時對該第一旗標暫存器31清除(CLR)，使該第一旗標訊號Flag1為該低準位。Referring to FIG. 2(c), FIG. 2(d), and FIG. 2(f), the second power-on reset signal Rst2 is simultaneously for each of the memory cells of the plurality of memory cells A1 to A4. The level is preset (SET) to the high level, and since the specific level is no longer generated, the reset action is no longer generated, and the first flag register 31 is cleared (CLR) to make the first The flag signal Flag1 is the low level.
該第一旗標暫存器31可判斷重置的產生是否由該第二電源開啟重置訊號Rst2或是由該第一電源開啟重置訊號Rst1所產生。當第二電源開啟重置訊號Rst2未產生重置時，該第一電源開啟重置訊號Rst1產生該特定準位，觸發該第一旗標暫存器31接收該預設準位Level，若預設準位Level為該第一電壓所產生的該高準位時，此時該第一旗標訊號Flag1的狀態為一第一狀態，為該高準位，用以通知微控器單元(未顯示)，作軟體重置(Software Reset)；當該第二電源開啟重置訊號Rst2產生時，將該第一旗標暫存器31的準位清除(CLR)為該低準位，此時該第一旗標訊號Flag1的狀態為一第二狀態，為該低準位。因此可由該第一旗標訊號Flag1在重置動作發生時的該高準位或是該低準位來判定重置的動作是否由該第一電源開啟重置訊號Rst1或是由該第二電源開啟重置訊號Rst2所產生。The first flag register 31 can determine whether the generation of the reset is generated by the second power-on reset signal Rst2 or by the first power-on reset signal Rst1. When the second power-on reset signal Rst2 does not generate a reset, the first power-on reset signal Rst1 generates the specific level, triggering the first flag register 31 to receive the preset level, if When the level is set to the high level generated by the first voltage, the state of the first flag signal Flag1 is a first state, and the high level is used to notify the microcontroller unit (not Displayed as a software reset; when the second power-on reset signal Rst2 is generated, the level of the first flag register 31 is cleared (CLR) to the low level. The state of the first flag signal Flag1 is a second state, which is the low level. Therefore, the first flag signal Flag1 can determine whether the reset action is enabled by the first power source to reset the signal Rst1 or by the second power source when the resetting action occurs at the high level or the low level. The reset signal Rst2 is generated.
該第一實施例為當重置一電子系統時，該電子系統所需 的電源開啟重置訊號為該低準位(Active-Low)動作時的例子，以下為當重置該電子系統時，該電子系統所需的電源開啟重置訊號為該高準位(Active-High)動作時的例子。The first embodiment is required for the electronic system when resetting an electronic system The power-on reset signal is an example of the low-level (Active-Low) action. The following is the power-on reset signal required by the electronic system when the electronic system is reset to the high level (Active- High) Example of action.
請參閱第三圖(a)，其圖為一第二移位暫存器23的內部元件圖，該第二移位暫存器23包含複數依序的記憶單元B1 ~BN ，組成該第二移位暫存器23。該複數依序的記憶單元B1 ~BN 的一輸入級記憶單元B1 的資料輸入端接收一預設準位Level，該複數依序的記憶單元B1 ~BN 的該每一記憶單元的時脈輸入端接收該除頻訊號S_CLK，對於該複數依序的記憶單元中相鄰的一前級記憶單元BN-1 與一後級記憶單元BN ，該前級記憶單元BN-1 的輸出端電連接於該後級記憶單元BN 的資料輸入端，該複數依序的記憶單元B1 ~BN 的該每一記憶單元的一第一清除端CLR接收一第二電源開啟重置訊號Rst2，該複數依序的記憶單元B1 ~BN 的一輸出級記憶單元BN 的輸出端產生該第一電源開啟重置訊號Rst1。Please refer to the third figure (a), which is an internal component diagram of a second shift register 23, and the second shift register 23 includes a plurality of sequential memory cells B 1 -B N , which constitute the The second shift register 23. The plurality of sequential data memory unit B 1 ~ B N input to an input stage of memory cell B 1 receives a predetermined level Level, the plurality of memory cells sequentially the B 1 ~ B N of each memory cell The clock input terminal receives the frequency-divided signal S_CLK, and the preceding-stage memory unit B N-1 and the latter-level memory unit B N in the complex sequential memory unit, the pre-level memory unit B N- an output terminal connected to the data input terminal of the rear stage B N of the memory unit, the plurality of sequential memory for each of the units B 1 ~ a clear terminal CLR B N first memory unit receiving a second power on The signal Rst2 is reset, and the output terminal of an output stage memory unit B N of the plurality of sequential memory cells B 1 -B N generates the first power-on reset signal Rst1.
請參閱第三圖(b)，其圖為該第一電源開啟重置訊號Rst1的應用之圖，包含一第二旗標暫存器32的時脈輸入端接收該數位式電源開啟重置產生電路2的該第一重置訊號Rst1作為一第二觸發時脈，該第二旗標暫存器32的資料輸入端接收該預設準位Level，該第二旗標暫存器32的一第二預設端SET接收該第二電源開啟重置訊號Rst2，該第二旗標暫存器32的輸出端產生一第二旗標訊號Flag2，提供軟體重置(Software Reset)的應用。Please refer to the third figure (b), which is a diagram of the application of the first power-on reset signal Rst1, and the clock input terminal of the second flag register 32 receives the digital power-on reset. The first reset signal Rst1 of the circuit 2 serves as a second trigger clock. The data input end of the second flag register 32 receives the preset level, and the second flag register 32 The second preset terminal SET receives the second power-on reset signal Rst2, and the output of the second flag register 32 generates a second flag signal Flag2 to provide a software reset application.
請參閱第三圖(c)，其圖為該第二重置訊號Rst2未重 置而該第一重置訊號Rst1發生重置時，該第二移位暫存器23、該第二旗標暫存器32的時序圖。請參閱第三圖(a)、第三圖(b)、第三圖(c)，其中一第二實施例為當該複數依序的記憶單元B1 ~BN 的N=4時，假設在該初始狀態的該複數依序的記憶單元B1 ~B4 所儲存的該複數未確定位元為1000，且該複數依序的記憶單元B1 ~B4 的一輸入級記憶單元B1 的資料輸入端接收該預設準位Level若為由一地電位所建立的該低準位，當該複數依序的記憶單元B1 ~B4 的該每一記憶單元的時脈輸入端接收該除頻訊號S_CLK為一低準位到該高準位變化時，便會將該複數依序的記憶單元B1 ~B4 的位元往下一級記憶單元做移位的動作，即第一次該低準位到該高準位變化時，該複數依序的記憶單元B1 ~B4 所儲存的位元為1000；第二次該低準位到該高準位變化時，該複數依序的記憶單元B1 ~B4 所儲存的位元為0100；第三次該低準位到該高準位變化時，該複數依序的記憶單元B1 ~B4 所儲存的位元為0010；第四次該低準位到該高準位變化時，該複數依序的記憶單元B1 ~B4 所儲存的位元為0001；第五次該低準位到該高準位變化時，該複數依序的記憶單元B1 ~B4 所儲存的位元為0000；該複數依序的記憶單元B1 ~B4 的最後一級記憶單元B4 所儲存的位元不再產生變化，此時該第二移位暫存器23的最後一級記憶單元B4 輸出該第一電源開啟重置訊號Rst1的該特定準位不再產生，因此無法產生重置的動作。Referring to FIG. 3(c), the second shift register 23 and the second flag are displayed when the second reset signal Rst2 is not reset and the first reset signal Rst1 is reset. A timing diagram of the register 32. Referring to the third figure (a), the third figure (b), and the third figure (c), a second embodiment is assumed when the complex sequential memory cells B 1 -B N have N=4. The complex undetermined bit stored in the complex sequential memory cells B 1 -B 4 in the initial state is 1000, and an input level memory cell B 1 of the complex sequential memory cells B 1 -B 4 The data input terminal receives the preset level, if the low level is established by a ground potential, and receives the clock input of each memory unit of the plurality of sequential memory units B 1 -B 4 When the frequency division signal S_CLK is a low level to the high level change, the bits of the plurality of sequential memory units B 1 to B 4 are shifted to the next level memory unit, that is, the first When the low level changes to the high level, the bits stored in the plurality of sequential memory cells B 1 to B 4 are 1000; when the low level changes to the high level, the complex number The bits stored in the sequential memory cells B 1 -B 4 are 0100; the third time the low level changes to the high level, the bits stored in the plurality of sequential memory cells B 1 -B 4 Is 00 10; the fourth time the low level changes to the high level, the bits stored in the plurality of sequential memory cells B 1 -B 4 are 0001; the fifth time the low level changes to the high level The bits stored in the plurality of sequential memory cells B 1 -B 4 are 0000; the bits stored in the last-level memory cell B 4 of the plurality of sequential memory cells B 1 -B 4 no longer change. At this time, the specific level of the first-stage memory unit B 4 of the second shift register 23 outputting the first power-on reset signal Rst1 is no longer generated, and thus the resetting operation cannot be generated.
當該複數依序的記憶單元B1 ~B4 的最後一級記憶單元B4 所儲存的位元為0到1的變化時，且該第二旗標暫存器32 的資料輸入端接收該預設準位Level為該地電位所建立的低準位時，該第二旗標訊號Flag2的準位為該低準位。以上的例子為該第二電源開啟重置訊號Rst2未發生重置的狀況，如果是該第二電源開啟重置訊號Rst2發生重置的狀況，請參閱第三圖(d)，其圖為該第二重置訊號Rst2發生重置時，該第二移位暫存器23、該第二旗標暫存器32的時序圖。When the plurality of memory cells sequentially last stage memory B cells B 1 ~ B 4 4 is stored bit changes from 0 to 1, and the second flag register data input terminal 32 receives the pre- When the level is set to the low level established by the ground potential, the level of the second flag signal Flag2 is the low level. The above example is a situation in which the second power-on reset signal Rst2 is not reset. If the second power-on reset signal Rst2 is reset, please refer to the third figure (d), which is shown in the figure. A timing diagram of the second shift register 23 and the second flag register 32 when the second reset signal Rst2 is reset.
請參閱第三圖(a)、第三圖(b)、第三圖(d)，該第二電源開啟重置訊號Rst2同時對該複數依序的記憶單元B1 ~B4 的每一個記憶單元的準位清除(CLR)成該低準位，並且因為不再產生該特定準位而不再產生重置動作，同時對該第二旗標暫存器32預設(SET)，使該第二旗標訊號Flag2為該高準位。Referring to the third figure (a), the third figure (b), and the third figure (d), the second power-on reset signal Rst2 simultaneously remembers each of the plurality of sequential memory cells B 1 -B 4 The level clearing (CLR) of the unit is at the low level, and the reset action is no longer generated because the specific level is no longer generated, and the second flag register 32 is preset (SET), so that the The second flag signal Flag2 is the high level.
該第二旗標暫存器32可判斷重置的產生是否由該第二電源開啟重置訊號Rst2或是由該第一電源開啟重置訊號Rst1所產生。當第二電源開啟重置訊號Rst2未產生重置時，該第一電源開啟重置訊號Rst1產生該特定準位，觸發該第二旗標暫存器32接收該預設準位Level，若預設準位Level為該地電位所建立的該低準位時，此時該第二旗標訊號Flag2的狀態為該第一狀態，為該低準位，用以通知微控器單元(未顯示)，作軟體重置(Software Reset)；當該第二電源開啟重置訊號Rst2產生時，將該第二旗標暫存器32的準位預設(SET)為該高準位，此時該第二旗標訊號Flag2的狀態為該第二狀態，為該高準位。因此可由該第二 旗標訊號Flag2在重置動作發生時的該高準位或是該低準位來判定重置的動作是否由該第二電源開啟重置訊號Rst2或是由該第一電源開啟重置訊號Rst1所產生。The second flag register 32 can determine whether the generation of the reset is generated by the second power-on reset signal Rst2 or by the first power-on reset signal Rst1. When the second power-on reset signal Rst2 does not generate a reset, the first power-on reset signal Rst1 generates the specific level, triggering the second flag register 32 to receive the preset level, if When the level is set to the low level established by the ground potential, the state of the second flag signal Flag2 is the first state, and the low level is used to notify the microcontroller unit (not shown) ), as a software reset (software reset); when the second power-on reset signal Rst2 is generated, the level of the second flag register 32 is preset (SET) to the high level. The state of the second flag signal Flag2 is the second state, which is the high level. So by the second The flag signal Flag2 determines whether the reset action is enabled by the second power-on reset signal Rst2 or the first power-on reset signal Rst1 when the reset action occurs at the high level or the low level. Produced.
請參閱第四圖，其圖為電源開啟重置控制電路6的架構圖，包含一類比式電源開啟重置產生電路3，該數位式電源開啟重置產生電路2，該第一旗標暫存器31，組合邏輯電路4，一電子系統5。該第二電源開啟重置訊號Rst2，電連接至該數位式電源開啟重置產生電路2與組合邏輯電路4；該第一電源開啟重置訊號Rst1電連接至該第一旗標暫存器31之時脈接收端與組合邏輯電路4；一第三電源開啟重置訊號Rst3與該第一旗標訊號Flag1，分別電連接至該電子系統5。Please refer to the fourth figure, which is a structural diagram of the power-on reset control circuit 6, including an analog power-on reset generation circuit 3, the digital power-on reset generation circuit 2, the first flag temporary storage 31, combinational logic circuit 4, an electronic system 5. The second power-on reset signal Rst2 is electrically connected to the digital power-on reset generation circuit 2 and the combination logic circuit 4; the first power-on reset signal Rst1 is electrically connected to the first flag register 31. The clock receiving end and the combination logic circuit 4; a third power-on reset signal Rst3 and the first flag signal Flag1 are electrically connected to the electronic system 5, respectively.
該數位式電源開啟重置產生電路2，包括該除頻器21與該第一移位暫存器22。The digital power-on reset generation circuit 2 includes the frequency divider 21 and the first shift register 22.
該類比式電源開啟重置產生電路3產生該第二電源開啟重置訊號Rst2，其中在一預設時段中，該第二電源開啟重置訊號Rst2具有一重置準位，該重置準位用以重置該電子系統5。The analog power-on reset generation circuit 3 generates the second power-on reset signal Rst2, wherein the second power-on reset signal Rst2 has a reset level in a preset period, the reset level Used to reset the electronic system 5.
該第一旗標暫存器31，其時脈輸入端接收該第一電源開啟重置訊號Rst1，其資料輸入端接收該預設準位Level且為該高準位，該第一旗標暫存器31的該清除端(CLR)接收該第二電源開啟重置訊號Rst2；該第一旗標暫存器31的輸出端產生該第一旗標訊號Flag1。The first flag register 31 receives the first power-on reset signal Rst1, and the data input terminal receives the preset level and is the high level, the first flag temporarily The clearing end (CLR) of the register 31 receives the second power-on reset signal Rst2; the output of the first flag register 31 generates the first flag signal Flag1.
該電源開啟重置控制電路6的操作方法，包括下列步 驟：步驟一，施加該第一電壓於該電源開啟重置控制電路6；步驟二，當該第一電壓上升到一起振電壓時，開始產生該振盪訊號P_CLK，並且因應一與該第一電壓相關的振盪訊號P_CLK而產生該除頻訊號S_CLK；步驟三，預設一二進位儲存變數，以在該電源開啟重置控制電路6被施加該第一電壓的一初始狀態下儲存該未確定儲存數位值，並且以一預設準位，填補該二進位儲存變數的最高位元來向該二進位儲存變數最低位元的方向移位，因應該除頻訊號S_CLK而移位一未確定儲存數位值，以產生該第一電源開啟重置訊號Rst1。其中該預設準位為一高準位與一低準位的其中之一。該未確定儲存數位值中包含一特定位元，該特定位元對應於一與該預設準位相反的一特定準位，當該特定位元被移位至該二進位儲存變數的最低位元且保留於最低位元時，該第一電源開啟重置訊號具有該特定準位，該特定準位用以重置該電子電路5。The method for operating the power-on reset control circuit 6 includes the following steps Step 1: Step 1: Applying the first voltage to the power-on reset control circuit 6; Step 2, when the first voltage rises to a resonant voltage, starting to generate the oscillation signal P_CLK, and corresponding to the first voltage The frequency-divided signal S_CLK is generated by the associated oscillation signal P_CLK; and in step 3, a binary storage variable is preset to store the undetermined storage in an initial state in which the power-on reset control circuit 6 is applied with the first voltage. a digit value, and filling the highest bit of the binary storage variable with a predetermined level to shift to the direction of the lowest bit of the binary storage variable, and shifting an undetermined storage digit value according to the frequency signal S_CLK To generate the first power-on reset signal Rst1. The preset level is one of a high level and a low level. The undetermined storage digit value includes a specific bit corresponding to a specific level opposite to the preset level, when the specific bit is shifted to the lowest bit of the binary storage variable The first power-on reset signal has the specific level, and the specific level is used to reset the electronic circuit 5.
在該電子系統5所需的電源開啟重置訊號為低電位動作時(Active-Low)，該組合邏輯電路較佳的實施例為一及邏輯閘(AND Gate)，該第二電源開啟重置訊號Rst2與該第一電源開啟重置訊號Rst1，分別電連接至該及邏輯閘(AND Gate)的兩輸入，以產生該第三電源開啟重置訊號Rst3。當該第二電源開啟重置訊號Rst2之準位為重置準位(本實施例為該低準位)或/且當該第一電源開啟重置訊號Rst1之準位為特定準位(本實施例為該低準位)時，該第三電 源開啟重置訊號Rst3對該電子系統5重置。When the power-on reset signal required by the electronic system 5 is a low-level operation (Active-Low), a preferred embodiment of the combinational logic circuit is an AND gate, and the second power is turned on and reset. The signal Rst2 and the first power-on reset signal Rst1 are respectively electrically connected to the two inputs of the AND gate to generate the third power-on reset signal Rst3. When the second power-on reset signal Rst2 is at a reset level (in the present embodiment, the low level) or / and when the first power-on reset signal Rst1 is at a specific level (this When the embodiment is the low level), the third power The source turn-on reset signal Rst3 resets the electronic system 5.
當該第二電源開啟重置訊號Rst2未發生重置時，該第一電源開啟重置訊號Rst1產生該特定準位，分別經過該組合邏輯電路4以產生該第三電源開啟重置訊號Rst3，對該電子系統5重置；經過該第一旗標暫存器31使該第一旗標訊號Flag1為該第一狀態，對該電子系統5重置。When the second power-on reset signal Rst2 is not reset, the first power-on reset signal Rst1 generates the specific level, respectively, through the combination logic circuit 4 to generate the third power-on reset signal Rst3, The electronic system 5 is reset; the first flag register 31 is set to the first state by the first flag register 31, and the electronic system 5 is reset.
當該第二電源開啟重置訊號Rst2發生重置時，該第二電源開啟重置訊號Rst2在一預定時段中產生該重置準位，分別對該數位式電源開啟重置產生電路2重置，使該第一電源開啟重置訊號Rst1不再產生該特定準位，使該第一旗標暫存器31的該第一旗標訊號Flag1為該第二狀態，不再對該電子系統5重置；同時經過該邏輯電路4，以產生該第三電源開啟重置訊號Rst3，對該電子系統5重置。When the second power-on reset signal Rst2 is reset, the second power-on reset signal Rst2 generates the reset level for a predetermined period of time, and respectively resets the digital power-on reset generation circuit 2 The first power-on reset signal Rst1 is no longer generated by the first power-on reset signal Rst1, so that the first flag signal Flag1 of the first flag register 31 is in the second state, and the electronic system 5 is no longer The logic circuit 4 is simultaneously passed to generate the third power-on reset signal Rst3 to reset the electronic system 5.
2‧‧‧數位式電源開啟重置產生電路2‧‧‧Digital power-on reset generation circuit
3‧‧‧類比式電源開啟重置產生電路3‧‧‧ analog power supply reset reset generation circuit
4‧‧‧組合邏輯電路4‧‧‧Combined logic circuit
5‧‧‧電子系統5‧‧‧Electronic system
6‧‧‧電源開啟重置控制電路6‧‧‧Power On Reset Control Circuit
22‧‧‧第一移位暫存器22‧‧‧First shift register
23‧‧‧第二移位暫存器23‧‧‧Second shift register
31‧‧‧第一旗標暫存器31‧‧‧First flag register
32‧‧‧第二旗標暫存器32‧‧‧Second flag register
T1 ~TN ‧‧‧T型正反器T 1 ~T N ‧‧‧T type flip-flop
A1 ~AN 、B1 ~BN ‧‧‧D型正反器或D LatchA 1 ~A N , B 1 ~B N ‧‧‧D type flip-flop or D Latch
P_CLK‧‧‧振盪訊號P_CLK‧‧‧ oscillation signal
S_CLK‧‧‧除頻訊號S_CLK‧‧‧frequency signal
Rst1‧‧‧第一電源開啟重置訊號Rst1‧‧‧First power on reset signal
Rst2‧‧‧第二電源開啟重置訊號Rst2‧‧‧Second power on reset signal
Rst3‧‧‧第三電源開啟重置訊號Rst3‧‧‧ third power on reset signal
Level‧‧‧預設準位Level‧‧‧predetermined level
Flag1‧‧‧第一旗標訊號Flag1‧‧‧first flag signal
Flag2‧‧‧第二旗標訊號Flag2‧‧‧Second flag signal
第一圖：VDD在電壓下降時的波形圖First picture: Waveform of VDD when the voltage drops
第二圖(a)：數位式電源開啟重置產生電路之架構方塊圖Figure 2 (a): Block diagram of the digital power-on reset generation circuit
第二圖(b)：除頻器的內部元件之圖Figure 2 (b): Diagram of the internal components of the frequency divider
第二圖(c)：第一實施例中第一移位暫存器之內部元件圖Second figure (c): internal component diagram of the first shift register in the first embodiment
第二圖(d)：第一實施例中第一旗標暫存器的連接圖Second figure (d): connection diagram of the first flag register in the first embodiment
第二圖(e)：第一實施例中第一重置序號產生重置之時序圖Second figure (e): Timing diagram of the first reset sequence number generation reset in the first embodiment
第二圖(f)：第一實施例中第二重置序號產生重置之時序圖Second figure (f): Timing diagram of the second reset sequence number generation reset in the first embodiment
第三圖(a)：第二實施例中第二移位暫存器之內部元件圖Third diagram (a): internal component diagram of the second shift register in the second embodiment
第三圖(b)：第二實施例中第二旗標暫存器的連接圖Third diagram (b): connection diagram of the second flag register in the second embodiment
第三圖(c)：第二實施例中第一重置序號產生重置之時序圖Third diagram (c): Timing diagram of the first reset sequence number generation reset in the second embodiment
第三圖(d)：第二實施例中第二重置序號產生重置之時序圖Third diagram (d): Timing diagram of the second reset sequence number generation reset in the second embodiment
第四圖：電源開啟重置控制電路的內部架構圖Figure 4: Internal architecture diagram of the power-on reset control circuit
2‧‧‧數位式電源開啟重置產生電路2‧‧‧Digital power-on reset generation circuit
3‧‧‧類比式電源開啟重置產生電路3‧‧‧ analog power supply reset reset generation circuit
4‧‧‧組合邏輯電路4‧‧‧Combined logic circuit
5‧‧‧電子系統5‧‧‧Electronic system
6‧‧‧電源開啟重置控制電路6‧‧‧Power On Reset Control Circuit
21‧‧‧除頻器21‧‧‧Delephone
22‧‧‧第一移位暫存器22‧‧‧First shift register
23‧‧‧第二移位暫存器23‧‧‧Second shift register
31‧‧‧第一旗標暫存器31‧‧‧First flag register
32‧‧‧第二旗標暫存器32‧‧‧Second flag register
T1 ~TN ‧‧‧T型正反器T 1 ~T N ‧‧‧T type flip-flop
A1 ~AN 、B1 ~BN ‧‧‧D型正反器或D LatchA 1 ~A N , B 1 ~B N ‧‧‧D type flip-flop or D Latch
P_CLK‧‧‧振盪訊號P_CLK‧‧‧ oscillation signal
S_CLK‧‧‧除頻訊號S_CLK‧‧‧frequency signal
Rst1‧‧‧第一電源開啟重置訊號Rst1‧‧‧First power on reset signal
Rst2‧‧‧第二電源開啟重置訊號Rst2‧‧‧Second power on reset signal
Rst3‧‧‧第三電源開啟重置訊號Rst3‧‧‧ third power on reset signal
Level‧‧‧預設準位Level‧‧‧predetermined level
Flag1‧‧‧第一旗標訊號Flag1‧‧‧first flag signal
Flag2‧‧‧第二旗標訊號Flag2‧‧‧Second flag signal
Claims (12)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW97145000A TWI382301B (en) | 2008-11-20 | 2008-11-20 | Control circuit for power-on-reset and its operating method |
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| TW97145000A TWI382301B (en) | 2008-11-20 | 2008-11-20 | Control circuit for power-on-reset and its operating method |
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| TW201020745A TW201020745A (en) | 2010-06-01 |
| TWI382301B true TWI382301B (en) | 2013-01-11 |
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| TW97145000A TWI382301B (en) | 2008-11-20 | 2008-11-20 | Control circuit for power-on-reset and its operating method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5586309A (en) * | 1992-06-11 | 1996-12-17 | Sierra Semiconductor Corporation | Universal programming interface for clock generators operable in a parallel programming mode and a serial programming mode |
| US20030142572A1 (en) * | 2002-01-28 | 2003-07-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device capable of reliable power-on reset |
| TW200727577A (en) * | 2006-01-12 | 2007-07-16 | Winbond Electronics Corp | Clock recovery circuit |
| TW200820626A (en) * | 2006-10-31 | 2008-05-01 | Realtek Semiconductor Corp | A clock and data recovery circuit and a method for adjusting loop bandwidth used thereby |
-
2008
- 2008-11-20 TW TW97145000A patent/TWI382301B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5586309A (en) * | 1992-06-11 | 1996-12-17 | Sierra Semiconductor Corporation | Universal programming interface for clock generators operable in a parallel programming mode and a serial programming mode |
| US20030142572A1 (en) * | 2002-01-28 | 2003-07-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device capable of reliable power-on reset |
| TW200727577A (en) * | 2006-01-12 | 2007-07-16 | Winbond Electronics Corp | Clock recovery circuit |
| TW200820626A (en) * | 2006-10-31 | 2008-05-01 | Realtek Semiconductor Corp | A clock and data recovery circuit and a method for adjusting loop bandwidth used thereby |
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