TWI273664B - Bumping process, bump structure, packaging process and package structure - Google Patents
Bumping process, bump structure, packaging process and package structure Download PDFInfo
- Publication number
- TWI273664B TWI273664B TW093108238A TW93108238A TWI273664B TW I273664 B TWI273664 B TW I273664B TW 093108238 A TW093108238 A TW 093108238A TW 93108238 A TW93108238 A TW 93108238A TW I273664 B TWI273664 B TW I273664B
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- Taiwan
- Prior art keywords
- layer
- forming
- bump
- ball
- wafer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000012858 packaging process Methods 0.000 title claims abstract description 17
- 229910000679 solder Inorganic materials 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims description 211
- 229910052751 metal Inorganic materials 0.000 claims description 98
- 239000002184 metal Substances 0.000 claims description 98
- 235000012431 wafers Nutrition 0.000 claims description 89
- 239000000463 material Substances 0.000 claims description 42
- 238000005476 soldering Methods 0.000 claims description 41
- 230000004888 barrier function Effects 0.000 claims description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 10
- 238000009713 electroplating Methods 0.000 claims description 9
- 229910000756 V alloy Inorganic materials 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 8
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 claims description 8
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 7
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 6
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 229910000969 tin-silver-copper Inorganic materials 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 229910001174 tin-lead alloy Inorganic materials 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 235000003642 hunger Nutrition 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 208000002599 Smear Layer Diseases 0.000 claims 2
- 239000000126 substance Substances 0.000 claims 2
- 229910000990 Ni alloy Inorganic materials 0.000 claims 1
- 239000011247 coating layer Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 abstract description 7
- 238000005272 metallurgy Methods 0.000 abstract description 3
- 230000035882 stress Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- GSJBKPNSLRKRNR-UHFFFAOYSA-N $l^{2}-stannanylidenetin Chemical compound [Sn].[Sn] GSJBKPNSLRKRNR-UHFFFAOYSA-N 0.000 description 1
- 241000283973 Oryctolagus cuniculus Species 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000037351 starvation Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L24/11—Manufacturing methods
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
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Description
1273664 11568twfl.doc/006 95-11-13 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種凸塊製程(Bumping process)、凸 塊結構(Bumping structure)、封裝製程(packaging ρΐΌα_ 以及封裝結構(Packaging structure),且特別是有關於一種 增加凸塊南度’以使晶片(Chip)與封裝基材(Packaging substrate)之間具有高可靠度之連接關係的凸塊製程、凸塊 結構、封裝製程以及封裝結構。 【先前技術】 在高度情報化社會的今日,多媒體應用的市場不斷地 急速擴張著。積體電路封裝技術亦需配合電子裝置的數位 化、網路化、區域連接化以及使用人性化的趨勢發展。為 達成上述的要求,必須強化電子元件的高速處理化、多功 能化、積集化、小型輕量化及低價化等多方面的要求,於 疋積體電路封裝技術也跟著朝向微型化、高密度化發展。 其中球格陣列式構裝(Ball Grid Array,BGA ),晶片尺寸 構裝(Chip-Scale Package,CSP ),覆晶構裝(nip Chip, F/C ) ’多晶片模組(施出七脚M〇dule,)等高密度 積體電路封裝技術也應運而生。而所謂積體電路封裝密度 的是單位面積所含有腳位(pin)數目多募的程度。對於 同饴度,,電路封裝而言,縮短配線的長度有助訊號傳遞 速度$提昇,是以凸塊的應用已漸成為高密度封裝的主流。 第1^〜1F圖依序繪示一習知凸塊製程的剖面流程 圖。凊先芩照第1A圖,首先提供一晶圓100。晶圓100 1273664 11568twfl.doc/006 95-11-13 具有多個銲墊102,配置於晶圓100之表面上。此外,晶 圓100還具有-保護層106,保護層1〇6係覆蓋於晶圓100 之表面上,並暴露出銲墊102之表面。而且,晶圓1〇〇更 具有一球底金屬層 104(Under Bump Metallurgy,UBM),配 置於銲墊102所暴露之表面及部份鄰近於銲墊1〇2之保護 層 106 〇 接著如第1B圖所示,於晶圓i⑻之表面上形成一光 阻層108。之後如第1C圖所示,利用曝光(ph〇t〇graphy) 及顯影(Development)等方式’在光阻層應上之對應於 銲塾102的位置,形成多個開σ嶋,並藉由開口施 暴路出球底金屬層104。 、接著如第1D圖所示,利用印刷(stencilprinting)的 方式,在開口 l〇8a内填入銲料,以於球底金屬層1〇4上形 成鮮料塊110。之後如第1E圖所*,移除光阻層1〇8,以 暴露出銲料塊110。 、最後如帛1F圖所示,進行-迴鋅(Reflow)的動作, 透過加熱的過程,使銲料塊11G處於微熔融的狀態下,並 =為其内聚力的作用’而成為—類似球體的形狀。當鲜料 塊110冷卻之後,便可在其對應的球底 球狀之凸塊ll〇a。 4 弟2圖緣示為習知完成凸塊製程之晶片與封裝基 =封裝示意圖。請共同參照第1F圖與第2圖,當完成 :100之凸塊製程之後,將對晶目1〇〇紐切割,以形 夕個獨立分開之晶片驗。接著,請參照第2圖,此曰v 1273664 95-11-13 11568twfl.doc/006 l〇〇a係以覆晶接合的方式,藉由凸塊n〇a而電性連接於 一封裝基材150之接點152。此外,更於晶片l〇〇a與封裝 基材150之間填入一底膠14〇(UnderflU),用以保護凸塊 ll〇a所裸露出之部分。 值得注意的是,上述封裝基材與晶片在受熱時,由於 熱月罗脹係數(Thermal expansion coefficient)之差異,因此會 叙生兩者所產生的熱應變(Thermal strain)不匹配的現象, 這也使得凸塊必須承受橫向之剪應力(Shear f〇rce)。當凸塊 父到的貞應力超過其承受範圍時即會產生破裂,造成晶片 與封裝基材之間的電性連接斷路。此外,藉由習知凸塊製 程所形成之凸塊,因光阻層之開口的侧壁係大致垂直於晶 圓表面,故所能填入開口之銲料的容積有限。因此,習: 凸鬼製私所a成之凸塊由於⑥度不^,所以容易被晶片與 封裝基材_熱錢所產生之剪應力破壞,使得封 ^ 。為改善此剪應力破壞之問題,可利用加長凸'塊垂 罝於晶圓表面方向之高度的方式來達到目的。 【發明内容】 四此,本發明的 从址 &你阢伢一種凸塊製程、凸女 而口製程以及封裝結構’適於增加凸塊之高度,^ 而m封裝基材之間具有高可靠度之連接關係。 基=述目的,本發明提出_種凸塊製程 ’晶_如具有多個銲墊以及用則 上,此金屬層例如係至少覆蓋住銲塾成=第^ !273664 11568 twfl.d〇c/〇〇6 95-11-13 接部’第一焊接部例如係配置於每個銲墊上方之金屬層 上。(d)形成多個似球底金屬層(pwudo—uBM)於每個第一焊 接部上。 其中,每個似球底金屬層的形成方法例如包括下列步 驟·(dl)形成一第一沾附層(wetting iayer)於第一焊接部 上。(d2)形成一阻障層(barrier iayer)於第一沾附層上。⑻) 形成一第二沾附層於阻障層上。此外,第一沾附層與第二 /占附層之材質例如係銅。阻障層之材質例如係鎳釩合金。 另外,在提供晶圓之後以及形成第一焊接部之前,例 如包括形成一圖案化光阻層於晶圓表面。其中,圖案化光 =層具有多個開口,且開口例如係將銲墊^方之金屬層暴 鉻。在似球底金屬層形成之後,例如更包括形成多個第二 焊接部於似球底金屬層上。其中,第二焊接部的形成方: 例如係電鍍或印刷。 而且,在形成苐一焊接部、似球底金屬層與第二焊接 部以及接著撥除圖案化光阻層後,例如對第一 二焊接部進行迴鲜鲁可於每個“ 结媒。 值得注意的是’在本實施例中首先係提供一具有多個 銲墊以及’護層的晶圓,之後形成—金屬層於晶圓上。 但是,任何熟習此項技術者在參照上述之揭露内容後岸 知,亦可贿供-财乡健狀封裝基觀代上述兩個 ^驟’並在封錄板上接續進行形成多個第—焊接部 續步驟。 8 1273664 11568twfl.doc/006 95-11-13 目的,本發明另提出—種凸塊結構。此凸塊 所構成。1中―卜接箱—似球底金屬層 風弟一 J:干接邛例如係配置於第一 3球=層例如,置於第—焊接部與第二焊接部之 i第-第二焊接部之外形例如係柱狀或球狀, 人入弟一焊接部之材質例如係錫錯合金、錫銀 ❼至或錫銀銅合金,並靴制其材質為相同或相显。 此金屬層例如係由一第一沾附層:、 2一=附層所構成。其中,第一沾附層例如係配置 於弟-知接部上。阻障層例如係配置於第—沾附層上。第 ==例如係配置於阻障層上。第—沾附層與第二沾附 曰之材貝例如係銅。阻障層之材質例如係鎳飢合金。 基於上述目的,本發明再提出一種雌製程,包括下 列,驟·⑻提供-晶圓’晶圓例如具有多個鮮墊以及用以 保遵晶圓並暴露出銲墊的—保護層。⑻形成—金屬層於晶 圓上至屬層例如係至少覆蓋住銲墊。⑷例如採用電鑛的 =式形成多個第-焊接部,第_焊接部例如係配置於每個 知墊上方之金屬層上。⑹形成多個似球底金屬層於每個第 :焊接部上。(e)例如採用紐或印刷的方式形成多個第二 丈干接部,第二焊接部例如係配置於每個銲墊上方之金屬層 士。(:0切割晶圓以形成多個晶片。(幻提供一封裝基材,封 裝基材之表面上例如具有多個接點。(h)例如採用迴銲的方 式接& a曰片上之弟一焊接部與封裝基材表面之接點。 其中,每個似球底金屬層的形成方法例如包括下列步 1273664 11568twfl.doc/〇〇6 95-11-13 一沾附層於第-焊接部上。(d2)形成-阻 ' /付層上。(d3)形成一第二沾附層於阻 |早增之材貝例如係鎳釩合金。 如包】二在提供晶圓之後以及形成第一焊接部之前,例 :層具有多個開口,且開口例如係將鲜塾上 …盖2上述目的,本發明更提出"*種封脑構。此封裝 :構::一封裳基材、至少-晶片與多個凸塊結構所構 X 封裝基材之表面上例如具有多個接點。晶片例 如係配置於封裝基材上方。晶片例如具有多個銲墊以及用 以保護晶片並暴露出銲墊的一保護層。此外,每個鲜塾上 例如係配置有—球底金屬層。凸塊結構例如係配置於封裝 ,材上的接點以及晶片上覆蓋銲墊的球底金屬層之間,其 詳細結構係大致與上述之凸塊結構相同。 /、 而且,封裝基材之表面上例如具有一焊罩層,配置於 接點以外^域。部份的凸塊結構中之似球底金屬層例如 係位在-第-水平高度’而其他的凸塊結構中之似球底金 屬層例如係位在一第二水平高度 綜上所述,根據本發明所提出之凸塊製程、凸塊結 構、封裝製程以及封裝結構,係以兩疊合之凸塊共同構^ 一凸塊結構,所以可以大幅增加凸塊結構之高度。因此, 在晶片與封裝基材完成封裝後,凸塊結構將對熱應力所產 I273664twfLd〇c /006 95-11-13 生之剪應力具有更高承受能力。所以,根據本發明所提出 之凸塊製程、凸塊結構、封裝製程以及封裝結構,可使凸 塊結構具有更大之高度,進而使晶片與封裝基材之間的電 性連接具有更高之可靠度。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細 說明如下。 【實施方式】 明參照弟3A〜3F圖,其依序繪示本發明一較佳實施 例之凸塊製程的剖面流程圖。首先請參照第3A圖,提供 一晶圓310,晶圓310例如具有多個銲墊314以及用以保 護晶圓310並暴露出銲墊314的一保護層316。接著,例 如形成一金屬層318於晶圓310上,金屬層318例如係覆 蓋銲墊314與保護層316。 此外,金屬層318例如係以濺鍍(Sputter)或蒸鍍 (Evaporation)的方式製作。金屬層318例如係由黏著層 (Adhesion layer)/阻障層/沾附層等三層金屬層(圖未示)所 構成。其中,黏著層係用以加強金屬層318與銲墊314之 間的結合性,阻障層係用以阻絕移動離子(m〇bile i〇ns)穿透 金屬層318而擴散到晶圓310中,而沾附層係用以加強金 屬層318與後續形成於其上之焊料的結合性。金屬層318 之材質例如係鈦/鎳釩合金/銅、鋁/鎳釩合金/銅或是其他能 達到上述目的之材質組合。 接著請參照第3B圖,形成例如一圖案化光阻層320 11 1273664 95-11-13 ll568twfl.doc/006 晶圓310上,以覆蓋住金屬層318。在本實施例中,光阻 層320例如係使用乾膜貼附形成,或是使用液態光阻以旋 轉塗佈法(Spin coating)形成。其中,圖案化光阻層32〇具 有多個開口 322,開口 322例如係位於銲墊314上方,^ 且暴露銲墊314上方之金屬層318。接著,例如係以電鍍 的方式將一銲料填入每個開口 322中,以形成多個第一^ 接部330。其中,第一銲接部33〇並不填滿開口 322。 稷者請參照第3C圖 、 -------- ^ 文、电戳双犮蒸鍍
方式形成似球底金屬層340於第一焊接部33〇上。其中 似球底金屬層340的形成方法例如係先形成一第一沾附 3j〇a於第-焊接部33〇上。接著,形成一阻障層鳩 占附層340a上。之後’再形成一第二沾附層3撕 阻障層340b上。 接著請參照帛3D圖與f 3E圖,例如係以電錢 ,方J將-銲料填人每個開口 322剩餘之空間中, =個第二銲接部350於似球底金屬層340上。接著
除。之後,將未被銲料塊330所覆蓋 =屬層3Μ移除’以形成多個球底金屬層施。當然, 在參照本案之技術内容後應可輕易推知, 行^若^成的方式亦可採科刷或是其他方式 ώ、岡安 木用17刷方式形成第一銲接部330,則可在 成圖木化光阻層32〇之前就將金 多個球底金屬居31Sa㈣〜層8圖案化,以形 部350的濟并;* 外,弟一銲接部330與第二銲 、-積可為相同或其他非1:1的比例,以期 12 127 3664gt ;wfl.doc/006 95-11-13 同配置高度之似球底金屬層34〇。 最後請參照第3E圖與第3F圖,對第-鮮接部330盘 第工銲接部350進行迴銲,以於每個球底金屬層皿上形 成-凸塊結構36G。其中,迴銲之方式例如係紅外線照射、 熟風強制對流等。
^下將介紹根據本發_提出之較佳實施例的凸塊 結構,請參照第3F圖。凸塊結構36〇係由一第一焊接部 330、:第二焊接部350與一似球底金屬層34〇所構成。其 中,第二焊接部350例如係配置於第一焊接部33〇上方。 似球底金屬層340例如係配置於第一焊接部33〇與第二焊 接部πο之間。第一焊接部330與第二焊接部35〇之外形 例如係柱狀或球狀,所以凸塊結構36〇的外型大致為長柱 形。因此,在凸塊結構具有相同總體積的條件下,可較習 知凸塊結構大幅增加其高度。此外,第一焊接部與第 二焊接部350之材質例如係錫鉛合金、錫銀合金或錫銀銅 合金,並不限制其材質之組成成分或是組成比例之異同。 此外,似球底金屬層340例如係由一第一沾附層 340a、一阻障層340b與一第二沾附層340c所構成。其中, 第一沾附層340a例如係配置於第一焊接部33〇上。阻障層 340b例如係配置於第一沾附層34〇a上。第二沾附層34二 例如係配置於阻障層340b上。第二焊接部350例如係配置 於弟二沾附層340c上。第一沾附層340a與第二沾附層34〇c 之材質例如係銅,以加強似球底金屬層340與第一銲料塊 330以及後續形成於似球底金屬層340上之銲料間的結合
13 12736¾ 568twfl.d〇c/〇〇6 95-11-13 障们働之㈣例如係軌合金,賴絕移動離子 請參照第4A〜4E圖’其依騎林發明—較 =之封裝製程的剖面流程圖。其中,第4a〜4d圖之紫程 2係與第3A〜3E _述本發日驗佳實補之凸塊製程 曰二:此即不再賢述。接著請參照帛4D〜4E圖,切割 = 形成多個晶片綱。同時,提供—封錄材別, 材^材Γϋ的表面上具有多個接點372。此外’封襄基 U 例如更具有—辉罩層374,配置於接點372 卜^區域。接著,例如採用迴銲的方式,接合晶片· 之弟二焊接部350與封裝基材37G表面之接點372。 此外,在接合晶片3〇〇與封裝基材37〇之後,更可 充一底膠380於晶片300與職基材37〇之間,用以保護 凸塊結構360所裸露出之部分並且分散應力。 值得注意的是,此封裳製程並不侷限於先在晶圓上完 成凸塊結構,凸塊結構亦可先於封裝基材上完成再與晶圓 接合’亦或是將凸塊結構之第一焊接部、第二焊接部鱼似 球底金屬層分別於晶圓與封裝基材上完成,再將晶圓與封 裝基材接合。 請參照第5A〜5F圖,其依序緣示本發明另一較佳實 施例之封裝製程的剖面流程圖。首先請參照第5A〜5c 圖,提供一晶圓410,晶圓41〇例如具有多個銲墊4i4以 及用_以保護晶圓410並暴露出銲墊414的一保護層416。 接著,例如形成一金屬層418於晶圓41〇上,金屬層418 I273664 1156 8twfl.d〇c/〇〇6 95-11-13 覆蓋銲墊414與保護層416。之後,例如係以電鍵 勺方式形成多個第一銲接部43〇於銲墊414上方之金屬層 418上。接著,例如以濺鑛、電鍍或是蒸鍍等方式形成似 =底金屬層44〇於第-焊接部43〇上。之後,將金屬層418 回案化以在每個銲墊上形成414 一球底金屬層41^。 接著明參照弟5D圖,提供一封裝基材470,封裝基 材470的表面上具有多個接點472。此外,封裝基材4几 之,面上例如更具有一焊罩層474,配置於接點472以外
之區域。接著,例如以印刷方式形成多個第二焊接塊450 於封裝基材470的接點472上。 接著請參照第5E圖與第5F圖,將第5C圖中的晶圓 410切割為多個晶片400。然後,例如採用迴銲的方式,接 合晶片400上之似球底金屬層44〇與封裝基材47〇表面之 第二焊接部450。
此外,在接合晶片400與封裝基材470之後,更可填 充一底膠480於晶片400與封裝基材470之間,用以保護 凸塊結構460所裸露出之部分並且分散應力。 第6圖緣示為根據本發明所提出之較佳實施例的封裝 結構之剖面示意圖。請參照第6圖,封裝結構5〇〇係由一 封裝基材510、至少一晶片52〇與多個凸塊結構53()所構 成。其中,封裝基材510之表面上例如具有多個接點M2。 晶片520例如係配置於封裝基材51〇上方。晶片52〇例如 具有多個銲墊522以及用以保護晶片52〇並暴露出銲墊 522的一保護層524。此外,每個銲墊522上例如係配置有 15 1273664 11568twfl.doc/006 95-11-13 一球底金屬層526。凸塊結構530例如係配置於封裝基材 510上的接點512以及晶片520上覆蓋銲墊522的球底金 屬層526之間。 此外,凸塊結構530係由一第一焊接部532、一第二 焊接部534與一似球底金屬層536所構成。其中,第一焊 接部532例如係配置於第二焊接部534上方。似球底金屬 層536例如係配置於第一焊接部532與第二焊接部534之 間。第一焊接部532與第二焊接部534之外形例如係柱狀 或球狀。此外,第一焊接部532與第二焊接部534之材質 例如係錫鉛合金、錫銀合金或錫銀銅合金,並不限制其材 質之組成成分或是組成比例之異同。似球底金屬層536之 結構與材質係與本發明所提岐佳實闕之凸塊結構的似 球底金屬層相同,於此不再贅述。另外,封裝基材51〇之 ^面上例如具有一焊罩層514,配置於接點512以外之區 域0 層別二結構530中之似球底金屬 530中之似球麻八弟水平兩度Ρ1,而其他的凸塊結構 Ρ2。直中,且有二536例如係位在一第二水平高度 別例如係編 底金屬層536的凸塊結構 層之高度的相異設計i j4 中。此種似球底金屬 強度。當然,似球底結構500具有較佳之結f 化。 -屬層536之配置高度亦可有更多 綜上所述’根據本發明所提出之凸塊製程 16 1273664 11568twfl.doc/006 95-1M3 構:程以及ί裂結構,由於似球底金屬層的隔離作 第—烊接部在迴銲之後,可藉由似球底 i屬層的刀隔而分別形成二獨立之球狀體,故可大幅辦加 f兔結狀高度。因此,在晶圓切割成多個晶片,並^覆 襞基材,連接後,凸塊結構將_應力 所蔣Ψ冑 '具有更高承受能力。也所以,根據本發明 凸塊結構、封裝製程以及封裝結構, 間的電性户進而使晶片與封衷基材之 用:二r:=i施:揭在露如上’然其並非 ===之’請專_所界定者為準。 圖。弟1A〜1F圖依序繪示一習知凸塊製程的剖面流程 封裝緣不為習知完成凸塊製程之晶片與封裝基材之 程的_精林翻—較佳實_之封裝製 製程序繪示本發㈣—較佳實施例之封裂 17 95-11-13 I273664twfi_d〇c/〇〇6 第6圖繪示為根據本發明所提出之較佳實施例的封裝 結構之剖面示意圖。 【圖式標示說明】 100 ·晶囡 l〇〇a ··晶片 102 :銲墊 106 :保護層 104 ··球底金屬層 108 :光阻層 108a :開口 110 :銲料塊 110a :凸塊 140 :底膠 150 :封裝基材 152 :接點 300、400、520 :晶片 310、410 ··晶圓 314、414、522 :銲墊 316、416、524 :保護層 318、418 ··金屬層 318a、418a、526 :球底金屬層 320 :圖案化光阻層 322 ··開口 330、430、532 :第一焊接部 95-11-13 I273664twn_d〇c/〇〇6 340、440、536 :似球底金屬層 340a、534 :第一沾附層 340b :阻障層 340c ··第二沾附層 350、450 :第二焊接部 , 360、530 :凸塊結構 370、470、510 :封裝基材 372、472、512 :接點 374、474、514 :銲罩層 _ 380、480 :底膠 500 ··封裝結構 P1 :第一水平高度 P2 :第二水平高度
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Claims (1)
1273664 11568twfl.doc/006 95-11-13 十、申請專利範圍: 1·一種凸塊製程,至少包括下列步驟: 曰口提供一晶圓,該晶圓具有複數個銲墊以及用以保護該 晶圓並暴露出該些銲墊的一保護層; 形成一金屬層於該晶圓上,該金屬層係至少覆蓋住該 些銲墊; 形成複數個第一焊接部於該些銲墊上方之該金屬層 上;以及 元成複數個似球底金屬層(pseucj〇eQBM)於該些第一 焊接部上。 其中該第 其中該些 其中該第 2·如申請專利範圍第1項所述之凸塊製程 一焊接部的形成方法包括電鍍。 3·如申請專利範圍第1項所述之凸塊製程 似球底金屬層的形成方法包括下列步驟: 形成一第一沾附層於該第一焊接部上; 形成一阻障層於該第一沾附層上;以及 形成一第二沾附層於該阻障層上。 4·如申請專利範圍第3項所述之凸塊製程 沾附層之材質包括銅。 5.如申請專利範圍第3項所述之凸塊製程,其中該第 P且P平層之材質包括鎳飢合金。 、6.如申請專利範圍第3項所述之凸塊製裎,其中該第 ‘沾附層之材質包括銅。 / 7.如申請專利範圍第i項所述之凸塊製程,其中該些 20 1273664 11568twfl.doc/006 95-11-13 似球底金屬層形成之後’更包括迴焊該些第一焊接部 8. 如申請專利範圍第i項所述之凸塊製程,其°中該些 似球底金屬層形成之後,更包括形成複數個第二焊接料 该些似球底金屬層上。 9. 如申請專利範圍第8項所述之凸塊製程,其中該第 一焊接部的形成方法包括電鍍以及印刷其中之一。 —10·如申請專利範圍第8項所述之凸塊製程,其中該些
弟二焊接部形成之後’更包括迴焊該些第—焊接部以及該 些第二焊接部。 11·如申凊專利範圍第8項所述之凸塊製程,其中提供 該晶圓之後以及形成該些第一烊接部之前,更包括形成一 圖案化光阻層於該晶圓表面,該圖案化光阻層具有複數個 開口’且該翻口係將該些銲墊上方之該金屬層暴露。 12·—種凸塊製程,適於形成複數個凸塊於一晶圓或是 一封裝基材之複數個接點上,該凸塊製程至少包括下列步 驟:
开>成複數個第一焊接部於該些接點上;以及 形成複數個似球底金屬層(Pseud〇-UBM)於該些第一 焊接部上。 —13·如申請專利範圍第12項所述之凸塊製程,其中該 第一焊接部的形成方法包括電鍍。 14·如申請專利範圍第12項所述之凸塊製程,其中該 些似球底金屬層的形成方法包括下列步驟: 形成一第一沾附層於該第一焊接部上; 21 1273664 11568twfl.doc/006 95-11-13 形成一阻障層於該第一沾附層上;以及 形成一第二沾附層於該阻障層上。 其中該 其中該 其中該 15·如申請專利範圍第14項所述之凸塊製 第一沾附層之材質包括銅。 & 斤16·如申請專利範圍第14項所述之凸塊製程 第一阻障層之材質包括鎳釩合金。 ^ 17·如申請專利範圍第14項所述之凸塊製程 第二沾附層之材質包括銅。 、 β卞〜现囷乐1z項尸斤迅之凸塊製程,其中該 些似球底金屬層形成之後,更包括迴焊該些第一焊接部。 19.如申請專利翻第12項所述之凸塊製程^豆°中該 些似球底金屬層形成之後,更包括形成複數二 於該些似球底金屬層上。 " 〜20·如申請專利範圍第19項所述之凸塊製程,其中該 第二焊接部的形成方法包括電鍍以及印刷其中之一了 μ #21.如申請專利範圍第19項所述之凸塊製程了其 些弟一焊接部形成之後,更包括迴焊該些第一 該些第二焊接部。 —_接部以及 22.如申請專利範圍第19項所述之凸塊製程, 些第-焊接部形成之前,更包括形成—圖案化光阻ς ς 晶圓或該封裝基材表面,該圖案化光阻層耳有疒㈢、Μ 口,且該些開口係將該些接點暴露。 後數個開 23·—種凸塊結構,至少包括: 一第一焊接部; 22 ^73664^^ 95-11-13 一第二焊接部,配置於該第一焊接部上方;以及 一似球底金屬層,配置於該第一焊接部與該第二焊接 部之間。 24.如申睛專利範圍第23項所述之凸塊結構,其中該 似球底金屬層包括: 一第一沾附層,配置於該第一焊接部上; 一,障層,配置於該第一沾附層上;以及 一第二沾附層,配置於該阻障層上。 斤25·如申請專利範圍第24項所述之凸塊結構,其中該 第一沾附層之材質包括銅。 26.如申請專利範圍第24項所述之凸塊 第一阻障層之材質包括鎳釩合金。 、中 第二:層申:材專質:第― 第一焊接其中該 第;===,構’其中該 第一 财23項所叙_構,立㈣ 料部之㈣紐勒合金、錫銀合金、錫銀銅合金亥 23 1273664 11568twfl.doc/006 其中之一。 十33·如申請專利範圍第23項所述之凸塊結構,其中該 第二焊接部之材質包括锡鉛合金、錫銀合金、錫銀銅合金 其中之一。 34·種封裝製程,至少包括下列步驟: 提供一晶圓,該晶圓具有複數個銲墊以及用以保護該 晶圓並暴露出該些銲墊的_保護層; 形成一金屬層於該晶圓上,該金屬層係至少覆蓋住該 些銲墊; 形成複數個第一焊接部於該些銲墊上方之該金屬層 上; 开乂成複數個似球底金屬層(pseu(j〇-UBM)於該些第一 焊接部上; ^ 將該晶圓切割成複數個晶片; &供一封裝基材,該基材之表面上具有複數個接點; 於該封裝基材之該些接點上形成複數個第二焊接 部;以及 令该些晶片上之該些似球底金屬層與該些第二焊接 部接合。 35·如申請專利範圍第34項所述之封裝製程,其中該 第一焊接部的形成方法包括電鍍。 36·如申請專利範圍第34項所述之封裝製程,其中該 些似球底金屬層的形成方法包括下列步驟: 形成一第一沾附層於該第一焊接部上; 24 I273664twfl,oc/006 95-11-13 形成一阻障層於該第一沾附層上;以及 形成一第二沾附層於該阻障層上。 37·如申請專利範圍第36項所述之封 第一沾附層之材質包括銅。 、U ’其中該 38·如申睛專利範圍第36項所述之封裝 第一阻障層之材質包括鎳釩合金。 & 一中该 39. 如中請專利範圍第%項所述之封 第二沾附層之材質包括銅。 枉其中该 40. 如申請專利範圍第34項所述之封 第二焊接部的形成方法包括電鍍以及印刷其^之_/、中该 41. 如申請專利範圍第34項所述之封&製程二 接部係藉由迴焊而與該些晶片上之該些似球^ 42. 曰如申請專利範圍第34項所述之封裂製程, 二弟一焊接部形成之前,更包括形成一圖案化 ^ 晶圓表面,該圖案化光阻層具有複數個開口 曰^亥 係將該些銲墊上方之該金屬層暴露。 開口 43·—種封裝製程,至少包括下列步驟: 提供一晶圓,該晶圓具有複數個銲墊以及 晶圓並暴露出該些銲墊的一保護層; 1示蠖该 些銲金制於該晶圓上,該金屬層係至少覆蓋住該 上形成複數個第一焊接部於該些銲墊上方之該金屬層 25 I2736^48twfl.doc/006 95-11-13 形成複數個似球底金屬層(Pseud〇_UBM)於該些一 焊接部上; _ 於该些似球底金屬層上形成複數個第二焊接部; 將該晶圓切割成複數個晶片; 、提供一封裝基材,該基材之表面上具有複數個接點; 以及 令該些晶片上之該些第二焊接部與該些接點接合。 44·如申請專利範圍第43項所述之封裝製程,其 第一焊接部的形成方法包括電鍍。 ” ^ 45·如申請專利範圍第43項所述之封裝製程,其中兮 些似球底金屬層的形成方法包括下列步驟: Λ 形成一第一沾附層於該第一焊接部上; 形成一阻障層於該第一沾附層上;以及 形成一第二沾附層於該阻障層上。 46·如申請專利範圍第45項所述之封裴製裎,其中 第一沾附層之材質包括銅。 一 ^ 47·如申請專利範圍第45項所述之封裝製裎,其中节 第一阻障層之材質包括鎳釩合金。 48·如申請專利範圍第45項所述之封裝製程,复中 第二沾附層之材質包括銅。 - —49·如申請專利範圍第43項所述之封裝製程,其中該 第二焊接部的形成方法包括電鍍以及印刷其中之一。人 5〇·如申請專利範圍第43項所述之封裝製程,其中兮 些晶片上之該些第二焊接部係藉由迴焊而與該些接點接 26 127361 fl.doc/006 95-11-13 合。 51·如申請專利範圍第幻 更包括形成-圖案化光阻層於該 且該些開口 些第-焊接部形成之前 之封裝製程,其中該 晶圓表面,該圖案化光阻層;^-圖案{ 係將該些銲塾上方之該金屬層^。個開口’ 52·—種封裝結構,至少包括· 基材之表面上具有複數個接點; 有硬數個銲墊以及用以倾該“ 保護層,其中每一該些銲塾上更配置有―:底亥的- 今曰結構,配置於觸裝基材上之該些接點與 忒曰曰片上覆盍該些銲墊之該球底金屬層之間,i 些凸塊結構包括: 八 μ 一第一桿接部; 一第二焊接部,配置於該第一焊接部上方;以及 似球底至屬層,配置於該弟^一谭接部與該第二焊接 部之間。 、53·如申請專利範圍第52項所述之封裝結構,其中該 似球底金屬層包括: 一第一沾附層,配置於該第一焊接部上; 一阻障層,配置於該第一沾附層上;以及 一弟一沾附層,配置於該卩且障詹上。 54·如申請專利範圍第幻頊所述之封裝結構,其中該 第一沾附層之材質包括銅。 、 27 rfl.doc/006 95-11-!3 rfl.doc/006 95-11-!3 其中 該 少55.如申請專利範圍第53項所述之封裝結構,其中該 第一阻障層之材質包括鎳飢合金。 〜56.如申請專利範圍第53項所述之封裳姑構 弟一沾附層之材質包括銅。 其中 其中 該 斤57.如申請專利範圍第52項所述之封襄録構’其中該 弟一焊接部之外形包括柱狀以及球狀其中之一。 該 黛-4專職㈣52項職之封裝録構 弟一知接°卩之外形包括柱狀以及球狀其中之〆。 ^如申請專利範圍第52項所述之 構 弟一知接部與該第二焊接部之材質相同。 篦申請專利範圍第52項所述之封襄始構,其中該 弟一知接部與該第二焊接部之材質相異。 —61·如申請專利範圍第53項所述之封裳结構,其中該 ^烊接部之材質包括錫錯合金、錫銀合‘、錫銀姻合金 具T之一。 〜62.如申請專利範圍第53項所述之狄構,其中該 =焊接部之材f包括錫錯合金、錫银合^錫银姻合金 具中之一。 “ 封裝魏圍第53項·之崎減,其中1 之、上更具有—料層,配置於_接點以外 份該= 申項所述,結構,其中部 高产些似球底金屬層係位在-第-水平 门度而其他该些凸塊結構中之 一第二水平高度。 二求底金屬層係位在 28 95-1M3 I273664twfl_d〇c/〇〇6 七、 指定代表圖: (一) 本案指定代表圖為:圖(6 )。 (二) 本代表圖之元件符號簡單說明: 500 :封裝結構 510 :封裝基材 512 :接點 514 :銲罩層 520 :晶片 522 :銲墊 524 :保護層 526 :球底金屬層 530 :凸塊結構 532 :第一焊接部 534 :第一沾附層 536 :似球底金屬層 P1 :第一水平高度 P2 :第二水平高度 八、 本案若有化學式時,請揭示最能顯示發明特徵 的化學式: 無
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JP4502204B2 (ja) * | 2005-03-22 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
AT506217B1 (de) * | 2008-05-28 | 2009-07-15 | Fronius Int Gmbh | Verfahren zur herstellung einer struktur an einer oberfläche eines metallischen werkstücks |
US8633592B2 (en) * | 2011-07-26 | 2014-01-21 | Cisco Technology, Inc. | Hybrid interconnect technology |
KR102007780B1 (ko) * | 2012-07-31 | 2019-10-21 | 삼성전자주식회사 | 멀티 범프 구조의 전기적 연결부를 포함하는 반도체 소자의 제조방법 |
KR102152865B1 (ko) * | 2014-02-06 | 2020-09-07 | 엘지이노텍 주식회사 | 인쇄회로기판, 이를 포함하는 패키지 기판 및 이의 제조 방법 |
US9379081B2 (en) * | 2014-03-24 | 2016-06-28 | King Dragon Nternational Inc. | Semiconductor device package and method of the same |
EP2924730A1 (en) * | 2014-03-25 | 2015-09-30 | Ipdia | Capacitor structure |
CN104505376A (zh) * | 2014-12-19 | 2015-04-08 | 华天科技(西安)有限公司 | 一种细节距钎料柱凸点互连结构及其制备方法 |
US9607973B1 (en) * | 2015-11-19 | 2017-03-28 | Globalfoundries Inc. | Method for establishing interconnects in packages using thin interposers |
US10076034B2 (en) * | 2016-10-26 | 2018-09-11 | Nanya Technology Corporation | Electronic structure |
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US5130779A (en) * | 1990-06-19 | 1992-07-14 | International Business Machines Corporation | Solder mass having conductive encapsulating arrangement |
JP2664878B2 (ja) * | 1994-01-31 | 1997-10-22 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 半導体チップパッケージおよびその製造方法 |
JP2951882B2 (ja) * | 1996-03-06 | 1999-09-20 | 松下電器産業株式会社 | 半導体装置の製造方法及びこれを用いて製造した半導体装置 |
US6642136B1 (en) * | 2001-09-17 | 2003-11-04 | Megic Corporation | Method of making a low fabrication cost, high performance, high reliability chip scale package |
JP3577419B2 (ja) * | 1998-12-17 | 2004-10-13 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
US6225206B1 (en) * | 1999-05-10 | 2001-05-01 | International Business Machines Corporation | Flip chip C4 extension structure and process |
US6281041B1 (en) * | 1999-11-30 | 2001-08-28 | Aptos Corporation | Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball |
US6333104B1 (en) * | 2000-05-30 | 2001-12-25 | International Business Machines Corporation | Conductive polymer interconnection configurations |
JP3723453B2 (ja) * | 2000-09-12 | 2005-12-07 | ローム株式会社 | 半導体装置 |
US6940178B2 (en) * | 2001-02-27 | 2005-09-06 | Chippac, Inc. | Self-coplanarity bumping shape for flip chip |
US6596621B1 (en) * | 2002-05-17 | 2003-07-22 | International Business Machines Corporation | Method of forming a lead-free tin-silver-copper based solder alloy on an electronic substrate |
US6740577B2 (en) * | 2002-05-21 | 2004-05-25 | St Assembly Test Services Pte Ltd | Method of forming a small pitch torch bump for mounting high-performance flip-flop devices |
TW578217B (en) * | 2002-10-25 | 2004-03-01 | Advanced Semiconductor Eng | Under-bump-metallurgy layer |
US7043830B2 (en) * | 2003-02-20 | 2006-05-16 | Micron Technology, Inc. | Method of forming conductive bumps |
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