TWI272481B

TWI272481B - Method and apparatus for performing multi-page write operations in a non-volatile memory system

Info

Publication number: TWI272481B
Application number: TW92125783A
Authority: TW
Inventors: Robert C Chang; Bahman Qawami; Farshid Sabet-Sharghi; Ping Li
Original assignee: Sandisk Corp
Priority date: 2002-10-28
Filing date: 2003-09-18
Publication date: 2007-02-01
Also published as: WO2004040454A3; AU2003268564A1; CN1703678A; WO2004040454A2; AU2003268564A8; TW200424846A

Abstract

Methods and apparatus for facilitating multi-page or multi-block operations within a non-volatile memory system. According to one aspect of the present invention, a method for performing a multi-page command includes obtaining a first page number of a first convention that identifies a first page associated with a non-volatile memory, and mapping the first page number to a second page number of a second convention. Like the first page number, the second page number also identifies the first page. Mapping the first page number to the second page number includes identifying a total number of districts associated with the non-volatile memory and a total number of pages associated with each block of a total number of blocks. Finally, the first page is accessed using the second page number and the multi-page command.

Description

1272481 玫、發明說明： t發明所屬技術領域】發明領域本發明係有關於下列共同待審中之美國專利申請案： 5 在2002年10月28日提出申請之美國專利申請案第 10/281，739號案，發明名稱為：非依電性儲存系統之磨損調勻技術（代理人文件編號：SANDP023/SDK0366.000US);在 2002年10月28曰提出申請之美國專利申請案第10/281，67〇號案’發明名稱為：追蹤非依電性記憶體系統中最常抹除 10區塊之技術（代理人文件編號： SANDP025/SDK0366.002US);在 2002年 10月 28 日提出申請之美國專利申請案第1〇/281，824號案，發明名稱為：追蹤非依電性記憶體系統中最不常抹除區塊之技術（代理人文件編號·· SANDP026/SDK0366.003);在2002年 10月 28 日提出 15申請之美國專利申請案第1〇/281，631號案，發明名稱為：用以分割邏輯區塊之方法與裝置（代理人文件編號： SANDP028/SDK0371.000US);在 2002年 10 月 28 日提出申請之美國專利申請案第10/281,855號案，發明名稱為：用以將區塊中之頁面分組之方法與裝置（代理人文件編號： 20 SANDP029/SDK0410.000US);以及在 2002 年 10 月 28 日提出申請之美國專利申請案第10/281,762號案，發明名稱為··用以分解與共用邏輯區塊相關聯之實體區塊的方法與裝置 (代理人文件編號·· SANDP030/SDK0416.000US);其中，該等申請案之全部内容係包含於此處以作為參考之用。 !272481 本發明大致係有關於大量數位資料儲存系統。更詳而 I本發明係有關於用以容許實質地同時以有效率之方式存取非依電性記憶體系統之多頁的系統與方法。【先前技術】發明背景諸如快閃記憶體儲存系統之非依電性記用係因此等印愔駚备„ 糸、、死之使體錢之緊密實體大小及可重複再規割非 10 15 =電性記憶體之能力而增加。快閃記憶體儲存系統之緊密貝體幻可促進將此等儲存系統使用於日漸普及之裝置内使用决閃疏體儲存系統之裝置包括(但不限於)數位相機、數位攝錄放影機、數位音_放器、手持式個人電腦、以及全球定㈣置等。可重複再規劃包括於快閃記憶體儲存系、’充之非依電性記憶體之能力允許㈣記憶體儲存系統之使用與再使用。 '' 邊又而3，快閃記憶體儲存系統可包括快閃記憶體卡及快閃Zfe體晶片組。快閃記憶體晶片組一般而言包括快閃記憶體構件以及控制器構件。通常，快閃記憶體晶片組係排置為可構組於置入式系統。此等總成或主機系統之製 20造者通书取得構件形式之快閃記憶體，以及其他構件，而後將快閃記憶體及其他構件構組為主機系統。自陕閃5己憶體讀取資料、抹除快閃記憶體之資料、及將資料寫入陕閃記憶體之處理係相對地耗費時間，特別係當貢料夏相對地高的時候。詳言之，當頁係重複或實質地 1272481 連繽存取時，為執行讀取操作、抹除操與存取快議體之頁有關的存取時間㈣明：入操作之要的。藉由_ ’每次快閃記憶體之駿存取2相當重被寫入頁時，存取時間可纽供二進錄使崎可 5 250微秒⑽及供多位準晶胞(MLC)快閃記憶體思用體用之約 (ms)。當欲寫入許多頁日夺，與將資料寫入許之1宅秒存取時間可高至以明顯地影響整體關之總能。 U體糸統之性因此’吾人所需者係可用以減少與非依電亦即’吾人所需者係可實質地藉由減少與非依電性Γ二之頁之貢料的讀取、抹除、或寫入有關之有致存取心月b改進非依電性記憶體系統之性能的處理及系統。 15 【發明内容】發明概要本發明係有關於用以促進非依電性記憶體系統之多頁或多區塊操作之系統及方法。根據本發明之一態樣，用以執行多頁命令之方法包括獲得第一慣則之可識別與非依電 2〇性記憶體有關的第—頁的第一頁數，及令第一頁數對映於第二慣則之第二頁數。如同第一頁數，第二頁數亦可識別第一頁。令第一頁數對映於第二頁數包括識別與非依電性記憶體有關之總區數及與總區塊數之每一區塊有關的總頁數。最後，第一頁係使用第二頁數及多頁命令而存取。 1272481 於一實施例中，此方法亦包括獲得第一慣則之可識別第二頁之第三頁數，令第三頁數對映於第二慣則之亦可識別第二頁之第四頁數，及使用第二頁數存取第一頁及實質地同時使用第四頁數存取第二頁。於此實施例中，存取第 5 一頁及存取第二頁可包括將資料寫入第一頁及第二頁與自第一頁及第二頁抹除資料中之一者。對多頁寫入處理而言，其可實質地一次寫入不同區之數頁。將此等多頁分組，使得快閃記憶體之每一區之一頁可實質地一次寫入，可容許與整體讀取與寫入處理有關之 10 時間量有效地減少。藉由有效地佈局記憶體，使得當使用者嘗試寫入資料於頁時，使用者可指定使用者慣則之有效地連續頁數，則使用者對記憶體之存取可有效率地發生。將使用者慣則之頁數轉換或對映為實際頁數可容許多頁命令被執行。當轉換或對映有效率地發生時，完成多頁寫入 15 處理所需之整體時間量可被減少，藉此增進包括快閃記憶體之整體系統之性能。供多頁寫入處理用之命令通常係命名為「多區塊規劃」操作，因為來自多個區塊之每一者之頁係同時於一單一存取時間被寫入。根據本發明之另一態樣，用以組織非依電性記憶體之 20 數個包括具有頁之區塊的區的方法包括將第一慣則之第一頁數分配予和第一區有關之第一頁，及將第二頁數分配予和第二區有關之第二頁。使用與包括於數區之總區數及與包括於第一區之總頁數有關之資訊，第一頁數係排置為可被轉換為與第一頁有關之第一實體頁數，且第二頁數係排 1272481 置為可被轉換為與第二頁有關之第二實體頁數。於一實施例中，與包括於數區之總區數及與包括於第一區之總頁數有關之資訊係至少部份地含於一資料結構，如查詢表之釋例所示。 5 根據本發明之再另一態樣，用以使用共同命令致動分組為排置為區之群組的記憶體元件被存取之方法包括使用第一慣則之識別器識別數個記憶體元件，及將第一慣則之識別器轉換為第二慣則之識別器。第二慣則之識別器係對應於非依電性記憶體之記憶體元件之實際位置。將第一慣 10 則之識別器轉換為第二慣則之識別器包括使用與總區數有關之資訊、與包括於每一群組之記憶體元件總數有關之資訊、及第一識別器。最後，此方法包括使用共同命令存取數個記憶體元件。於一實施例中，使用與總區數有關之資訊、與包括於 15 每一群組之記憶體元件總數有關之資訊、及第一識別器，將第一慣則之識別器轉換為第二慣則之識別器包括對包括與第二慣則的識別器有關之資訊的資料結構編索引。於此實施例中，此資料結構可為查詢表。於另一實施例中，此等群組可為區塊且記憶體元件可為實體頁。 20 於閱讀下文之詳細說明及研討圖式之各種圖表後，本發明之此等及其他優點將更為清楚。圖式簡單說明藉由參考附隨圖式及下文之詳細說明可對本案有最佳之瞭解，其中： 1272481 第la圖係包括非依電性記憶體的一般主機系統之圖式表示。第lb圖係諸如第la圖的記憶體裝置120之記憶體裝置之圖式表不。 5 第lc圖係包括置入式非依電性記憶體之主機系統之圖式表示。第2a圖係根據本發明之一實施例之非依電性記憶體的區塊之圖式表示。 φ 第2 b圖係根據本發明之一實施例之諸如第2 a圖的被分 10 組為區之區塊202之非依電性記憶體的區塊的圖式表示。第3a圖係根據本發明之一實施例之諸如第2b圖的區 212的非依電性記依體構件之區的圖式表示。第3b圖係根據本發明之一實施例之被分組為多頁區段之非依電性記依體構件之頁的圖式表示。 15 第4圖係根據本發明之一實施例之頁已被分配轉換頁數之非依電性記憶體之區的圖式表示。 · 第5圖係根據本發明之一實施例之將與非依電性記憶體之區塊有關之轉換頁數對映為實際實體頁數之對映的圖式表示。 20 第6圖係根據本發明之一實施例之被分組為區及單元之具有轉換頁數的數個區塊之圖式表示。第7圖係根據本發明之一實施例之可被用以促進多頁存取或規劃操作的查詢表之圖式表示。第8圖係根據本發明之一實施例之說明與執行諸如系 10 1272481 統之非依電性記憶體系統的多頁寫入操作之處理有關之步驟的處理流程圖。第9圖係根據本發明之一實施例之說明與牽涉使用查詢表之多頁寫入處理有關之步驟的處理流程圖。 5 第10圖係根據本發明之一實施例之說明與執行諸如系統之非依電性記憶體系統的讀取操作之處理有關之步驟的處理流程圖。第11圖係根據本發明之一實施例之說明與牽涉使用查詢表之讀取處理有關的步驟的處理流程圖。 10 第12圖係根據本發明之一實施例之系統架構的圖式方塊圖表不。【實施方式】較佳實施例之詳細說明 15 減少讀取、抹除、或寫入諸如NAND快閃記憶體之非依電性記憶體之資料所需之負擔量可致動包括非依電性記憶體之整體系統的性能之改進。通常，非依電性記憶體系統之單一頁係於任意給定時間存取，例如，對非依電性記憶體之一存取時間。由於寫入一頁之存取時間之範圍可自 20 供二進位快閃記憶體用之約250微秒（// s)至供多位準晶胞 (MLC)快閃記憶體用之多於約一毫秒(ms)，多寫入處理係相對地耗費時間，且因此，不利地影響整體非依電性記憶體系統之性能。為有效地減少於非依電性記憶體執行諸如寫入操作之 11 A，7248l k作所需之時間量，亦即，為增進整體系統之寫入速度，頁可於任一時間被寫入。亦即，實質地於單一存取時間致動多於一頁被寫入之多頁寫入操作可被實施。一般而 ° ’致動夕頁規劃而使多頁可一起被規劃，例如寫入、或 5 士矣 ’取、或抹除可減少與規劃處理有關之時間量。舉例言之， §賁料係實質地於相同時間被寫入MLC快閃記憶體之四頁日可’寫入處理所使用之整體時間量可自約四ms減少為約一。因此，寫入操作可更有效率地發生。快閃記憶體系統，或更一般言之，可自將資料讀取、 1〇抹除、及寫入頁或區塊之多頁命令之使用獲得利益的非依黾性記憶體裝置，一般而言包括快閃記憶體卡及晶片組。通常，快閃記憶體系統係被用以與主機系統一起使用，以使此主機系統可將資料寫入快閃記憶體系統或自快閃記憶體系統讀取資料。然而，某些快閃記憶體系統包括置入式 15 快閃記憶體及執行於主機上以實質地作用為供置入式快閃記憶體用之控制器之軟體，如下文將參考第lc圖說明者。參考第la圖，其將說明包括諸如緊密快閃記憶體 (CompactFlash Memory)卡之非依電性記憶體裝置之一般主機系統。主機或電腦系統100—般而言包括容許微處理器 20 108、隨機存取記憶體(RAM)112、及輸入/輸出電路116通信之系統匯流排104。應瞭解者為，主機系統100可一般地包括其他構件，例如因供說明之故而未顯示之顯示器裝置及網路裝置。一般而言，主機系統100可捕捉包括（但不限於)靜態影 12 1272481 =訊、音頻資訊、及視頻影像資訊等資訊。此種資訊可 ^ 並以热線方式傳送至主機系統100。在主機系統可貝貝地為任意系統的同時，主機系統觸通常係為諸、數位相機、視頻攝影機、蜂巢式通信I置、音頻播放器、或視頻—播放ϋ。然而，應瞭解者為，_般而言，主機系統立/可U地為可儲存資料或資訊，及檢索資料或資訊之任意系統。 10 15 20 《主機系統100亦可為僅捕捉資料，或僅檢索資料之系亦即於一貫施例中，主機系統100可為儲存資料之專系、先或主機系統觸可為讀取資料之專用系統。藉由釋例:主機系統⑽可為排置為僅寫人或儲存資料之記憶體寫、时任擇地，主機系統100可為諸如通常係排置為可讀取或檢索貧料，且未捕捉資料之MP3播放器之裝置。在一實施例中係為可移除之非依電性記憶體裝置之非又電〖生°己丨思體裝置120係被排置為可與匯流排104介接以儲存貢訊。任選輸入/輸出電路區塊13〇可容許非依電性記憶體衣置120間接地與匯流排1〇4介接。當以前述方式實施吩，輸入/輸出電路區塊132係作用為可減少匯流排1〇4之負載如同热於此技者可瞭解者。非依電性記憶體裝置12〇包括非依電性記憶體124及任選記憶體控制系統128。於一實施例中，非依電性記憶體裝置12〇可實施於一單晶片或晶粒上。任擇地，非依電性記憶體裝置120可實施於一多晶片模組’或可形成一晶片組且可一起使用以作為非依電性記憶體裝置120之多個分散構件上。非依電性記憶體裝置120之 13 1272481 一實施例將參考第比圖於下文作更為詳細之說明。非依電性記憶體124，例如諸如NAND快閃記憶體之快閃€ fe體，係排置為可儲存資料，使得資料可於需要時被存取及續取。儲存於非依電性記憶體124之資料亦可於適合 5時抹除，雖然應瞭解者為，非依電性記憶體124内之某些資料係為不可抹除。儲存資料、讀取資料、及抹除資料等處理一般而言係由記憶體控制系統128所控制，或於未存有圮憶體控制系統128時，藉由以微處理器108所執行之軟體控制。非依電性記憶體124之操作可藉由本質地令非依電性記 10憶體124之扇區更為實質地且平均地磨損而加以管理，以使非依電性記憶體124之壽命可實質地最大化。非依電性記憶體裝置12〇已大致地說明為包括任選記憶體控制系統128，亦即控制器。通常，非依電性記憶體裝置120可包括供非依電性記憶體124用之分離晶片，且記憶 15體控制系統128，亦即控制器發揮功用。藉由釋例，於包括 (但不限於)PC卡、緊密快閃記憶體卡、多媒體卡、及保全數位卡之非依電性§己憶體裝置包括可實施於分離晶片之控制器的同時，其餘非依電性記憶體裝置可不包括實施於分離晶片之控制裔。於非依電性記憶體裝置120並未包括分離 20記憶體及控制裔晶片之一實施例中，記憶體及控制器功能可集積於單一晶片，如同熟於此技者所瞭解者。任擇地，圮憶體控制系統128之功能性可藉由微處理器1〇8而提供，如同上文所述之非依電性記憶體裝置12〇並未包括記憶體控制器128之實施例。 14 1272481 參考第lb圖，根據本發明之一實施例，非依電性記憶體裝置120將更為詳細地說明。如同上文所說明者，非依電性記憶體裝置120包括非依電性記憶體124且可包括記憶體控制系統128。雖然於記憶體124係為諸如置入式NAND裝 5置時，非依電性記憶體裝置120可不包括控制系統128，但記憶體124及控制系統128，或控制器可為非依電性記憶體裝置120之主要構件。記憶體124可為形成於半導體基板上之記憶體晶胞陣列，其中，資料之一或多個位元係藉由將電荷之二或更多位準中之一者儲存於記憶體晶胞之個別儲 10 存元件而儲存於個別記憶體晶胞。非依電性快閃電氣可抹除唯讀記憶體(EEPROM)係為供此種系統用之常見形式記憶體之釋例。當以前述方式實施時，控制系統128係經由匯流排15而與主機電腦或其他使用記憶體系統之系統通信以儲存資 15 料。一般而言，匯流排15係為第1圖之匯流排1〇4之部份。控制系統128亦控制可包括記憶體晶胞陣列^之記憶體124 之操作以寫入藉由主機所提供之資料、讀取主機所要求之貧料、並貫施各種标作記憶體124之雜務功能。一般而t，控制系統128包括具有相關非依電性軟體記憶體、各種邏輯 20 電路、及類似物之一般目的微處理器。一或多個狀態機亦經常被包括以控制特定常式之性能。於一實施例中，記憶體晶胞陣列11通常係藉由控制系統128或微處理器108而經由位址解碼器17定址。於此實施例中，解碼器17應用正確電壓於陣列11之閘極與位元線以 15 1272481 規^貝料而自藉由控制系統128定址之記憶體晶胞群組讀取貢料或抹除藉由控制系統128定址之記憶體晶胞群組。額外電路19包括控制取決於被規劃於晶胞之定址群組之資料而應㈣陣列元件的電壓的規劃驅動器。電路19亦包括感 5應放大器及其他自記憶體晶胞之定址群組讀取資料所需之電路:欲規劃於陣列η之資料，或最近自p車列11讀取之資料通$係儲存於控制系統128之緩衝器記憶體η。控制系統 128通$亦含有各種供用以暫時地儲存命令及狀態資料與馨類似物之暫存器。 10 陣列11被劃分為大量之區塊〇(BLOCK 0)至區塊 N(BLOCK N)記憶體晶胞。如同對快閃EEpR〇M系統而言係為晋通的，區塊通常係抹除之最小單元。亦即，每一區塊含有最小數目之一併被抹除之記憶體晶胞。每一區塊通常係劃分為數頁。如熟於此技者將可瞭解者。頁可被認為係 15規劃之最小單元。亦即，基本規劃操作可將資料寫入記憶體曰曰胞之最小一頁或自記憶體晶胞之最小一頁讀取資料。一或多個資料扇區通常係儲存於每一頁内。如第lb圖所示，一扇區包括使用者資料及負擔資料。負擔資料通常包括自扇區之使用者資料計算之錯誤校正碼(ECC)。當資料係 2〇被規劃於陣列11時，控制系統128之部份23可計算ECC，並於資料係自陣列11讀取時，檢查ECC。任擇地，ECC係儲存於與其所附屬之使用者資料不同之頁或不同之區塊。對應於磁碟驅動機之扇區大小，使用者資料扇區通常係為512位元組。負擔資料通常係為額外之16位元組。資料 16 1272481 羽區隶#見者係被包括每一頁，但二或更多扇區可代之以幵y成頁。一般而言，任意數目之頁可形成一區塊。藉由釋例，區塊可自8頁至512、1024或更多頁而形成。區塊數目係被選擇以提供系統記憶體所欲之資料儲存容量。 5陣列11通常係被分割為數個次陣列(未顯示》每一次陣列含有區塊比例’其於某種程度上係彼此獨立賴作以增加各種記憶體操純行之平行性程度。數個次陣列之使用之一釋例係說明於美國專利第5,890，192號，該專利之全部内容在此係作為本發明之參考資料。 1〇於一實施例中，非依電性記憶體係被置入於諸如主機系統之系統中。第1〇圖係包括置入式非依電性記憶體之主機系統之圖式表示。一般而言，主機或電腦系統15〇包括容 • σ午主機系統150之其他構件（未顯示）之微處理器158、 RAM162、及輸入/輸出電路166通信之系統匯流排154。諸 15如快閃記憶體之非依電性記憶體17 4容許資訊被儲存於主機系統150。介面180可被提供於非依電性記憶體174及匯流排154間，以令資訊可自非依電性記憶體174讀取及將資訊寫入非依電性記憶體174。非依電性記憶體174可藉由有效地執行被排置為可控 20制非依電性記憶體174之軟體或軔體中之一者或全部的微處理器158而加以管理。亦即，微處理器158可執行諸如軟體碼裝置或軔體碼裝置等容許控制非依電性記憶體174之碼裝置（未顯示）。可為與微處理器158内部之CPU封裝之快閃兄憶體、分離快閃ROM、或位於非依電性記憶體174内部 17 1272481 之此等碼裝置，如將於下文說明者，可令非依電性記憶體 174内部之實體區塊被定位址，且可將資訊儲存於實體區塊、可自實體區塊讀取資訊、及自實體區塊將資訊抹除。一般而言，當使用者寫入資料時，使用者有效地將資 5料寫入媒體，例如諸如快閃記憶體卡或包括快閃記憶體置入於其間之系統的非依電性記憶體系統之例。如熟於此技者將可瞭解者’使用者可指定欲將資料寫入之區塊或甚至可指定欲將資料寫入之頁。諸如第la圖之非依電性記憶體 124、或第lc圖之非依電性記憶體174之非依電性記憶體通 10常被劃分為區塊，如同前文所述。第2a圖係根據本發明之一實施例之非依電性記憶體的區塊之圖式表示。非依電性記憶體可被劃分為個別與邏輯區塊（未顯示）有關之實體區塊0」至N」202。於所不之實施例中，每一區塊202皆包括約二十一頁，雖然應瞭解者為，一般而言，區塊202可 15包括任意數目之頁，諸如六十四頁。一般而言，區塊202之數目與包括於區塊202之頁的數目可取決於非依電性記憶體之大小。通常，區塊202之頁係實質地連續。亦即，如圖所示，可為非依電性記憶體之第一區塊之區塊「〇」2〇2a包括頁〇 20至31。一般而言，非依電性記憶體之下一區塊係為包括頁 32至63之區塊「1」2〇2b。一般而言，非依電性記愧體之區塊202係為連續，且一般而言，區塊2〇2之頁亦為連續。區塊202可被分組為區，如第2b圖所示。區塊2〇2可被分組之區212之數目係取決於欲於一讀取處理、抹除處理、 18 1272481 或寫入處理一次存取之頁數，且因此，可廣泛地改變。舉例言之，區塊202可被分組之區數可自實質地同時存取約兩頁時之約二區至實質地同時存取約三十二頁時之約三十二區。 5 區塊係分組為四區212。因此，每四區塊212¾:分組為一特定區212。藉由釋例，區塊「〇」2〇2a及區塊「4」202e 係包括於區「0」212a，同時區塊「1」2〇2b、區塊「5」202h、及區塊「N-2」202k係包括於區「1」212b。更一般言之，具有區塊數為四的倍數之區塊202可被包括於區「〇」212a、 10具有區塊數為四的倍數加一之區塊2〇2可被包括於區「1」 212b、具有區塊數為四的倍數加二之區塊2〇2可被包括於區「2」212c、且具有區塊數為四的倍數減一之區塊2〇2可被包括於區「3」212d。第3a圖係根據本發明之一實施例之諸如第处圖的區 15 212之非依電性記憶體構件之區的圖式表示。如圖所示，具有區塊數為四的倍數之實體區塊2〇2係有效地對齊於區「〇」 212a，同時，具有區塊數為四的倍數加一之實體區塊2〇2係有效地對齊於區「1」212b等。應瞭解者為，一般而言，區 212可包括任思數目之區塊2〇2。通常，包括於每一區212之 20區塊202之數目係取決於包括，但不限於被劃分為區塊202 之非依電性記憶體構件之整體大小、區212之數目、及包括於每一區塊202之頁數等因子。一般而言，每一區212之單一頁可實質地於相同時間被存取，例如，如同多頁區段，使得每一區212之頁可於單一 19 !272481 存取時間被抹除或寫入。亦即，具有相對於區212之個別區塊起點之相同頁偏移的實體頁302可使用諸如多區塊或多頁規劃命令之多區塊存取命令而存取為單元3〇4，如第％圖所示。為致動多頁寫入之發生，使得諸如多連續頁之多頁 5皆實質地被一次寫入，與每一區212有關之頁可於單一存取時間被存取。藉由釋例，區「〇」212a之頁「12」302a、區 1」212b之頁「44」302b、區「2」212c之頁「76」302c、及區「3」212d之頁「108」302d可實質地使用單一多區塊參規劃命令而被寫入。 10 一般而言，可有效地使用多區塊命令存取之頁數可取決於區塊202已被分組之區212之數目。舉例言之，若有四區212，則個別皆位於不同區212之四頁可被分組為實質地於相同時間被存取之多頁區段。任擇地，當有八區時，與每一區有關之一頁可使用多區塊或多頁命令而被存取，使 15得此等八頁可貫質地於相同時間被存取。如前文所述，藉由一次存取多頁，與諸如讀取、抹除、及寫入操作之處理 _ 有關之時間量可被減少，藉此可增進整體非依電性記憶體系統或快閃記憶體系統之性能。當數頁同時被寫入時，於多頁寫入命令期間，對記憶 20體之不同區之貝貝連續頁的存取通常係吾人所欲的。由於欲寫入之頁被寫入不同區且每一區通常具有其所有之資料快取(cache)，使用者資料多頁可被傳送至多區資料快取。而後，使用者資料多頁可同時於單一存取時間被規劃於非依電性記憶體。 20 1272481 為促進供使用者（亦即，希冀存取非依電性記憶體系統之非依電性記憶體之實體頁之個人）用之規劃操作，與諸如第3b圖所示之實體頁有關之頁數可實質地被轉換為使用者或轉換頁數。頁數之轉換可使頁數以上升順序跨區分配。 5 第4圖係根據本發明之一實施例之頁已被分配轉換頁數的非依電性記憶體之區的圖式表示。區412係排置為可使區「0」412a包括具有為區412之總數的倍數(例如四倍）的區塊數420的區塊402。類似地，區「1」412b包括具有為區412 之總數的倍數加一之區塊數420的區塊402，區「2」412c包 10 括具有為區412之總數的倍數加二之區塊數420的區塊 402，且區「3」412d包括具有為區412之總數的倍數加三之區塊數420的區塊402。區412之區塊402可被組織為具有單元數430之單元。單元數430可有效地識別區412之區塊402之位置。舉例言之， 15 單元數「〇」430a可識別每一區412之第一區塊402。詳言之，區「0」412a之區塊402a、區「1」412b之區塊402b、區「2」 412c之區塊402c、及區「3」412d之區塊402d係個別與單元數「0」430a有關。於包括於區塊402之實際頁數係具有實體頁數之實體 20頁的同時，如下文將參考第5圖說明者，使用者或轉換頁數之使用可令使用者更輕易地指定其所希冀於單一存取時間存取支持多於一頁之存取的整體系統的頁數。通常，當頁於多頁區段存取時，存取頁係與相同單元數430有關。藉由釋例，單元數「0」430a之頁可使用多頁存取命令同時存取。 21 1272481 如前所述，旱元數「0」430a包括每一區412之一區塊42〇。因此，來自區塊420a至d之每一者之頁可被存取為單元數「〇」43〇a之多頁區段之部份。當使用者指定其所希冀存取之轉換頁數時，一般而 5言，轉換頁數係被轉換或對映於可供控制器軔體或軟體使用以存取適當頁之實際頁數。第5圖係根據本發明之一實施例之將與非依電性圯憶體之區塊有關之轉換頁數對映為實際實體頁數之對映的圖式表示。當多頁區段53〇係使用單一存取時間而欲抹除或欲寫入時，一般而言，具有來自每一 10區412之一區塊502之轉換頁數504係包括於區段530。藉由釋例，當欲於單一存取時間存取多頁區段53〇時，控制器軔體或軟體將通常有效地存取具有轉換頁數5〇4之頁。包括具有轉換頁數504之多頁區段53〇可有效地被對映於包括具有對應於具有轉換頁數5〇4之實際實體頁數5〇4, 15的頁之多頁區段530，。詳言之，當使用者指定具有欲存取以供讀取、抹除、或寫入目的之轉換頁數5〇4的頁時，控制器軔體或軟體通常判定具有實際頁數别，之頁係對應於具有轉換頁數504之頁。藉由釋例，當多頁區段5純括具有為轉換頁數「8」、「9」、「！〇」、及「11」之轉換頁數504之 20頁日π ’控制為軔體或軟體可判定多區段53〇對應於包括具有個別為實際實體頁數「2」、「34」、「66」、及「98」之實際貫體頁數504’之頁的多頁區段53()，。換言之，轉換頁數「8」係對映於實際實體頁數「2」、轉換頁數「9 」係對映於實際貫體頁數「34」、轉換頁數「1〇」係對映於實際實體頁數 22 1272481 「66」、且轉換1數「u」係對映於實際實的數「98。為使轉換頁數對映於實際實體頁數，或更—卜= 為使第-慣則之頁數對映於第二_之^，__胃數之數學演算法可被_判定實際實體紐。於中，此種演算法包括使用查詢表’如將參考第7圖說:：。及包括具有轉 -般而言，令實際實體頁數可被㈣給定轉換頁數之演曾法或計算包括判定相關區數、相關單元數、換頁數之頁的區塊之位置或偏移。FIELD OF THE INVENTION The present invention is related to the following copending U.S. Patent Application: U.S. Patent Application Serial No. 10/281, filed on Oct. 28, 2002. Case No. 739, the name of the invention is: Wear and Leveling Technology for Non-Electrical Storage Systems (Attorney Docket No.: SANDP023/SDK0366.000US); U.S. Patent Application Serial No. 10/281, filed on Oct. 28, 2002, The 67 nickname 'invention' name is: Tracking the most commonly used technique for erasing 10 blocks in non-electrical memory systems (agent file number: SANDP025/SDK0366.002US); filed on October 28, 2002 U.S. Patent Application Serial No. 1/281,824, entitled "Tracking the Most Infrequently Erasable Blocks in Non-Electrical Memory Systems (Agent File Number··SANDP026/SDK0366.003); U.S. Patent Application Serial No. 1/281,631, filed on Oct. 28, 2002, entitled,,,, ); in 2002 10 U.S. Patent Application Serial No. 10/281,855, filed on Jan. 28, the title of which is: the method and apparatus for grouping pages in a block (attorney file number: 20 SANDP029/SDK0410.000US); U.S. Patent Application Serial No. 10/281,762, filed on Oct. 28, 2002, the disclosure of which is incorporated herein by reference. SANDP030/SDK0416.000US); the entire contents of each of which are incorporated herein by reference. !272481 The present invention is generally directed to a large number of digital data storage systems. More specifically, the present invention relates to systems and methods for allowing multiple pages of a non-electrical memory system to be accessed substantially simultaneously and efficiently. [Prior Art] Background of the Invention Non-electricity recording systems such as flash memory storage systems are therefore required to print „ 、、、、、、、、、、、、、紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密紧密The ability to increase the capacity of electrical memory. The close-up of the flash memory storage system can facilitate the use of such storage systems in devices that are increasingly popular in devices using, but not limited to, digital devices. Cameras, digital video recorders, digital sounders, handheld personal computers, and global (four) devices. Repeatable re-planning included in flash memory storage, 'charged non-electric memory The ability allows (4) the use and reuse of the memory storage system. '' Side by side, the flash memory storage system may include a flash memory card and a flash Zfe body chip set. The flash memory chip set is generally Including flash memory components and controller components. Typically, the flash memory chipset is arranged to be grouped in a built-in system. The assembly or host system is in the form of a component. Flash flash Body, and other components, and then flash memory and other components into a host system. Read data from the Shanyin 5 memory, erase the flash memory data, and write the data into the Shaanxi flash memory The processing is relatively time consuming, especially when the tribute is relatively high in summer. In particular, when the page is repeated or substantially 1,272,481 consecutive accesses, in order to perform read operations, erase operations and access The access time of the page of the fast object (4) is as follows: the operation is required. By _ 'every flash memory access 2 is quite heavily written to the page, the access time can be added to the second Recording can be 5 250 microseconds (10) and for multi-level cell (MLC) flash memory thinking about the use of the body (ms). When you want to write many pages, and write the data to the 1 The access time of the homes can be as high as to significantly affect the overall energy of the whole. The nature of the U-system is therefore 'the ones we need can be used to reduce the non-electricity, that is, the people who need it can actually borrow By reducing the reading, erasing, or writing of the quarantine of the non-electrical Γ2 page, the access is improved. SUMMARY OF THE INVENTION The present invention relates to systems and methods for facilitating multi-page or multi-block operation of a non-electrical memory system. In one aspect of the invention, a method for executing a multi-page command includes obtaining a first arbitrarily identifiable first page number of a first page related to a non-electrical memory, and making the first page number The second page number reflected in the second habit. Like the first page number, the second page number can also identify the first page. The first page number is reflected on the second page number including the identification and non-electricity memory. The total number of pages and the total number of pages associated with each block of the total number of blocks. Finally, the first page is accessed using the second page number and multiple page commands. 1272481 In an embodiment, the method It also includes obtaining the third page of the first identifiable second page, so that the third page is reflected in the second rule, and the fourth page of the second page is also recognized, and the second page is used. Accessing the first page and substantially simultaneously accessing the second page using the fourth page number. In this embodiment, accessing the fifth page and accessing the second page may include writing data to the first page and the second page and erasing the data from the first page and the second page. For multi-page write processing, it can write pages of different regions substantially at a time. These multiple pages are grouped such that one page of each zone of the flash memory can be substantially written once, allowing for an effective reduction in the amount of time associated with the overall read and write process. By effectively arranging the memory, when the user attempts to write data to the page, the user can specify the number of consecutive pages of the user's habit, and the user's access to the memory can occur efficiently. Converting or mapping the number of pages of the user's habits to the actual number of pages allows for many page commands to be executed. When conversion or mapping occurs efficiently, the overall amount of time required to complete the multi-page write 15 process can be reduced, thereby enhancing the overall system performance including the flash memory. The command for multi-page write processing is usually named "Multi-block planning" operation because the pages from each of the multiple blocks are simultaneously written at a single access time. According to another aspect of the present invention, a method for organizing 20 non-electrical memory blocks including a block having a page includes assigning a first page number of the first rule to the first region The first page, and the second page is allocated to the second page related to the second zone. Using the information relating to the total number of zones included in the number zone and the total number of pages included in the first zone, the first page number is arranged to be converted into the first physical page number associated with the first page, and The second page number row 1272481 is set to be converted to the second physical page number associated with the second page. In one embodiment, the information relating to the total number of zones included in the number zone and the total number of pages included in the first zone is at least partially contained in a data structure, as illustrated by the interpretation of the lookup table. In accordance with still another aspect of the present invention, a method for accessing a memory element grouped as a group of zones using a common command comprises using a first conventional identifier to identify a plurality of memories The component, and the identifier that converts the first conventional identifier into the second inertia. The second conventional identifier corresponds to the actual position of the memory component of the non-electrical memory. Converting the first conventional recognizer to the second customary recognizer includes using information relating to the total number of zones, information relating to the total number of memory components included in each group, and a first recognizer. Finally, the method involves accessing several memory elements using a common command. In one embodiment, the information of the total number of zones is used, the information related to the total number of memory components included in each group of 15 is used, and the first identifier is used to convert the first conventional identifier into a second The idiom recognizer includes an indexing of the data structure including information relating to the identifier of the second idiom. In this embodiment, the data structure can be a lookup table. In another embodiment, the groups can be tiles and the memory elements can be physical pages. These and other advantages of the present invention will become more apparent after reading the detailed description of the <RTIgt; BRIEF DESCRIPTION OF THE DRAWINGS The present invention can be best understood by reference to the accompanying drawings and the detailed description below, wherein: 1272481 The first drawing is a schematic representation of a general host system including non-electrical memory. Figure lb is a pictorial representation of a memory device such as memory device 120 of Figure la. 5 The lc diagram is a graphical representation of a host system including built-in non-electrical memory. Fig. 2a is a diagram showing a block of a non-electrical memory according to an embodiment of the present invention. φ 2b is a pictorial representation of a block of non-electrical memory of a block 202 that is divided into groups of regions, such as Figure 2a, in accordance with an embodiment of the present invention. Fig. 3a is a schematic representation of a region of a non-electrical memory member, such as region 212 of Fig. 2b, in accordance with an embodiment of the present invention. Figure 3b is a pictorial representation of a page of non-electrical responsive member members grouped into a plurality of page segments in accordance with an embodiment of the present invention. 15 Figure 4 is a pictorial representation of a region of a non-electrical memory that has been assigned a number of converted pages in accordance with an embodiment of the present invention. Figure 5 is a graphical representation of the mapping of the number of converted pages associated with a block of non-electrical memory to the mapping of the actual number of physical pages, in accordance with an embodiment of the present invention. 20 Figure 6 is a pictorial representation of a plurality of blocks grouped into regions and units having converted pages in accordance with an embodiment of the present invention. Figure 7 is a pictorial representation of a lookup table that can be used to facilitate multi-page access or planning operations in accordance with an embodiment of the present invention. Figure 8 is a process flow diagram illustrating the steps associated with performing the processing of a multi-page write operation of a non-electrical memory system such as the system 12 1272481, in accordance with an embodiment of the present invention. Figure 9 is a process flow diagram illustrating the steps associated with multi-page write processing involving the use of a lookup table in accordance with an embodiment of the present invention. 5 Figure 10 is a process flow diagram illustrating the steps associated with performing a process such as a read operation of a non-electrical memory system of a system, in accordance with an embodiment of the present invention. Figure 11 is a process flow diagram illustrating the steps associated with the read processing involving the use of a lookup table in accordance with an embodiment of the present invention. 10 Figure 12 is a diagram of a block diagram of a system architecture in accordance with an embodiment of the present invention. [Embodiment] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 15 Reducing the amount of burden required to read, erase, or write data of a non-electrical memory such as a NAND flash memory can be actuated including non-electricality. Improvements in the performance of the overall system of memory. Typically, a single page of a non-electrical memory system is accessed at any given time, for example, access time to one of the non-electrical memory. Since the access time for writing a page can range from about 250 microseconds (//s) for 20-bit flash memory to more for multi-level cell (MLC) flash memory. With about one millisecond (ms), multi-write processing is relatively time consuming and, therefore, adversely affects the performance of the overall non-electrical memory system. In order to effectively reduce the amount of time required to perform 11 A, 7248l k, such as write operations, on non-electrical memory, that is, to increase the write speed of the overall system, the page can be written at any time. . That is, a multi-page write operation that actually activates more than one page to be written at a single access time can be implemented. In general, the 'however page' is programmed so that multiple pages can be planned together, such as writing, or 5 士', or erasing, to reduce the amount of time associated with planning processing. For example, the § data is written to the four pages of the MLC flash memory at substantially the same time. The overall amount of time used for the write process can be reduced from about four ms to about one. Therefore, the write operation can occur more efficiently. A flash memory system, or more generally, a non-dependent memory device that benefits from the use of data reading, erasing, and writing multiple pages of pages or blocks, generally The words include flash memory cards and chipsets. Typically, a flash memory system is used with the host system to enable the host system to write data to or read data from the flash memory system. However, some flash memory systems include a built-in 15 flash memory and a software that is executed on the host to function substantially as a controller for the embedded flash memory, as will be referred to lc. Illustrator. Referring to Figure la, a general host system including a non-electrical memory device such as a compact flash memory card will be described. The host or computer system 100 generally includes a system bus 34 that allows the microprocessor 20 108, random access memory (RAM) 112, and input/output circuitry 116 to communicate. It should be appreciated that host system 100 can generally include other components, such as display devices and network devices that are not shown for illustrative purposes. In general, the host system 100 can capture information including, but not limited to, static image 12 1272481 = video, audio information, and video image information. This information can be transmitted to the host system 100 in a hotline. While the host system can be any system, the host system touch is usually a digital camera, a video camera, a cellular communication device, an audio player, or a video-player. However, it should be understood that, in general, the host system is a system that can store data or information, and retrieve data or information. 10 15 20 The host system 100 can also capture data only, or only retrieve data. In the consistent application, the host system 100 can be used to store data, or the host system can be used to read data. Dedicated system. By way of example: the host system (10) can write for memory that is arranged to write only people or store data, and optionally, the host system 100 can be readable or retrieved, such as in a normal system, and not A device for capturing MP3 players. In one embodiment, the non-electrical memory device is a removable non-electrical memory device 120 that is arranged to interface with the bus bar 104 to store the tribute. The optional input/output circuit block 13 can allow the non-electrical memory device 120 to indirectly interface with the bus bar 1〇4. When the phenotype is implemented in the foregoing manner, the input/output circuit block 132 functions to reduce the load of the bus bar 1〇4 as it is known to those skilled in the art. The non-electrical memory device 12 includes a non-electrical memory 124 and an optional memory control system 128. In one embodiment, the non-electrical memory device 12 can be implemented on a single wafer or die. Alternatively, the non-electrical memory device 120 can be implemented in a multi-die module' or can form a wafer set and can be used together as a plurality of discrete components of the non-electrical memory device 120. Non-electrical memory device 120 13 1272481 An embodiment will be described in more detail below with reference to the figures. The non-electrical memory 124, such as a flash memory such as a NAND flash memory, is arranged to store data so that the data can be accessed and renewed as needed. The data stored in the non-electrical memory 124 can also be erased at a suitable time of 5, although it should be understood that certain materials in the non-electrical memory 124 are not eradicable. The processing of storing data, reading data, and erasing data is generally controlled by the memory control system 128, or by the software executed by the microprocessor 108 when the memory control system 128 is not present. control. The operation of the non-electrical memory 124 can be managed by essentially making the sectors of the non-electrical memory 124 more substantial and evenly worn to maximize the lifetime of the non-electrical memory 124. Can be substantially maximized. The non-electrical memory device 12A has been generally described as including an optional memory control system 128, i.e., a controller. In general, the non-electrical memory device 120 can include a separate wafer for the non-electrical memory 124, and the memory control system 128, i.e., the controller, functions. By way of example, the non-electrical compliant memory device including, but not limited to, a PC card, a compact flash memory card, a multimedia card, and a security digital card includes a controller that can be implemented on a separate wafer. The remaining non-electrical memory devices may not include the control of the discrete wafers. In the embodiment where the non-electrical memory device 120 does not include the separation of the memory and the control chip, the memory and controller functions can be aggregated on a single wafer, as is known to those skilled in the art. Optionally, the functionality of the memory control system 128 can be provided by the microprocessor 1 , 8, as described above for the non-electrical memory device 12 〇 not including the implementation of the memory controller 128 example. 14 1272481 Referring to Figure lb, a non-electrical memory device 120 will be described in greater detail in accordance with an embodiment of the present invention. As explained above, the non-electrical memory device 120 includes a non-electrical memory 124 and may include a memory control system 128. Although the non-electrical memory device 120 may not include the control system 128 when the memory 124 is such as a built-in NAND device 5, the memory 124 and the control system 128, or the controller may be non-electrical memory. The main components of the body device 120. The memory 124 can be a memory cell array formed on a semiconductor substrate, wherein one or more of the data are stored in the memory cell by one of two or more levels of charge. Individual storage elements are stored in individual memory cells. Non-electrical fast lightning can be erased. Read-only memory (EEPROM) is an example of a common form of memory for such systems. When implemented in the manner previously described, control system 128 communicates with the host computer or other system using the memory system via bus bar 15 to store the funds. In general, the busbar 15 is part of the busbar 1〇4 of Figure 1. The control system 128 also controls the operation of the memory 124, which may include the memory cell array, to write the data provided by the host, read the poor materials required by the host, and perform various chores labeled as memory 124. Features. In general, control system 128 includes a general purpose microprocessor having associated non-electrical software memory, various logic 20 circuits, and the like. One or more state machines are also often included to control the performance of a particular routine. In one embodiment, memory cell array 11 is typically addressed via address decoder 17 by control system 128 or microprocessor 108. In this embodiment, the decoder 17 applies the correct voltage to the gate and bit lines of the array 11 to read the tribute or wipe from the memory cell group addressed by the control system 128 at 15 1272481. In addition to the memory cell group addressed by control system 128. The additional circuit 19 includes a plan driver that controls the voltage of the array element depending on the data being addressed to the address group of the unit cell. The circuit 19 also includes circuitry required to read data from the address group of the amplifier and other self-memory cells: data to be planned for the array η, or data that has recently been read from the p-column 11 The buffer memory η of the control system 128. The control system 128 also contains various registers for temporarily storing command and status data and singular analogs. 10 Array 11 is divided into a large number of block 〇 (BLOCK 0) to block N (BLOCK N) memory cells. As with the flash EEpR〇M system, the block is usually the smallest unit erased. That is, each block contains a minimum number of memory cells that are erased. Each block is usually divided into several pages. Those skilled in the art will be able to understand. The page can be considered as the smallest unit of the 15 plan. That is, the basic planning operation can write data to the smallest page of the memory cell or read data from the smallest page of the memory cell. One or more data sectors are typically stored in each page. As shown in Figure lb, a sector includes user data and burden information. The burden profile typically includes an error correction code (ECC) calculated from the user data of the sector. When the data system is planned for array 11, portion 23 of control system 128 can calculate the ECC and check the ECC when the data system reads from array 11. Optionally, the ECC is stored on a different page or a different block than the user profile to which it is attached. Corresponding to the sector size of the disk drive, the user data sector is typically 512 bytes. The burden profile is usually an additional 16-bit tuple. Information 16 1272481 The district is included in each page, but two or more sectors can be replaced by pages. In general, any number of pages can form a block. By way of example, blocks can be formed from 8 to 512, 1024 or more pages. The number of blocks is selected to provide the data storage capacity desired by the system memory. 5 Array 11 is typically divided into a number of sub-arrays (not shown) each time the array contains a block ratio 'which is somewhat independent of each other to increase the degree of parallelism of various memory gymnastics. An example of the use of the invention is described in U.S. Patent No. 5,890,192, the entire disclosure of which is incorporated herein by reference. In a system such as a host system, the first diagram is a pictorial representation of a host system that includes built-in non-electrical memory. In general, the host or computer system 15 includes the other of the host system 150. A microprocessor (158) of components (not shown), a RAM 162, and a system bus 154 for communicating with the input/output circuit 166. The 15 non-volatile memory devices such as flash memory allow information to be stored in the host system 150. The interface 180 can be provided between the non-electrical memory 174 and the bus 154 to enable information to be read from the non-electrical memory 174 and to write information to the non-electrical memory 174. Sex memory 174 It is managed by a microprocessor 158 that efficiently executes one or all of the software or cartridges that are arranged to be controllable 20 non-electrical memory 174. That is, the microprocessor 158 can execute, such as software. A code device or a body code device or the like that allows control of the non-electrical memory 174 (not shown). It may be a flash memory, a separate flash ROM, or a CPU packaged inside the microprocessor 158. The code devices of the non-electrical memory 174 internal 17 1272481, as will be explained below, enable the physical blocks inside the non-electric memory 174 to be located, and the information can be stored in the physical block. The information can be read from the physical block and erased from the physical block. Generally, when the user writes the data, the user effectively writes the information to the media, such as, for example, flash memory. A card or an example of a non-electrical memory system including a system in which a flash memory is placed. As will be appreciated by those skilled in the art, the user can specify a block to which data is to be written or even Specify the page to which the data is to be written. Such as the The non-electric memory pass 10 of the electrical memory 124, or the non-electrical memory 174 of the lcth diagram, is often divided into blocks, as described above. Figure 2a is an embodiment in accordance with the present invention. The non-electrical memory can be divided into individual physical blocks 0" to N" 202 related to logical blocks (not shown). In an embodiment, each block 202 includes about twenty pages, although it should be understood that, in general, block 202 can include any number of pages, such as sixty-four pages. In general, blocks The number of 202s and the number of pages included in block 202 may depend on the size of the non-electrical memory. Typically, the pages of block 202 are substantially continuous. That is, as shown, the block "〇" 2〇2a, which may be the first block of the non-electrical memory, includes pages 20 to 31. In general, a block below the non-electrical memory is a block "1" 2 〇 2b including pages 32 to 63. In general, the block 202 of the non-electrical recording body is continuous, and in general, the page of the block 2〇2 is also continuous. Blocks 202 can be grouped into zones as shown in Figure 2b. The number of regions 212 in which blocks 2〇2 can be grouped depends on the number of pages to be accessed in one read process, erase process, 18 1272481, or write process, and thus, can vary widely. For example, the number of zones that block 202 can be grouped can be from approximately two zones of approximately two pages at substantially the same time to approximately thirty-two zones of approximately thirty-two pages while substantially simultaneously accessing. The 5 block groups are grouped into four zones 212. Therefore, each of the four blocks 2123⁄4: is grouped into a specific area 212. By way of example, the block "〇" 2〇2a and the block "4" 202e are included in the district "0" 212a, while the blocks "1" 2〇2b, the block "5" 202h, and the block" The N-2" 202k system is included in the zone "1" 212b. More generally, the block 202 having a multiple of four blocks may be included in the area "〇" 212a, 10 having a multiple of four blocks plus one block 2〇2 may be included in the area " 1" 212b, block 2 〇 2 having a block number of four multiples plus two blocks 2 〇 2 may be included in the area "2" 212c, and having a number of blocks of four minus one may be included In the district "3" 212d. Figure 3a is a pictorial representation of a region of a non-electrical memory member such as region 15 212 of the first embodiment, in accordance with an embodiment of the present invention. As shown in the figure, the physical block 2〇2 having a multiple of four blocks is effectively aligned with the area "〇" 212a, and at the same time, the physical block 2〇2 having a multiple of four blocks plus one. It is effectively aligned to the area "1" 212b and the like. It should be understood that, in general, zone 212 may include a block number 2〇2. In general, the number of 20 blocks 202 included in each zone 212 is determined by, but not limited to, the overall size of the non-electrical memory components divided into blocks 202, the number of zones 212, and included in each A factor such as the number of pages of a block 202. In general, a single page of each zone 212 can be accessed substantially at the same time, for example, as a multi-page section, such that pages of each zone 212 can be erased or written at a single 19!272481 access time. In. That is, the physical page 302 having the same page offset relative to the start of the individual blocks of the region 212 can be accessed as a unit 3〇4 using a multi-block access command such as a multi-block or multi-page plan command, such as The % map shows. To actuate the occurrence of multi-page writes, multiple pages 5, such as multiple consecutive pages, are substantially written once, and pages associated with each of the regions 212 can be accessed at a single access time. By way of example, the page "12" 302a of the "〇" 212a, the page "44" 302b of the area 1" 212b, the page "76" 302c of the area "2" 212c, and the page "108" of the area "3" 212d 302d can be written substantially using a single multi-block reference plan command. In general, the number of pages that can be effectively accessed using multi-block commands may depend on the number of regions 212 in which block 202 has been grouped. For example, if there are four regions 212, then four pages that are individually located in different regions 212 can be grouped into multiple page segments that are substantially accessed at the same time. Optionally, when there are eight zones, one page associated with each zone can be accessed using a multi-block or multi-page command such that the eight pages are accessible at the same time. As described above, by accessing multiple pages at a time, the amount of time associated with processing such as reading, erasing, and writing operations can be reduced, thereby enhancing the overall non-electrical memory system or faster. The performance of the flash memory system. When several pages are simultaneously written, during the multi-page write command, access to the successive pages of the different areas of the memory 20 is generally desirable. Since the page to be written is written to a different area and each area usually has its own data cache, multiple pages of user data can be transferred to the multi-zone data cache. Multiple pages of user data can then be scheduled for non-reactive memory at the same time. 20 1272481 To facilitate the planning operation for users (ie, individuals who wish to access physical pages of non-electrical memory of non-electrical memory systems), related to physical pages such as shown in Figure 3b The number of pages can be substantially converted to the user or converted pages. The conversion of the number of pages allows the number of pages to be allocated across regions in ascending order. 5 Figure 4 is a pictorial representation of a region of a non-electrical memory in which a page has been assigned a number of converted pages in accordance with an embodiment of the present invention. Zone 412 is arranged such that zone "0" 412a includes block 402 having a block number 420 that is a multiple (e.g., four times) the total number of zones 412. Similarly, zone "1" 412b includes block 402 having a block number 420 that is a multiple of the total number of zones 412 plus one, and zone "2" 412c includes blocks that have multiples of the total number of zones 412 plus two. Block 402 of number 420, and area "3" 412d includes block 402 having a block number 420 that is a multiple of the total number of zones 412 plus three. Block 402 of area 412 can be organized as a unit having a unit number 430. Unit number 430 can effectively identify the location of block 402 of zone 412. For example, a 15 unit number "〇" 430a can identify the first block 402 of each zone 412. In detail, the block 402a of the area "0" 412a, the block 402b of the area "1" 412b, the block 402c of the area "2" 412c, and the block 402d of the area "3" 412d are the individual and the number of units. 0" 430a related. While the actual number of pages included in the block 402 is 20 pages of the entity having the number of physical pages, as will be explained below with reference to FIG. 5, the use of the user or the number of converted pages allows the user to more easily specify the number of pages. It is desirable to access the number of pages of the overall system supporting more than one page of access in a single access time. Typically, when a page is accessed in a multi-page extent, the access page is associated with the same number of cells 430. By way of example, pages of unit number "0" 430a can be accessed simultaneously using multiple page access commands. 21 1272481 As mentioned earlier, the ND number "0" 430a includes a block 42 每一 for each zone 412. Thus, pages from each of blocks 420a through 420 can be accessed as part of a multi-page segment of the number of cells "〇" 43〇a. When the user specifies the number of conversion pages that he or she wishes to access, in general, the number of conversion pages is converted or mapped to the actual number of pages available to the controller body or software for accessing the appropriate page. Figure 5 is a graphical representation of the mapping of the number of converted pages associated with a block of non-electrical memory to the actual number of physical pages, in accordance with an embodiment of the present invention. When a multi-page section 53 is to be erased or to be written using a single access time, in general, the number of converted pages 504 having a block 502 from each of the 10 zones 412 is included in section 530. . By way of example, when multiple page segments 53 are to be accessed at a single access time, the controller body or software will typically effectively access pages with a number of converted pages of 5〇4. The multi-page section 53 including the converted page number 504 can be effectively mapped to a multi-page section 530 including pages having the actual physical page number 5〇4, 15 having the converted page number 5〇4, . In particular, when the user specifies a page having a number of converted pages 5 to 4 to be accessed for erasing, erasing, or writing, the controller body or software usually determines that there is an actual number of pages. The page corresponds to the page with the number of converted pages 504. By way of example, when the multi-page section 5 is provided with a 20-page day π ' of the number of converted pages 504 for the number of converted pages "8", "9", "!〇", and "11", it is controlled as a body. Or the software determinable multi-segment 53 〇 corresponds to a multi-page section including pages having actual physical page numbers 504 ′ which are individual actual physical page numbers “2”, “34”, “66”, and “98”. 53 (),. In other words, the number of converted pages "8" is mapped to the actual number of physical pages "2", the number of converted pages "9" is mapped to the actual number of pages "34", and the number of converted pages is "1". The actual number of physical pages 22 1272481 "66", and the conversion of the number "u" is mapped to the actual number "98. In order to make the number of converted pages to the actual number of physical pages, or - bu = for the first - The number of pages of the habit is mapped to the second _^, the mathematical algorithm of the __ stomach number can be determined by the actual entity. In this algorithm, the algorithm includes using the lookup table as described in Figure 7: And including, in general, the actual physical page number can be given by (4) the number of converted pages or the position of the block including the number of relevant units, the number of related units, the number of pages changed, or Offset.

10 15 參考第6圖，可使用轉換頁數判定實際頁數之公式將參考本發明之-實施例說明如下。—般而言，諸如與例如區塊602a之頁604a之頁有關的轉換頁數可表示「 ^10 15 Referring to Fig. 6, a formula for determining the actual number of pages using the number of converted pages will be described with reference to the present invention - the following. In general, the number of converted pages, such as those associated with pages 604a of block 602a, may indicate "^"

文所述，非依電性記憶體之每一區塊6〇2可與表示為「z 之區622及表示為「U」之單元630兩者有關。舉例言之，包括頁616之區塊602f可被包括於區「1」622b及單元「工」 630b，同時，包括頁612之區塊602d可被包括於區「3」622d 及單元「0」630a。如圖所示，一般而言，非依電性記憶體可包括任意數目之區622及單元630。除此之外，區塊602之大小，亦即，區塊602之頁數可廣泛地改變。為方便說明，總區數可表示 2〇為「T_D」且總單元數可表示為「T_U」，同時，區塊602 之總頁數可表示為「TJ5」。通常，總區數「T-D」、總單元數「T_U」、及區塊602之總頁數「TJP」可被考量為係與非依電性記憶體有關之參數。一般而言，非依電性記憶體之特定頁之轉換頁數，如 23 1272481 同具有表示為「X」之相關轉換頁數的頁616b之釋例，可以下式識別：As described herein, each block 6〇2 of the non-electrical memory can be associated with both the region 630 indicated as "z" and the cell 630 indicated as "U". For example, block 602f including page 616 can be included in zone "1" 622b and cell "work" 630b, while block 602d including page 612 can be included in zone "3" 622d and cell "0". 630a. As shown, in general, the non-electrical memory can include any number of regions 622 and cells 630. In addition, the size of block 602, i.e., the number of pages of block 602, can vary widely. For convenience of explanation, the total number of zones can be expressed as "T_D" and the total number of cells can be expressed as "T_U", and the total number of pages of block 602 can be expressed as "TJ5". In general, the total number of zones "T-D", the total number of cells "T_U", and the total number of pages of block 602 "TJP" can be considered as parameters related to non-electrical memory. In general, the number of pages converted to a particular page of a non-electrical memory, such as 23 1272481, with the interpretation of page 616b having the number of converted pages indicated as "X", can be identified by:

X = (U * T—D * T一P) + (S * T一D) + Z 此處「S」係表示含有與轉換頁數「X」有關之頁之區塊起 5 點與轉換頁數「X」之位置間之偏移650或頁數。「s」值之範圍可自約為0至約「T P-1」，同時，「Z」值可為約「t D-1丨。亦即，實質地任意轉換頁數可表示為區622、單元630、偏移650、總區數「TJD」、總單元數「Τ_υ」、及區塊602之總頁數「Τ-Ρ」之函數。對總區數「TJD」為四，且每一區塊 10 602之總頁數為三十二之實施例而言，轉換頁數「X」可被識別為下式： X = (U * 4 * 32) + (S * 4) + Ζ 應瞭解者為，雖然轉換頁數「X」係顯示為位於區塊6〇2f 之轉換頁數，一般而言，轉換頁數「X」可實質地位於任意 15 區塊。當轉換頁數「X」為已知時，對應於轉換頁數「X」之區「Z」622、單元「U」630、及偏移「s」650可被判定。應瞭解者為，對應於轉換頁數「X」之區「Z」622、單元「U」630、及偏移「S」650亦對應於對映於轉換頁數rx」 20 之實際實體頁數。換言之，對轉換頁數而言，區「Z」622、單元「U」630、及偏移「S」650係為相同的，因為其係供對應實際實體頁數用。因此，一旦轉換頁數「X」係為已知，且與轉換頁數「X」有關之區「Z」622、單元「U」630、及偏移「S」650係為已知，則實際頁數「p—N」可被判定。 24 !27248l 當「x」係藉由總區數「T、D」加以劃分時，如同使用邊如「MQD」運算子之剩餘部份運算子加以狀者， _頁數「X」，區「Z」622可被判定為係剩餘部份,， Q「Z」622可以下述之轉換頁數「χ」之函數表示： z = X % T D 此處’「％」係為熟於此技者所熟知之剩餘部份運算子。到應於轉換頁數「X」之單元「u」咖可以轉換頁數「χ」之函數表示：X = (U * T - D * T - P) + (S * T - D) + Z Here "S" indicates that the block containing the page related to the number of converted pages "X" is 5 points and the conversion page The offset between the positions of the number "X" is 650 or the number of pages. The "s" value can range from about 0 to about "T P-1", and the "Z" value can be about "t D-1 丨. That is, the substantially arbitrary number of pages can be expressed as area 622. The function of the unit 630, the offset 650, the total number of zones "TJD", the total number of cells "Τ_υ", and the total number of pages of the block 602 "Τ-Ρ". For the embodiment in which the total number of regions "TJD" is four and the total number of pages per block 10 602 is thirty-two, the number of converted pages "X" can be identified as follows: X = (U * 4) * 32) + (S * 4) + Ζ It should be understood that although the number of converted pages "X" is displayed as the number of converted pages located in block 6〇2f, in general, the number of converted pages "X" can be substantially Located in any of the 15 blocks. When the number of converted pages "X" is known, the area "Z" 622, the unit "U" 630, and the offset "s" 650 corresponding to the number of converted pages "X" can be determined. It should be understood that the area "Z" 622, the unit "U" 630, and the offset "S" 650 corresponding to the number of converted pages "X" also correspond to the actual number of pages mapped to the number of converted pages rx"20. . In other words, for the number of converted pages, the area "Z" 622, the unit "U" 630, and the offset "S" 650 are the same because they are used for the actual physical number of pages. Therefore, once the number of converted pages "X" is known, and the area "Z" 622, the unit "U" 630, and the offset "S" 650 related to the number of converted pages "X" are known, the actual The number of pages "p-N" can be determined. 24 !27248l When "x" is divided by the total number of zones "T, D", as with the remainder of the operation of the "MQD" operator, the number of pages is "X", the zone " Z"622 can be judged as the remainder of the system, and Q "Z" 622 can be expressed as a function of the number of converted pages "χ": z = X % TD where '%' is a skilled person The remaining part of the operator is well known. The function "u" which should be converted to the number of pages "X" can be converted to the number of pages "χ".

u = X / (τ一D * TJP) 1〇 —般而言，當單元「U」63〇係計算為分數值時，單元4 之實際「值」可藉由實質地四捨五人至最近整數值而判定。」舉例5之，若總區數「τ—D」為四且總頁數「τ_ρ」為三十二’若轉換頁數「X」係轉換頁數「3」，則單;「U」—63〇通常係判定為單元「〇」63〇a。u = X / (τ - D * TJP) 1 〇 In general, when the unit "U" 63 is calculated as a fractional value, the actual "value" of the unit 4 can be substantially rounded up to the nearest whole Determined by the value. For example 5, if the total number of districts "τ-D" is four and the total number of pages "τ_ρ" is thirty-two, if the number of converted pages "X" is the number of converted pages "3", then "U" - 63〇 is usually judged as the unit "〇" 63〇a.

15、…與轉換頁數「X」有關之偏移「s」亦可使用下列表示判定為係轉換頁數「X」之函數： s = (X / T一D) % τ一P ^轉換頁數「X」係為轉換頁數「3」、總區數「T一D」為四、 2且區塊602之總胃數「τ—p」為三十二時，則偏移「s」65〇 20可計算為零，亦即，轉換頁數「3」係為其相關區塊之第— 頁。類似地’當轉換頁數「X」係為轉換頁數「8」、總區數「T一D」為四、且區塊6〇2之總頁數「τ一p」為三十二時，則偏和S」65〇可計具為二，亦即，轉換頁數「8」係為其相關區塊之第三頁。 25 1272481 參考第6圖，對應於轉換頁數「χ」之實際實體頁數「P_N」可被表示為參數及轉換頁數「χ」之函數，且因此，可以區「Z」622、單元「U」_、及偏移「S」咖如下： P一N = (u * T一D * TJP) + (Z * T p) + s 或簡化為： p一N = S + (((u * T—D) + Z” τ B) 10 15 20 於一實施财，實際實㈣數「P_N」可僅實f地表示為轉換頁數「X」及參數之函數，亦即，總區數「T D」、及區塊繼之總頁數「T_P」。亦即，藉由實質地以替換厂z」及s」消除U」，貫際貫體頁數Γρ一Ν」亦可被計算為： P-N = X + ((X % T_D)，(τ_ρ _1)} _ ((χ ; τ^〇) % τ ρ) ,(τ D _ 1} 使用上文所述表示，區「z」622、單元ru」63〇、及偏移「S」650之計算可有效地被消除。一再次參考第5圖，若非依電性記憶體包括四區似且每區，502包括二十二頁，當使用者嘗試寫入頁撕c時，亦 17田轉換頁數係為轉換頁數「1〇」時，區「z」可計算為·· Z = X % T—D = 10 % 4 = 2 且單元「U」可計算為： U = X/( 丁—d*t—p) = 10/(4*32) = 0 同時，偏移「S」可被計算為： S - (X / T^D) % τ^Β = (10 / 4) % 32 = 2.5 % 32 = 2 亦即’轉換頁數「l〇」5〇4c可被計算為係位於區「2 j 412c，及二頁之偏移之單元「0」，如第5圖所示。當 Z - ? TT ^ —、U == 0、且s = 2時，實際實體頁數「p_N」可 26 1272481 被判定如下： P_N = S + (U * TJD + Ζ) * Τ—P = 2 + (0 * 4 + 2) * 32 = 66 因此，轉換頁數「10」係對應於實際實體頁數「66」。任擇地，實際實體頁數「P_N」亦可計算如下： 5 P一N = X + ((X % T—D) * (T一P -1)) - ((X / T一D) % TJP) * (T一D - 1) =10 + ((10 % 4) * (32 - 1)) -（(10 / 4) % 32) * (4 - 1) =66 雖然牽涉上文所述有關第6圖之公式之計算可實質地執行於使用者發出命令讀取或寫入諸如NAND快閃記憶體 10 之非依電性記憶體之頁的任意時間，當與此種計算有關之負擔可被考慮為係為過度時，此計算可有效地經由使用諸如查詢表之資料結構而被簡化。藉由釋例，一般而言，雖然與執行計算以識別實際實體頁之位置之頁數有關的負擔並不明顯，當記憶體空間允許儲存於控制器軔體或軟體之 15 相對小之資料結構的實施時，已執行之計算可被簡化，且負擔可更為減少。因此，於許多情形中，多頁寫入處理之性能可更為改進。應瞭解者為，當查詢表過大時，例如，佔用超過約512位元組時，且係考量為佔用控制器軔體或軟體之過多空間時，將轉換頁數轉換為實際頁數之計算可以 20 上文有關第6圖之說明而執行，無需使用查詢表。換言之，一般而言，計算是否應被執行以替代存取查詢表之判定可根據適當查詢表之預期大小而產生。查詢表可被計算及儲存於控制器軔體或軟體内部，使得當對映欲被執行以有效地將轉換頁數轉換為實際實體頁 27 1272481 數時，查詢表可被存取以獲得對映資訊。第7_根據本發明之一實施例之可被用以促進多頁存取或規劃操作的查^ 表之圖式表示。一般言之，查詢表750之入口數可至少部份地取決於非依電性記憶體之單元的頁數。藉由釋例，每一 5入口可被排置為佔用一位元組，且與圖表有關之位元組數可取決於單元之頁數。藉由釋例，當非依電性記憶體包括個別包括三十二頁之區塊，且係分組為四區時，每一單元可包括四區塊。因此，與每一單元有關之頁數係為128，且因此入口數、查詢表750佔用之位元組可約為128。查詢表 10 入口數可有效地表示為：15, ... the offset "s" related to the number of converted pages "X" can also be determined by the following function as a function of converting the number of pages "X": s = (X / T - D) % τ - P ^ conversion page When the number "X" is the number of conversion pages "3", the total number of regions "T-D" is four, and the total stomach number "τ-p" of the block 602 is thirty-two, the offset is "s". 65〇20 can be calculated as zero, that is, the number of converted pages "3" is the first page of its relevant block. Similarly, when the number of converted pages "X" is the number of converted pages "8", the total number of pages "T-D" is four, and the total number of pages "τ-p" of the block 6〇2 is thirty-two. , the partial and S"65" can be counted as two, that is, the number of converted pages "8" is the third page of the relevant block. 25 1272481 Referring to Figure 6, the actual physical page number "P_N" corresponding to the number of converted pages "χ" can be expressed as a function of the parameter and the number of converted pages "χ", and therefore, the area "Z" 622, unit " U"_, and offset "S" coffee are as follows: P_N = (u * T_D * TJP) + (Z * T p) + s or simplified to: p - N = S + (((u * T—D) + Z” τ B) 10 15 20 In practice, the actual (four) number “P_N” can be expressed only as a function of the number of converted pages “X” and parameters, that is, the total number of zones “ TD", and the block followed by the total number of pages "T_P". That is, by essentially replacing the factory with the replacement of the factory z" and s", the number of pages can be calculated as: PN = X + ((X % T_D), (τ_ρ _1)} _ ((χ ; τ^〇) % τ ρ) , (τ D _ 1} is expressed as described above, the zone "z" 622, unit The calculation of ru"63" and offset "S" 650 can be effectively eliminated. Referring again to Figure 5, if the non-electrical memory includes four regions and each region, 502 includes twenty-two pages, when used When attempting to write a page to tear c, the number of pages converted by 17 is the number of converted pages "1". "z" can be calculated as · Z = X % T - D = 10 % 4 = 2 and the unit "U" can be calculated as: U = X / ( D - d * t - p) = 10 / (4 * 32 ) = 0 At the same time, the offset "S" can be calculated as: S - (X / T^D) % τ^Β = (10 / 4) % 32 = 2.5 % 32 = 2 That is, 'conversion page number' l 〇"5〇4c can be calculated as the unit "2 j 412c, and the offset of the two pages, "0", as shown in Figure 5. When Z - ? TT ^ -, U == 0, and When s = 2, the actual physical page number "p_N" can be determined as follows: P_N = S + (U * TJD + Ζ) * Τ - P = 2 + (0 * 4 + 2) * 32 = 66 Therefore, The number of converted pages "10" corresponds to the actual number of physical pages "66". Optionally, the actual number of physical pages "P_N" can also be calculated as follows: 5 P - N = X + ((X % T - D) * ( T-P -1)) - ((X / T - D) % TJP) * (T - D - 1) = 10 + ((10 % 4) * (32 - 1)) - ((10 / 4) % 32) * (4 - 1) = 66 Although the calculation involving the formula of Fig. 6 described above can be substantially performed by the user issuing a command to read or write a non-powered device such as NAND flash memory 10. Any time of the page of sexual memory, when there is such a calculation When the burden can be considered to be excessive, this calculation can be effectively simplified by using a data structure such as a lookup table. By way of example, in general, although the burden associated with performing the calculation to identify the number of pages of the actual physical page is not significant, the memory space allows for a relatively small data structure stored in the controller body or software. At the time of implementation, the calculations that have been performed can be simplified and the burden can be reduced. Therefore, in many cases, the performance of multi-page write processing can be improved. It should be understood that when the lookup table is too large, for example, when it occupies more than about 512 bytes, and the system considers the excessive space occupied by the controller body or the software, the calculation of converting the converted page number to the actual number of pages may be 20 Executed above for the description of Figure 6, without the use of a lookup table. In other words, in general, the decision whether the calculation should be performed instead of accessing the lookup table can be made based on the expected size of the appropriate lookup table. The lookup table can be computed and stored inside the controller body or software so that when the entropy is executed to effectively convert the number of converted pages to the actual physical page number 27 1272481, the lookup table can be accessed to obtain the mapping News. 7A Schematic representation of a lookup table that can be used to facilitate multi-page access or planning operations in accordance with an embodiment of the present invention. In general, the number of entries in lookup table 750 can depend, at least in part, on the number of pages of non-electrical memory cells. By way of example, each 5 entry can be queued to occupy a tuple, and the number of bytes associated with the chart can depend on the number of pages of the unit. By way of example, when the non-electrical memory includes blocks that individually include thirty-two pages, and the cells are grouped into four regions, each cell may include four blocks. Therefore, the number of pages associated with each unit is 128, and thus the number of entries, the number of bytes occupied by lookup table 750 can be about 128. The number of entries in the lookup table 10 can be effectively expressed as:

Number一Of一Entries = T—D * Τ_Ρ 為便於說明，查詢表750包括個別對應於區塊之第一單元之頁的128個入口。然而，一般言之，入口數可取決於區數「Τ一D」，且因此，單元之區塊數，與包括於單元之區塊 15 Τ-Ρ」之大小而改變。查詢表750可增加或有效地編碼，使得用以經由與第一單元之最後一頁有關之轉換頁數，諸如轉換頁數「127」對映轉換頁數「〇」之入口係有效地表示於查詢表750。一般而言，查詢表750可使用下列表示而增加： 20 Table一Entry一Value[P，(Z，S)] = (Ζ * (Τ一Ρ 一 1)) 一（s * (Tjd 一 1) 此處’ Table—Entry—Value係為儲存於查詢表75〇之入口之值，區「Z」係為與轉換頁數「P」有關之頁所在之區，且「s」係與轉換頁數「P」有關之頁所在的含有此頁之區塊的頁的偏移。Table_Entry—Value可被放置於藉由下式所識別之圖表位 28 1272481Number - Of - Entries = T - D * Τ _ Ρ For convenience of explanation, the lookup table 750 includes 128 entries individually corresponding to the pages of the first unit of the block. However, in general, the number of entries may depend on the number of zones "Τ一D", and therefore, the number of blocks of the cell varies with the size of the block 15 Τ-Ρ included in the cell. The lookup table 750 can be added or effectively encoded such that the number of converted pages, such as the number of converted pages "127", is effectively represented by the number of converted pages associated with the last page of the first unit. Look up table 750. In general, lookup table 750 can be incremented using the following representations: 20 Table - Entry - Value [P, (Z, S)] = (Ζ * (Τ一Ρ一1)) One (s * (Tjd - 1) Here, 'Table-Entry-Value is the value stored in the entry of the query table 75〇, the area "Z" is the area where the page related to the converted page number "P" is located, and the "s" system and the number of converted pages The offset of the page containing the block of this page in the page related to "P". Table_Entry_Value can be placed in the chart bit 28 1272481 identified by the following formula

Table 一 Entry 一 Location[P’] = p，％ (τ d * TP) 藉由釋例，於有四區且每一區塊含有三十二頁之系統中，轉換頁數「4」係與偏移「}」之區「〇」有關。因此，轉換 5頁數「4」可被計算為與查詢表750之「-3」之入口值有關。對應於轉換頁數「P」之實際頁數可使用查詢表75〇而判定如下：Table - Entry - Location[P'] = p, % (τ d * TP) By way of example, in a system with four regions and each block containing thirty-two pages, the number of pages converted is "4" The area of the offset "}" is related to "〇". Therefore, the conversion of 5 pages "4" can be calculated to be related to the entry value of "-3" of the lookup table 750. The actual number of pages corresponding to the number of converted pages "P" can be determined using the lookup table 75〇 as follows:

Actual—Page—Number = P’ + TABLE[P，％ (T—D * Τ P)] 此處，TABLE[]係儲存於對應於轉換頁數「p」之圖表入口之 10值。因此，對應於轉換頁數「p」之實際頁數亦可使用下式判定：Actual—Page—Number = P’ + TABLE[P,% (T—D * Τ P)] Here, TABLE[] is stored in the value of 10 of the chart entry corresponding to the number of converted pages “p”. Therefore, the actual number of pages corresponding to the number of converted pages "p" can also be determined using the following formula:

Actual Page Number = PJ + % τ τλ\ ^ ^ 一 W % T—D) * (T一P - 1) - ((P，/ T_D) % TJP) * (T-D - 1) 因此’於有四區且每一區塊含有三十二頁之系統内，轉換頁數「4」可對映於實際頁數％。如此—來，於欲寫入為 15此種系統之多頁區段之轉換頁數「4」至「7」的情形中，查詢表750，或更詳言之，查詢表之入口 754、756、758、及760可被用以判定欲於一存取時間個別寫入為多頁區段之實際非連續實體頁q」、「33」、「65」、及「97」。當查詢表750,或實質地任意類似資料結構被實施，諸 2〇如計算及儲存時，於控制器軔體或軟體内，實際實體頁數之計算係有效地為相對快速之具有最小計算的查詢表。因此，諸如多頁寫入命令之多頁存取操作玎相對有效率地發生。芩考第8圖’與執行諸如包括MLC快閃記憶體之系統的 29 1272481 非依電性記憶體系統之多頁寫入操作之處理有關的步鱗將根據本發明之一實施例說明如下。執行多頁寫入操作之處理800開始於步驟804，其中，使用者提供欲使用使用者頁慣則或轉換頁數寫入非依電性記憶體之頁的資料。於一實 5 施例中，當資料被輸入不同區時，使用者可發出一序列資料輸入命令，且控制器軔體或軟體可實質地響應於每一資料輸入命令發出諸如11H虛設規劃命令之虛設規劃命令，同時，資料仍被輸入於不同區，如同包含於此處以作為參考之可於加州太陽谷(Sunnyvale, California)之SanDisk公司獲 10 得之2001年八月改版之「512Mbit NAND快閃產品手冊(512 Mbit NAND Flash Product Manual)」所述者。一旦使用者提供欲寫入之資料’演算法可被執行，或更一般言之，於步驟808 ’計异可被執行以有效地令轉換頁數對映於實際實體頁數。可被執行之適當計异已於先前參考第6圖說明如上。 15 於對映計算執行後，於步驟812，使用者頁或轉換頁數被對映或轉換為實際實體頁數。而後，於步驟816,欲寫入之資料係使用多頁規劃命令或寫入處理而被寫入於非依電性記憶體系統或媒體之實際實體頁。換言之，實體頁之多頁區段約係於一存取時間被寫入。多頁規劃命令可包括快 20取規劃命令，例如可令實體規劃發生之15H快取規劃命令。一旦頁被寫入，執行多頁寫入操作之處理即為完成。替代執行數個計算以將使用者或轉換頁數對映於實際實體頁數，查詢表可被用以促進將轉換頁數對映為實際實體頁數，如前文參考第7圖所作之說明。第9圖係根據本發 30 1272481 明之一實施例之說明與牽涉使用查詢表的多頁寫入處理有關之步驟的處理流程圖。執行多頁寫入操作之處理900開始於步驟904，其中，使用者使用使用者或轉換頁數提供欲寫入之資料。而後，轉換頁數被用於步驟908，例如，經由存 5 取諸如第7圖之查詢表之查詢表，藉由控制器軔體或軟體判定對應於轉換頁數之實際實體頁數。一旦轉換頁數與其對應實際頁數間之對映被判定，資料係使用多頁或多區塊規劃命令於步驟912被寫入實際頁。於資料被寫入於實際頁後，寫入資料之處理即為完成。 10 如前所述，除規劃或寫入處理外，多頁或多區塊命令可被用以令多頁或區塊被抹除。一般言之，發生以讀取已使用多頁或多區塊命令寫入之頁的讀取操作可改變。參考第10圖，其將說明與根據本發明之一實施例之讀取處理有關的步驟。執行讀取操作之處理1000開始於步驟1004，其 15 中，使用者使用使用者頁慣則或轉換頁數指定欲讀取資料之非依電性記憶體之頁。一旦指定欲讀取資料之轉換頁數，演算法可被執行，或更一般言之，於步驟1008，計算可被執行以有效地將轉換頁數對映於實際實體頁數。可執行之適當計算係已於上文說明，如參考第6圖說明之釋例。 20 於對映計算執行後，於步驟1012，使用者頁或轉換頁數被對映或轉換為實際實體頁數。而後，於步驟1016，欲讀取之資料係使用讀取命令而自非依電性記憶體系統之實際實體頁讀取。一旦頁被讀取，執行讀取操作之處理即為完成。 31 ^481 作為讀^操作人㈣之情形’查詢表可被用以促進查詢表之讀取# ^ 又之一貫施例之說明與牽涉使用 5 用者希冀讀取或存取之資料之使用者二=供= 戰’對應轉換魏之實際實數圖之查: 了精由存取诸如弟7 10 頁數被判定後，“_12二4對應於轉換頁數之實際 ^ „ 、〆，貝料係自實際頁被獲得或讀取。-旦資料被讀取，讀取資料之處理即為完成。 :般㈣’與致動多頁規劃命令被執行或致動轉換頁數被對映於實際頁數㈣之魏性雜供於㈣，例如， 15 規劃碼裝置或主機系統之勒體。根據本發明之-實施例之與提供於主機系統之軟體_體有關之適#系統架構的實施例顯示於第12圖。-般而言，系統架構700包括各種模組，其可包括，但不限於應时賴㈣4、线管理者模組708、貢料管理者模組712、資料整體性管理者716、及裝置s理者及介面模組72G。-般而言，系統架構7⑻可使用可藉由諸如第la圖之處理器1〇8之處理器存取的軟體碼裝 20 置或軔體而執行。一般而言，應用介面模組704可排置為與主機、作業系統、或使用者直接通信。應用介面模組7〇4亦與系統管理者模組708及資料管理者模組712通信。當使用者欲讀取、寫入、或格式化快閃記憶體時，使用者發出要求予作業系統， 32 1272481 專要求被傳至應用介面模組704。取決於此等要求，應用 "面枳組704將此等要求導至系統管理者模組或資料管理者 712 〇系統管理者708包括系統初始化次模組724、抹除次數區塊官理次模組726、及電力管理區塊次模組73〇。一般而言，系統初始化次模組724係排置為可致動初始要求被處理，且通常係與抹除次數區塊管理次模組726通信。除與應用介面模組7〇4通信外，系統管理者模組7〇8亦係與資料管理者模組712及裝置管理者及介面模組72〇通 1〇信。與系統管理者模組7〇8及應用介面模組704兩者通信之貢料管理者模組712可包括提供頁或區塊對映之功能性。資料管理者模組712亦可包括與作業系統及檔案系統介面層有關之功能性。與系統管理者模組708、資料管理者712、及資料整體 15性官理者716通信之裝置管理者及介面模組720通常提供快 :記憶體介面’且包括與硬體摘要有關之諸如1/〇介面之功忐性。資料整體性管理者模組716可提供其他功能性之ecc 革振。、雖然上文所說明者僅係本發明之數實施例，應瞭解者為於不悖離本發明之精神或範圍之情況下，本發明可以 ^他數種形式實施。藉由釋例，諸如將轉換頁數對映於實 f頁數之多頁寫入或多區塊抹除操作之多頁操作已大致地說明為係適於供MLCNAND快閃記憶體使用。然而，應瞭解者為，此處所說明之技術及方法可實質地執行於任意適 33 1272481 當之非依電性記憶體，例如二進位NAND快閃記憶體，以增進可能發生之讀取、寫入、及抹除處理之效率。一般而言，查詢表可包括任意數目之入口。舉例言之，當單元之頁數較小且有少數單元包括於非依電性記憶體構 5 件時，查詢表可包括所有值，使其僅需執行基本最小計算以判定對應於轉換頁數之實際頁數。快閃記憶體之大小及快閃記憶體之區塊的大小可廣泛地改變。於區塊之大小已大致地說明為包括約三十二頁之同時，區塊可包括任意數目之頁，或更詳言之，任意數 10 目之產生區塊之元件。舉例言之，區塊可包括約六十四個元件或頁。因此，系統之區塊數目可加以改變。於512Mb 之二進位NAND快閃記憶體中，若區塊包括個別含有約 512位元組之約三十二頁，4096個總實體區塊係表現於快閃記憶體。任擇地，於512Mb之MLC NAND快閃記憶體 15 中，若每一實體區塊包括個別含有約512位元組之約六十四頁，2048個總實體區塊係表現於快閃記憶體。一般而言，頁之大小亦可改變。與本發明之各種方法有關之步驟可廣泛地改變。一般而言，步驟可被增加、移除、再排序、及警告。因此，目 20 前之釋例應考量為供說明之用、而非供限制之用，且本發明並未限於此處所作之詳細說明，而係可於後附申請專利範圍之範圍内進行修改。【圖式簡單說明3 34 1272481 第la圖係包括非依電性記憶體的一般主機系統之圖式表示。第lb圖係諸如第la圖的記憶體裝置120之記憶體裝置之圖式表示。 5 第lc圖係包括置入式非依電性記憶體之主機系統之圖式表不。第2a圖係根據本發明之一實施例之非依電性記憶體的區塊之圖式表示。 0 第2b圖係根據本發明之一實施例之諸如第2a圖的被分 10 組為區之區塊202之非依電性記憶體的區塊的圖式表示。第3a圖係根據本發明之一實施例之諸如第2b圖的區 212的非依電性記依體構件之區的圖式表示。第3b圖係根據本發明之一實施例之被分組為多頁區段之非依電性記依體構件之頁的圖式表示。 15 第4圖係根據本發明之一實施例之頁已被分配轉換頁數之非依電性記憶體之區的圖式表示。 · 第5圖係根據本發明之一實施例之將與非依電性記憶體之區塊有關之轉換頁數對映為實際實體頁數之對映的圖式表示。 20 第6圖係根據本發明之一實施例之被分組為區及單元之具有轉換頁數的數個區塊之圖式表示。第7圖係根據本發明之一實施例之可被用以促進多頁存取或規劃操作的查詢表之圖式表示。第8圖係根據本發明之一實施例之說明與執行諸如系 35 1272481 統之非依電性記憶體系統的多頁寫入操作之處理有關之步驟的處理流程圖。第9圖係根據本發明之一實施例之說明與牽涉使用查詢表之多頁寫入處理有關之步驟的處理流程圖。 5 第10圖係根據本發明之一實施例之說明與執行諸如系統之非依電性記憶體系統的讀取操作之處理有關之步驟的處理流程圖。第11圖係根據本發明之一實施例之說明與牽涉使用查詢表之讀取處理有關的步驟的處理流程圖。 10 第12圖係根據本發明之一實施例之系統架構的圖式方塊圖表示。Actual Page Number = PJ + % τ τλ\ ^ ^ A W % T—D) * (T - P - 1) - ((P, / T_D) % TJP) * (TD - 1) Therefore 'There are four zones In the system where each block contains thirty-two pages, the number of converted pages "4" can be mapped to the actual number of pages. Thus, in the case of the number of conversion pages "4" to "7" of the multi-page section to be written as 15 such systems, the lookup table 750, or more specifically, the entry 754, 756 of the lookup table. , 758, and 760 can be used to determine actual non-contiguous physical pages q", "33", "65", and "97" to be individually written as a multi-page segment at an access time. When the lookup table 750, or substantially any similar data structure is implemented, such as when computing and storing, in the controller body or software, the actual number of physical pages is effectively calculated to be relatively fast with minimal computation. Query the table. Therefore, a multi-page access operation such as a multi-page write command occurs relatively efficiently. Reference numerals relating to the processing of a multi-page write operation of a non-electrical memory system such as 29 1272481 including a system including an MLC flash memory will be described below in accordance with an embodiment of the present invention. The execution of the multi-page write operation process 800 begins in step 804 where the user provides information to be written to the page of the non-electrical memory using the user page convention or the number of converted pages. In the embodiment of the present invention, when the data is input into different areas, the user can issue a sequence of data input commands, and the controller body or software can substantially issue a command such as 11H dummy planning in response to each data input command. Dummy planning commands, at the same time, the data is still entered in different areas, as included in the reference to the SanDisk company in Sunny Valley, California, which was awarded the "512Mbit NAND flash" in August 2001. The product manual (512 Mbit NAND Flash Product Manual) is described. Once the user provides the data to be written, the algorithm can be executed, or more generally, the step 808 can be performed to effectively cause the number of converted pages to be mapped to the actual number of physical pages. Appropriate calculations that can be performed have been previously described above with reference to Figure 6. 15 After the mapping calculation is performed, in step 812, the number of user pages or converted pages is mapped or converted to the actual number of physical pages. Then, in step 816, the data to be written is written to the actual physical page of the non-electrical memory system or media using a multi-page plan command or write process. In other words, a multi-page section of a physical page is written about an access time. The multi-page planning command may include a quick-fetch planning command, such as a 15H cache planning command that enables the entity to plan. Once the page is written, the processing of performing a multi-page write operation is completed. Instead of performing several calculations to map the number of users or converted pages to the actual number of physical pages, the lookup table can be used to facilitate mapping the number of converted pages to the actual number of actual pages, as explained above with reference to Figure 7. Figure 9 is a process flow diagram of the steps associated with the multi-page write process involving the lookup table in accordance with an embodiment of the present invention. The process 900 of performing a multi-page write operation begins in step 904, where the user provides the data to be written using the user or the number of converted pages. Then, the number of converted pages is used in step 908, for example, by fetching a lookup table such as the lookup table of Fig. 7, by the controller body or software to determine the actual number of physical pages corresponding to the number of converted pages. Once the mapping between the number of converted pages and its corresponding actual number of pages is determined, the data is written to the actual page in step 912 using a multi-page or multi-block programming command. After the data is written to the actual page, the processing of writing the data is completed. 10 As mentioned earlier, in addition to planning or write processing, multiple page or multi-block commands can be used to erase multiple pages or blocks. In general, a read operation that occurs to read a page that has been written using a multi-page or multi-block command can be changed. Referring to Fig. 10, there will be explained steps relating to the reading process according to an embodiment of the present invention. The process 1000 of performing a read operation begins in step 1004, in which the user specifies the page of the non-electrical memory to be read using the user page convention or the number of converted pages. Once the number of conversion pages for which the data is to be read is specified, the algorithm can be executed, or more generally, at step 1008, the calculation can be performed to effectively map the number of converted pages to the actual number of physical pages. The appropriate calculations that can be performed are described above, as explained with reference to Figure 6. 20 After the mapping calculation is performed, in step 1012, the number of user pages or converted pages is mapped or converted to the actual number of physical pages. Then, in step 1016, the data to be read is read from the actual physical page of the non-electrical memory system using the read command. Once the page is read, the processing to perform the read operation is completed. 31 ^ 481 As a case of reading ^ operator (4) 'The lookup table can be used to facilitate the reading of the lookup table. ^ ^ The description of the consistent application and the users involved in the use of 5 users to read or access the data Two = for = war 'corresponding to the conversion of Wei's actual real number map: After the fine access is determined by the brother 7 10 pages, "_12 2 4 corresponds to the actual number of converted pages ^, 〆, shell material Obtained or read from the actual page. Once the data is read, the processing of reading the data is completed. : (4)' and the actuating multi-page planning command is executed or the number of conversion pages is mapped to the actual number of pages (4). (4) For example, 15 planning code device or host system. An embodiment of a system architecture relating to a software body provided to a host system in accordance with an embodiment of the present invention is shown in FIG. In general, the system architecture 700 includes various modules, which may include, but are not limited to, time dependent (4) 4, line manager module 708, tribute manager module 712, data integrity manager 716, and device s. Manager and interface module 72G. In general, system architecture 7(8) can be implemented using a software code device or body that can be accessed by a processor such as processor 1-8 of FIG. In general, the application interface module 704 can be arranged to communicate directly with a host, a operating system, or a user. The application interface module 〇4 also communicates with the system manager module 708 and the data manager module 712. When the user wants to read, write, or format the flash memory, the user issues a request to the operating system, and the 32 1272481 special request is transmitted to the application interface module 704. Depending on these requirements, the application "face group 704 directs these requirements to the system manager module or data manager 712. The system manager 708 includes the system initialization sub-module 724, the erasure number block, and the number of times. The module 726 and the power management block sub-module 73 are. In general, the system initialization sub-module 724 is arranged to be actuatable for initial processing and is typically in communication with the erasures block management sub-module 726. In addition to communicating with the application interface module 7.4, the system manager module 〇8 is also associated with the data manager module 712 and the device manager and interface module 72. The tribute manager module 712 in communication with both the system manager module 〇8 and the application interface module 704 can include functionality to provide page or block mapping. The data manager module 712 can also include functionality related to the operating system and file system interface layer. The device manager and interface module 720 that communicates with the system manager module 708, the data manager 712, and the data entity 15 manager 716 typically provides a fast: memory interface 'and includes a hardware abstract such as 1 / The interface is functional. The data integrity manager module 716 can provide other functional ecc vibrations. While the invention has been described by way of example only, the present invention may be embodied in various forms without departing from the spirit and scope of the invention. By way of example, a multi-page operation such as multi-page write or multi-block erase operation that maps the number of converted pages to real f pages has been generally described as being suitable for use with MLCNAND flash memory. However, it should be understood that the techniques and methods described herein can be substantially implemented in any non-electrical memory, such as binary NAND flash memory, to enhance the possible reading and writing. The efficiency of incoming and outgoing processing. In general, the lookup table can include any number of entries. For example, when the number of pages of the unit is small and a few units are included in the non-electrical memory structure, the lookup table may include all values so that only basic minimum calculations need to be performed to determine the number of converted pages. The actual number of pages. The size of the flash memory and the size of the block of the flash memory can vary widely. While the size of the block has been generally described as including about thirty-two pages, the block may include any number of pages, or more specifically, any number of elements of the resulting block. For example, a block may include about sixty-four elements or pages. Therefore, the number of blocks in the system can be changed. In the 512Mb binary NAND flash memory, if the block includes about thirty-two pages each containing about 512 bytes, 4096 total physical blocks are represented in the flash memory. Optionally, in the 512 Mb MLC NAND flash memory 15, if each physical block includes about 64 pages each having about 512 bytes, 2048 total physical blocks are represented by flash memory. . In general, the size of the page can also vary. The steps associated with the various methods of the invention can vary widely. In general, steps can be added, removed, reordered, and warned. Therefore, the previous examples are intended to be illustrative and not limiting, and the present invention is not limited to the details described herein, but may be modified within the scope of the appended claims. . [Simple diagram of the diagram 3 34 1272481 The first diagram is a schematic representation of a general host system including non-electrical memory. Figure lb is a pictorial representation of a memory device such as memory device 120 of Figure la. 5 The lc diagram is a diagram of the host system including the embedded non-electrical memory. Fig. 2a is a diagram showing a block of a non-electrical memory according to an embodiment of the present invention. 0 2b is a pictorial representation of a block of non-electrical memory of a block 202 of a group of regions, such as Figure 2a, in accordance with an embodiment of the present invention. Fig. 3a is a schematic representation of a region of a non-electrical memory member, such as region 212 of Fig. 2b, in accordance with an embodiment of the present invention. Figure 3b is a pictorial representation of a page of non-electrical responsive member members grouped into a plurality of page segments in accordance with an embodiment of the present invention. 15 Figure 4 is a pictorial representation of a region of a non-electrical memory that has been assigned a number of converted pages in accordance with an embodiment of the present invention. Figure 5 is a graphical representation of the mapping of the number of converted pages associated with a block of non-electrical memory to the mapping of the actual number of physical pages, in accordance with an embodiment of the present invention. 20 Figure 6 is a pictorial representation of a plurality of blocks grouped into regions and units having converted pages in accordance with an embodiment of the present invention. Figure 7 is a pictorial representation of a lookup table that can be used to facilitate multi-page access or planning operations in accordance with an embodiment of the present invention. Figure 8 is a process flow diagram illustrating the steps associated with the processing of a multi-page write operation such as the non-electrical memory system of the system, in accordance with an embodiment of the present invention. Figure 9 is a process flow diagram illustrating the steps associated with multi-page write processing involving the use of a lookup table in accordance with an embodiment of the present invention. 5 Figure 10 is a process flow diagram illustrating the steps associated with performing a process such as a read operation of a non-electrical memory system of a system, in accordance with an embodiment of the present invention. Figure 11 is a process flow diagram illustrating the steps associated with the read processing involving the use of a lookup table in accordance with an embodiment of the present invention. 10 Figure 12 is a pictorial block diagram representation of a system architecture in accordance with an embodiment of the present invention.

【圖式之主要元件代表符號表】 11 記憶體晶胞陣列 15 匯流排 17 位址解碼器 19 附加電路 21 緩衝器記憶體 23 部份 100 主機系統、電腦糸統 104 系統匯流排 108 微處理器 112 隨機存取記憶體 116 輸入/輸出電路 120 非依電性記憶體裝置 124 非依電性記憶體 128 任選記憶體控制系統 130 介面 150 主機、電腦糸統 154 系統匯流排 158 微處理器 162 隨機存取記憶體 166 輸入/輸出電路 174 非依電性記憶體 180 介面 36 1272481 202a、202b、202c、202d、202e、202f、202g、202h、202i、202j、 202k、202卜 402a、402b、402c、402d、402e、402f、420a、420b、 420c、420d、420e、420f、502a、502b、502c、502d、602a、602b、 602c、602d、602e、602f 區塊 0 至 159、M-63 至M 頁 212a、212b、212c、212d、412a、412b、412c、412d、622a、622b、 622c、622d、區[Main component representative symbol table of the figure] 11 Memory cell array 15 Busbar 17 Address decoder 19 Additional circuit 21 Buffer memory 23 Part 100 Host system, computer system 104 System bus 108 Microprocessor 112 Random Access Memory 116 Input/Output Circuit 120 Non-Electrical Memory Device 124 Non-Electrical Memory 128 Optional Memory Control System 130 Interface 150 Host, Computer System 154 System Bus 158 Microprocessor 162 Random access memory 166 input/output circuit 174 non-electrical memory 180 interface 36 1272481 202a, 202b, 202c, 202d, 202e, 202f, 202g, 202h, 202i, 202j, 202k, 202 402a, 402b, 402c , 402d, 402e, 402f, 420a, 420b, 420c, 420d, 420e, 420f, 502a, 502b, 502c, 502d, 602a, 602b, 602c, 602d, 602e, 602f blocks 0 to 159, M-63 to M pages 212a, 212b, 212c, 212d, 412a, 412b, 412c, 412d, 622a, 622b, 622c, 622d, zone

302a、302b、302c、302d、504a、504b、504c、504d、504a，、504b，、 504c’、504d’、604a、604b、612a、612b、616a、616b 頁 304、430a、430b、630a、630b 單元 530、530’ 多頁區段 650 偏移 700 系統架構 704 應用介面模組 708 系統管理者模組 712 資料管理者模組 716 資料完整性管理者模組 720 裝置管理者與介面模組 724 系統初始化次模組 730 電力管理區塊次模組302a, 302b, 302c, 302d, 504a, 504b, 504c, 504d, 504a, 504b, 504c', 504d', 604a, 604b, 612a, 612b, 616a, 616b page 304, 430a, 430b, 630a, 630b unit 530, 530' multi-page segment 650 offset 700 system architecture 704 application interface module 708 system manager module 712 data manager module 716 data integrity manager module 720 device manager and interface module 724 system initialization Secondary module 730 power management block secondary module

726 抹除次數區塊管理次模組750 查詢表 754、756、758、760 入口 800、900、1000、11〇〇處理 804、808、812、816、904、908、912、1004、1008、1012、1016、 1104、1108、1112 步驟 37726 erasure order block management sub-module 750 query table 754, 756, 758, 760 entries 800, 900, 1000, 11 〇〇 processes 804, 808, 812, 816, 904, 908, 912, 1004, 1008, 1012 , 1016, 1104, 1108, 1112 Step 37

Claims

127248¾ 092125783 號專利申請案：中文申請專利範圍替換本(95:%|月:丨拾、申請專利範圍： ° 1· 一種用以執行多頁命令之方法，該方法包含·· 獲得一第一頁數，該第一頁數係為一第一慣則中之一者，該第一頁數係排置為可識別一與一非依電性記憶體有關之第一頁；令該第-頁數對映於-第二頁數，該第二頁數係為一第二慣财之-者，該第二頁數係排置為可識別該第一頁，其中，令該第-頁數對映於該第二頁數包括識別一與該非依電性記憶體有關之總區數及—與總區塊數之每一區塊有關之總頁數；以及使用該第二頁數及該多頁命令存取該第一頁。 2·如申請專利範圍第1項所述之方法，其更包括：獲得一第三頁數’該第三頁數係為該第一慣則中之 -者’該第三頁數係排置為可識別—與—非依電性記憶體有關之第二頁；令該第三頁數對映於-第四頁數，該第四頁數係為該第二慣則中之一者，該第四頁數係排置為可識別該第一頁，以及使用该第二頁數存取該第一頁及實質地同時使用該第四頁數存取該第二頁。 3.如申請專利範圍第2項所述之方法，其中，存取該第一頁及存取該第二頁包括將資料寫入該第一頁及該第二頁。乂一 4·如申請專利範圍第2項所述之方法，其中，該第一頁係 95654-950828.doc Ϊ272481Patent application No. 1272483⁄4 092125783: Replacement of Chinese patent application scope (95:%|Month: Pick up, patent application scope: ° 1 · A method for executing a multi-page command, the method includes ·· obtaining a first page The first page number is one of a first rule, the first page number is arranged to identify a first page related to a non-electrical memory; The number is mapped to the second page number, the second page number is a second customary money, the second page number is arranged to identify the first page, wherein the first page number is Mapping the second page number includes identifying a total number of regions associated with the non-electrical memory and a total number of pages associated with each of the total number of blocks; and using the second page number and the The multi-page command accesses the first page. 2. The method of claim 1, further comprising: obtaining a third page number - the third page number is in the first rule - The third page number is identifiable—the second page related to the non-electrical memory; the third page is mapped to the fourth The fourth page number is one of the second habits, the fourth page number is arranged to identify the first page, and the first page is accessed using the second page number and the substance The method of claim 2, wherein accessing the first page and accessing the second page comprises writing data to the second page. The first page and the second page. The method of claim 2, wherein the first page is 95654-950828.doc Ϊ 272481

匕括於-第—區且該第二頁係包括於—第二區。Included in the -th district and the second page is included in the second zone.

6· 8· 9· 10. 如申η月專利範圍第1項所述之方法，其中，令該第一頁數對映於该第二頁數更包括識別該第—頁所在之—區。如申請專利範圍第5項所述之方法，其中，令該第—頁數對映於該第二頁數更再包括識別該第-頁所在之一區塊’及自該區塊之-起點狀該第—頁之一偏移。如申請專利第i項所述之方法，其中，該非依電性汜憶體係為一 NAND快閃記憶體。如申請專利範圍第7項所述之方法，其中，該胸〇快閃記憶體係為一 MLCNAND快閃記憶體。 -種用以執行多頁命令之方法，該方法包含：獲得一第一頁數，該第一頁數係為一第一慣則中之者’口亥第-頁數係排置為可識別一與一非依電性記憶體有關之第一頁； ―,令該第—頁數對映於—第二頁數，該第二頁數係為二第二慣則中之—者’該第二頁數係排置為可識別該第 ^頁，其中，令該第-頁數對映於該第二頁數包括使用 -第-值對一資料結構編索引，該第一值係使用該第一頁數而判定，該資料結構_置為含㈣映資訊；以及使用該第二頁數及該多頁命令存取該第一頁。如申請專利襲第9項所述之方法，其更包括：獲得-第三頁數，該第三頁係為該第—慣則中之一者’該第三頁數係排置為可識別_與該非依電性記憶體體有關之第二頁； 95654-950828.doc -2 - …/ 4第二頁數對映於—第四頁數，該第四頁數係為 6亥弟二慣則中之—者，該第四頁數係排置為可識別該第二頁，其中，令該第三該對映於該第四頁數包括使用一弟二值對該資料結構編㈣，該第二值係'使用該第三頁數而判定；以及使用該第二頁數存敢兮楚石 ^ 仔取δ亥弟一頁及實質地同時使用该第四頁數存取該第二頁。 U·如申請專利範圍第Π)項所述之方法，其中，存取該第一頁及存取該第二頁包括將f料寫人該第—頁及該第二頁0 •如申請專利範圍第10項所述 ΜΜ述之方法，其中，該第一頁係包括於一第一區且該第二頁係包括於一第二區。 13·如申請專利範圍第9 只汀述之方法，其中，該非依電性記憶體係為一 NAND快閃記憶體。 14·如申請專利範圍第13項所述貝尸汀返之方法，其中，該NAND快閃記憶體係為一 MLCNAND快閃記憶體。 15.一種用以輯雜電性記憶體之數區之方法，該等數區之母-區皆包括至少—區塊，該等數區之每—區之該至少一區塊包括數頁，該方法包含：只双丁一興該等數區之第！’ a第-頁數係為—第_慣則中之—者；以及 #分配一第二頁數予—與該等數區之-第二區有關之第一頁’其巾’使用與包括於該等數區之—總區數及包括於該第—區之-總頁數有關之資訊，該第一頁數係 95654-950828.doc 1272481 Γ^8：23 i * . .. i ' 、•价山 · ^ 1哪心罘一貰體貝，且該第二頁數係排置為可被轉換為—與該第二頁有關之第二實體頁數。 16· =申請專利範圍第15項所述之方法，其中，與包括於該雜區之該總區數及包括於該第一區之該總頁數有關之该資訊係至少部份地包含於一資料結 1入如申料利範圍第15項所述之方法，其中，該第二頁數係實質地連續於該第一頁數。从如申請專利範圍第15項所述之方法，其中，該第一頁及該第二頁係排置為可使用—單—多頁命令而存取。 19·如申請專利範圍第18項所述之方法，其中，該單一多頁命令係為-排置為可使用該第一實體頁數及該第二實體頁數而將資料寫入該第-頁及該第二頁之多頁寫入命令。 ^ 20· 一種非依電性記憶體系統，其包含：一非依電性記憶體，該非依電性記憶體包括數頁，該等數頁係排置於數個區塊，料數麵塊係排置於數區，該等數頁包括一第一頁；〜用以獲得一第一頁數之碼裝置，該第一頁數係為一 H貝則中之-者，該第-胃數係排置為可識別該頁； #用以令該第-頁數對映於_第二頁數之碼裝置，該弟-頁數係、為-第二慣則中之_者，該第二頁數係排置為可識_第-頁，其巾，用以令該第—頁數對映於該 95654-950828.doc -4- !27248l 28 j 年月曰修ί/丨正替換頁第一頁數之該等碼裝置包括用以識別一總區數及與一違總區塊數之每一區塊有關之該等數頁之總數的碼裝置；用以使用該第二頁數存取該第一頁之碼裝置；以及用以儲存該等碼装置之一記憶體。 21·如申請專利朗第2G項所述之系統，其更包括：用以獲得一第三頁數之碼裝置，該第三頁數係為該第丨貝則中之一者，該第三頁數係排置為可識別該等數頁之一第二頁；用以令該第三頁數對映於一第四頁數之碼裝置，該第四頁數係為該第二慣則中之一者，該第四頁數係排置為可識別該第二頁；以及用以使用該第二頁數存取該第一頁及實質地同時使用該第四頁數存取該第二頁之碼裝置。 22·如申請專利範圍第21項所述之系統，其中，用以存取該 =一頁及用以存取該第二頁之該等碼裝置包括用以將 >料寫入該第一頁及該第二頁之碼裝置。 23. 如申請專利範圍第21項所述之系統，其中，該第一頁係包括於一第一區且該第二頁係包括於該第二區。 24. 如申請專利範圍第2〇項所述之系統，其中，用以令該第 -頁數對映於該第二頁數之該等碼裝置更包括用以識別該第一頁所在之一區的碼裝置。 2 5.如申請專利範圍第2 4項所述之系統，其中，令該第一頁數對映於該第二頁數更包括識別該第—頁所在之一區 95654-950828.doc 1272481 κ 」塊，及自該區塊之一起點判定該第一頁之一偏移。 26.如申請專利範圍第20項所述之系統，其中，該非依電性 5己憶體係為一 MLC NAND快閃記憶體。 27· —種非依電性記憶體系統，其包含：一非依電性記憶體，該非依電性記憶體包括一頁； _ 、用以維持—資料結構之碼裝置，該f料結構係排置為含有對映資訊；用以獲得-第-頁數之碼裝置，該第一頁數係為一第一慣則中之—者’該第—頁數係排置為可識別該第— 頁；用以令該第-頁數對映於—第二頁數之碼裝置，該第二頁數係為-第二慣财之—者，該第二頁數係排置為可識別該第-頁，其中，令該第—頁數對映於該第二頁數包括使用一第一值對該資料結構編索引，該第一值係使用該第一頁數而判定；用以使用該第二頁數存取該第—頁之碼裝置；以及用以儲存該等碼裝置及該資料結構之一區域。 28.如申請專利範圍第27項所述之系統，其更包括：用以獲知一第三頁數之碼裝置，該第三頁數係為該第-十貝則中之-者’該第三頁數係排置為可識別一包括於該非依電性記憶體之第二頁；用以令該第三頁數對映於一第四頁數之碼裝置，該第四頁數係為該第二慣則中之—者，該第四頁數係排置 95654-950828.doc !272481 =可識別該第二頁，其中，用以令該第三頁數對映於該第四頁數之該等碼裝置包括用以使用—第料結構編索引之碼裝置，該第二值係使用該第三頁=而判定；以及用以使用該第二頁數存取該第一頁及實質地同時使用該第四頁數存取該第二頁之碼裝置。 29.如申請專利範圍第28項所述之系統，其中，用以存取該第—頁及用以存取該第二頁之該等碼裝置包括用以將資料寫入該第-頁及該第二頁之碼裝置。 3 0 ·如申請專利範圍第2 8項所述之系統，其中，該第一頁係包括於-第-區且該第二頁係包括於_第二區。 31·如申請專利範圍第27項所述之純，其中，該非依電性記憶體係為一 MLCNAND快閃記憶體。 32. -種用以組織非依電性記憶體之數區之系統，該等數區之每-區包括至少-區塊，該等數區之每一區之該至少一區塊包括數頁，該系統包含·· 用以將-第-頁數分配予—與該等數區之一第一區有關之第-頁的碼裝置，該第―頁數係為—第一慣則中之一者；用以將-第二頁數分配予—與該等數區之一第二區有關之第二頁的碼裝置，其中，使用與包括於該等數區之-總區數及包括於該第一區之一總頁數有關之資訊’該第一頁數係排置為可被轉換為一與該第一頁有關之第-實體該，且該第二頁係排置為可被轉換為一與 95654-950828.doc 1272481 3肩，6. The method of claim 1, wherein the mapping of the first page to the second page further comprises identifying a region in which the first page is located. The method of claim 5, wherein the mapping of the first page to the second page further comprises identifying a block of the first page and starting from the block One of the first page offsets. The method of claim i, wherein the non-electrical memory system is a NAND flash memory. The method of claim 7, wherein the chest flash memory system is a MLCNAND flash memory. a method for executing a multi-page command, the method comprising: obtaining a first page number, wherein the first page number is a first one of the first habits, and the number of pages is set to be identifiable a first page associated with a non-electrical memory; ―, the first page number is mapped to the second page number, and the second page number is the second second rule The second page number is arranged to identify the page, wherein the mapping of the first page to the second page comprises indexing a data structure using a -value-value, the first value is used Determining, by the first page number, the data structure _ is set to contain (four) mapping information; and accessing the first page using the second page number and the multi-page command. The method of claim 9, wherein the method further comprises: obtaining - a third page, the third page being one of the first rules - the third page is ranked as identifiable _The second page related to the non-electrical memory body; 95654-950828.doc -2 - .../ 4 The second page number is mapped to the fourth page number, and the fourth page number is 6 Haidi II In the habit, the fourth page number is arranged to identify the second page, wherein the third mapping of the fourth page number includes using the second binary value to edit the data structure (4) The second value is determined by using the third page number; and using the second page number to save the daring stone, taking a page of δ hai, and substantially simultaneously accessing the fourth page number Two pages. U. The method of claim 2, wherein accessing the first page and accessing the second page comprises writing the material to the first page and the second page. The method of claim 10, wherein the first page is included in a first zone and the second page is included in a second zone. 13. The method of claim 9, wherein the non-electrical memory system is a NAND flash memory. 14. The method according to claim 13, wherein the NAND flash memory system is a MLCNAND flash memory. 15. A method for composing a number of electrical memory regions, wherein each of the parent regions of the plurality of regions includes at least a block, and the at least one block of each of the plurality of regions includes a plurality of pages. The method includes: Only the double Ding Yixing the number of the number of zones! ' a page number is - in the _ idiom - and # 分配 a second page number - the first page related to the second area - the second area of the 'the towel' use and include Information relating to the total number of zones and the total number of pages included in the first zone, the first page number is 95654-950828.doc 1272481 Γ^8:23 i * . .. i ' , • price mountain · ^ 1 which is a heart-shaped shell, and the second page number is arranged to be converted into - the number of second physical pages related to the second page. The method of claim 15 wherein the information relating to the total number of zones included in the zone and the total number of pages included in the zone is at least partially included in The method of claim 15, wherein the second page number is substantially continuous with the first page number. The method of claim 15, wherein the first page and the second page are arranged to be accessible using a single-multiple page command. The method of claim 18, wherein the single multi-page command is - arranged to write data to the first physical page number and the second physical page number - page and multiple page write commands for the second page. ^20· A non-electrical memory system, comprising: a non-electrical memory, the non-electrical memory comprising a plurality of pages, the plurality of pages are arranged in a plurality of blocks, and the number of blocks is The row is placed in a number of pages, the pages include a first page; ~ used to obtain a first page number of code devices, the first number of pages is one of the H-shells, the first-stomach The number system is arranged to recognize the page; # is to make the first page number to be mapped to the second page number device, the brother-page number is - in the second rule, the The second page is arranged to be _page-, and the towel is used to make the number of pages to be displayed in the 95654-950828.doc -4- !27248l 28 j months 曰 ί 丨The code device for replacing the first page of the page includes code means for identifying a total number of zones and a total number of the pages associated with each block of the total number of blocks; for using the second The number of pages accesses the code device of the first page; and a memory for storing the code device. 21. The system of claim 2, wherein the method further comprises: obtaining a third page number device, the third page number being one of the third mussels, the third The number of pages is arranged to identify a second page of the plurality of pages; a code device for mapping the third page number to a fourth page number, the fourth page number being the second rule One of the fourth page numbers is arranged to recognize the second page; and to access the first page using the second page number and substantially simultaneously use the fourth page number to access the first page Two-page code device. The system of claim 21, wherein the means for accessing the page and for accessing the second page comprises writing > The page and the code device of the second page. 23. The system of claim 21, wherein the first page is included in a first zone and the second page is included in the second zone. 24. The system of claim 2, wherein the means for causing the page number to be mapped to the second page further comprises identifying one of the first page The code device of the area. 2. The system of claim 24, wherein the mapping of the first page to the second page further comprises identifying a region of the first page 95654-950828.doc 1272481 κ The block, and one of the starting points of the block determines an offset of the first page. 26. The system of claim 20, wherein the non-electrical memory system is an MLC NAND flash memory. 27. A non-electrical memory system comprising: a non-electrical memory, the non-electrical memory comprising a page; _, a code device for maintaining a data structure, the f structure Arranging to include the mapping information; to obtain a -page number of code device, the first page number is in a first habit - the 'the first page number is arranged to identify the first - a page; a code device for mapping the first page number to the second page number, the second page number being - the second one, the second page number being ranked as identifiable The first page, wherein the mapping the first page number to the second page number comprises indexing the data structure using a first value, the first value being determined by using the first page number; Accessing the first page of code devices using the second page number; and storing the code device and an area of the data structure. 28. The system of claim 27, further comprising: a device for learning a third page number, the third page number being the one in the tenth The three pages are arranged to identify a second page included in the non-electrical memory; the third page is used to map the third page to a fourth page number, the fourth page is In the second convention, the fourth page number is 95654-950828.doc !272481=the second page is identifiable, wherein the third page number is used to map the fourth page to the fourth page. The number of code devices includes a code device for indexing using a first material structure, the second value is determined using the third page =; and the first page is accessed using the second page number and The fourth page number is used to access the second page of code devices substantially simultaneously. 29. The system of claim 28, wherein the means for accessing the page and for accessing the second page comprises means for writing data to the page and The code device of the second page. The system of claim 28, wherein the first page is included in the -th region and the second page is included in the second region. 31. The purity as described in claim 27, wherein the non-electrical memory system is a MLCNAND flash memory. 32. A system for organizing a number of regions of non-electrical memory, each of the regions including at least a block, the at least one block of each of the regions including a plurality of pages The system includes a code device for assigning a -page number to a first page associated with a first region of the equal number region, the first page number being - in the first routine a code device for assigning a second page number to a second page associated with a second region of the plurality of regions, wherein the total number of zones included and included in the number of regions is included Information relating to the total number of pages in one of the first zones 'the first page number is arranged to be converted into a first entity related to the first page, and the second page is arranged to be Was converted to a shoulder with 95654-950828.doc 1272481 3

該第二頁有關之第二實體頁數；以及一用以儲存該等碼裝置之記憶體。 33 34 .如申請專利範圍第32項所述之系統，其更包括用以使用一單一多頁命令存取該第一頁與該第二頁之碼裝置。 .一種用以執行多頁命令之系統，該系統包含：用以獲得一第一頁數之裝置，該第一頁數係為一第一慣則中之一者，該第一頁數係排置為可識別一與一非依電性記憶體有關之第一頁；用以令该第一頁數對映於一第二頁數之裝置，該第一頁數係為一第二慣則中之一者，該第二頁數係排置為可識別該第一頁，其中，用以令該第一頁數對映於該第二頁數之該等裝置包括用以識別一與該非依電性記憶體有關之總區數，及一與一總區塊數之每一區塊有關之總頁數的裝置；以及用以使用該第二頁數存取該第一頁之裝置。 35. 如申請專利範圍第34項所述之系統，其更包括：用以獲得-第三頁數之裝置，該第三頁數係為該第一慣則中之一者’該第三頁數係排置為可識別—與一非依電性記憶體有關之第二頁；一用以令該第三頁數對映於一第四頁數之裝置置為四頁數係為該第二慣則中之—者，該第四頁數係可識別該第二頁；以及不用以使用該第二頁數存取該第一頁及實使用該第四頁數存取該第二頁之裝置。 3日、 95654-950828.doc Ϊ272481The second page relates to the second physical page number; and a memory for storing the code device. 33. The system of claim 32, further comprising means for accessing the first page and the second page using a single multi-page command. A system for executing a multi-page command, the system comprising: means for obtaining a first page number, the first page number being one of a first rule, the first page number The first page related to the non-electrical memory is identified; the device for mapping the first page to the second page, the first page is a second In one of the ways, the second page number is arranged to identify the first page, wherein the means for causing the first page number to be mapped to the second page number comprises identifying one and the other a device for the total number of pages associated with the electrical memory, and a total number of pages associated with each of the blocks of the total number of blocks; and means for accessing the first page using the second number of pages. 35. The system of claim 34, further comprising: means for obtaining - a third page number, the third page number being one of the first habits 'the third page The number is arranged to be identifiable - a second page related to a non-electrical memory; a device for causing the third page to be mapped to a fourth page to be a four page number In the second habit, the fourth page number identifies the second page; and the second page is not accessed by using the second page number and the second page is accessed using the fourth page number Device. 3rd, 95654-950828.doc Ϊ272481

36·如申請專利範圍第34項所述之系統，其中，該非依電性記憶體係為一 MLC NAND快閃記憶體。 37· —種用以執行多頁命令之系統，該系統包含：用以獲得一第一頁數之裝置，該第一頁數係為一第一慣則中之一者，該第一頁數係排置為可識別一與一非依電性記憶體有關之第一頁；用以令該第一頁數對映於一第二頁數之裝置，該第二頁數係為一第二慣則中之一者，該第二頁數係排置為可識別該第一頁，其中，用以令該第一頁數對映於該第二頁數之該等裝置包括用以使用一第一值對一資料結構編索引之裝置，該資料結構係排置為含有對映資訊；以及用以使用該第二頁數存取該第一頁之裝置。 38·如申請專利範圍第37項所述之系統，其更包括：用以獲得一第三頁數之裝置，該第三頁數係為該第慣則中之一者，該第三頁數係排置為可識別一與該非依電性記憶體有關之第二頁；用以令該第三頁數對映於一第四頁數之裝置，該第四頁數係為該第二慣則中之—者，該第四頁數係排置為可識別該第二頁，其中，用以令該第三頁數對映於該第四頁數之該等裝置包括用以使用一第二值對該資料結構編索引之裝置，該第二值係使用該第三頁數而判定；以及用以使用該第二頁數存取該第一頁及實質地同時 95654-950828.doc I27248if 8激 J 土替換: 使用該第四頁數存取該第二頁之裝置。 39.如申請專利範圍第37項所述之系統，其中，該非依電性吕己憶體係為一 MLC NAND快閃記憶體。 40· —種使用共用命令存取數個記憶體元件之方法，該等數個纪憶體元件係被分組為一非依電性記憶體之數個群組，該等數個群組係排置於數區，該方法包含：使用一第一慣則之識別器識別該等數個記憶體元件；實質地將該第一慣則之該等識別器轉換為該第二慣則之識別器，該第二慣則之該等識別器係排置為對應於該非依電性記憶體之該等數個記憶體元件之實際位置，其中，將該第一慣則之該等識別器轉換為該第二慣則之識別器包括使用與包括於該等數區之一總區數有關之 > 訊、與包括於該等數個群組之每一群組之一記憶體元件總數有關之資訊、及該第一識別器；以及使用該共用命令存取該等數個記憶體元件。 41·如申請專利範圍第4〇項所述之方法，其中，該第一慣則之可識別包括於該等數區之一第一區的該等數個記憶體7L件之一第一記憶體元件的一第一識別器係排置為具有一第一值，該第一慣則之可識別包括於該等數區之一第二區的該等數個記憶體元件之一第二記憶體元件的一第二識別器係排置為具有一第二值，其中，該第二值係為該第一值加一之值。 42·如申請專利範圍第41項所述之方法，其中，該第一記憶 95654-950828.doc -10- 1272481 9| 日修(夕止替換頁體元件並未直接實體地連續於該第二記憶體元件。 43·如申請專利範圍第40項所述之方法，其中，使用該共用命令存取該等數個記憶體元件包括實質地使用該共用命令之-單-實例將請寫人該等數個記憶體元件，及使用5亥共用命令之一單一實例自該等數個記憶體元件抹除資料中之一者。攸如申請專利範圍第40項所述之方法，其中，使用與包括於該等數區之該總區數有關之該資訊、與包括於該等數，群組之每—群組之—記憶體總數有關的該資訊、及該第—識別器將該第-慣則之該等識別器轉換為該第二慣則之識別器包括對包括與該第二慣則之該等識別器有關之資訊之一資料結構編索引。仏如申請專利範圍第40項所述之方法，其中，使用與包括於該等數區之該總區數有關之該資訊、與包括於該等數個群組之每—群組之—記憶韻財_該資訊、及該第-識別器將該第一慣則之該等識別器轉換為該第二慣則之識別器包括：執行-計算，該計算侧置為可狀料二慣則之對應於該第-慣則之-第一識別器的一第二識別器，其中’該計算使用與包括於鱗數區之該總區數有關之該資訊、與包括於該等數個群組之每—群組之_記憶體總數有關的該資訊。 ^ 扣·如申請專利範圍第4〇項所述之方法，其中，該等數個群經係為數㈣塊，且料數個記憶體元件係為數個實體 95654-950828.doc -11 -36. The system of claim 34, wherein the non-electrical memory system is an MLC NAND flash memory. 37. A system for executing a multi-page command, the system comprising: means for obtaining a first page number, the first page number being one of a first rule, the first page number The device is arranged to identify a first page associated with a non-electrical memory; a device for mapping the first page number to a second page number, the second page number being a second In one of the habits, the second page number is arranged to identify the first page, wherein the means for causing the first page number to be mapped to the second page number comprises using one The first value is an apparatus for indexing a data structure, the data structure is arranged to contain mapping information; and means for accessing the first page using the second page number. 38. The system of claim 37, further comprising: means for obtaining a third page number, the third page number being one of the first rules, the third page number The device is arranged to identify a second page associated with the non-electrical memory; the device for mapping the third page to a fourth page, the fourth page is the second And wherein the fourth page number is arranged to identify the second page, wherein the means for causing the third page number to be mapped to the fourth page number comprises using a A device for indexing the data structure, the second value is determined using the third page number; and the first page is accessed using the second page number and substantially simultaneously 95654-950828.doc I27248if 8 激J earth replacement: The device that accesses the second page using the fourth page number. 39. The system of claim 37, wherein the non-electricality system is an MLC NAND flash memory. 40. A method for accessing a plurality of memory elements using a common command, the plurality of memory elements being grouped into a plurality of groups of non-electrical memory, the plurality of groups Placed in the number field, the method includes: identifying the plurality of memory elements using a first conventional identifier; substantially converting the identifiers of the first inertia into the identifiers of the second inertia The identifiers of the second habit are arranged to correspond to actual positions of the plurality of memory elements of the non-electrical memory, wherein the identifiers of the first habit are converted into The second conventional identifier includes using a > information relating to a total number of regions included in the plurality of regions, and relating to a total number of memory components of each of the groups included in the plurality of groups Information, and the first identifier; and accessing the plurality of memory elements using the common command. The method of claim 4, wherein the first conventional identifiable one of the first plurality of memory 7L pieces included in the first region of the equal number region is first memory a first identifier of the body element is arranged to have a first value, the first habit identifying a second memory of the one of the plurality of memory elements included in the second area of the one of the equal parts A second identifier of the body element is arranged to have a second value, wherein the second value is a value of the first value plus one. 42. The method of claim 41, wherein the first memory 95654-950828.doc -10- 1272481 9| day repair (the replacement of the page body element is not directly physically continuous to the second The method of claim 40, wherein accessing the plurality of memory elements using the common command comprises substantially using the common command - a single-instance One of a plurality of memory elements, and one of the plurality of memory elements is erased from the data using a single instance of the 5-Hui common command. For example, the method of claim 40, wherein The information relating to the total number of the total number of zones included in the number zone, the information relating to the total number of memories included in each of the groups, the group, and the first identifier - Converting the identifiers of the identifiable identifiers to the second idiom comprises indexing a data structure comprising information relating to the identifiers of the second idiom. For example, claim 40 Method, wherein, using and package The information relating to the total number of the total number of zones, and each of the groups included in the plurality of groups - the memory of the memory - the information, and the first-identifier to the first rule The identifiers of the identifiers converted into the second habits include: an execution-calculation, the calculation side being a second of the first identifiers corresponding to the first-segment a recognizer, wherein 'the calculation uses the information relating to the total number of the total number of zones included in the scalar zone, and the information relating to the total number of _ memories included in each of the plurality of groups. The method of claim 4, wherein the plurality of group warp systems are a number (four) block, and the number of memory elements is a plurality of entities 95654-950828.doc -11 -

1272481 頁。 47.如申請專利範圍第40項所述之方法，其中，該非依電性記憶體係為一 NAND快閃記憶體。 95654-950828.doc 12- 28. 127$ 偏 J25783 號專利申請案中文圖式替換頁(95年8月 100- 116 112 120- 12A- 128- -108 非依電性記憶體任選記憶體控制系統輸入/輸出電路隨機存取記憶體微處理器 130- .104 介面 —工第 la勗1272481 pages. 47. The method of claim 40, wherein the non-electrical memory system is a NAND flash memory. 95654-950828.doc 12- 28. 127$ partial Chinese translation of J25783 patent application (August 95-116 112 120- 12A- 128--108 non-electric memory optional memory control System Input/Output Circuit Random Access Memory Microprocessor 130-.104 Interface - Gongdi La勖

120 127#洗|土5783號專利申請案中文圖式替換頁(95年8月）120 127#洗|土5783 Patent Application Chinese Graphic Replacement Page (August 95)

第lc匱 T979ZLS1 I年月曰修(東)止替換頁， ¥MK5783號專利申譆^—— 丨，中文圖式替換頁(95年8月）The lc匮 T979ZLS1 I year month repair (east) stop replacement page, ¥MK5783 patent application —— ^—— 丨, Chinese graphic replacement page (August 95)

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