TWI271857B - Solid-state image pickup device using charged-coupled devices and method for fabricating the same - Google Patents
Solid-state image pickup device using charged-coupled devices and method for fabricating the same Download PDFInfo
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H01L27/144—Devices controlled by radiation
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Abstract
Description
1271857 玖、發明說明： 【發明所屬之技術領域】 本發明關於一種使用電荷耦合裝置（Charged Coupled Devices，CCD)之固態攝像設備，尤指關於一種使用cCD 組裝固遙攝像設備的方法，其能夠簡化或修改製程以增加 產出率、藉由使入射光之擴散反射最小而克服不精確的光 收集、且避免光入射在鄰近單元上，以及使用據以組裝之 CCD的固態攝像設備。1271857 发明Invention Description: [Technical Field] The present invention relates to a solid-state imaging device using a Charged Coupled Device (CCD), and more particularly to a method for assembling a solid-state imaging device using a cCD, which can simplify Or modifying the process to increase the yield, overcome inaccurate light collection by minimizing the diffuse reflection of incident light, and avoid light being incident on adjacent cells, and using a solid-state imaging device with which the CCD is assembled.
【先前技術】 第1圖係顯不使用具有一般蜂房式結構之Ccd的固態 攝像設備之俯視圖。 如第1圖顯示，使用CCD之固態攝像設備包括一形成在 一半導體基材1之表面上的光阻部分1〇，一形成在光阻部分 1 0之外側的介面部分6 0，一形成在介面部分6 〇之外側的輸 出傳送部分70，及一鄰接到輸出傳送部分7〇之一端的輸出 單元80。[Prior Art] Fig. 1 is a plan view showing a solid-state image pickup apparatus which does not use a Ccd having a general honeycomb structure. As shown in Fig. 1, a solid-state image pickup apparatus using a CCD includes a photoresist portion 1 formed on a surface of a semiconductor substrate 1, and an interface portion 60 formed on the outer side of the photoresist portion 10, one formed in An output transfer portion 70 on the outer side of the interface portion 6 and an output unit 80 adjacent to one end of the output transfer portion 7''.
形成在半導體基材1上之光阻部分1()包括8光電轉換元 件行20、8光電轉換元件列21、4垂直傳送CCD 30，以及32 讀出閘極區域4 0。 各8光電轉換元件行20包括在一 p型井内之η型區域中 的4光電轉換元件22。同樣地，各8光電轉換元件列2 1包括4 光電轉換元件22。 各垂直傳送CCD 30皆包括一在ρ型井内之η型區域中 5 1271857 構成的電荷傳送通道（未_ ^ . 4不），该p型井係形成在半導俨其 材1之一表面上，5第一偯这带卞V體基 、電極3 2係形成在半導體 之表面的電絕緣膜丨，其橫過平面圖中之電荷傳送；： 且4第一傳运電極33形成在半導體基材i之上 二 膜上，橫過平面圖中之電荷傳送通道。例如，第_^緣 傳送電極32和33係分别形成在第Hu”/: -及第電極32和33係沿t荷傳送通道交替地The photoresist portion 1 () formed on the semiconductor substrate 1 includes 8 photoelectric conversion element rows 20, 8 photoelectric conversion element columns 21, 4 vertically transmitting CCD 30, and 32 read gate region 40. Each of the eight photoelectric conversion element rows 20 includes four photoelectric conversion elements 22 in an n-type region in a p-type well. Similarly, each of the eight photoelectric conversion element columns 2 1 includes four photoelectric conversion elements 22. Each of the vertical transfer CCDs 30 includes a charge transfer path (not _^.4) formed in the n-type region in the p-type well, and the p-type well is formed on one surface of the semi-conductive material 1 5, the first 卞V body group, the electrode 32 is an electrically insulating film 形成 formed on the surface of the semiconductor, which is transferred across the charge in the plan view; and 4 the first transfer electrode 33 is formed on the semiconductor substrate On the second film above i, traverse the charge transfer channel in the plan view. For example, the _^ edge transfer electrodes 32 and 33 are formed at the Hu"/:- and the second electrodes 32 and 33, respectively, along the t-load transfer channel.
各讀出閘極區域40係由斜線所指，其係鋸齒狀y 。 介面部分60包括12電荷傳送級，係連接到構成垂 送CCD 30之電荷傳送通道的—端。各該12電荷傳送級包括 一被引至電荷傳送通道之介面單元電荷傳送通道（未顯 不），且形成在半導體基材！上的3傳送電極61、Μ及Μ其中 之一，係橫越平面圖中的介面單元電荷傳送通道。 第2圖係使用c C D的先前技術固態攝像設備之像素的 斷面圖。 如第2圖中所示，用於使用CCD 2 〇〇之先前技術固態攝 像設備的光二極體（pD)區域，係形成使得一第一 p型井 111 (將近3微米厚）係使用雜質植入等形成在一 ^型半導體 基材110上，接著一 η型雜質摻雜區域（PDN)l 13係形成在第 一 P型井111上，且最後一 p型雜質摻雜區域（PDP)114係形成 在η型雜質摻雜區域Π3之表面上。 該Ρ型雜質摻雜區域1 1 4係以一較高濃度之ρ型雜質摻 雜，使得其變成ρ +型摻雜區域，故防止產生在光二極體表 面上之電子流入該光二極體區域中。同樣地，形成在ρ型雜 6 1271857 質摻雜區域114下之η型雜質摻雜 只心雜&域1 1 3，係藉由向其植入 離子以累積電子。 另一方面，第一 p型井11丨係形成在n型雜質摻雜區域 113下，以控制輝散和快門控制。在此，第_ρ型井U1愈深， 用於累積光的區域愈大，因而增加其靈敏性。 第一 p型井111在其中形成一電位阻障以在光二極體區 域内收集電子。若電子過量，會將過量電子依據劑量單位 抽取到η型半導體基材1 1 〇。 由於第一 ρ型井111的深度愈大，在該深度方向中之光 二極體區域愈寬，故會累積相對較大量的電子，因而增加 靈敏性。然而，若第一 ρ型井11丨過深，因為電子係由紅外 光以及紅可見光產生’可能在彩色重製上會有負面效應。 因此’基於最佳能量和劑量單位，第一 ρ型井應由離子植入。 一第二ρ型井115係形成在η型半導體基材no表面上之 第一 Ρ型井111上。第二ρ型井115係藉由預定距離與η型雜質 摻雜區域113隔開。第二ρ型井115在其表面周圍形成一埋入 式CCD(BCCD)118。BCCD 118依據施加至多晶矽電極141 和1 43的電壓累積且傳送電子。 傳送閘極（TG) 11 9和通道停止區域（CST) 11 7係形成在n 型雜質摻雜區域113和第二ρ型井115間。在此，TG 119連接 n型雜質摻雜區域113與第二ρ型井115,且CST 117防止電子 桃到鄰近單元。 在形成如上述之結構後，一第一保護膜1 2 1係形成在包 括n型雜質摻雜區域113和第二p型井115的表面上。多晶石夕 7 1271857 電極1 4 1和1 43係形成在第一保護膜上，其係使用化學氣相 沉積（CVD)形成在第二p型井115之上側。 在形成多晶矽電極141和143後，第二保護膜123會覆蓋 在其上側。之後，一金屬光遮蔽膜i 24係藉由蝕刻形成在第 二保護膜1 2 3上，使得η型雜質摻雜區域11 3被開啟。 在形成金屬光遮蔽膜124以使η型雜質摻雜區域113開 啟後，一硼磷矽玻璃（BPSG)層125係沉積在其上。之後， 一鈍化膜或平坦化膜126係形成在BPSG膜125上，且接著藉 由平坦化製程加以平坦化。隨後，一濾色器圖案1 3 〇係形成 在該鈍化膜或平坦化膜1 2 6之已平坦化表面上。 另一方面，在藉由平坦化技術平坦化Bp S G 1 2 5後，一 濾色器圖案1 3 0可形成在已平坦化之b p s G 1 2 5上。在此情 況下’先前技術之優點在於該製程可簡化，且當堆疊折射 率與BPSG 125不同之鈍化膜或平坦化膜ι26時可降低擴散 反射。 然而，在使用CCD之先前技術固態攝像設備中，由於 金屬光遮蔽膜係已形成’且接著BPSG膜形成在金屬光遮蔽 膜上’ BPSG膜之凹部的曲率係相當大。因此，入射在bpsg 膜上之光係大幅地擴散，使得光收集無法正常地施行。同 時，入射光係大幅地折射且傳播至其他鄰近一特定像素之 像素，從而使圖像品質惡化。 此外，在堆豐金屬光遮蔽膜之情況下，由於多晶石夕電 極等之出現’在金屬光遮蔽膜上會有翹曲。因此，具有麵 曲在其上而曲率相對較大之金屬光遮蔽膜會難以蝕刻。當 8 1271857 蝕刻此一金屬光遮蔽膜時，其將難以精確地蝕刻。 同時’當平坦化沉積在金屬光遮蔽膜上之BPSG膜時， 可此曰損壞多晶矽電極。即，當b p s 〇膜如第3 a圖所示沉積 在金屬光遮蔽膜上時，BPSG膜凹部之最低點（由「b」所指） 的位置可旎低於多晶矽電極之最高點（由「&」所指）。因此， 田平坦化製程施加於具有此結構之B p s 〇膜時，結果可能造 成例如移除多晶矽電極之上部，如第讣圖所示。 【發明内容】 因此’本發明係鑑於上述問題進行，且本發明之目的 在於提供種使用CCD用於組裝固態攝像設備之方法，其 能簡化或修改製程以增加產出率、藉由使入射光之擴散反 射最小而克服不精確之光收集、且避免光入射在鄰近單元 上，以及使用此方法組裝CCD之固態攝像設備。 依據本發明一態樣，上述及其他目的可藉由提出一種 使用電荷耦合裝置（CCD)之固態攝像設備而達成，該固態 攝像設備包括形成在半導體基材表面上之n型雜質摻雜區 域和埋入式電荷耦合裝置（BCCD)區域。該固態攝像設備至 少包含一第一保護膜，其係形成在η型雜質摻雜區域和 BCCD區域上，多晶矽電極，其係製備在已形成於bccD區 域上之第一保護膜上；一第二保護膜，其覆蓋該等多晶矽 電極上·’一 BPSG膜，其係以預定厚度形成在該第一和第二 保護膜之上表面上；一金屬光遮蔽膜，其形成在該Bps(j 膜上’使彳于η型雜質摻雜區域可被開啟；及一鈍化膜或一平 1271857 坦化膜，其係形成在該金屬光遮蔽膜及已開啟之η型雜質摻 雜區域上。 較佳的是，第一和第二保護膜可由Si〇2、SiON、SiN 中之一形成。 較佳的是，金屬光遮蔽膜可藉由堆疊W、Mo、Ti、WSi、 Mo Si、Ti Si中之一或其任何組合形成。Each of the read gate regions 40 is indicated by a diagonal line and is serrated y. The interface portion 60 includes 12 charge transfer stages connected to the ends of the charge transfer channels constituting the drop CCD 30. Each of the 12 charge transfer stages includes a via unit charge transfer path (not shown) that is directed to the charge transfer channel and is formed on the semiconductor substrate! One of the upper transfer electrodes 61, Μ and Μ is across the interface cell charge transfer path in the plan view. Fig. 2 is a cross-sectional view showing a pixel of a prior art solid-state image pickup device using c C D . As shown in Fig. 2, the photodiode (pD) region of the prior art solid-state imaging device using CCD 2 形成 is formed such that a first p-type well 111 (nearly 3 μm thick) is used for impurity implantation. The input is formed on a semiconductor substrate 110, and then an n-type impurity doping region (PDN) 13 is formed on the first P-well 111, and the last p-type impurity doped region (PDP) 114 It is formed on the surface of the n-type impurity doping region Π3. The germanium-type impurity doping region 1 1 4 is doped with a higher concentration of p-type impurity, so that it becomes a ρ + -type doped region, thereby preventing electrons generated on the surface of the photodiode from flowing into the photodiode region. in. Similarly, the n-type impurity doped under the p-type impurity 6 1271857 doped region 114 is doped only with the core & field 1 1 3 by implanting ions thereto to accumulate electrons. On the other hand, the first p-type well 11 is formed under the n-type impurity doping region 113 to control the divergence and shutter control. Here, the deeper the _p-type well U1, the larger the area for accumulating light, thereby increasing its sensitivity. The first p-well 111 forms a potential barrier therein to collect electrons in the photodiode region. If the electron is excessive, excess electrons are extracted into the n-type semiconductor substrate 1 1 依据 depending on the dosage unit. Since the depth of the first p-type well 111 is larger, the wider the photodiode region in the depth direction, a relatively larger amount of electrons are accumulated, thereby increasing the sensitivity. However, if the first p-type well 11 is too deep, since the electrons are generated by infrared light and red visible light, there may be a negative effect on color reproduction. Therefore, based on the optimal energy and dosage unit, the first p-type well should be implanted by ions. A second p-type well 115 is formed on the first crucible well 111 on the surface of the n-type semiconductor substrate no. The second p-type well 115 is separated from the n-type impurity doped region 113 by a predetermined distance. The second p-type well 115 forms a buried CCD (BCCD) 118 around its surface. The BCCD 118 accumulates and transmits electrons in accordance with voltages applied to the polysilicon electrodes 141 and 143. A transfer gate (TG) 11 9 and a channel stop region (CST) 11 7 are formed between the n-type impurity doping region 113 and the second p-type well 115. Here, the TG 119 connects the n-type impurity doping region 113 and the second p-type well 115, and the CST 117 prevents the electron peach from reaching the adjacent cell. After forming the structure as described above, a first protective film 112 is formed on the surface including the n-type impurity doping region 113 and the second p-type well 115. Polycrystalline stone eve 7 1271857 Electrodes 1 4 1 and 1 43 are formed on the first protective film, which is formed on the upper side of the second p-type well 115 by chemical vapor deposition (CVD). After the polysilicon electrodes 141 and 143 are formed, the second protective film 123 covers the upper side thereof. Thereafter, a metal light shielding film i 24 is formed on the second protective film 1 2 3 by etching so that the n-type impurity doping region 11 3 is turned on. After the metal light shielding film 124 is formed to turn on the n-type impurity doping region 113, a boron phosphide glass (BPSG) layer 125 is deposited thereon. Thereafter, a passivation film or planarization film 126 is formed on the BPSG film 125 and then planarized by a planarization process. Subsequently, a color filter pattern 13 is formed on the planarized surface of the passivation film or planarization film 1 2 6 . On the other hand, after planarizing Bp S G 1 2 5 by the planarization technique, a color filter pattern 1 30 can be formed on the flattened b p s G 1 2 5 . In this case, the advantage of the prior art is that the process can be simplified, and the diffusion reflection can be reduced when the passivation film or the planarization film ι26 having a refractive index different from that of the BPSG 125 is stacked. However, in the prior art solid-state image pickup apparatus using the CCD, since the metal light shielding film has been formed 'and then the BPSG film is formed on the metal light shielding film', the curvature of the concave portion of the BPSG film is considerably large. Therefore, the light system incident on the bpsg film is largely diffused, so that light collection cannot be performed normally. At the same time, the incident light is largely refracted and propagates to other pixels adjacent to a particular pixel, thereby deteriorating the image quality. Further, in the case of a metal light-shielding film, there is warpage on the metal light-shielding film due to the occurrence of polycrystalline silicon or the like. Therefore, a metal light shielding film having a curvature thereon and having a relatively large curvature may be difficult to etch. When 8 1271857 etches this metal light shielding film, it will be difficult to etch accurately. At the same time, when the BPSG film deposited on the metal light shielding film is planarized, the polycrystalline germanium electrode can be damaged. That is, when the bps ruthenium film is deposited on the metal light shielding film as shown in Fig. 3a, the lowest point of the concave portion of the BPSG film (indicated by "b") can be lower than the highest point of the polysilicon electrode (by " &"). Therefore, when the field planarization process is applied to the B p s ruthenium film having this structure, as a result, it is possible to cause, for example, removal of the upper portion of the polysilicon electrode, as shown in the figure. SUMMARY OF THE INVENTION Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a method for assembling a solid-state image pickup device using a CCD, which can simplify or modify a process to increase a yield, by making incident light The solid-state imaging device that minimizes diffuse reflection while overcoming inaccurate light collection and avoids incidence of light on adjacent cells, and assembles the CCD using this method. According to an aspect of the present invention, the above and other objects can be attained by providing a solid-state image pickup device using a charge coupled device (CCD) including an n-type impurity doped region formed on a surface of a semiconductor substrate and Buried charge coupled device (BCCD) region. The solid-state image pickup device comprises at least a first protective film formed on the n-type impurity doped region and the BCCD region, and the polycrystalline germanium electrode is prepared on the first protective film which has been formed on the bccD region; a protective film covering the polysilicon electrodes, a 'BPSG film, which is formed on the upper surface of the first and second protective films with a predetermined thickness; a metal light shielding film formed at the Bps (j film) The upper surface of the n-type impurity doping region can be turned on; and a passivation film or a flat 1271857 can be formed on the metal light shielding film and the opened n-type impurity doping region. Yes, the first and second protective films may be formed of one of Si〇2, SiON, and SiN. Preferably, the metal light shielding film may be stacked by W, Mo, Ti, WSi, Mo Si, Ti Si One or any combination thereof is formed.
較佳的是，BPS G膜之厚度大於從第一保護膜之上表面 到第二保護膜之上表面的總和，且BPSG膜的厚度可為1200 埃至2 0 0 0埃。 本發明另一態樣提供一種使用電荷耦合裝置（CCD)以 組裝固態攝像設備之方法，該固態攝像設備包括形成在半 導體基材之表面上的η型雜質摻雜區域和埋入式電荷耦合 裝置（BCCD)區域。該方法至少包含以下步驟：形成一第一 保護膜於η型雜質摻雜區域和BCCD區域上；形成二多晶石夕 電極於BCCD區域上部之第一保護膜上，且接著形成一第二 保護膜於該二多晶矽電極上；形成一已平坦化B P S G膜在第 一及第二保護膜上；形成一金屬光遮蔽膜於BPSG膜上，使 得η型雜質摻雜區域被開啟；及形成一鈍化膜或平坦化膜於 5玄金屬光遮蔽膜及BPSG膜上’以形成一遽色器圖案於其 上。 較佳的是，BPSG膜係沉積至厚度大於從第一保護膜之 上表面到第二保護膜之上表面的總和，且BP S G膜係藉由化 學機械研磨（CMP)平坦化。 較佳的是，該CMP可進行直到已平坦化之BPSG臈厚度 10Preferably, the thickness of the BPS G film is greater than the sum of the surface from the upper surface of the first protective film to the upper surface of the second protective film, and the thickness of the BPSG film may be from 1200 angstroms to 200 angstroms. Another aspect of the present invention provides a method of assembling a solid-state image pickup device using a charge coupled device (CCD) including an n-type impurity doped region and a buried charge coupled device formed on a surface of a semiconductor substrate (BCCD) area. The method comprises at least the steps of: forming a first protective film on the n-type impurity doped region and the BCCD region; forming a dipolycrystalline electrode on the first protective film on the upper portion of the BCCD region, and then forming a second protection Forming a planarized BPSG film on the first and second protective films; forming a metal light shielding film on the BPSG film, causing the n-type impurity doped region to be turned on; and forming a passivation The film or planarization film is formed on the 5th metal light shielding film and the BPSG film to form a color former pattern thereon. Preferably, the BPSG film is deposited to a thickness greater than the sum from the upper surface of the first protective film to the upper surface of the second protective film, and the BP S G film is planarized by chemical mechanical polishing (CMP). Preferably, the CMP can be performed until the thickness of the BPSG has been flattened 10
1271857 不小於從第一保護膜之上表面到第二保護膜 和° 較佳的是，形成金屬光遮蔽膜之步驟可 濺或CVD沉積W或WSi至預定厚度；且僅蝕亥丨 區域的上側。 依據使用電荷耦合裝置（CCD)之固態攝4 於組裝該固態攝像設備的方法，由於BPS G膜 光遮蔽膜前形成，BPS G膜表面之曲率相當小 BPSG膜藉由平坦化技術整平時，多晶矽電極 同時，由於BPS G膜被平坦化，故可使入 射最小，因此入射在特定像素上之光可正常 不會被傳播到鄰近像素，以致不會使圖像品 此外，由於金屬光遮蔽膜係形成在已平 膜上，故易於施行蝕刻以打開金屬光遮蔽膜 確地施行。 【實施方式】 現將參考附圖詳細說明一種使用依據本 實施例之電荷耦合裝置（CCD)的固態攝像設> 用於組裝該固態攝像設備之方法。 第4圖係使用依據本發明之CCD的固態泰 面圖。 如第4圖顯示，固態攝像設備300係形成 近3微米厚之第一 p型井層211使用雜質植入^ 之上表面的總 包括：使用喷 丨η型雜質摻雜 襄設備，及用 已在形成金屬 。因此，當 ι不會被損傷。 射光之擴散反 地收集，且光 質惡化。 坦化之BPSG ，此外亦可精 發明較佳具體 I，以及一種 卜像設備之斷 ，使得厚度將 =形成在一 η型 11 1271857 半導體基材210上，接著一 n型雜質摻雜區域（pDN)2i3係形 成在第一 P型井211上，且最後一 P型雜質摻雜區域（pDp)2i4 係形成在η型雜質摻雜區域213之表面上。 該Ρ型雜質摻雜區域214係以一較高濃度之ρ型雜質摻 雜，使得其變成一 Ρ +型摻雜區域，其防止在光二極體表面 上產生之電子流入光二極體區域中。同樣地，形成在ρ型雜 質掺雜區域214下之η型雜質摻雜區域213係藉由向其植入 離子以累積電子。 一第二ρ型井層215係形成在^型半導體基材21〇表面上 之第一 ρ型井211上。第二ρ型井層215係以預定距離與η型雜 質摻雜區域213隔開。第二ρ型井215在其表面周圍形成一埋 入式CCD(BCCD)218°BCCD 218依據施加至多晶矽電極241 和243的電壓累積且傳送電子。 一傳送閘極（TG)2 1 9和通道停止區域（CST)2 1 7係形成 在η型雜質摻雜區域213和第二ρ型井層215之間。在此，TG 219連接η型雜質摻雜區域213與第二ρ型井215，且CST217 防止電子跳到鄰近單元。 在形成如上述之結構後，一第一保護膜22 1係形成在η 型雜質摻雜區域213、第二ρ型井層215、及製備在η型雜質 摻雜區域213的表面上及第二ρ型井層215上之BCCD區域 218。較佳的是，第一保護膜221係藉由堆疊si〇2、si〇N、 SiN中之一或其任何組合而形成。 二多晶矽電極241和243係藉由化學氣相沉積（CVD)和 蝕刻形成以在BCCD區域21 8之表面的第一保護膜221上部 12 1271857 分地重疊。 多晶矽電極241和243係形成在一薄第二保護膜223 上。較佳的是，第二保護膜223係藉由堆疊Si〇2、si〇N、1271857 not less than from the upper surface of the first protective film to the second protective film and °. Preferably, the step of forming the metal light shielding film may deposit W or WSi to a predetermined thickness by sputtering or CVD; and only the upper side of the etched area . According to the method of assembling the solid-state image pickup device using a solid-state image pickup device (CCD), since the BPS G film is formed before the light shielding film, the curvature of the surface of the BPS G film is relatively small. When the BPSG film is flattened by the flattening technique, the polycrystalline silicon is formed. At the same time, since the BPS G film is flattened, the incidence can be minimized, so that light incident on a specific pixel can be normally not propagated to adjacent pixels, so that the image product is not caused by the metal light shielding film system. It is formed on the flat film, so it is easy to perform etching to open the metal light shielding film to be performed. [Embodiment] A solid-state image pickup device using a charge coupled device (CCD) according to the present embodiment will now be described in detail with reference to the accompanying drawings, and a method for assembling the solid-state image pickup device. Figure 4 is a solid state plan view of a CCD according to the present invention. As shown in FIG. 4, the solid-state imaging device 300 is formed to form a first p-type well layer 211 of approximately 3 micrometers thick. The use of the impurity implanted surface includes: using a sputum-n-type impurity-doped germanium device, and In the formation of metal. Therefore, when ι is not damaged. The spread of the light is collected in reverse, and the light quality deteriorates. The canned BPSG can also be invented by a preferred embodiment I, and a device device is broken so that the thickness will be formed on an n-type 11 1271857 semiconductor substrate 210 followed by an n-type impurity doped region (pDN). 2i3 is formed on the first P-type well 211, and the last P-type impurity doped region (pDp) 2i4 is formed on the surface of the n-type impurity doped region 213. The germanium-type impurity doping region 214 is doped with a higher concentration of p-type impurity, so that it becomes a Ρ +-type doped region which prevents electrons generated on the surface of the photodiode from flowing into the photodiode region. Similarly, the n-type impurity doping region 213 formed under the p-type impurity doping region 214 is formed by implanting ions to accumulate electrons. A second p-type well layer 215 is formed on the first p-type well 211 on the surface of the semiconductor substrate 21. The second p-type well layer 215 is spaced apart from the n-type impurity doped region 213 by a predetermined distance. The second p-type well 215 forms a buried CCD (BCCD) around its surface. The 218° BCCD 218 accumulates according to the voltage applied to the polysilicon electrodes 241 and 243 and transmits electrons. A transfer gate (TG) 2 1 9 and a channel stop region (CST) 2 17 are formed between the n-type impurity doped region 213 and the second p-type well layer 215. Here, the TG 219 connects the n-type impurity doping region 213 with the second p-type well 215, and the CST 217 prevents electrons from jumping to adjacent cells. After forming the structure as described above, a first protective film 22 1 is formed on the n-type impurity doped region 213, the second p-type well layer 215, and on the surface of the n-type impurity doped region 213 and second. A BCCD region 218 on the p-type well layer 215. Preferably, the first protective film 221 is formed by stacking one of si〇2, si〇N, SiN, or any combination thereof. The two poly germanium electrodes 241 and 243 are formed by chemical vapor deposition (CVD) and etching to overlap the upper portion 12 1271857 of the first protective film 221 on the surface of the BCCD region 218. The polysilicon electrodes 241 and 243 are formed on a thin second protective film 223. Preferably, the second protective film 223 is stacked by Si〇2, si〇N,
SiN中之一或其任何組合而形成。。 第二保護膜223以預定厚度形成一平坦化硼磷石夕玻璃 (BPS G)膜225於其上。平坦化BPSG膜225係沉積在第一保護 膜221以及第二保護膜223之上表面上。 由於在多晶矽電極241和243之上部及n型雜質摻雜區 域213之上部間具有段差，^8(}膜225係藉由噴濺或（：^〇沉 積在第一以及第二保護膜221和22 3之表面上，其中BpSG 膜22 5具有翹曲。表面翹曲之BPSG膜225可藉由諸如化學機 械研磨（CMP)等平坦化技術加以整平。 在平坦化前，BPSG膜225必須沉積使得其沉積厚度（由 「b」指示）係大於自第一保護膜22 1之上表面到第二保護膜 223的上表面之厚度（由「a」指不）。因此，當平坦化製程 係施加至BPSG膜225時，可防止多晶矽電極24丨和243受平 坦化損傷。 BPSG膜225最好是形成將近1200埃至2000埃厚。在此 情況下，多晶矽電極241和243係形成800埃至1〇〇〇埃厚，且 第二保護膜223係形成400埃至800埃厚。 一金屬遮蔽膜224係形成於BPSG膜225上，使得n型雜 質摻雜區域213不被遮蔽。金屬光遮蔽膜224係藉由堆疊 W、Mo、Ti中之一或其任何組合而形成。同樣地，金屬光 遮蔽膜224係藉由堆疊WSi、MoSi、TiSi中之一或其任何組 13 1271857 合而形成。 同時，BPSG膜225在其表面上形成一平坦純化膜或平 坦化膜226，且一濾色器圖案230係形成於該平坦鈍化膜或 平坦化膜2 2 6上。 第5 a至5 d圖係說明使用依據本發明之c C D製造固態攝 像設備的方法之斷面圖。請參考附圖，以下將詳盡描述該 特定製程。Formed in one of SiN or any combination thereof. . The second protective film 223 is formed with a planarized borophosphite glass (BPS G) film 225 at a predetermined thickness. The planarized BPSG film 225 is deposited on the upper surfaces of the first protective film 221 and the second protective film 223. Since there is a step difference between the upper portion of the polysilicon electrodes 241 and 243 and the upper portion of the n-type impurity doping region 213, the film 225 is deposited by the sputtering or the first and second protective films 221 and On the surface of 22 3, wherein the BpSG film 22 5 has warpage, the surface warped BPSG film 225 can be leveled by a planarization technique such as chemical mechanical polishing (CMP). Before the planarization, the BPSG film 225 must be deposited. The thickness of the deposition (indicated by "b") is made larger than the thickness from the upper surface of the first protective film 22 1 to the upper surface of the second protective film 223 (indicated by "a"). Therefore, when the planarization process is performed When applied to the BPSG film 225, the polysilicon electrodes 24 and 243 are prevented from being damaged by planarization. The BPSG film 225 is preferably formed to a thickness of approximately 1200 angstroms to 2000 angstroms. In this case, the polysilicon electrodes 241 and 243 are formed to 800 angstroms to 1 Å is thick, and the second protective film 223 is formed to be 400 angstroms to 800 angstroms thick. A metal masking film 224 is formed on the BPSG film 225 such that the n-type impurity doping region 213 is not shielded. The film 224 is stacked by one of W, Mo, Ti or any combination thereof Similarly, the metal light shielding film 224 is formed by stacking one of WSi, MoSi, TiSi or any group 13 1271857. Meanwhile, the BPSG film 225 forms a flat purification film or a planarization film on the surface thereof. 226, and a color filter pattern 230 is formed on the flat passivation film or the planarization film 226. Figures 5a to 5d illustrate a section of a method of manufacturing a solid-state image pickup apparatus using the CD of the present invention. Referring to the drawings, the specific process will be described in detail below.
首先，一包括η型雜質摻雜區域213之雜質摻雜區域和 BCCD區域218與井層係形成在半導體基材21〇上。因為此等 製程係與上述相同，以下省略詳細說明。 其次，第一保護膜221係藉由堆疊Si02、SiON、SiN中 之一或其任何組合，而形成在η型雜質摻雜區域213和BCCD 區域2 1 8上。二多晶石夕電極2 4 1和2 4 3係藉由沉積和餘刻形成 在已形成於BCCD區域218的表面上之第一保護膜221上。之 後，一第二保護膜223係藉由堆疊Si〇2、SiON、SiN中之一 或其任何組合，形成於二多晶石夕電極2 4 1和2 4 3上。 在依據此等製程形成第二保護膜223後（如第5a圖所 示），一 BPSG膜225係以預定厚度形成在第一及第二保護膜 221及223上，如第4a圖中顯示。 當堆疊BPSG膜225時，其中在形成第二保護膜223之部 分處係凸狀’而在形成已開啟之η型雜質摻雜區域2 1 3部分 處係凹狀。BPSG膜225最好堆疊地較厚以提升其凹部之曲 率，且較薄以減少其凹狀部分之曲率。 在此，BPSG膜225應沉積超過預定厚度（由r b」指示）， 14 1271857 使得多晶矽電極241和243在平坦化製程中不會損傷。即， B P S G膜2 2 5應丨儿積使付其比自第一保護膜2 2 1之上表面到 第二保遵膜2 2 3的上表面之厚度的總和（由第5圖中r a」指 示）更厚。 如第5b圖所示之已沉積BPS G膜225係藉由諸如化學機 械研磨（CMP)之平坦化製程整平。藉由化學機械研磨（CMp) 用於BPSG膜225上表面的平坦化製程係連續地進行，直到 已平坦化BPSG膜225之厚度不小於自第一保護膜221之上 表面到第 <一保護膜2 2 3的上表面之總和。即，平坦化製程可 在多晶矽電極241和243未受CMP損壞前進行。 其次’ BPSG膜225在其上形成一金屬光遮蔽膜224。如 第5c圖所示，金屬光遮蔽膜2 24係藉由蝕刻形成，使得η型 雜質摻雜區域2 1 3之上側得以開啟。 即，該金屬光遮蔽膜224係類似地形成，使得w、Μ〇、 Ti、WSi、MoSi、TiSi中一或多於至少二者係使用喷濺或 化學氣相沉積（CVD)依預定厚度沉積在BPSG膜225之上表 面上，且為了開啟η型雜質摻雜區域213之上表面，在η型雜 質摻雜區域213上之金屬光遮蔽膜224係藉由钱刻移除。 因此，當金屬光遮蔽膜224係如第5d圖所示形成時，一 純化膜或平坦化膜226係依預定厚度形成在金屬光遮蔽膜 224表面上。之後，一濾色器圖案23〇係形成在鈍化膜或平 坦化膜226表面上。在此，鈍化膜或平坦化膜226係藉由化 學機械研磨（CMP)平坦化。 雖然本發明較佳具體實施例已為了示範目的加以揭 15 1271857 露，熟習此項技術人士應理解在不脫離隨附申請專利範圍 所揭示之本發明範疇及精神下，各種修改、增加及替代皆 屬可能。 【圖式簡單說明】 本發明前述及其他目的、特徵與其他優點將可從以上 結合附圖之詳細說明中更加暸解，其中： 第1圖係使用具有一般蜂房式結構之CCD的固態攝像First, an impurity doped region including a n-type impurity doped region 213 and a BCCD region 218 and a well layer are formed on the semiconductor substrate 21A. Since these processes are the same as described above, detailed descriptions are omitted below. Next, the first protective film 221 is formed on the n-type impurity doped region 213 and the BCCD region 2 1 8 by stacking one of SiO 2 , SiON, SiN or any combination thereof. The two polycrystalline silicon electrodes 2 4 1 and 2 4 3 are formed on the first protective film 221 which has been formed on the surface of the BCCD region 218 by deposition and ruling. Thereafter, a second protective film 223 is formed on the dicrystalline electrodes 2 4 1 and 2 4 3 by stacking one of Si 2 , SiON, SiN or any combination thereof. After the second protective film 223 is formed in accordance with the processes (as shown in Fig. 5a), a BPSG film 225 is formed on the first and second protective films 221 and 223 with a predetermined thickness as shown in Fig. 4a. When the BPSG film 225 is stacked, a portion where the second protective film 223 is formed is convex, and a portion where the opened n-type impurity doped region 2 1 3 is formed is concave. The BPSG film 225 is preferably stacked thicker to increase the curvature of its recess and is thinner to reduce the curvature of its concave portion. Here, the BPSG film 225 should be deposited over a predetermined thickness (indicated by r b "), and 14 1271857 is such that the polysilicon electrodes 241 and 243 are not damaged during the planarization process. That is, the BPSG film 2 2 5 is the sum of the thicknesses from the upper surface of the first protective film 2 2 1 to the upper surface of the second film 2 2 3 (by the image in FIG. 5) Indication) thicker. The deposited BPS G film 225 as shown in Fig. 5b is leveled by a planarization process such as chemical mechanical polishing (CMP). The planarization process for the upper surface of the BPSG film 225 by chemical mechanical polishing (CMp) is continuously performed until the thickness of the planarized BPSG film 225 is not less than the upper surface from the first protective film 221 to the first < The sum of the upper surfaces of the membranes 2 2 3 . That is, the planarization process can be performed before the polysilicon electrodes 241 and 243 are not damaged by the CMP. Next, the BPSG film 225 has a metal light shielding film 224 formed thereon. As shown in Fig. 5c, the metal light shielding film 24 is formed by etching so that the upper side of the n-type impurity doping region 2 1 3 is turned on. That is, the metal light shielding film 224 is similarly formed such that one or more of w, Μ〇, Ti, WSi, MoSi, TiSi are deposited by sputtering or chemical vapor deposition (CVD) according to a predetermined thickness. On the upper surface of the BPSG film 225, and in order to turn on the upper surface of the n-type impurity doping region 213, the metal light shielding film 224 on the n-type impurity doping region 213 is removed by money. Therefore, when the metal light shielding film 224 is formed as shown in Fig. 5d, a purification film or a planarization film 226 is formed on the surface of the metal light shielding film 224 with a predetermined thickness. Thereafter, a color filter pattern 23 is formed on the surface of the passivation film or the flattening film 226. Here, the passivation film or planarization film 226 is planarized by chemical mechanical polishing (CMP). While the preferred embodiment of the present invention has been described by way of example only, it is understood by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the invention as disclosed in the appended claims. It is possible. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, features and other advantages of the present invention will become more apparent from
第2圖係使用CCD之先前技術固態攝像設備的像素之 斷面圖； 第3a與3b圖係描述使用CCD組裝先前技術固態攝像 設備的先前技術方法中之問題的斷面圖； 第4圖係使用依據本發明之CCD的固態攝像設備之斷 面圖；及 第5a至5d圖係描述使用依據本發明之CCD以製造固 態攝像設備的方法之斷面圖。2 is a cross-sectional view of a pixel of a prior art solid-state imaging device using a CCD; FIGS. 3a and 3b are cross-sectional views showing a problem in a prior art method of assembling a prior art solid-state image pickup device using a CCD; A sectional view of a solid-state image pickup apparatus using a CCD according to the present invention; and Figs. 5a to 5d are sectional views for describing a method of manufacturing a solid-state image pickup apparatus using the CCD according to the present invention.
【主要元件符號說明】 1 半 導 體 基 材 10 光 阻 部 分 20 光 電 轉 換 元 件行 21 光 電 轉 換 元件列 22 光 電 轉 換 元 件 30 垂 直 傳 送 CCD 32 第 一 傳 送 電 極 33 第 二 傳 送 電極 40 讀 出 閘 極 區 域 60 介 面 部 分 16 1271857[Main component symbol description] 1 semiconductor substrate 10 photoresist portion 20 photoelectric conversion element row 21 photoelectric conversion element column 22 photoelectric conversion element 30 vertical transfer CCD 32 first transfer electrode 33 second transfer electrode 40 read gate region 60 interface Part 16 1271857
6 1 傳送電極 63 傳送電極 80 輸出單元 111第一 p型井 114p型雜質摻雜區域 116鈍化/平坦化膜 118 埋入式 CCD/BCCD 1 2 1第一保護膜 124金屬光遮蔽膜 126鈍化/平坦化膜 1 4 1多晶矽電極 200 CCD 213 η型雜質摻雜區域 215第二ρ型井層 218 BCCD 221第一保護膜 224金屬光遮蔽膜 226鈍化/平坦化膜 241多晶矽電極 3 00固態攝像設備 62 傳送電極 70 輸出傳送部分 110 η型半導體基材 113 η型雜質摻雜區 域 115 第二Ρ型井 117 通道停止區域 119 傳送閘極 123 第二保護膜 125 BPSG層/膜 130 濾色器圖案 143 多晶碎電極 211 第一 Ρ型井 214 Ρ型雜質摻雜區 域 217 通道停止區域 219 傳送閘極 223 第二保護膜 225 BPSG層/膜 230 濾色器圖案 243 多晶碎電極 176 1 transfer electrode 63 transfer electrode 80 output unit 111 first p-type well 114p type impurity doped region 116 passivation/planarization film 118 buried CCD/BCCD 1 2 1 first protective film 124 metal light shielding film 126 passivation / Planar film 1 4 1 polysilicon electrode 200 CCD 213 n-type impurity doped region 215 second p-type well layer 218 BCCD 221 first protective film 224 metal light shielding film 226 passivation / planarization film 241 polycrystalline germanium electrode 3 00 solid-state imaging device 62 Transfer electrode 70 Output transfer portion 110 n-type semiconductor substrate 113 n-type impurity doped region 115 second germanium well 117 channel stop region 119 transfer gate 123 second protective film 125 BPSG layer / film 130 color filter pattern 143 Polycrystalline electrode 211 First well type 214 Ρ type impurity doped region 217 Channel stop region 219 Transfer gate 223 Second protective film 225 BPSG layer / film 230 Color filter pattern 243 Polycrystalline electrode 17
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050006860A KR100697701B1 (en) | 2005-01-25 | 2005-01-25 | APPARATUS AND METHOD FOR MANUFACTURING Charge-Coupled Device |
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| TW200627632A TW200627632A (en) | 2006-08-01 |
| TWI271857B true TWI271857B (en) | 2007-01-21 |
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| KR (1) | KR100697701B1 (en) |
| TW (1) | TWI271857B (en) |
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| JPH04218965A (en) * | 1990-11-01 | 1992-08-10 | Sharp Corp | Solid state pickup device |
| JP3248225B2 (en) * | 1992-04-08 | 2002-01-21 | ソニー株式会社 | Method for manufacturing solid-state imaging device |
| JP2755176B2 (en) * | 1994-06-30 | 1998-05-20 | 日本電気株式会社 | Solid-state imaging device |
| JP2002319668A (en) * | 2001-04-24 | 2002-10-31 | Fuji Film Microdevices Co Ltd | Solid-state imaging device and manufacturing method therefor |
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2005
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| KR20060086048A (en) | 2006-07-31 |
| KR100697701B1 (en) | 2007-03-20 |
| TW200627632A (en) | 2006-08-01 |
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