TWI268603B - Poly fuse ROM with MOS device based cell structure and the method for read and write therefore - Google Patents
Poly fuse ROM with MOS device based cell structure and the method for read and write thereforeInfo
- Publication number
- TWI268603B TWI268603B TW091100020A TW91100020A TWI268603B TW I268603 B TWI268603 B TW I268603B TW 091100020 A TW091100020 A TW 091100020A TW 91100020 A TW91100020 A TW 91100020A TW I268603 B TWI268603 B TW I268603B
- Authority
- TW
- Taiwan
- Prior art keywords
- fuse element
- gate
- terminal
- surrounds
- read
- Prior art date
Links
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
- H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
A one-time programmable (OTP) structure is implemented using a self-aligned silicided (SALICIDE) poly-silicon fuse. In an example embodiment, the OTP structure is laid out as a fuse element having a first terminal and a second terminal. A switching transistor having a drain, source, and a gate surrounds the fuse element. The drain is coupled to the second terminal of the fuse element surrounds the fuse element. The gate surrounds the drain. The source surrounds the gate. To build transistor with sufficient drive capability for programming the fuse element, the geometry of the gate is laid out in a serpentine or an equivalent pattern increase the effective W/L. A feature of this layout is that OTP cells may be abutted to one-another to form an array. Metallization is arranged so that row lines connect to the first terminal of the fuse element and column lines connect to the gate of the switching transistor. The arrangement enables the placing of read and write circuits at opposite sides of the array. All of the gates in a column may be read simultaneously while providing write current to program one fuse at a time.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US72341300A | 2000-11-27 | 2000-11-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
TWI268603B true TWI268603B (en) | 2006-12-11 |
Family
ID=24906158
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091100020A TWI268603B (en) | 2000-11-27 | 2002-01-03 | Poly fuse ROM with MOS device based cell structure and the method for read and write therefore |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1340262A2 (en) |
JP (1) | JP2004515061A (en) |
TW (1) | TWI268603B (en) |
WO (1) | WO2002043152A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI587138B (en) * | 2013-03-07 | 2017-06-11 | 英特爾股份有限公司 | Random fuse sensing |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE60327551D1 (en) * | 2002-12-05 | 2009-06-18 | Nxp Bv | PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR ARRANGEMENT |
US7136322B2 (en) * | 2004-08-05 | 2006-11-14 | Analog Devices, Inc. | Programmable semi-fusible link read only memory and method of margin testing same |
GB0516423D0 (en) * | 2005-08-10 | 2005-09-14 | Cavendish Kinetics Ltd | Fuse cell, array and circuit therefor |
JP2009506577A (en) * | 2005-08-31 | 2009-02-12 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Random access electrically programmable E-fuse ROM |
KR101780828B1 (en) | 2012-02-06 | 2017-09-22 | 매그나칩 반도체 유한회사 | Nonvolatile memory device |
US20140027778A1 (en) * | 2012-07-25 | 2014-01-30 | International Rectifier Corporation | Robust Fused Transistor |
EP3382712B1 (en) | 2017-03-31 | 2020-11-04 | Nxp B.V. | Memory system |
FR3087290B1 (en) | 2018-10-16 | 2020-11-06 | St Microelectronics Sa | MEMORY POINT |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5553462A (en) * | 1978-10-13 | 1980-04-18 | Int Rectifier Corp | Mosfet element |
JPS5846174B2 (en) * | 1981-03-03 | 1983-10-14 | 株式会社東芝 | semiconductor integrated circuit |
JPS5863147A (en) * | 1981-10-09 | 1983-04-14 | Toshiba Corp | Semiconductor device |
JPS58197874A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Semiconductor device and manufacture thereof |
JP3158738B2 (en) * | 1992-08-17 | 2001-04-23 | 富士電機株式会社 | High breakdown voltage MIS field-effect transistor and semiconductor integrated circuit |
US5412593A (en) * | 1994-01-12 | 1995-05-02 | Texas Instruments Incorporated | Fuse and antifuse reprogrammable link for integrated circuits |
US5748025A (en) * | 1996-03-29 | 1998-05-05 | Intel Corporation | Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit |
US5976943A (en) * | 1996-12-27 | 1999-11-02 | Vlsi Technology, Inc. | Method for bi-layer programmable resistor |
US5909049A (en) * | 1997-02-11 | 1999-06-01 | Actel Corporation | Antifuse programmed PROM cell |
JPH1187696A (en) * | 1997-09-12 | 1999-03-30 | Matsushita Electric Works Ltd | High breakdown strength semiconductor device |
-
2001
- 2001-11-19 EP EP01997848A patent/EP1340262A2/en not_active Withdrawn
- 2001-11-19 WO PCT/EP2001/013467 patent/WO2002043152A2/en active Application Filing
- 2001-11-19 JP JP2002544786A patent/JP2004515061A/en active Pending
-
2002
- 2002-01-03 TW TW091100020A patent/TWI268603B/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI587138B (en) * | 2013-03-07 | 2017-06-11 | 英特爾股份有限公司 | Random fuse sensing |
Also Published As
Publication number | Publication date |
---|---|
WO2002043152A3 (en) | 2002-09-19 |
WO2002043152A2 (en) | 2002-05-30 |
JP2004515061A (en) | 2004-05-20 |
EP1340262A2 (en) | 2003-09-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |