TWI262907B - A planarize ceramic substrate - Google Patents

Abstract

This invention provides a design of using porous materials on the planarization of ceramic substrate. This planarized substrate consists of ceramic substrate, a buffer layer, and a nanostructure layer. The said ceramic substrate can provide the structural strength and also good surface-mount capability. The said buffer layer provides the adhesion between the said ceramic substrate and the said nanostructure layer. The said nanostructure layer provides the required surface smoothness to the ceramic substrate for performing thin-film processing techniques and also enhancing adhesion for further metallization. This nanostructure layer also provides required properties such as thermal conductivity, electrical insulation, dielectrics, etc for integrated electronics devices.

Description

1262907 九、發明說明： 【發明所屬之技術領域】 ^發明提供—種表面平坦化之陶絲板，係湘多孔性材料 ^成陶莞基板表面平坦化，提供後續膜層附著力要求之結構設 的平ΐΐίΞ用於目前電子資訊通訊、光電、顯示器產業中基材 【先前技術】 在目前的薄膜元件製程中，表面平坦度的要求相當重要，尤 其以晶圓或玻璃為基材的製造業，基材表面平坦化的處理，需要 ^寸出相當的成本；此外，積體電路製程巾麵倾_平坦化 術，亦是元件製造成功與否的關鍵。 $目前，關於表面平坦化的處理方法，一般採用機械研磨法、 化學機械研磨法(chemical mechanical polishing，CMP)、化學姓刻 去硼礙石夕玻璃(BPSG)的咼溫重流、或是旋塗式玻璃法(s〇G)，利 用，些方式處理後的S面平坦度或是薄膜的附著力(a—)皆有 疋限制，且製程複雜，製造成本太高，如表1係習知技術平坦 化方法比較表。 1262907 國專利號碼專利名稱 別（文獻出處）（文獻名稱）技 術 重 點先前技術缺失 49448361262907 IX. Description of the invention: [Technical field to which the invention belongs] The invention provides a ceramic plate with a flat surface, which is a flat porous material of the porous material of the ceramics, and provides a structure for the subsequent adhesion of the film. The flat sheet is used in the current electronic information communication, optoelectronics, and display industries. [Prior Art] In the current thin film device manufacturing process, surface flatness requirements are very important, especially in the manufacturing of wafer or glass substrates. The flattening of the surface of the substrate requires considerable cost; in addition, the integrated circuit manufacturing process is also the key to the success of component manufacturing. At present, the treatment method for surface flattening generally adopts mechanical grinding method, chemical mechanical polishing (CMP), chemical surrogate to remove the temperature of the ribs of the glass (BPSG), or spin. The coated glass method (s〇G), using the S flatness of the treated method or the adhesion of the film (a-), has a limitation, and the manufacturing process is complicated, and the manufacturing cost is too high, as shown in Table 1. Know the technical flattening method comparison table. 1262907 National Patent Number Patent Name (Document Source) (Document Name) Technology Focus on Prior Art Defect 4944836

Chem-mech polishing method for producing coplanar metal/insulator films on a substrate 提供VLSI甚至ULSI CMP所使用的化學漿料相 (Ultra-Large Semiconductor當昂貴，製程複雜不容易掌Chem-mech polishing method for producing coplanar metal/insulator films on a substrate Provides chemical slurry phase for VLSI and even ULSI CMP (Ultra-Large Semiconductor is expensive, process is not easy to handle)

Integration) ’ ”全面性平坦控，並且缺乏有效的CMP 化(Global Planarization)”。利 用機械式研磨再配合適當 的化學研漿’將晶片表面高 低起伏不一的輪廓加以磨 平。CMP可提供被研磨表 面高達94%以上的平坦度。 終點偵測系統，以及研磨過 程中容易導入污染物等缺 點0 美Integration) ’” comprehensive flatness control and lack of effective Global Planarization”. The mechanical grinding is combined with the appropriate chemical slurry to smooth the contours of the wafer surface with high and low undulations. CMP provides flatness of up to 94% of the surface being polished. End point detection system, and the possibility of easily introducing contaminants during the grinding process

Silicon Processing for the VLSISilicon Processing for the VLSI

Basics of Thin Films 以旋塗(Spin Coating)的方 式覆蓋一層液態溶液再經 適當的熱處理來達到晶片 表面的介電層平坦化的目 旋塗式玻璃(Spin-On Glass) 製程僅能提供介電層局部 性(Local)的平坦程度。在應 用時容易造成微粒 國Basics of Thin Films Spin-on Glass is a spin-on glass that is coated with a liquid solution by spin coating and then heat treated to achieve dielectric layer flattening on the wafer surface. The degree of flatness of the layer locality. It is easy to cause particulate matter when applied

Solid State TechnologySolid State Technology

Viscous Behavior of Phosphosilicate, Borophosphosilicate and Germano-phosphosili cate Glasses in VLSI Processing. 的。S〇G對鬲低起伏的外觀(particies)、膜層龜裂及剝離 具有很好的填溝(Gap Fill) (Delamination)的現象，此外 能力。 使用CVD技術先沉積一層 玻璃轉變溫度(GlassViscous Behavior of Phosphosilicate, Borophosphosilicate and Germano-phosphosili cate Glasses in VLSI Processing. S〇G has a good Gap Fill (Delamination) phenomenon for the low undulating appearance, film cracking and peeling, in addition to the ability. Pre-deposition of a glass transition temperature using CVD technology (Glass

Transition Temperature)較低 的硼磷矽玻璃(BPSG， Borophosphosilicate)，再利 用熱流(Flow)法使BPSG再 高溫下流動來達到平坦化。 尚有殘餘溶劑出氣Transition Temperature) Lower borophosphosilicate (BPSG, Borophosphosilicate), which is then flow-flowed to achieve flattening at a higher temperature. Residual solvent is still out

Solid StateSolid State

TechnologyTechnology

Chemical Etching 沉積一層厚度超過所需甚 多的Si〇2，再以非等向性蝕 刻(Anisotropic Etch)的方 法’將此Si〇2回ϋ (Etch-back)至所需的厚度 (Outgassing)的問題。 BPSG製程所需的b2H6和 PH3為具劇毒性之氣體，僅 適用於金屬化之前的隔離 用介電層之平坦化，當以在呂 為主的金屬層覆蓋至表面 後BPSG熱流法即不適用。 回餘法僅能獲得部份 ^坦化的結果，無法得到後 續金屬化製程所需要局部 性或全面性的介電層平坦 性。 1262907 【發明内容】 其士麦疋本發明之主要目的，在於提供一種表面平坦化之陶瓷 p;著力多孔性材料達成陶瓷基反表面平坦化，並增進膜層 者力之、、、°構没計，以解決上述之缺失。 提供ίίΐίΛ目的，本發明提供—齡面平坦化之喊基板， *一太^力的要求’係於—基板3。依序形成—緩衝層20 的声層i該奈米結構層1Q提供薄膜製程技術所需平坦 附^力轉:接f之釘紮效果、以符合後續金屬化和電子材料之 熱、電絕緣、介f以及其它整合軒元件所需之特性。 陶奢表面平坦化之陶絲板’係卿多孔性材料促使 平坦化，可達成提供後續膜層附著力要求，簡化習 知之千坦化製程，降低製造成本之效益。 【實施方式】 種表面平坦化之陶£基板，係利用多孔性材料 in板平坦化，提供後_相著力要求之結構設 杜ιη°1既心時包括基板30、緩衝層20、奈米結構層10。奈米 ;程麟職平㈣絲及所雜紅釘紮效 雷以屬化和電子材料之附著力與導熱、電絕緣、介 石、電子ί件所需之特性，其材料係選自沸石、類沸 相i S、介孔複材#多孔,崎料所《的雜，或由該群 以上的材料所組成。緩衝層20提供基板30與奈 /技的接著，其材料係選自釉料、玻璃、陶£、介孔物質、 ^ 1 旻材if組成的群組，或由該群組其中至少—種以上的材料 摄提供結構強度及表面固著，而緩衝層可與奈米結 g層為同-層’且該緩衝層或該奈求結構層可由—層或多層所構 為俾f貴審查委㈣本發明之目的、特徵及功效得獲致更 深入土，、解與删，雜本發明之具體技術分為平坦度、 力及可貫祕等三方面’她合圖式說明於后： !2629〇7 【實施例一】平坦度测試 示意圖。實施方法基板平坦化設計之結構 膜塗佈之製程於-基板3 〇上依體之漿料，以-般厚 構層，並經一高溫烘烤即可。I v 衝層2 〇及一奈米結 緩衝層2 0為轴料、奈米妹構^ Ί n = 土板3 〇為氧化銘材質、 例以X-光繞射°第2圖為本實施 波峰為類沸石自組成結構周期性：列：::？、中X_光繞射圖譜的 :實施例以掃描式電子顯所為 ;，貝微鏡放大後可清楚觀察到該基及= 奈米結構層10之結構，第4岡目,丨&生 技衝層20及多孔性 其圖譜中曲線(curve) ^則為表面平坦度測量所得的結果， 測結果印證本發明 落差量標示於_中’此量 平^ 月對基板表面平坦化具有一埃⑷尺寸級的表面 【實施例二】吸附力測試Chemical Etching deposits a layer of Si〇2 with a thickness exceeding the required amount, and then 'Etch-back' to the desired thickness (Outgassing) by an anisotropic Etch method. problem. The b2H6 and PH3 required for the BPSG process are highly toxic gases. They are only suitable for the planarization of the dielectric layer before the metallization. The BPSG heat flow method is not applicable when the metal layer covered by the Lu is covered to the surface. . The back-recovery method can only obtain partial and canned results, and it is impossible to obtain the local or comprehensive dielectric layer flatness required for the subsequent metallization process. 1262907 [Summary of the Invention] The main purpose of the present invention is to provide a surface flattening ceramic p; the force of the porous material to achieve the ceramic surface anti-surface flattening, and to enhance the film layer of force, To solve the above missing. In view of the above, the present invention provides a substrate for flattening the age, and the requirement of a force is attached to the substrate 3. Sequentially formed - the acoustic layer of the buffer layer 20, the nanostructure layer 1Q provides the flattening effect required for the thin film process technology: the pinning effect of the f, in order to conform to the subsequent metallization and the thermal and electrical insulation of the electronic material, And the characteristics required for other integrated components. The ceramic tile surface of the ceramic surface is flattened, which can achieve the requirements of providing subsequent adhesion of the film, simplifying the conventional process and reducing the manufacturing cost. [Embodiment] A substrate having a flat surface is flattened by a porous material in a plate, and a structure for providing a post-reaction force is provided. The substrate 30 includes a substrate 30, a buffer layer 20, and a nanostructure. Layer 10. Nano; Cheng Lin's level (four) wire and the red nailing effect of the lightning and the characteristics of the electronic material and thermal conductivity, electrical insulation, median stone, electronic components, the material is selected from zeolite, The boiling-like phase i S, mesoporous composite material #porous, the material of the "material", or composed of materials above the group. The buffer layer 20 provides a substrate 30 followed by a technique, the material of which is selected from the group consisting of glaze, glass, ceramic, mesoporous material, ^ 1 coffin if, or at least one or more of the group. The material is provided to provide structural strength and surface fixation, and the buffer layer may be the same layer as the nano-g layer and the buffer layer or the layer may be composed of layers or layers. The purpose, characteristics and effects of the present invention are obtained in a deeper way, and the specific techniques of the present invention are divided into three aspects: flatness, force and perseverance, and her description is as follows: !2629〇 7 [Embodiment 1] Schematic diagram of flatness test. The structure of the method for flattening the substrate is carried out. The process of film coating is carried out on a substrate 3, which is a thick layer of a body, and is baked at a high temperature. I v Punch layer 2 〇 and one nanometer junction buffer layer 20 0 is the axial material, nanometer structure ^ Ί n = soil plate 3 〇 is the oxidation of the material, for example X-ray diffraction ° Figure 2 is the implementation The crest is the periodicity of the zeolite-like self-constituting structure: column:::? , X-ray diffraction pattern: the embodiment is based on scanning electron display; after the amplification of the shell micromirror, the structure of the base and the nanostructure layer 10 can be clearly observed, the fourth order, the 丨 & The curve of the technique layer 20 and the porosity of the technique is the result of the measurement of the surface flatness. The result of the test proves that the amount of the drop of the invention is marked in the middle of the substrate. (4) Dimensional surface [Example 2] Adsorption test

板，所示為本發明實施例一之附著力測試在平括化A 達6.5_仍有極佳的附著力。 即使銘祕 施例三】可實施性測試 的電瓣雌姆㈣作之二極體 積體電Λ 為本發明實施例在和旦基板上製作虹〇 * RLCD ，”肩不在平坦化基板上可以製作具有二極體(diode) ，、 频轉，證本實關平坦錄之餘本 ） 限定t 並描述了所選擇之較佳實施例，當不能以之 明申^利^之耗圍，即凡熟悉本技術的人均可明瞭，依本發. 本發;專利斤:任何形式或是細節上可能之變化，均未脫離 个I明專利涵盍之精神與範圍。 1262907 【圖式簡單說明】 表1為習知技術平坦化方法比較表。 第1圖為本發明之奈米結構對基板平坦化機 第2圖為本發明實施例一之x_光繞射觀察 、jL。 第3圖為本發明實施例-之SEM觀察所得二@ °曰。 =圖為本㈣實關—之絲平坦心指^彳之 上The board, shown as the adhesion test of the first embodiment of the present invention, has excellent adhesion in flattening A up to 6.5. Even if the secret application example 3] can be implemented for the test of the electric valve female (four) for the two-pole volume electrophoresis, for the embodiment of the invention, the rainbow trout* RLCD is fabricated on the substrate and the substrate can be fabricated on the flat substrate. It has a diode, a frequency conversion, and a clear copy of the certificate. It defines t and describes the preferred embodiment chosen. Anyone familiar with the technology can understand, according to the present invention. This patent; patent jin: any form or details of possible changes, are not separated from the spirit and scope of a patent. 1262907 [Simple diagram] 1 is a comparison table of a conventional technique flattening method. Fig. 1 is a view showing a nanostructure-to-substrate flattening machine of the present invention. Fig. 2 is an x-ray diffraction observation and jL according to the first embodiment of the present invention. Inventive Example - SEM observation of the obtained two @ °曰. = Figure-based (four) real off - the silk flat heart refers to ^ above

弟5a圖，本發明實施例一之附著力測試 工J 光祕财式侧出轉示賴 弟5 b圖為本發明實施例一 =光罩烟方式細出銘線之光學圖片土。板上錄6.5贿銘膜 =a。圖為本發明實施例—在平坦基板上製作之二極體的電性特 ΪΓ。圖為本挪實關—在平域板上製作虹D積體電路示 【主要元件符號說明】 奈米結構層·.···· 緩衝層· · · · ·::: · · ·.....1 〇 基板· · · · · · · · 2 0 ······......30 9Figure 5a, the adhesion test of the first embodiment of the present invention, the J-ray secret type, and the transfer of the Lai brother 5 b diagram is the first embodiment of the invention = the photomask soil of the mask smoke method. On the board recorded 6.5 bribe Ming film = a. The figure is an electrical feature of a diode fabricated on a flat substrate in accordance with an embodiment of the invention. The picture is based on the reality - the production of the rainbow D integrated circuit on the flat domain board [main component symbol description] nano structure layer ······ buffer layer · · · · ·::: · · ·.. ...1 〇 substrate · · · · · · · · 2 0 ······...30 9

Claims (1)

1262907 泰 、—ij#專利範圍： I I f :ϊή 1 一種表面平坦化之陶瓷基板，其包括 j一一 ·—上::义 一基板； 一緩衝層，形成於該基板之上；及 一奈米結構層，形成於該緩衝層之上， 自二n層提供魏板無奈*結構層的接著，畔質可選 ί;ΐ^4 ^ ί材貝了為/弗石、_石、介孔物質、介孔複材或上述材料德 2.，申請專利範圍第！彻述之_縣面平坦化 中，该結構具有導熱、電絕緣、介電以及其它整 ^二 型被動元件=)、電感()、電容(〇動元件及其整合 3·如申請專利範圍第丄項所述之—種表面平坦化之 中，該結構具有導熱、電絕緣、介電以及其它整 ^ ς 型主動元件m 冑胃蝴渐件及其整合 項所述之—縣面平坦化之喊基板，其 之料;rt 魏緣、介如及其它整合電子元件所需 雷射二極體(1黯diode)、發光二極體(咖）、場 ^射源(Field Emitter)等發光元件之基板。 範圍第1賴述之—縣面平坦化之喊基板，其 U了構具有導熱:魏緣、、介電以及其它整合電子元件所需 動元件之光波導、光债測器等光被動元件及其整合型光被 =申請專娜圍第i賴述之—縣面平坦化之喊基板，其 結構具有導熱、電絕緣、介電以及其它整合電子元件所需 之特性，以作為光放大器、光開關、光調節等光主動元件及找 10 1262907 合型光主動元件之基板1262907 泰,—ij# Patent Range: II f :ϊή 1 A surface-flattened ceramic substrate comprising: a one-on-one: a substrate; a buffer layer formed on the substrate; The rice structure layer is formed on the buffer layer, and the second layer provides the Weiban helpless* structural layer, and the bottom quality is optional; ΐ^4^ 395 材贝为为佛石, _石, mesoporous Substance, mesoporous composite material or the above material de 2., the scope of patent application! In the _ county plane flattening, the structure has thermal conductivity, electrical insulation, dielectric and other integral passive components =), inductance (), capacitance (swinging components and their integration 3) as claimed In the surface flattening described in the item, the structure has thermal conduction, electrical insulation, dielectric and other integral active elements, and the flattening of the county surface Shouting the substrate, its material; rt Weiyuan, such as the laser diode (1黯diode), light-emitting diode (coffee), field emitter (Field Emitter) and other light-emitting components required for integration of electronic components The substrate is the first in the range of the county-level flattening substrate, which has a heat-conducting structure: an optical waveguide, an optical waveguide, and other optical components that integrate the dynamic components required for electronic components. Passive components and their integrated light are used to apply for the design of the flat surface of the county, which has the characteristics of heat conduction, electrical insulation, dielectric and other integrated electronic components. Amplifier, optical switch, light adjustment and other optical active components and find 10 1 262907 substrate of combined light active device