1260516 五、發明說明（1) 【發明所屬之技術領域】 本發明係為一種有關於電路佈局（layout)偵錯程序執 行之方法，特別是指一種根據電路佈局主要設計階段之進 行而自動執行偵錯程序之控制偵錯程序執行之方法。 【先前技術】 電子裝置的普及給人們的生活帶來了許多的便利並成 為不可或缺的物品，而作為電子元件安插與連結介面的電 路板（如，印製電路板（printed circuit board，PCB) 、集成電路板、軟式印刷電路板（flexible print circuit，FPC))是廣泛應用於各種電子相關產品中的基 礎零組件。 隨著目前市場對電子裝置輕薄短小與高速的要求，所 以各廠商們莫不希望能夠縮小電路板的面積以滿足市場的 需求，而隨著廒商對電路板面積的限制，使電路板的設計 (如，電路佈局（layout))的困難度也相對的增加並且更 為重要，其中電路佈局的優劣可直接的影響電子裝置的品 質與增加生產成本，甚至是企業的聲譽及商機。 舉例來說，當電路佈局具有瑕疵時，透過此電路佈局 所生產的電子裝置可能具有許多不良品，因此需浪費許多 重工的時間而造成生產成本的增加，或直接影響產品之品 質。而在網際網路發達的現在買方隨時都可透過網路了解 產品之評價做為選購產品之參考，因此品質不穩定的產品 透過網路傳播可能影響其銷售量，甚至是推出此產品的企 業之聲譽也可能相對的受到影響。1260516 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field The present invention relates to a method for performing a circuit layout debugging program, and particularly to automatically performing detection according to a main design stage of a circuit layout. The method of controlling the execution of the wrong program by the wrong program. [Prior Art] The popularity of electronic devices has brought many conveniences to people's lives and has become an indispensable item, and as a circuit board for inserting and connecting interfaces of electronic components (for example, printed circuit boards (PCBs) ), integrated circuit boards, and flexible printed circuits (FPC) are the basic components that are widely used in various electronic related products. With the current market demand for light, short, and high speed electronic devices, manufacturers do not want to reduce the area of the circuit board to meet the needs of the market, and with the limitations of the board area, the design of the circuit board ( For example, the difficulty of circuit layout is relatively increased and more important. The quality of circuit layout can directly affect the quality of electronic devices and increase production costs, even the reputation and business opportunities of enterprises. For example, when the circuit layout has flaws, the electronic device produced through this circuit layout may have many defective products, so that a lot of rework time is wasted, which causes an increase in production cost or directly affects the quality of the product. Nowadays, the current Internet-developed buyers can use the Internet to understand the evaluation of products as a reference for purchasing products. Therefore, the spread of unstable products through the Internet may affect their sales, even the company that launched this product. The reputation may also be relatively affected.
第6頁 1260516 五、發明說明（2) 一般電路佈局的設計程序主要分為四個階段，此四個 階段分別為定位佈置（p 1 acement)階段、線路佈置 (r 〇 u t i n g)階段、測點佈置（ΐ e s ΐ ρ 〇 i n t)階段、以及 發行（r e 1 e a s e)階段。其中每一設計階段的都會直接影 響到產品的品質。 習知電路佈局應用程式都提供了偵錯選項，以提供電 路佈局人員（1 a y 〇 u t e n g i n e e r)在每一設計階段完成時 ，利用偵錯選項找出設計缺失並及時的修正。但因所提供 的使用操作介面不夠便利，因此當電路佈局人員忙碌時常 會因疏忽而忘記執行债錯程序，而造成許多損失。 舉例來說，習知的偵錯選項並未能於每個階段完成後 提出警示，以讓電路佈局人員適時執行偵錯程序，因此當 錯誤產生時將難以確認是哪一階段所產生，且相關的設計 内容都可能一併產生錯誤而需重新設計。 因此，如何控制偵錯程序在電路佈局的設計階段中適 時的執行，以減少錯誤產生以及重工時間並維持設計品質 ，實為各企業與電路佈局人員所共同企盼的。 【發明内容】 本發明的目的乃為解決上述問題，提出一種電路佈局 (layout)執行偵錯程序之控制方法，透過確認電路佈局 各設計階段的完成，適時地讓各偵錯程式自動執行，以防 止電路佈局人員疏忽所造成的錯誤，並減少電路佈局人員 之工作量。 此方法包括下列步驟：提供具有啟始選項以及偵錯選Page 6 1260516 V. Description of the invention (2) The design procedure of the general circuit layout is mainly divided into four stages, which are respectively the positioning arrangement (p 1 acement) stage, the line arrangement (r 〇uting) stage, and the measuring point. Arrange (ΐ es ΐ ρ 〇int) phase, and release (re 1 ease) phase. Each of these design stages directly affects the quality of the product. The conventional circuit layout application provides a debugging option to provide circuit layout personnel (1 a y 〇 u t e n g i n e e r) to use the debug option to find design missing and timely corrections when each design phase is completed. However, because the user interface is not convenient enough, when the circuit layout personnel are busy, they often neglect to forget to execute the debt-correcting procedure, causing many losses. For example, the conventional debugging option does not provide a warning after each stage is completed, so that the circuit layout personnel can execute the debugging program at the right time, so it will be difficult to confirm which stage is generated when the error occurs, and the relevant The design content may be wrong and needs to be redesigned. Therefore, how to control the debugging program in the design phase of the circuit layout in a timely manner to reduce error generation and rework time and maintain design quality is a common expectation of enterprises and circuit layout personnel. SUMMARY OF THE INVENTION The object of the present invention is to solve the above problems, and to provide a control method for executing a debugging program in a circuit layout. By confirming the completion of each design phase of the circuit layout, the debugging programs are automatically executed in time. Prevent circuit layout personnel from negligent errors and reduce the workload of circuit layout personnel. This method includes the following steps: providing start options and debugging options
第7頁 1260516 五、發明說明（3) 項之使用者操作介面；透過前述之啟始選項開啟欲編輯的 電路佈局檔案，此電路佈局檔案中具有一個可確認各偵錯 選項之執行狀態的進度表。然後根據進度表上所紀錄的執 行狀態，將未執行之偵錯選項顯示於使用者操作介面上。 確認未執行之各偵錯選項所具有的警示内容與其所對 應之偵測内容是否相同；當確認相同時，令一個預設的偵 錯程序執行，並且將促使此偵錯程序執行之偵錯選項的執 行狀態切換為已執行；再根據執行狀態的切換，變更進度 表之内容；再確認是否還有未執行之偵錯選項，若沒有未 執行之偵錯選項，則視為電路佈局之設計已全部完成。 為使對本發明的目的、特徵及其功能有進一步的暸解 ’兹配合圖不說明如下： 【實施方式】 「第1圖」係本發明電路佈局（lay out)執行偵錯程序 之控制方法的方法流程圖。如圖所示本實施例主要的流程 步驟如下： 首先，提供具有啟始選項以及數個偵錯選項的使用者 操作介面（步驟2 0 0);啟始選項可開啟電路佈局檔案中 之電路圖以繼續修編工作，而偵錯選項是根據一般電路佈 局中的四個主要設計階段而相應的設置。 此四個設計階段分別為定位佈置（p 1 acement)階段 、線路佈置（r 〇 u t i n g)階段、測點佈置（t e s t ρ 〇 i η ΐ )階段、以及發行（r e 1 ease)階段，而所相應設置的選 項為定位偵錯（p 1 a c e m e n t c h e c k)選項、線路彳貞錯Page 7 1260516 V. The user interface of the invention (3); the circuit layout file to be edited is opened through the aforementioned start option, and the circuit layout file has a progress to confirm the execution status of each debug option. table. The unexecuted debug options are then displayed on the user interface based on the execution status recorded on the schedule. Confirm that the debug content of each unexecuted debug option has the same detection content as its corresponding detection content; when the confirmation is the same, a preset debug program is executed, and the debug option that causes the debugger to execute is selected. The execution state is switched to executed; then the content of the schedule is changed according to the switching of the execution state; and whether there is an unexecuted debugging option, if there is no unexecuted debugging option, the circuit layout design is considered all finished. In order to further understand the object, features and functions of the present invention, the following figures are not described as follows: [Embodiment] The first embodiment is a method for controlling a circuit for laying out a debugging program according to the present invention. flow chart. The main process steps of this embodiment are as follows: First, a user operation interface having a start option and a plurality of debug options is provided (step 200); the start option can open the circuit diagram in the circuit layout file. The revision work continues, and the debug options are set according to the four main design phases in the general circuit layout. The four design phases are the p 1 acement phase, the r 〇uting phase, the test point arrangement (test ρ 〇i η ΐ ) phase, and the release (re 1 ease) phase, respectively. The options set are the positioning error (p 1 acementcheck) option, the line is wrong.
1260516 五、發明說明（4) (routing check)選項、測點偵錯（test point check )選項以及發行债錯（r e 1 e a s e ch e c k)選項。 其中，定位偵錯選項用以確認元件是否完全擺放至電 路圖中；線路偵錯選項用以確認擺放到電路圖中的各元件 是否都有拉好適當的走線（trace);而測點偵錯選項則 是用來確認「測點」是否已經設定。此「測點」為生產單 位用以確認電路板中基本訊號與功能之量測點。 另外，發行偵錯選項則用以確認走線是否有短路或斷 路之狀況，以及底片（artwork)檔是否製作完成。底片 檔是透過電路圖轉換而生成用來交由其它單位執行接續後 製工作所需之檔案。 然後，透過啟始選項開啟具有進度表之電路佈局檔案 (步驟2 1 0);進度表中係記錄著各偵錯選項之執行狀態 (如，已執行或未執行）。此電路佈局檔案中除了進度表 外更包含了電路圖以及底片檔…等。而電路佈局檔案稽案 名稱的設置係需包含一個可顯示版本資訊（如，試作版、 正式版或發行版）之代表號。其中，試作版與正式版之差 異為，正式版在電路圖中增設「測點」，另外正式版與發 行版之差異為發行版增加了底片檔。 然後，根據進度表將未執行之各偵錯選項顯示於使用 者操作介面上（步驟2 2 0)。接著，依序確認未執行的各 偵錯選項所具有的警示内容與其所對應之偵測内容是否相 同（步驟2 3 0);各警示内容係用來確認各偵錯選項所對 應的設計階段是否完成，而各偵測内容則是根據各偵錯選1260516 V. Invention description (4) (routing check) option, test point check option and issue error (r e 1 e a s e ch e c k) option. The positioning error detection option is used to confirm whether the component is completely placed in the circuit diagram; the line debugging option is used to confirm whether each component placed in the circuit diagram has a proper trace; The wrong option is used to confirm if the "measurement point" has been set. This “measurement point” is the measurement point used by the production unit to confirm the basic signals and functions in the board. In addition, the issue debugging option is used to confirm whether the trace has a short circuit or open condition, and whether the artwork file is completed. The film file is a file created by circuit diagram conversion to be used by other units to perform subsequent work. Then, the circuit layout file with the schedule is opened by the start option (step 2 1 0); the execution status of each debug option (for example, executed or not executed) is recorded in the schedule. In addition to the schedule, this circuit layout file contains circuit diagrams and film files...etc. The setting of the circuit layout file audit name must include a representative number that can display the version information (for example, trial version, official version or release version). Among them, the difference between the trial version and the official version is that the official version adds "measurement point" in the circuit diagram, and the difference between the official version and the release version adds a negative file to the distribution. Then, the unexecuted debug options are displayed on the user's operation interface according to the schedule (step 2 2 0). Then, it is sequentially confirmed whether the warning contents of the unexecuted debugging options are the same as the corresponding detection content (step 2 3 0); each warning content is used to confirm whether the design phase corresponding to each debugging option is Completed, and each detected content is selected according to each debugging
第9頁 1260516 五、發明說明（5) 項所對應的設計階段而選定。 例如，定位偵錯選項所對應的設計階段為定位佈置階 段，而確認定位佈置階段完成之方法為確認電路佈局檔案 中電路圖内未擺放元件之值為零，因此警示内容將設定為 零，且未擺放元件之值將視為偵測内容。因此當警示内容 相同於偵測内容時，即表示各個元件都已經擺放至電路圖 中（未擺放元件之值等於零）。 線路偵錯選項所對應的設計階段為線路佈置階段，而 確認線路佈置階段完成之方法為確認未設置完成（拉好） 之走線（trace)值為零。因此警示内容將設定為零，且 未完成之走線值將視為偵測内容。而當警示内容相同於偵 測内容時，即表示各個元件之走線皆已設定。 測點偵錯選項所對應的設計階段為測點佈置階段，而 確認測點佈置階段完成之方法為確認電路佈局檔案之檔案 名稱中代表版本之代表號係為正式版本。因此警示内容將 設定為正式版本之代表號，且檔案名稱之代表號將做為偵 測内容。而當警示内容相同於偵測内容時，即表示電路圖 中「測點」已設定完成。 發行偵錯選項所對應的設計階段為發行階段，而確認 發行階段完成之方法為確認電路佈局檔案中已具有底片檔 。因此警示内容將設定為底片檔之副檔名或檔名，且檔案 名稱中底片檔之副檔名或檔名將視為偵測内容。因此當警 示内容相同於偵測内容時，表示電路佈局檔案中已具有底 片檔（底片檔已製作完成）。Page 9 1260516 V. Inventive Note (5) The design phase corresponding to the item is selected. For example, the design phase corresponding to the positioning debugging option is the positioning and arranging phase, and the method for confirming that the positioning and arranging phase is completed is to confirm that the value of the unplaced component in the circuit diagram in the circuit layout file is zero, so the warning content is set to zero, and The value of the unplaced component will be considered as the detected content. Therefore, when the content of the warning is the same as the detected content, it means that each component has been placed in the circuit diagram (the value of the unplaced component is equal to zero). The design phase corresponding to the line debugging option is the line layout phase, and the method of confirming the completion of the line layout phase is to confirm that the trace value of the unset completion (pull) is zero. Therefore, the alert content will be set to zero, and the unfinished trace value will be treated as the detected content. When the content of the warning is the same as the content of the detection, it means that the routing of each component has been set. The design phase corresponding to the measuring point debugging option is the measuring point layout phase, and the method of confirming the measuring point layout phase is to confirm that the representative version of the representative version of the file layout file is the official version. Therefore, the warning content will be set to the official version of the representative number, and the representative number of the file name will be used as the detection content. When the content of the warning is the same as the detected content, it means that the "measurement point" in the circuit diagram has been set. The design phase corresponding to the release debugging option is the release phase, and the method of confirming the completion of the release phase is to confirm that the circuit layout file already has a negative file. Therefore, the warning content will be set as the file name or file name of the film file, and the file name or file name of the film file in the file name will be regarded as the detection content. Therefore, when the warning content is the same as the detected content, it means that the circuit layout file already has a bottom file (the film file has been created).
第10頁 1260516 五、發明說明（6) 然後，當比對結果為相同時，則促使預設的偵錯程序 開始執行，並將偵錯選項之執行狀態切換為已執行（步驟 2 4 0);當各偵錯選項之比對結果相同時，代表其所相應 的各設計階段已經完成，此時可促使電路佈局應用程式 (例如，愛爾蘭商明導國際股份有限公司（M e n t 〇 r Graphics (Ireland) Ltd)所推出之 Design Manager軟體 ，以及華萊科技公司（Valor Computerized Systems)所推 出之電腦辅助工程系統軟體）開始執行相應之偵錯程序， 以確認設計中之錯誤。 然後，根據執行狀態的切換，變更進度表之内容（步 驟2 5 0);當各偵錯選項分別完成後，將變更其顯示於使 用者操作介面上之執行狀態，以提醒電路佈局人員最新的 偵錯狀態，並將電路佈局檔案中紀錄各偵錯選項執行狀態 的進度表相對更新。 最後，確認是否有未執行之偵錯選項（步驟2 6 0)； 當確認使用者操作介面上沒有未執行之偵錯選項時，則代 表所有設計階段都已經完成則結束所有程序。另外當確認 尚有未執行之偵錯選項時，則重新執行步驟2 3 0以讓未執 行之偵錯選項接續執行。 另外，當步驟2 3 0之比對結果係為不相同時，則會接 續執行步驟2 6 0以確認是否有未執行之偵錯選項。 請再參閱「第2圖」係為使用者操作介面之使用示意 圖。如圖所示使用者操作介面1 0中係顯示具有啟始選項1 1 以及數個偵錯選項（如，定位偵錯選項1 2、線路偵錯選項Page 10 1260516 V. Description of the invention (6) Then, when the comparison result is the same, the preset debug program is caused to start execution, and the execution state of the debug option is switched to executed (step 2 4 0) When the results of the matching options are the same, it means that the corresponding design phases have been completed, which can promote the circuit layout application (for example, the company M 〇r Graphics (Ment 〇r Graphics ( The Design Manager software from Ireland) Ltd. and the computer-aided engineering system software from Valor Computerized Systems began to implement the corresponding debugging procedures to confirm errors in the design. Then, according to the switching of the execution state, the content of the schedule is changed (step 2 50); when the debugging options are respectively completed, the execution state displayed on the user operation interface is changed to remind the circuit layout personnel of the latest Debug status and update the schedule in the circuit layout file to record the execution status of each debug option. Finally, verify that there are unexecuted debug options (step 2 60 0); when there are no unexecuted debug options on the user interface, then all programs are terminated when all design phases have been completed. Also, when you have confirmed that there are still unexecuted debugging options, re-execute step 2 3 0 to allow the unexecuted debugging options to continue. In addition, when the result of the comparison of step 203 is different, step 260 is continued to confirm whether there is an unexecuted debugging option. Please refer to "Figure 2" for a schematic diagram of the user interface. As shown in the figure, the user interface 10 displays the start option 1 1 and several debug options (eg, location error detection option 1 2, line debug option).
1260516 五、發明說明（7) 1 3、測點偵錯選項1 4以及發行偵錯選項1 5)，其中各偵錯 選項可透過以粗細字體、字體底線或以顏色變化等方式， 做為提示方式以提示電路佈局人員各偵錯選項的執行狀態 〇 舉例來說，啟始選項1 1與定位偵錯選項1 2係以細字體 顯示，表示此兩個選項係執行過（已完成）；而線路偵錯 選項1 3係以粗字體顯示即表示此選項係正在執行；另外測 點偵錯選項1 4以及發行偵錯選項1 5係以以粗字體顯示且有 陰影的方式顯示，則代表此兩個選項尚未執行過（尚未完 成）。在實際的應用上各偵錯選項的執行狀態表示方式並 未限定，只要達到能夠讓電路佈局人員辨識各種狀態即可 〇 透過本發明之控制方法，不僅可讓電路佈局人員在電 路佈局之設計時，確實的執行全部的偵錯程序以維持電路 佈局設計的品質，更可進而增加產品的穩定性。 以上所述者，僅為本發明其中的較佳實施例而已，並 非用來限定本發明的實施範圍；即凡依本發明申請專利範 圍所作的均等變化與修飾，皆為本發明專利範圍所涵蓋。1260516 V. Invention description (7) 1 3, measuring point debugging option 1 4 and issuing debugging option 1 5), each of which can be used as a hint by using a thick font, a font bottom line or a color change. The method is to prompt the circuit layout personnel to execute the debugging status of each debugging option. For example, the starting option 1 1 and the positioning debugging option 1 2 are displayed in a fine font, indicating that the two options are executed (completed); Line debugging option 1 3 is displayed in bold font to indicate that this option is being executed; in addition, the measuring point debugging option 1 4 and the issuing debugging option 1 5 are displayed in bold font and shaded, which means this Two options have not been executed (not yet completed). In the actual application, the execution state of each debug option is not limited. As long as the circuit layout personnel can recognize various states, the control method of the present invention can be used to not only allow the circuit layout personnel to design the circuit layout. It does perform all the debugging procedures to maintain the quality of the circuit layout design, which in turn increases the stability of the product. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; that is, the equivalent variations and modifications made by the scope of the present invention are covered by the scope of the present invention. .
第12頁 1260516 圖式簡單說明 【圖式簡單說明】 第1圖係為本發明之方法流程圖；及 第2圖係本發明使用者操作介面之使用示意圖。 [ 圖 式符號~ 說明 ] 10 使 用 者 操 作 介 11 啟 始 選 項 12 定 位 偵 錯 選 項 1 3 線 路 偵 錯 選 項 14 測 點 偵 錯 選 項, 1 5 發 行 偵 錯 選 項 步 驟 200 提 供 具 有 啟 始 作 介 面 步 驟 210 透 過 啟 始 選 項 案 步 驟 220 根 據 進 度 表 將 項 顯 示 於 使 用 步 驟 230 確 認 未 執 行 的 與 其 所 對 應 之 步 驟 240 令 預 設 的 偵 錯 之 執 行 狀 態 切 步 驟 250 根 據 執 行 狀 態 步 驟 260 確 認 是 否 有 未 選項以及偵錯選項的使用者操 開啟具有進度表之電路佈局檔 執行狀態為未執行之各彳貞錯選 者操作介面上 各偵錯選項所具有的警示内容 偵測内容是否相同 程序開始執行，並將偵錯選項 換為已執行 的切換，變更進度表之内容 執行之偵錯選項Page 12 1260516 Brief description of the drawings [Simplified description of the drawings] Fig. 1 is a flow chart of the method of the present invention; and Fig. 2 is a schematic view showing the use of the user interface of the user of the present invention. [Symbol ~ Description] 10 User Interface 11 Start Option 12 Position Debug Option 1 3 Line Debug Option 14 Point Detect Option, 1 5 Issue Debug Option Step 200 Provides a Start Interface Step 210 According to the start option step 220, the item is displayed according to the schedule, and the step 240, which is unexecuted, is used to confirm the unexecuted step 240, and the execution status of the preset debugging is performed. Step 250 According to the execution status step 260, it is confirmed whether there is a non-option and The user of the debugging option opens the circuit layout file with the schedule, and the execution status of the circuit layout file is unexecuted. The error detection options of the error detection options on the operation interface of the error detection device are the same as the program execution, and will detect Change the wrong option to the executed switch, change the content of the schedule to execute the debug option
第13頁Page 13