TWI250580B - Method for manufacturing anti-punch-through semiconductor device - Google Patents

Method for manufacturing anti-punch-through semiconductor device Download PDF

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TWI250580B
TWI250580B TW093137010A TW93137010A TWI250580B TW I250580 B TWI250580 B TW I250580B TW 093137010 A TW093137010 A TW 093137010A TW 93137010 A TW93137010 A TW 93137010A TW I250580 B TWI250580 B TW I250580B
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trench
manufacturing
doped region
breakdown
substrate
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TW093137010A
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TW200620461A (en
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Min-San Huang
Rex Young
Su-Yuan Chang
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Powerchip Semiconductor Corp
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Priority to US10/908,379 priority patent/US7195982B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Physics & Mathematics (AREA)
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Description

12505 视—/c 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件的製造方法，且特 別是有關於一種防止擊穿（anti_punch-through)的半導體元 件的製造方法。 【先前技術】 隨著積體電路產業的快速發展，在要求電路積集化 越來越高的情況下，整個電路元件大小的設計也被迫往尺 寸不停縮小的方向前進。當半導體元件的尺寸逐漸縮小 時’元件之間的距離也會相對的縮小，當其距離縮短到某 一疋的程度之後，各種因製程積集度提高所衍生的問題便 會發生。因此，如何製造出尺寸縮小、高積集度，又能兼 顧其品質的半導體元件是產業的一致目標。 圖1所繪示為習知一種半導體元件的剖面示意圖。 请參照圖1 ’半導體元件包括基底1〇〇、介電層1〇2、溝 渠式元件104與摻雜區106 °其中，介電層ι〇2位於基底 100上方，而溝渠式元件104位於部分基底1〇〇與介電層 102中，且摻雜區106位於溝渠式元件1〇4下方之基底1〇〇 中。 然而，隨著半導體元件積集度的提高，傳統之半導 體元件的製造方法出現了許多挑戰。例如是，由於半導體 製程積集度的提高，而相鄰的溝渠式元件104之間的距離 也相對縮短，因此容易造成兩相鄰的摻雜區106之間產生 電性擊穿(punchthroughX如圖1中所示之箭頭1〇8)的問 I2505W29tw,d〇c/c ’此問題會造成相鄰的溝渠式元件刚之間產生不正常 ，電性導it，而使得元件操作速度與元件魏不佳，甚至 是造成元件短路(short)或斷路(〇pen)，進而大大地影塑 個製程的良率與可靠度。 曰 【發明内容】 ，有鑑於此，本發明的目的就是在提供一種防止擊穿 的半導體7G件的製造方法，能夠避免因元件之間的電性擊 穿的問題，使得元件操作速度與元件效能不佳，進而影響 到製程的良率與可靠度。 、 本發明提出一種防止擊穿的半導體元件的製造方 法，此方法係適用於基底，且此基底中已形成有平行排列 的多數個元件隔離結構以定義出多數傭主動區，且這些元 件隔離結構之上表面突出於基底表面。另外，在基底上已 形成有平行排列的多條導體層，這些導體層與元件隔離結 構父錯’在導體層下方且位於每兩個元件隔離結構之間已 形成有多數個溝渠式元件，而溝渠式元件包括設置於溝渠 底部的第一導電型摻雜區。此方法包括先於元件隔離結構 及導體層之側壁形成間隙壁，然後再以間隙壁為罩幕進行 摻貝植入製程，以於兩相鄰之第一導電型摻雜區之間形成 第二導電型摻雜區。 依照本發明的較佳實施例所述，上述之形成間隙壁 之方法包括於基底上形成絕緣材料層，然後進行一非等向 性蝕刻製程，移除部分絕緣材料層以形成之。其中，間隙 壁之材質包括氮化石夕。 !25〇5^29_ 依照本發明的較佳實施例所述，上述第二導電型摻 雜區之範圍由間隙壁的厚度所調整。 依照本發明的較佳實施例所述，上述策_導電型摻 雜區為P型摻雜區，而第二導電型摻雜區則為N 雜 區。 雜 依照本發明的較佳實施例所述，上述第一導電型摻 =區為N型摻雜區，而第二導電型摻雜區則為p型摻^ 依照本發明的較佳實施例所述，上述之溝渠— 為溝渠式記憶體。 70 依照本發明的較佳實施例所述，上述之溝渠 為溝渠式電容器。 χ疋牛 依照本發明的較佳實施例所述，上述之溝渠 為溝渠式電晶體。 〃工凡件 =得:件效能不佳，進而影響到製程的良 ϋ度本發明係可利用間隙壁的厚度以精準 〇 lit夕Κ ，女名匕犯4 具有防止擊穿特性的區域所使用的製 、由於本發明係利用間隙壁做為罩幕，以自行對準 ^式’進行摻質植人製程，以於元件的摻雜區之間形且 =止擊料性龍域。因此，本發啊避免因產生電ς =制防止擊穿特性的區域的大小。此外，本發明之= =防止擊穿特性的區域所使㈣製程可與互 氧^ 可發揮很大的功效。 —I大的成本，即 為讓本發明之上述和其他目的、特徵和優點能更明 I25〇5814Q29_/c 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 圖2A至圖2C係繪示為本發明一較佳實施例的防止 擊穿的半導體元件的製造方法的流程上視圖。圖3A至圖 3C為分別繪示圖2A至圖2C中沿M，線之剖面圖。圖4A 至圖4C為分別繪示圖2A至圖2C中沿ΙΙ-ΙΓ線之剖面圖。 首先，請同時參照圖2A、圖3A與圖4A，提供一基 底200。此基底200例如是矽基底。此基底200已形成有 平行排列的多數個元件隔離結構202，以定義出多數個主 動區204，且這些元件隔離結構2〇2之上表面突出於基底 200表面。其中，元件隔離結構2〇2的形成方法例如是淺 溝渠隔離法(Shallow Trench Isolation，STI)。 另外，在基底200上已形成有平行排列的多條導體 層206，而這些導體層2〇6與元件隔離結構2〇2係交錯排 列。其中，導體層206的材質例如是摻雜多晶矽，而其形 成方法例如疋利用化學氣相沈積法形成一層未摻雜多晶石夕 層後’進仃離子植人步驟以形成之；或者也可以採用臨場 (in-situ)植入摻質的方式，利用化學氣相法法形成之。而 且’在各條導體層2〇6下方、且位於每兩個元件隔離結構 202之間的主動區2〇4中已形成有多數個溝渠式元件施， 其中，溝渠式元件208例如是溝渠式電容器、溝渠式電晶 體或溝渠式記憶體。 木I日日 在-實施例中’在基底200上可形成介電㉟214，其 I2505^4Q29twfd〇c/c :3L2= Γ才質例如是氧切、氧化矽/氣化矽/氧化 2疋其他合適之材質，而其形成方法例如是化學氣相沈 積法。 n刑ibi卜，溝渠式元件識包括設置於溝渠训底部的 忒2區』其中’ n型摻雜區212之形成方法例如 ^ ,入衣私。同樣地，因為製程積集度的提高 ，兩相 :乡雜區212亦容易發生電性擊穿h如 的問題。 B ) 接著，請同時參照圖2B、圖SB與圖犯，於基底· =成-層絕緣材料層216。其中，此絕緣材料層216的 貝例如疋氮切，而其形成方法例如是化學氣相沈積 繼之，請同時參照圖2C、圖3C與圖4C，移除部分 部分絕緣材料層216，而於元件隔離結構2〇2與導體層2〇6 之侧壁形成間随216a。其中，移除部分絕緣材料層216 以形成㈣:壁216a之方法例如是進行—非等向性姓刻製 程0 隨後，以間隙壁216a為罩幕，進行一摻質植入製程 22〇，以於兩相鄰之摻雜區212之間形成一 p型換 區 218。 " 特別是，P型摻雜區218與N型摻雜區212互為不 同摻質的摻雜區，所以P型摻雜區218可做為具有防止 擊穿特性的區域，以防止電性擊穿的問題。亦即是，p型 摻雜區218可用以避免因相鄰的N型摻雜區212之間的 12505¾ 29twf.doc/c 電性導通，耐彡響元件效能的問題。 在士述的實施例中，溝渠式元件施的 Γρ :止擊穿特性的區域係分別採用N型摻雜= 及P型摻雜區為例以詳Λ訪叫 L、 丄心雜 =二’本發明亦可採用‘式 ί摻雜區之間形成二=;穿於= 製耘的良率與提高製程的可靠度。 。 在本發明中，Ρ型摻雜區118 厚度調整。換句話說’本=二 =:、的厚度以準確的定義出預形成之推雜區的= 212):fi^::彳::係於元件之摻雜區(Ν型摻雜區 12)之間$成與其不同摻#之摻雜區(ρ鮮雜區 Γ==穿’而其係利用間隙壁⑽為罩 特性的區_ 出具有可防止擊穿 件間產生電性不正常導通的現t =)，Γ免相鄰的元 ，擊穿，如此可改善製程的良率卩與提 另外，本發明之防止擊穿的摻雜 離f構=與導體層206所圍出的“區域(如二3 不），且其係以間隙壁族為罩幕，以自行對準方式進行
他的摻雜區域(如N 離子植入製程，因此將不會有影響其 型摻雜區212)的問題。 曰" 值得注意的是，本發 的方法可與互補式金氧半導體權 =本發明不需耗費龐大的人力與成本，即°可發揮很大的
雖然本發明已以較佳實施例揭露如上，麸苴月 ^艮，發明，何熟w此技藝者，在不_本發明之南 =粑_ ’ t可作些許之更動制飾，因此本發明之 濩乾圍當視後附之申請專利範圍所界定者為準。 ’ 【圖式簡單說明】 圖1所繪示為習知-種半導體元件的剖面示意圖。 圖2A至圖2C係繪示為本發明一較佳實施例的防止 擊穿的半導體元件的製造方法的流程上視圖。 圖3A至圖3C係繪示為本發明一較佳實施例的防止 擊穿的半導體元件的製造方法的流程剖面圖，且其分別繪 示圖2A至圖2C中沿Ι-Γ線之剖面圖。
圖4A至圖4C係繪示為本發明一較佳實施例的防止 擊穿的半導體元件的製造方法的流程剖面圖，且其分別緣 示圖2A至圖2C中沿Π-ΙΓ線之剖面圖。 【主要元件符號說明】 100、200 :基底 102、214 :介電層 104 ·溝渠式元件 11 125058^, 106 :摻雜區 108 :箭頭 202 :元件隔離結構 204 :主動區 206 :導體層 208 :溝渠式元件 210 :溝渠 212 ·· N型摻雜區 216 :絕緣材料層 216a :間隙壁 218 : P型摻雜區 220 :摻質植入製程
12

Claims (1)

  1. I25058029twf_d〇c/c 十、申請專利範面： 1.=種防止擊穿的半導體元件的製造方法，適用於一 基=雜底巾已形成有平行㈣的多數個元件隔離結構 以疋義出多數魅動區，且該些元件隔離結構之上表面突 出於該基絲面，在該基底上已形成有平行制的多條導 體層’該些導體層與該些元件隔離結構交錯，在各該些導 ，層下方、且位於每兩該些元件隔離結構之間的該些主動 區中已形財錄個溝渠^件，各該些賴式it件包括
    設置於=溝渠底部的一第一導電型摻雜區，該方法包括： ”於δ亥些元件隔離結構及該些導體層之侧壁形成一間 隙壁；以及 以該間隙壁為罩幕進行-摻質植入製程，以 鄰之該第-導電型摻雜區之間形成—第二導電型播雜區。 2. 如申請專利範圍第1項所述之防止擊穿的半導體3 件的衣造方法，其中形成該間隙壁之方法包括： _ 於該基底上形成一絕緣材料層；以及
    進行-非等向性酬製程，移除部分魏緣材料層 3. 如申請專利範圍第i項所述之防止擊穿的 件的製造方法，其巾該_壁之材f包括氮切。7 4. 如申請專利範圍第丨項所述之防止擊穿 件的製造方法，其中該第二導電型摻雜區 ; 壁的厚度浦。 間β 5. 如申請專利範圍第【項所述之防止擊 件的製造方法，其中該第-導電型摻雜區型接雜^ 13 1250581^^ 該第二導電型摻雜區為n型摻雜區。 元 6·如申請專利範圍第1項所述之防止擊穿的半導體 件的製造方法，其中該第—導電型摻雜 該第二導電型摻雜區為p型摻雜區。 萬 7·如申請專利範圍第丨項所述之防止擊穿的半導體元 件的製造方法，其巾該㈣渠式元件為溝渠式記憶體。 8·如申請專利範圍弟1項所述之防止擊穿的半導體元 件的製造方法，其中該些溝渠式元件為溝渠式電容器。 9·如申請專利範圍第丨項所述之防止擊穿的半導體元 件的製造方法，其中該些溝渠式元件為溝渠式電晶體。 14
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