1245905 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種電壓峰值檢知器，尤指利用一差動放大器 (differential amplifier)、一充電電晶體(charging transistor)、一電 容器、一輸出級以及一電流鏡電路所組成以求獲得精確電壓峰值之互補式 金氧半（CMOS)電子電路。 【先前技術】 電壓峰值檢知器係一種電子電路，能夠測得一電壓波形之最大值，質 言之，該電路之輸入為—變動之電壓信號，而其輸出則是該輸人電壓波形 之最大值。 〜在許多應用中，輸入電壓信號之峰值必須被測出，然後將之以直流電 型怨保留住以便後續分析、使用。一個脈衝串之尖峰值常比它的平均值要 更有用，例如當執行破壞性測試時，就有必要追尋出並保持峰值信號，而 量測電麼信號在傳輸媒介上之衰減量、卖員比至數位轉換器（a/d converter)、最大近似解碼系統（maxi_ 加⑺心 以及用以檢測核輻射之脈衝信號檢測電路等也需要用到電壓峰值檢知器。 先前技藝(prior art)中，電壓峰值檢知器之最簡單作法係令輸入電壓 b虎通，二極體，而對電容充電，以便取得該輸人電壓波形之學值。 如第-圖所不，當輸入電壓v⑽大於電容器c之電壓時，二極體 =充電作用，直到輸入電壓V(IN)到達其最大值，電容器C不能 再、“充琶’此時輸出電壓^_即表示輸人電獻⑽之峰值。 卿正端間存 =二極體D，此電路無法精確地檢得輸入電 真換言之，輸出糖_與輸人霞聊之峰值之 二退二Γ導通糖d之誤差。亦即，卿⑽O)=MM(V(IN))-Vd， 係0·之暫態分析模擬結果）。 子於迕夕應用而言，上述二極體導 1245905 為了能夠精確地檢測輸入之峰值電壓，迄今，有許多精密電料值檢 π之技術被提出，例如於美國專利案第US5謝939、刷2746、55搬7、、 t96f45，_、刪238和6472861號以及中華民國專利細8220146 號中所揭露者均是，該等技術均能精確地檢測輸入信號之岭值霞， 於該等電麼峰值檢知器均使用到一個以上之運算放大器，因此仍存在有電 路、，D構複雜、佔用的晶片面積大等缺失，實不利於積體電路之要求。 最近，錢種Μ使關運算放大^難链峰值檢知器之技術被 ^，例如中華民國專利案第9_722號：「電壓峰值檢知器」（其主要 ，表圖如第三圖卿)和第9_88冑：「具雙充電路徑之電辟值檢知 :」C、主要代表圖如細圖所示）中所揭露者喊，該等技術均係以一差 和一電流鏡所組成的電路來取代運算放大器，由於並不使用到運 ’具備電路結構簡單、姑用的晶片面積小以及有利於裝置 之小型化#多重功效。 但由於該等技觸使狀差滅Α||具有對^ ^ ^ 出級於戶^八41此外’6玄等技術並未於峰值檢知器中設置輸出級，輸 Γϊΐϊίί峰值電壓被外部電路擁取時可有效保持該輸入峰值電 ί動動作而降低，甚至遭受破壞。另，該等技術亦未考慮到 ^電壓（0verSh⑽她鄉簡稱㈣效應，熟悉差動放 t 白可由差動放大器之電虔轉換特性曲線(v〇ltage t譲fer \’欲使差動放大器—方之驅動電晶體呈流通有該差動 方驅^雷日_電二之¥通狀態，戦於該—方驅動電晶體之輸人端與另一 旦電端間施加至少—超量電壓VGS之電壓差。注意，此超 二誤差’因此，該等技術於精確度方面 慮到上述缺失之精密電料值檢知器之技術被提出， l^92120739 m: 。 ④斤不）’雖§兄第五圖所示電路已對電麼峰值檢知器提出一種 錢’惟該電路仍有改進空間，例如因該電路於輸出級中使用到 1245905 以上之電阻器而導致消耗過大晶片面積之問題，並且_電路易叫 ㈣導致降低精確度之問題(請參考該第9謂39號專利宰說日 第24至28行之記載），因此還有改進空間存在。1兄月曰弟9頁 。。，树明之主要目的係㈣—機齡叙龍峰值檢知 二:的晶片面積小以及具高集積度，並且兼具電路結構簡單、 j重功效，同時亦設置有輸出級以有效防止因外部電 動作而遭致破壞所保持之輸入峰值電壓。 頁取 本^^欠要目的係提出一駐補式金氧半娜)結構之電壓峰值檢 知為，/、可有效消除差動放大器之超量電壓效應。 【發明内容】 的本^明所提出之互補式金氧半(⑽s)電壓峰值檢知器係由—差動放大 Γ二充電電晶體2、—電容器C、—輸出級3以及—電流鏡電路4所組 八，5玄差動放大器係以非對稱式結構來設計，亦即僅使用單邊之負 ，電晶體’且該負載電晶體與該充電電晶體共同構成—電流鏡，因此可較 ，統之精密電壓夸值檢知器（即中華民國專利案第9_722和刪聰號 專利=揭露之電壓峰值檢知幻少二個臟電晶體。此外，本發明所提出 ^電，峰值檢知器設置有輸出級，且該輸出級巾並未使用到 50ΜΩ以上之 电阻為’ E)此不但具有較高之集積度’並且能避免所保持之輸騎值電壓 不致因外部電路之擷取動作而遭致破壞，同日嫌具精確地調整並輸出所保 持之輪入峰值電壓之功能。另，本發明亦可有效雜差減大器之超量電 壓效應。 【實施方式】 根據上述之目的，本發明提出一種新穎之互補式金氧半(CM〇s)電壓峰 ，，知器’如第六圖所示，其係由一差動放大器卜一充電電晶體2、一電 MC、;-輸出級3以及-電流鏡電路4所組成，該差動放大器丄是使用非對 稱性之電路組態來設計’其係由丽〇s電晶體丽丨、丽2以及pM〇s電晶體Μρι所 組成’其中，湖M0S電晶體_!和丽2係做為驅動器（driver)使用，而該pM〇s 1245905 電晶體MP1則作為負載電晶體使用。湖M〇s電晶體腿和_2之間極(购)係 分別接受輸入電壓信號V⑽及電容器上之電壓信號v⑹，源極(簡連 接在一起，並連接至電流鏡電路4，而其汲極則分別與負載電晶體肥丨及電 源供應電壓Vdd相連接。 請再參考第六圖，負載電晶體MP1與充電電晶體Mp2共同構成一電流 鏡’且该PM0S電晶體MP1和MP2之源極均與電源供應電壓腿連接，而閘極 則連接在起，並連接至丽〇S電晶體丽1之沒極，同時該pMQS電晶體Μρι之 閘極與，極係連接在—起，以形成„電流鏡；再者，pMQS電晶體肥2之沒極 係與電容IIG之-端連接，而該電容器G之另_端則接地：此外，輸出級3係 由-NM0S電晶麵3所組成，並連接在電源供應電壓觀與輸出端之間。另， 電流鏡電路4係由NM0S電晶継N4、MN5、MN6以及-電阻器R所組成，該電流 鏡黾路4係用以產生一參考電流iR，並將該參考電流&經由該醒呢電晶體 .5所域之電流鏡鏡職，提供—_參考電流㈣鏡射比率之電 流Ib至該差動放大器1，同日神軸湖電晶體·和_域之電流鏡 鏡射後，提供-與該參考電流1化成鏡射比率之電流1〇仍至該輸出級3。 為了便於說明起見，以下之推導過程，均將金氧半電晶體#〇rCAD Pspice中之最簡單模型來描述，且不考慮通道長度調變(如_ }邮匕 modulation)效應。但於後續之模擬驗證時，則考慮了〇rCAD化贞⑵中之 所有電晶體參數（當然包括通道長度調變效應）。 w首先推導參考電流IR、流經差触Α||1之電流㈣及越輸出級3之 電流Ιουτ，由第六圖所示之電流鏡電路4可知，參考電流Ir等於 lR=(Vdd - VGS5)/R ⑴ 其中，VGS5為NM0S電晶體丽5之閘源極電壓VGS5，其可由下列方程式求得· (Vdd - VGS5)/R= [KP.WN5/(2.LN5)] · (VGS5 -Vtns)2 (2) 方程式（2)中之WNS和LN5分別表示該mm〇s電晶體丽5之有效通道寬度及 有效通道長度’ KP表示GrGAD Pspiee巾之-金氧半電晶體模型參數，而Vtn5 則表示該_S電晶體MN5之零基底偏壓之臨限電壓（zen)_bias thresh〇ld voltage)。再者，由第六圖所示之電流鏡電路4並配合電流鏡電路之工作原 理可为別求出流經差動放大器1之電流IB以及流經輸出級3之電流I 〇 u τ， 1245905 其結果為1245905 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a voltage peak detector, especially using a differential amplifier, a charging transistor, a capacitor, an output A complementary metal-oxide-semiconductor (CMOS) electronic circuit composed of a stage and a current mirror circuit to obtain accurate voltage peaks. [Prior technology] The voltage peak detector is an electronic circuit that can measure the maximum value of a voltage waveform. In other words, the input of the circuit is a variable voltage signal, and its output is the input voltage waveform. The maximum value. ~ In many applications, the peak value of the input voltage signal must be measured and then retained as a direct current type for subsequent analysis and use. The peak value of a burst is often more useful than its average value. For example, when performing a destructive test, it is necessary to track down and maintain the peak signal, and measure the attenuation of the signal on the transmission medium. Voltage-to-peak detectors are also required for ratio converters (a / d converters), maximum approximate decoding systems (maxi_ plus heartbeat, and pulse signal detection circuits to detect nuclear radiation). Prior art The simplest method of the voltage peak detector is to make the input voltage b tiger pass, diode, and charge the capacitor in order to obtain the value of the input voltage waveform. As shown in the figure-when the input voltage v⑽ is greater than When the voltage of the capacitor c, the diode = charging effect, until the input voltage V (IN) reaches its maximum value, the capacitor C can no longer, "charge" at this time the output voltage ^ _ means the peak value of the input power. Between the positive terminal and the diode = diode D, this circuit cannot accurately detect the input electric truth. In other words, the error between the output sugar _ and the peak value of the input Xia Liao is 2 Γ and the error of the conduction sugar d. That is, Qing ⑽O) = MM (V (IN))-Vd, which is the transient state of 0 · To analyze the simulation results). In terms of application, in order to accurately detect the peak voltage of the input, the above-mentioned diode diode 1245905, so far, many precision electrical value detection techniques have been proposed, such as in the US patent case No. As disclosed in US5, Xie 939, Brush 2746, 55, 7, t96f45, _, 238 and 6462861, and the Republic of China Patent No. 8220146, all of these technologies can accurately detect the ridge value of the input signal. In these electrical peak detectors, more than one operational amplifier is used, so there are still missing circuits, complex D structures, and large chip areas, which are not conducive to the requirements of integrated circuits. Recently, money The technique of mega-amplifying the operation of the peak-chain detector is described in, for example, the Republic of China Patent No. 9_722: "Voltage Peak Detector" (the main table is shown in Figure 3) and 9_88: "Detection of electrical value detection with dual charging paths:" C, the main representative is shown in the detailed diagram) shouted, these technologies are to replace the operational amplifier with a circuit composed of a difference and a current mirror Because it does not make To transport 'includes a simple circuit structure, regardless of a small wafer area and facilitate the miniaturization of the device # multiple effects. However, due to these technologies, the difference is eliminated. A || It has a level of ^ ^ ^ which is higher than that of households ^ 8 41. In addition, '6 Xuan and other technologies have not set an output stage in the peak detector. The peak voltage of the input voltage is external circuit. It can effectively keep the input peak electric movement and reduce, even suffer damage. In addition, these technologies also do not take into account the ^ voltage (0verSh⑽ abbreviated ㈣ effect), familiar with the differential amplifier t white can be converted to the characteristic curve of the differential amplifier (v〇ltage t 譲 fer \ 'to make the differential amplifier — The driving transistor of the square is in the state of passing through the differential driving ^ Lei Ri_Dianji ¥, and at least-the excess voltage VGS is applied between the input terminal of the square driving transistor and the other terminal. Voltage difference. Note that this super two error 'so, these technologies have been proposed in terms of accuracy to take into account the above-mentioned missing precision electrical value detector, l ^ 92120739 m:. ④ Jin Bu)' Although § brother The circuit shown in the fifth figure has proposed a kind of money for the electric peak detector. However, the circuit still has room for improvement. For example, the circuit consumes too much chip area due to the use of resistors above 1245905 in the output stage. And _ the circuit is easy to call, which leads to the problem of reducing the accuracy (please refer to the records in the 24th to 28th lines of the 9th and 39th patent claim day), so there is still room for improvement. , The main purpose of Shuming is Ji Longxi Longfeng Detection 2: The chip has a small area and high integration, and has both a simple circuit structure and j-effects. It also has an output stage to effectively prevent the input peak voltage maintained by external electrical actions from being damaged. Page The main purpose of taking this problem is to propose a voltage peak detection of a quasi-compensated metal oxide semiconductor structure, which can effectively eliminate the excess voltage effect of the differential amplifier. [Summary of the invention] The complementary metal-oxide-half (⑽s) voltage peak detector proposed by the present invention is-differential amplification Γ two charging transistor 2,-capacitor C,-output stage 3 and-current mirror circuit The eight and five differential amplifiers of Group 4 are designed with an asymmetric structure, that is, using only a single-side negative transistor, and the load transistor and the charging transistor are formed together-a current mirror, so it can be compared The traditional precision voltage exaggeration detector (that is, the Republic of China Patent No. 9_722 and the Cong Cong patent = the disclosed voltage peak detection is less than two dirty transistors. In addition, the present invention provides a power and peak detection The device is provided with an output stage, and the output stage is not used with a resistance of more than 50MΩ is E. This not only has a high integration degree, but also can prevent the maintained input and output voltage from being caused by the external circuit's capture action. The damage caused, the same day it seems to have the function of accurately adjusting and outputting the maintained peak voltage. In addition, the present invention is also effective for the excessive voltage effect of the noise difference reducer. [Embodiment] According to the above purpose, the present invention proposes a novel complementary metal-oxide-half (CM0s) voltage peak. The detector is shown in the sixth figure, which is charged by a differential amplifier. Crystal 2, an electric MC,-an output stage 3 and-a current mirror circuit 4, the differential amplifier 丄 is designed using asymmetrical circuit configuration ' 2 and the pM0s transistor Mρι ', among which the Lake M0S transistor_! And Li 2 series are used as drivers, and the pM0s 1245905 transistor MP1 is used as a load transistor. The pole (purchase) between the MOS transistor transistor and _2 receives the input voltage signal V⑽ and the voltage signal v⑹ on the capacitor, respectively. The source (simplifiedly connected together and connected to the current mirror circuit 4), and its drain The poles are respectively connected to the load transistor fertilizer and the power supply voltage Vdd. Please refer to the sixth figure again, the load transistor MP1 and the charging transistor Mp2 together form a current mirror ', and the source of the PM0S transistor MP1 and MP2 Both are connected to the power supply voltage leg, and the gate is connected to the ground, and connected to the MOSFET of the MOS transistor RY1, and the gate of the pMQS transistor Μρι is connected to the electrode to form „Current mirror; Moreover, the pole of pMQS transistor 2 is connected to the-terminal of capacitor IIG, and the other _ terminal of capacitor G is grounded: In addition, output stage 3 is composed of -NM0S transistor surface 3 , And is connected between the power supply voltage and the output terminal. In addition, the current mirror circuit 4 is composed of NMOS transistor N4, MN5, MN6, and-resistor R. The current mirror circuit 4 is used to generate a reference Current iR, and passes the reference current & through the wake-up transistor. 5 The current mirror provides the current of the reference current 比率 mirroring ratio Ib to the differential amplifier 1, and after the current mirror mirroring of the same sun god lake electric crystal and _ domain, provides-and the reference current 1 into a mirror The current of the emission ratio is still 10 to the output stage 3. For the convenience of explanation, the following derivation process describes the simplest model in the metal-oxide semiconductor transistor # 〇rCAD Pspice, and does not consider the channel length modulation (Such as _} modulation) effect. However, in the subsequent simulation verification, all transistor parameters (including channel length modulation effect) in the cadmium are considered. First, the reference current IR and current are derived. Through the current 差 of the differential contact A || 1 and the current Ιουτ of the output stage 3, it can be known from the current mirror circuit 4 shown in the sixth figure that the reference current Ir is equal to lR = (Vdd-VGS5) / R ⑴, where VGS5 is The gate-source voltage VGS5 of NM0S transistor Li 5 can be obtained from the following equation: (Vdd-VGS5) / R = [KP.WN5 / (2.LN5)] · (VGS5 -Vtns) 2 (2) Equation ( 2) WNS and LN5 respectively represent the effective channel width and effective channel length of the mm0 transistor Li 5 'KP represents G rGAD Pspiee-metal oxide semi-transistor model parameters, and Vtn5 represents the threshold voltage (zen) voltage of the zero-base bias of the _S transistor MN5. Furthermore, as shown in the sixth figure The current mirror circuit 4 shown in conjunction with the working principle of the current mirror circuit can be obtained by not obtaining the current IB flowing through the differential amplifier 1 and the current I 〇u τ, 1245905 flowing through the output stage 3. The result is
Ib= Ir · (Wn4/LN4) /(WN5/LN5) ⑶ Ι〇υτ= Ir · (Wn6/LN6) /(WN5/LN5) ⑷ 其中，Ww和LW分別表示該腿〇s電晶體腿之有效通道寬度及有效通道長 度，而WN0和LN6則分別表示該麵0S電晶體丽6之有效通道寬度及有效 電流Id (MNl) (5) 接著，當輸入電壓V(IN)大於電容器上之電壓y(c)時 會大於Id (MN2)，且Ib = Ir · (Wn4 / LN4) / (WN5 / LN5) ⑶ Ι〇υτ = Ir · (Wn6 / LN6) / (WN5 / LN5) ⑷ Among them, Ww and LW respectively indicate that the leg of the transistor is effective Channel width and effective channel length, and WN0 and LN6 represent the effective channel width and effective current Id (MNl) (0) of the 0S transistor Li 6 on the face. Then, when the input voltage V (IN) is greater than the voltage y on the capacitor (c) is greater than Id (MN2), and
Id (MN1) + Id (MN2) = IBId (MN1) + Id (MN2) = IB
Id (MNl) = -Id (MP1) 由於PMOS電晶體MP1及MP2係構成一電流鏡，因此 -Id (MP1) = -Id (MP2) ，故可對電容器C進行充電動作。 當電容器上之電壓V(C)等於輸入電壓v⑽之峰值電壓時 Id (MNl) - Id (MN2) =IB / 2 ，此時仍會對電容器C進行充電動作。 (6) ⑺ 電流 ⑻ 依據差動放大ϋ之電轉換特性曲線得知：電容紅之電顯c (OverShoot Voltagefi#Vos) 能將NMQSf 迫域止賴，侧⑽㉟體麵城止狀態時 電電晶體即停止對電容器c進行充電作用，此時電容器上之電壓v(c)為 V (C) — Vpeak + V〇S 、、 (9) 由於此日守的NM0S電晶體簡2係工作於飽和區，而腦s電晶體腿恰 和區進入截止區，因此，可由下列關係方程式求出VGS2及VGS1 :Id (MNl) = -Id (MP1) Since the PMOS transistors MP1 and MP2 form a current mirror, -Id (MP1) = -Id (MP2), so the capacitor C can be charged. When the voltage V (C) on the capacitor is equal to the peak voltage of the input voltage v⑽, Id (MNl)-Id (MN2) = IB / 2, the capacitor C will still be charged at this time. (6) ⑺ Current⑻ According to the electrical conversion characteristic curve of the differential amplifier 知, we know that the capacitor red electric display c (OverShoot Voltagefi # Vos) can force the NMQSf to the limit, and the transistor is in the state of decent city stop. Stop charging capacitor c. At this time, the voltage v (c) on the capacitor is V (C) — Vpeak + V0S, (9) Since the NMOS transistor transistor 2 that works today is working in the saturation region, The brain s transistor's leg is just in the region of the cut-off region, so VGS2 and VGS1 can be obtained from the following relationship equation:
Id (MN2) = IBId (MN2) = IB
Id (MNl) - 〇 故超量電壓Vos等於 n (10) (11) 其中Id (MNl)-〇 so the excess voltage Vos is equal to n (10) (11) where
Vos- VGS2 - VGS1 = [2 · Ιβ · Ln2/(kp · Wn2)]1/2 (⑵ ，WN2和Lnz分別表示_s電晶麵2之有效通道寬度及有效通道長度 1245905 有關超量電壓Vos之推導可參考Kenneth R. Laker及Willy M.C. Sansen 合著由McGRAW-Hill 出版「Design of analog integrated circuits and systems」一書中之第357至375頁。 之後，當輸入電壓V (IN)由峰值電壓Vpeak往下掉時，因nm〇S電晶體丽1 已進入截止狀態，因此電流 -Id (MP1) = -Id (MP2) = 0 (13) 所以充電電晶體不會再對電容器C進行充電動作，因此電容器上之電壓八〇 仍會固定維持在方程式（9)之電壓。 請再參考第六圖，電容器上之電壓v⑹扣抵一個NM〇s電晶體丽3之問源 極電壓VGS3後，即成為電壓峰值檢知器之輸出電壓ν(〇υτ)，亦即 V(OUT) - V(C) - VGS3 (14) 於此，為了易於設計以及能在大輸入電壓^⑽)範圍内，均能精確地檢 測出輸入電壓V(IN)信號之峰值電壓，於是可將輸出級3中之NM0S電晶體丽3 之基底與源極連接在一起，俾藉此以消除該麵％電晶體丽3之基底效應 (body effect)，此時方程式（14)可改寫為 V(OUT) = V(C) - Vtn3 - [2 · Ιουτ · lN3/(KP · WN3)]1/2 (15) 其中，WN*LN分別表示該NMOS電晶體丽3之有效通道寬度及有效通道長度， 而Vim則表示該NM0S電晶體MN3之零基底偏壓之臨限電壓。 卜、最後，由方程式（9)、（丨2)、（14)及（15)得知，欲使輸出電壓ν(〇υτ) 等於輸入峰值電壓VPeak，則須 (16)Vos- VGS2-VGS1 = [2 · Ιβ · Ln2 / (kp · Wn2)] 1/2 (⑵, WN2 and Lnz respectively represent the effective channel width and effective channel length of _s transistor 2 and the effective channel length is 1245905. The derivation can refer to pages 357 to 375 in the book "Design of analog integrated circuits and systems" published by McGRAW-Hill, co-authored by Kenneth R. Laker and Willy MC Sansen. Then, when the input voltage V (IN) is changed from the peak voltage When Vpeak goes down, because the nm0S transistor Li1 has entered the cut-off state, the current -Id (MP1) = -Id (MP2) = 0 (13) So the charging transistor will not charge the capacitor C anymore. Therefore, the voltage 80 on the capacitor will still be fixed and maintained at the voltage of equation (9). Please refer to the sixth figure again. After the voltage v⑹ on the capacitor is deducted from the source voltage VGS3 of an NMOS transistor 3, That is the output voltage ν (〇υτ) of the voltage peak detector, that is, V (OUT)-V (C)-VGS3 (14) Here, for ease of design and in the range of large input voltage ^ ⑽), Can accurately detect the peak voltage of the input voltage V (IN) signal, so the output stage 3 can be The base of NM0S transistor Li 3 is connected to the source, so as to eliminate the body effect of the transistor% Li 3 of this surface. At this time, equation (14) can be rewritten as V (OUT) = V ( C)-Vtn3-[2 · Ιουτ · lN3 / (KP · WN3)] 1/2 (15) where WN * LN represents the effective channel width and effective channel length of the NMOS transistor Li 3 respectively, and Vim indicates Threshold voltage of zero base bias of the NMOS transistor MN3. Finally, according to equations (9), (2), (14), and (15), if the output voltage ν (〇υτ) is equal to the input peak voltage VPeak, then (16)
Vos = VGS3 亦即 [2 · IB · LN2/(KP · WN2)]1/2 = Vtns + [2 · Ι〇υτ · LN3/(KP · WN3)]1/2 藉此即可輕易地設計出電壓峰值檢知器。 （17) #本發明所提出之電壓峰值檢知器之〇rCADpSpice暫態分析模擬結果，如 第七圖所不’由該模擬結果可註實，本發明所提出之電壓峰值檢知器可精 確且f效地檢知輸入電壓波形之峰值電壓。第七圖係以丨㈣丨3模型且使用 〇· 25微米CMOS製程錄加以模擬（細〇s電晶體和·電晶體之零基底偏 1245905 壓臨限電壓值Vtq分別為-0· 5V和0· 5V)，其中，PM0S電晶體MP卜MP2之通道 寬長比均為（W/LM2 · 0·25μιη/0·25μιη)，NM0S電晶體MN1 ' MN4和丽5之通 道寬長比均為（1/：〇=(0.25以111/0.25|11111)，腿08電晶體丽2之通道寬長比為 (W/L)-(4. 5 · 0. 25μιη/0. 25μιη) ，NM0S 電晶體 ΜΝ3 之通道寬長比為 (W/L)=(12· 5 · 0· 25μπι/0· 25μπι)，M)S 電晶體 MN6 之通道寬長比為 (W/LH〇.25pm/(10 · 0·25μιη))，電阻器R之電阻值為180K歐姆，至於電容 夯C之電容值則為3pF。 本發明之電壓峰值檢知器在使用時可於電容器C兩端並聯連接一 開關，該開關係用以提供一放電路徑，以便將電容器上所儲存之電荷放電， 俾利於下次輸入電壓信號之峰值檢測。 【發明功效】 本發明所提出之電壓峰值檢知器，具有如下功效： (1)高集積度：由於本發明所提出之電壓峰值檢知器僅使用了w@PM〇s電晶 體、6個_S電晶體、1個電阻器以及HgJ電容器，且於輸出級中並未使 用到5曰〇ΜΩ社之修n，因此不但電路架構繼、簡單、使用的電晶 體數畺 >、並且因不品使用運异放大器及未使用到5〇船以上之電阻 器，因而也具有較高之集積度； ⑵高精確度：嫉本㈣所翻之賴峰錄可纽消除差動放大器 之超置電壓效應，因此可有效提轉值檢知器之精確度； ⑶輸出糖(_不會因外部電路之擷取而有 之電壓峰值檢知器設置有輪出级，_叮女# μ 个知73敝出 電壓不朗外«狀 圍内 π ^⑽式或⑼紅可能賴化均未麟 圍。因此，所細I技術蝴之改變都包括在本發明之申請專利範” 1245905 【圖式簡單說明】 第-圖係顯示第-先前技藝中輕峰值檢知器之電路圖； 丨號）中之電壓峰 第三圖係顯示第二切技藝(即中華民國專利案第贿 值檢知器之電路圖； 、 丨號）中之電壓峰 第四圖係顯示第三先前技藝（即中華民國專利案咖孙 值檢知器之電路圖； 、 第五==第四先前技藝(即中錢國專利案·丨助9號 值檢知态之電路圖； 手 第六圖係顯示本發明較佳實施例之電壓峰值檢知· 第七圖明電鮮值檢知器之輸入電壓韻、二上之電壓信 號及輸出電壓信號之暫態分析時序圖。 [元件符號說明] 1 差動放大器 3 輸出級 V(IN)輸入電壓信號 V(OUT)輸出電壓信號 C 電容器Vos = VGS3, which is [2 · IB · LN2 / (KP · WN2)] 1/2 = Vtns + [2 · Ι〇υτ · LN3 / (KP · WN3)] 1/2 so that you can easily design Voltage peak detector. (17) #The rCADpSpice transient analysis simulation result of the voltage peak detector proposed by the present invention, as shown in the seventh figure, can be confirmed by the simulation result, and the voltage peak detector proposed by the present invention can be accurate And f effectively detects the peak voltage of the input voltage waveform. The seventh diagram is modeled using the 丨 ㈣ 丨 3 model and using a 25 μm CMOS process record (fine zero-s transistor and zero-base bias of the transistor 1245905. The voltage threshold voltage Vtq is -0.5 V and 0, respectively. · 5V), where the channel width and length ratio of PM0S transistor MP and MP2 are all (W / LM2 · 0 · 25μιη / 0 · 25μιη), and the channel width and length ratio of NM0S transistor MN1 'MN4 and Li5 are both ( 1 /: 〇 = (0.25 to 111 / 0.25 | 11111), the channel width-length ratio of leg 08 transistor Li 2 is (W / L)-(4.5.0.25 μm / 0. 25 μιη), NM0S transistor The channel width-length ratio of MN3 is (W / L) = (12 · 5 · 0 · 25μπι / 0 · 25μπι), and the channel width-to-length ratio of M) S transistor MN6 is (W / LH0.25.25pm / (10 · 0 · 25μιη)), the resistance value of the resistor R is 180K ohms, and the capacitance value of the capacitor C is 3pF. When the voltage peak detector of the present invention is in use, a switch can be connected in parallel at both ends of the capacitor C. The open relationship is used to provide a discharge path to discharge the charge stored in the capacitor, which is beneficial to the next input voltage signal. Peak detection. [Effects of the invention] The voltage peak detector proposed by the present invention has the following effects: (1) High integration: Because the voltage peak detector proposed by the present invention uses only w @ PM〇s transistor, 6 _S transistor, 1 resistor, and HgJ capacitor, and the 5th omegaΩ company's repair n is not used in the output stage. Therefore, not only the circuit architecture is continuous, simple, the number of transistors used> >, and The use of different amplifiers and resistors that have not been used for more than 50 ships, so it also has a high degree of integration; ⑵High accuracy: Lai Fenglu, which is turned over by this book, can eliminate the over-position of the differential amplifier Voltage effect, so it can effectively improve the accuracy of the value detector; ⑶ output sugar (_ will not be due to the capture of external circuits, the voltage peak detector is equipped with a wheel-out stage, _ 叮 女 # μ 知73 no voltage spacious Long outer «shape around π ^ ⑽ formula ⑼ red or may rely neither of Lin circumference. Thus, I fine art of the butterfly changes are included in the patent application of the present invention is simple and Fan" 1245905 [FIG formula Description]-The figure shows the circuit of the light peak detector in the prior art Figure; No. 丨) The third figure of the voltage peak shows the second cut technique (ie, the circuit diagram of the bribe value detector of the Republic of China patent case; No. 丨) The fourth figure shows the third prior technique (That is, the circuit diagram of the Sun value detector of the Republic of China patent case;, the fifth == the fourth prior art (that is, the circuit diagram of the Zhongqian patent case, the No. 9 value detection state; the sixth diagram of the hand shows this The voltage peak detection of the preferred embodiment of the invention. The seventh diagram shows the timing diagram of the transient analysis of the input voltage rhyme, the voltage signal on the second and the output voltage signal of the electrical fresh value detector. [Element Symbol Description] 1 Differential Amplifier 3 output stage V (IN) input voltage signal V (OUT) output voltage signal C capacitor
Ib流過差動放大器之電流 Ir參考電流 MP1第一 PM0S電晶體 MN1第一 NM0S電晶體 MN3第三NM0S電晶體 MN5第五NM0S電晶體 2 充電電晶體 4 電流鏡電路 V(C) 電容器上之電壓信號 Vdd 電源供應電壓 D 二極體 I out 流過輪出級之電流 R 電阻器 MP2 第二PM0S電晶體 MN2 第二NM0S電晶體 MN4 第四NM0S電晶體 MN6 第六NM0S電晶體 12Ib Current flowing through the differential amplifier Ir Reference current MP1 First PM0S transistor MN1 First NM0S transistor MN3 Third NM0S transistor MN5 Fifth NM0S transistor 2 Charging transistor 4 Current mirror circuit V (C) on the capacitor Voltage signal Vdd Power supply voltage D Diode I out Current flowing through the wheel output stage R resistor MP2 second PM0S transistor MN2 second NM0S transistor MN4 fourth NM0S transistor MN6 sixth sixth NM0S transistor 12