CN101788598A - Voltage peak detection circuit and operating method thereof - Google Patents
Voltage peak detection circuit and operating method thereof Download PDFInfo
- Publication number
- CN101788598A CN101788598A CN200910228740A CN200910228740A CN101788598A CN 101788598 A CN101788598 A CN 101788598A CN 200910228740 A CN200910228740 A CN 200910228740A CN 200910228740 A CN200910228740 A CN 200910228740A CN 101788598 A CN101788598 A CN 101788598A
- Authority
- CN
- China
- Prior art keywords
- output
- source
- amplifying unit
- terminal
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
The invention relates to a voltage peak detection circuit, comprising a differential amplifying unit, a common-source amplifying unit and a source following unit; and the operating method thereof includes signal acquisition, signal comparison, signal amplification, signal source following output, peak voltage following and recording. The invention has the advantages that: (1) peak of high speed voltage signal can be detected; (2) voltage detuning of circuit is reduced; (3) circuit structure is simple, no extra compensation is required, and practicability is strong.
Description
(1) technical field:
The present invention relates to a kind of voltage detecting circuit and method of work thereof, the especially a kind of voltage peak detection circuit and method of work thereof that can detect high speed voltage signal peak value.
(2) background technology:
In the voltage peak detection system, need the floating voltage signal, catch the peak value of voltage signal, and it is preserved, offer subsequent process circuit.The detection speed of voltage peak detection circuit has directly determined the top speed of the signal of handling, want to catch the peak value of high speed signal, just need voltage peak detection circuit at a high speed, general circuit can produce than mistake when detecting high speed signal, need significantly improve power consumption usually and come raising speed.
(3) summary of the invention:
The objective of the invention is to design a kind of voltage peak detection circuit and method of work thereof, it can overcome the deficiencies in the prior art, on the basis that does not increase power consumption and circuit complexity, has improved the detection speed of voltage peak.
Technical scheme of the present invention: a kind of voltage peak detection circuit comprises that input signal Vsig terminal, supply voltage vdd terminal, voltage peak detect output Vpeak terminal, is characterized in that it comprises that difference amplifying unit, common source amplifying unit and source are with the unit; Wherein, the input end of said difference amplifying unit connects input signal Vsig terminal, voltage peak detects output Vpeak terminal, supply voltage vdd terminal and ground, and its output terminal connects the input end of common source amplifying unit; The input end of said common source amplifying unit connects supply voltage vdd terminal and ground, and its output terminal connects the input end of source with the unit; Said source connects supply voltage vdd terminal and ground with the input end of unit, and its output terminal connects voltage peak and detects output Vpeak terminal.
Above-mentioned said difference amplifying unit manages M1, PMOS pipe M2, NMOS pipe M3, NMOS pipe M4 by PMOS and current sink I1 constitutes; Wherein, the grid of said PMOS pipe M1 is connected with the drain electrode of the grid of PMOS pipe M2, PMOS pipe M2 and the drain electrode of NMOS pipe M4, its source electrode is connected supply voltage vdd terminal jointly with the source electrode of PMOS pipe M2, and its drain electrode is connected with the drain electrode of NMOS pipe M3 and the input end of common source amplifying unit; The grid of said NMOS pipe M3 is connected with input signal Vsig terminal, and the source electrode that its source electrode and NMOS manage M4 is connected the input end of current sink I1 jointly; The grid of said NMOS pipe M4 detects output Vpeak terminal with voltage peak and is connected, and its drain electrode is connected with the grid of PMOS pipe M1, the drain electrode of PMOS pipe M2; The output head grounding of said current sink I1.
Above-mentioned said common source amplifying unit is made of PMOS pipe M5 and resistance R 1; Wherein, said resistance R 1 one end ground connection, the other end is connected with the drain electrode of PMOS pipe M5; The grid of said PMOS pipe M5 is connected with the drain electrode of PMOS pipe M1 and the drain electrode of NMOS pipe M3, and its source electrode is connected with supply voltage vdd terminal, and its drain electrode also is connected with the input end of source with the unit.
Above-mentioned said source is made of NMOS pipe M6 and capacitor C hold with the unit; Wherein, said capacitor C hold one end ground connection, the other end is connected with the source electrode of NMOS pipe M6, grid and the voltage peak detection output Vpeak terminal of NMOS pipe M4; The grid of said NMOS pipe M6 is connected with the drain electrode of PMOS pipe M5, and its drain electrode is connected with supply voltage VDD.
A kind of voltage peak detection circuit is characterized in that it can be applied to voltage peak detection circuit, especially the high speed signal voltage peak detection circuit.
A kind of method of work of voltage peak detection circuit is characterized in that it is to be made of following steps:
1. input signal terminal Vsig gathers applied signal voltage to be detected, carry out the difference amplification with NMOS pipe M3, the NMOS pipe M4 of voltage peak detection output Vpeak process difference amplifying unit, PMOS pipe M1 and PMOS pipe M2 constitute current mirror load, and the double-end signal after difference is amplified becomes single-ended signal output; Current sink I1 provides bias current for the difference amplifying unit;
2. the common source amplifying unit carries out second level amplification with the output signal of difference amplifying unit, and this level adopts common source structure for amplifying, with the load of resistance R 1 as the common source amplification;
3. the source is carried out with output with the unit with the output signal of common source amplifying unit in the source, improves the peak-value-holding function that output driving force and realization keep rising, and capacitor C hold keeps output voltage V peak;
4. detect output Vpeak when high than voltage peak as input signal Vsig, the output of difference amplifying unit reduces, and causes the output of common source amplifying unit to raise, and Vpeak is drawn high with the unit through the source then, thereby realizes that peak value follows; When input signal Vsig is lower than Vpeak, the output of difference amplifying unit raises, cause the output of common source amplifying unit to reduce, the NMOS pipe M6 grid of source with the unit dragged down, this level does not have electric current to flow through, so Vpeak remains unchanged under the effect of capacitor C hold, so just realized the peak value maintenance, the Vpeak final entry crest voltage of Vsig.
Superiority of the present invention: 1. both realized following fast of signal with the unit, and realized that again the peak value of signal kept, and can detect the peak value of high speed voltage signal by the source; 2. amplify with common source by difference and amplify the secondary amplification, improved the open-loop gain of circuit, reduced the voltage imbalance of circuit; 3. the common source amplifier stage adopts resistance as load, has reduced the output impedance of this level, has raised the frequency of inferior limit, has expanded circuit bandwidth, thereby has improved speed; 4. circuit constitutes simply, need not extra compensation, and is practical.
(4) description of drawings:
Fig. 1 is that (wherein, Fig. 1-a is a common voltage peak detection circuit structural drawing to common voltage peak detection circuit figure of the prior art; Fig. 1-b is the result curve of common voltage peak detection circuit when input 100KHz signal).
(wherein, Fig. 2-a is a circuit structure diagram to Fig. 2 for the circuit diagram of the related a kind of voltage peak detection circuit of the present invention; Fig. 2-b is the result curve of circuit of the present invention when importing the 100KHz signal).
(5) embodiment
Embodiment: a kind of voltage peak detection circuit (is seen Fig. 2-a), is comprised that input signal Vsig terminal, supply voltage vdd terminal, voltage peak detect output Vpeak terminal, is characterized in that it comprises that difference amplifying unit, common source amplifying unit and source are with the unit; Wherein, the input end of said difference amplifying unit connects input signal Vsig terminal, voltage peak detects output Vpeak terminal, supply voltage vdd terminal and ground, and its output terminal connects the input end of common source amplifying unit; The input end of said common source amplifying unit connects supply voltage vdd terminal and ground, and its output terminal connects the input end of source with the unit; Said source connects supply voltage vdd terminal and ground with the input end of unit, and its output terminal connects voltage peak and detects output Vpeak terminal.
Above-mentioned said difference amplifying unit (sees that Fig. 2-a) is made of PMOS pipe M1, PMOS pipe M2, NMOS pipe M3, NMOS pipe M4 and current sink I1; Wherein, the grid of said PMOS pipe M1 is connected with the drain electrode of the grid of PMOS pipe M2, PMOS pipe M2 and the drain electrode of NMOS pipe M4, its source electrode is connected supply voltage vdd terminal jointly with the source electrode of PMOS pipe M2, and its drain electrode is connected with the drain electrode of NMOS pipe M3 and the input end of common source amplifying unit; The grid of said NMOS pipe M3 is connected with input signal Vsig terminal, and the source electrode that its source electrode and NMOS manage M4 is connected the input end of current sink I1 jointly; The grid of said NMOS pipe M4 detects output Vpeak terminal with voltage peak and is connected, and its drain electrode is connected with the grid of PMOS pipe M1, the drain electrode of PMOS pipe M2; The output head grounding of said current sink I1.
Above-mentioned said common source amplifying unit (sees that Fig. 2-a) is made of PMOS pipe M5 and resistance R 1; Wherein, said resistance R 1 one end ground connection, the other end is connected with the drain electrode of PMOS pipe M5; The grid of said PMOS pipe M5 is connected with the drain electrode of PMOS pipe M1 and the drain electrode of NMOS pipe M3, and its source electrode is connected with supply voltage vdd terminal, and its drain electrode also is connected with the input end of source with the unit.
Above-mentioned said source (sees that Fig. 2-a) is made of NMOS pipe M6 and capacitor C hold with the unit; Wherein, said capacitor C hold one end ground connection, the other end is connected with the source electrode of NMOS pipe M6, grid and the voltage peak detection output Vpeak terminal of NMOS pipe M4; The grid of said NMOS pipe M6 is connected with the drain electrode of PMOS pipe M5, and its drain electrode is connected with supply voltage VDD.
A kind of voltage peak detection circuit is characterized in that it can be applied to the high speed signal voltage peak detection circuit.
A kind of method of work of voltage peak detection circuit is characterized in that it is to be made of following steps:
1. input signal terminal Vsig gathers applied signal voltage to be detected, carry out the difference amplification with NMOS pipe M3, the NMOS pipe M4 of voltage peak detection output Vpeak process difference amplifying unit, PMOS pipe M1 and PMOS pipe M2 constitute current mirror load, and the double-end signal after difference is amplified becomes single-ended signal output; Current sink I1 provides bias current for the difference amplifying unit;
2. the common source amplifying unit carries out second level amplification with the output signal of difference amplifying unit, and this level adopts common source structure for amplifying, with the load of resistance R 1 as the common source amplification;
3. the source is carried out with output with the unit with the output signal of common source amplifying unit in the source, improves the peak-value-holding function that output driving force and realization keep rising, and capacitor C hold keeps output voltage V peak;
4. detect output Vpeak when high than voltage peak as input signal Vsig, the output of difference amplifying unit reduces, and causes the output of common source amplifying unit to raise, and Vpeak is drawn high with the unit through the source then, thereby realizes that peak value follows; When input signal Vsig is lower than Vpeak, the output of difference amplifying unit raises, cause the output of common source amplifying unit to reduce, the NMOS pipe M6 grid of source with the unit dragged down, this level does not have electric current to flow through, so Vpeak remains unchanged under the effect of capacitor C hold, so just realized the peak value maintenance, the Vpeak final entry crest voltage of Vsig.
Below with reference to accompanying drawings the present invention is described in further details:
By Fig. 1-b " result curve of common voltage peak detection circuit when importing the 100KHz signal " as can be seen, when input signal Vsig raises, voltage peak detects output Vpeak and follows stablely inadequately, distortion is bigger, and the Vsig peak value is 1V, and Vpeak finally remains on 1.05V, and big overshoot is arranged.
And after using circuit of the present invention, result curve is shown in Fig. 2-b, and Vpeak tightly follows Vsig, and distortion is very little, and finally remains on 1.0V, does not have overshoot substantially.
Circuit of the present invention is applicable to any voltage peak detection circuit.
Claims (6)
1. a voltage peak detection circuit comprises that input signal Vsig terminal, supply voltage vdd terminal, voltage peak detect output Vpeak terminal, is characterized in that it comprises that difference amplifying unit, common source amplifying unit and source are with the unit; Wherein, the input end of said difference amplifying unit connects input signal Vsig terminal, voltage peak detects output Vpeak terminal, supply voltage vdd terminal and ground, and its output terminal connects the input end of common source amplifying unit; The input end of said common source amplifying unit connects supply voltage vdd terminal and ground, and its output terminal connects the input end of source with the unit; Said source connects supply voltage vdd terminal and ground with the input end of unit, and its output terminal connects voltage peak and detects output Vpeak terminal.
2. according to a kind of voltage peak detection circuit described in the claim 1, it is characterized in that said difference amplifying unit is managed M1, PMOS pipe M2, NMOS pipe M3, NMOS pipe M4 by PMOS and current sink I1 constitutes; Wherein, the grid of said PMOS pipe M1 is connected with the drain electrode of the grid of PMOS pipe M2, PMOS pipe M2 and the drain electrode of NMOS pipe M4, its source electrode is connected supply voltage vdd terminal jointly with the source electrode of PMOS pipe M2, and its drain electrode is connected with the drain electrode of NMOS pipe M3 and the input end of common source amplifying unit; The grid of said NMOS pipe M3 is connected with input signal Vsig terminal, and the source electrode that its source electrode and NMOS manage M4 is connected the input end of current sink I1 jointly; The grid of said NMOS pipe M4 detects output Vpeak terminal with voltage peak and is connected, and its drain electrode is connected with the grid of PMOS pipe M1, the drain electrode of PMOS pipe M2; The output head grounding of said current sink I1.
3. according to a kind of voltage peak detection circuit described in the claim 1, it is characterized in that said common source amplifying unit is made of PMOS pipe M5 and resistance R 1; Wherein, said resistance R 1 one end ground connection, the other end is connected with the drain electrode of PMOS pipe M5; The grid of said PMOS pipe M5 is connected with the drain electrode of PMOS pipe M1 and the drain electrode of NMOS pipe M3, and its source electrode is connected with supply voltage vdd terminal, and its drain electrode also is connected with the input end of source with the unit.
4. according to a kind of voltage peak detection circuit described in the claim 1, it is characterized in that said source is made of NMOS pipe M6 and capacitor C hold with the unit; Wherein, said capacitor C hold one end ground connection, the other end is connected with the source electrode of NMOS pipe M6, grid and the voltage peak detection output Vpeak terminal of NMOS pipe M4; The grid of said NMOS pipe M6 is connected with the drain electrode of PMOS pipe M5, and its drain electrode is connected with supply voltage VDD.
5. according to a kind of voltage peak detection circuit described in the claim 1, it is characterized in that it can be applied to voltage peak detection circuit, especially the high speed signal voltage peak detection circuit.
6. the method for work of a voltage peak detection circuit is characterized in that it is to be made of following steps:
1. input signal terminal Vsig gathers applied signal voltage to be detected, carry out the difference amplification with NMOS pipe M3, the NMOS pipe M4 of voltage peak detection output Vpeak process difference amplifying unit, PMOS pipe M1 and PMOS pipe M2 constitute current mirror load, and the double-end signal after difference is amplified becomes single-ended signal output; Current sink I1 provides bias current for the difference amplifying unit;
2. the common source amplifying unit carries out second level amplification with the output signal of difference amplifying unit, and this level adopts common source structure for amplifying, with the load of resistance R 1 as the common source amplification;
3. the source is carried out with output with the unit with the output signal of common source amplifying unit in the source, improves the peak-value-holding function that output driving force and realization keep rising, and capacitor C hold keeps output voltage V peak;
4. detect output Vpeak when high than voltage peak as input signal Vsig, the output of difference amplifying unit reduces, and causes the output of common source amplifying unit to raise, and Vpeak is drawn high with the unit through the source then, thereby realizes that peak value follows; When input signal Vsig is lower than Vpeak, the output of difference amplifying unit raises, cause the output of common source amplifying unit to reduce, the NMOS pipe M6 grid of source with the unit dragged down, this level does not have electric current to flow through, so Vpeak remains unchanged under the effect of capacitor C hold, so just realized the peak value maintenance, the Vpeak final entry crest voltage of Vsig.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910228740A CN101788598A (en) | 2009-11-25 | 2009-11-25 | Voltage peak detection circuit and operating method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910228740A CN101788598A (en) | 2009-11-25 | 2009-11-25 | Voltage peak detection circuit and operating method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101788598A true CN101788598A (en) | 2010-07-28 |
Family
ID=42531886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910228740A Pending CN101788598A (en) | 2009-11-25 | 2009-11-25 | Voltage peak detection circuit and operating method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101788598A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102692549A (en) * | 2012-06-18 | 2012-09-26 | 苏州硅智源微电子有限公司 | Peak detection integrated circuit |
| CN103575962A (en) * | 2013-11-07 | 2014-02-12 | 苏州爱科博瑞电源技术有限责任公司 | Passive peak value follower circuit |
| CN104022759A (en) * | 2014-06-13 | 2014-09-03 | 中国兵器工业集团第二一四研究所苏州研发中心 | High precision monolithic integration narrow pulse peak-holding circuit |
| CN104569557A (en) * | 2014-03-26 | 2015-04-29 | 深圳市依崇微电子科技有限公司 | Rail-to-rail peak detection circuit and method |
| CN105652071A (en) * | 2016-02-22 | 2016-06-08 | 深圳市明微电子股份有限公司 | Pulse peak amplitude measuring device and measuring circuit thereof |
| CN106247915A (en) * | 2016-07-07 | 2016-12-21 | 南京航空航天大学 | A kind of PLCD sensor signal conditioning circuit followed based on peak value and method thereof |
| CN106656113A (en) * | 2016-11-24 | 2017-05-10 | 北京无线电测量研究所 | CMOS differential modulation pulse detection circuit and method |
| CN111190044A (en) * | 2020-03-10 | 2020-05-22 | 无锡恒芯微科技有限公司 | Peak detection circuit in self-powered system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61107171A (en) * | 1984-10-31 | 1986-05-26 | Toshiba Corp | Peak detection circuit |
| JPH0194268A (en) * | 1987-10-05 | 1989-04-12 | Nec Corp | Peak holding circuit |
| TWI245905B (en) * | 2004-10-19 | 2005-12-21 | Hsiuping Inst Technology | CMOS peak voltage detector |
| CN1804688A (en) * | 2006-01-20 | 2006-07-19 | 西安西北工业大学科技产业集团公司 | Output buffer circuit for drive voltage in liquid crystal display drive control chip |
| US7525347B1 (en) * | 2006-10-20 | 2009-04-28 | Marvell International Ltd. | Differential peak detector |
-
2009
- 2009-11-25 CN CN200910228740A patent/CN101788598A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61107171A (en) * | 1984-10-31 | 1986-05-26 | Toshiba Corp | Peak detection circuit |
| JPH0194268A (en) * | 1987-10-05 | 1989-04-12 | Nec Corp | Peak holding circuit |
| TWI245905B (en) * | 2004-10-19 | 2005-12-21 | Hsiuping Inst Technology | CMOS peak voltage detector |
| CN1804688A (en) * | 2006-01-20 | 2006-07-19 | 西安西北工业大学科技产业集团公司 | Output buffer circuit for drive voltage in liquid crystal display drive control chip |
| US7525347B1 (en) * | 2006-10-20 | 2009-04-28 | Marvell International Ltd. | Differential peak detector |
Non-Patent Citations (1)
| Title |
|---|
| 与非网: "基本的CMOS模拟电路", 《HTTP://WWW.EEFOCUS.COM/BOOK/08-09/415510070957.HTML》 * |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102692549A (en) * | 2012-06-18 | 2012-09-26 | 苏州硅智源微电子有限公司 | Peak detection integrated circuit |
| CN103575962A (en) * | 2013-11-07 | 2014-02-12 | 苏州爱科博瑞电源技术有限责任公司 | Passive peak value follower circuit |
| CN103575962B (en) * | 2013-11-07 | 2016-03-02 | 苏州爱科博瑞电源技术有限责任公司 | Passive peak value follower circuit |
| CN104569557A (en) * | 2014-03-26 | 2015-04-29 | 深圳市依崇微电子科技有限公司 | Rail-to-rail peak detection circuit and method |
| CN104022759A (en) * | 2014-06-13 | 2014-09-03 | 中国兵器工业集团第二一四研究所苏州研发中心 | High precision monolithic integration narrow pulse peak-holding circuit |
| CN104022759B (en) * | 2014-06-13 | 2016-07-20 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of high-precision single integrated narrow pulse peak holding circuit |
| CN105652071A (en) * | 2016-02-22 | 2016-06-08 | 深圳市明微电子股份有限公司 | Pulse peak amplitude measuring device and measuring circuit thereof |
| CN105652071B (en) * | 2016-02-22 | 2018-12-28 | 深圳市明微电子股份有限公司 | Pulse spike amplitude measurement device and its measuring circuit |
| CN106247915A (en) * | 2016-07-07 | 2016-12-21 | 南京航空航天大学 | A kind of PLCD sensor signal conditioning circuit followed based on peak value and method thereof |
| CN106247915B (en) * | 2016-07-07 | 2018-11-09 | 南京航空航天大学 | A kind of PLCD sensor signal conditioning circuits followed based on peak value and its method |
| CN106656113A (en) * | 2016-11-24 | 2017-05-10 | 北京无线电测量研究所 | CMOS differential modulation pulse detection circuit and method |
| CN111190044A (en) * | 2020-03-10 | 2020-05-22 | 无锡恒芯微科技有限公司 | Peak detection circuit in self-powered system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101788598A (en) | Voltage peak detection circuit and operating method thereof | |
| CN102820857B (en) | Transimpedance amplifier with broad band and high gain | |
| CN101826844B (en) | Power amplifier and signal amplifying method based on power amplifier | |
| TWI509979B (en) | Electronic system, radio frequency power amplifier and method for dynamic adjusting bias point. | |
| CN105591619B (en) | Power amplifier | |
| TW201334399A (en) | Power amplifier | |
| CN101521489A (en) | Amplifier and class AB amplifier | |
| CN109391236B (en) | Signal amplification circuit and millimeter wave signal amplification circuit | |
| CN101789765A (en) | Low power consumption high efficiency operational amplifier circuit and operating method thereof | |
| CN204652315U (en) | A kind of high-power amplifier drive circuit | |
| CN102882476B (en) | High-bandwidth amplifying circuit | |
| CN105429599A (en) | Feed-forward common-gate trans-impedance amplifier circuit with active inductor structure | |
| CN201611365U (en) | Small-signal peak voltage detection circuit | |
| CN112886932A (en) | Power amplifier with linear design | |
| CN201541242U (en) | Operational amplifier circuit for processing photoelectric signal | |
| CN103546106A (en) | Signal amplification circuit | |
| CN105897208B (en) | A kind of noninductive low-noise amplifier of high-gain automatic biasing | |
| CN104333336A (en) | Phase-splitting circuit applied to transimpedance amplification circuit | |
| CN108183691A (en) | Folded-cascode op amp | |
| CN201294487Y (en) | Low noise DC servo circuit | |
| CN204633717U (en) | Power amplifier | |
| CN103391050A (en) | CMOS (Complementary Metal Oxide Semiconductor) low noise amplifying device | |
| CN104901631A (en) | Power amplifying device | |
| CN104901632A (en) | Power amplifier | |
| CN202906839U (en) | High frequency bandwidth amplifier circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20100728 |