TWI243436B - Semiconductor package and fabrication method of the same - Google Patents

Semiconductor package and fabrication method of the same Download PDF

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Publication number
TWI243436B
TWI243436B TW091112957A TW91112957A TWI243436B TW I243436 B TWI243436 B TW I243436B TW 091112957 A TW091112957 A TW 091112957A TW 91112957 A TW91112957 A TW 91112957A TW I243436 B TWI243436 B TW I243436B
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Taiwan
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sub
main
semiconductor package
wafer
chip
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TW091112957A
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English (en)
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Kyei-Chan Park
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Dongbuanam Semiconductor Inc
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    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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1243436 A7 B7 發明説明（） 【發明所屬技術領域】 本發明係關於半導體封裝；更詳t〆 又，係相關包含多 數半導體晶片之多晶片型半導體封裝及复制1 '、衣4方法。 【習知技術】 近年’幾乎所有採用半導體晶片（半暮 ♦體π件）等的電 子系統（譬如：電腦、P C S、行動電話、P D A堂 寻），為滿足使 用者的要求’已逐漸趨向於高機能化及小刮 旦 輕1化，乃屬 現狀。隨可對應此趨勢的設計及製造步驟抽 邱筏術的劃時代發 展’電子系統中所採用的半導體晶片或半翼 导體封裝亦將高 機能化及小型輕量化。 較為眾所週知的半導體晶片封裝技術，士， 有如：多晶片模 組（MCM; Multi Chip Module)封裝、多曰 μ -5- 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) (請先閲讀背面之注意事項再場寫本頁} 、一叮. 經濟部智慧財產局員工消費合作社印製 曰日月封裝（MCP ; multi chip package)等。 該 等 之 中， 多晶片 模 組（MCM)封裝 係 如 第 3 圖 所 示 ) 在 由 薄 膜 式 金屬 薄膜、 陶 瓷或基 板所構 成 的 基 體 300 上 採 用 打 線 接 合、 捲帶式 接 合、覆 晶式接 合 等 方 法 ， 安 裝 多 數 個 半 導 體 晶片 3 0 2，3 0 4，3 0 6後再施行封裝的技術 〇 在 第 3 圖中 ，第一 半 導體晶 片302 係 呈 利 用 打 線 接 合 而 安 裝 的 狀 態， 第二半 導 體晶片 3〇4係 呈 利 用 捲 帶 式 接 合 而 安 裝 的 狀 態， 第三半 導 體晶片 3 06則 呈 利 用 覆 晶 式 接 合 而 安 裝 的 狀 態。 元件編 號 3 08係 指pGA輸出入端子， '3 10 係 指 BGA輸出入端子。 此外’多晶片封裝（MCP)係將二個以上的半導體晶 1243436 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 片，構裝於已限定大小之封裝内的技術，乃屬於採用打線 接合將複數半導體晶片構裝於引線架或基板上的技術。如 第4圖所示，具有利用打線接合在基板4 0 2上搭載複數個 半導體晶片404 a，404b，並採用絲線40 8將各半導體晶片 404a，404b的腳位連接於外接導線40 6上的構造，整體構 造具有埋藏於如環氧模組化合物（e ρ ο X y m ο 1 d i n g compound:EMC)400等之中的幵》態。 但是，如上述的習知多晶片模組封裝及多晶片封裝， 因為係在由薄膜式金屬薄膜、陶瓷或基板所構成的基板 上，採用打線接合、捲帶式接合、覆晶式接合等方法，安 裝必要所需的多數個半導體晶片，或利用打線接合將複數 半導體晶片構裝於基板上，再利用環氧模組化合物進行埋 藏構造的特性，因此在小型輕量化上便有極限限制。 經濟部智慧財產局員工消費合作社印製 此外，因為習知封裝具有採用絲線等將半導體晶片腳 位與外接導線予以連結的構造，因此將產生半導體封裝的 品質及可靠性降低的問題（即，電特性降低問題）。特別係 採用 EMC的習知半導體封裝將隨環氧模組化合物（EMC) 所產生α粒子源，而導致半導體封裝可靠性的明顯降低， 且EMC將污染裝置的主動區域，而造成封裝可靠性降低的 問題。 【發明欲解決之課題】 本發明乃為解決上述習知技術問題點者，提供一種可 達小型輕量化，且可提高封裝產品可靠性的半導體封裝及 -6- 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐） 1243436 A7 B7 五、發明説明（） 其製造方法。 【解決課題之手段】 緣是，為達上述目的，本發明其中一態樣係提供一種 半導體封裝，乃在含有相互電連接之複數半導體晶片的半 導體封裝中，具備有：具有引線架或基板的機能，且在外周 緣设有複數主晶片腳位的主半導體晶片，安裝於上述主半 導體晶片上的既定部位處，並在外周緣處設有複數副晶片 腳位之至少一個副半導體晶片；依使上述主晶片腳位及副 晶片腳位裸露出的方式，於埋藏上述副半導體晶片的形 態，形成於上述主半導體晶片上的絕緣層；在上述裸露出 的任意主晶片腳位與副晶片腳位之間，或任意副晶片腳位 與其他副晶片腳位之間予以電連接，並包含有形成於上述 主晶片腳位上的下部阻障層，與形成於上述下部阻障層上 的晶種層，與形成於上述晶種層上的金屬層之複數金屬圖 案；以及形成於複數金屬圖案上既定部分上的複數焊接端。 再者，本發明之另一態樣，係提供一種半導體封裝之 製造方法，乃製造含有相互電連接之複數半導體晶片的半 導體封裝之方法；具備有：在具有引線架或基板的機能，且 於外周緣設有複數主晶片腳位的主半導體晶片上之既定部 分處，塗布黏著劑的步驟；將在外周緣處設有複數副晶片 腳位之至少一個副半導體晶片，安裝於上述黏著劑上的步 驟；依埋藏上述至少一個副半導體晶片，且使上述主晶片 腳位及副晶片腳位裸露出的形態，而形成於絕緣層的步 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) ------,......-« « , (請先閲讀背面之注意事項再填寫本頁) 、\呑 經濟部智慧財產局員工消費合作社印製 1243436 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 驟；形成將任意主晶片腳位與副晶片腳位之間，或任意副 晶片腳位與其他副晶片腳位之間予以電連接之複數金屬圖 案的步驟；在已形成上述複數金屬圖案的主半導體晶片整 面上’塗布封裝材之後，裸露出所選擇到各金屬圖案上部 其中一部份的步驟；在上述裸露出的金屬圖案上部形成焊 接端的步驟；以及在上述各焊接端上部安裝焊球的步驟。 【發明實施形態】 本發明之上述及其他目的之各項優點，由本說明書中 所描述及所附圖示中應可清楚明瞭。 以下，參照所添附圖示，就本發明較佳實施例進行詳 細說明。 本發明之核心技術主旨，乃不同於採用打線接合、捲 帶式接合、覆晶式接合等而在如金屬薄膜、陶瓷、基板等 基體上，安裝多數個半導體晶片的習知半導體封裝，本發 明係在具引線架或基板功用的單一半導體晶片上，採用金 屬圖案直接安裝複數半導體晶片。藉由此種技術便可輕易 的達成本發明之目的。 經濟部智慧財產局員工消費合作社印製 第1 A圖〜第1 K圖所示係就本發明較佳實施例，製造 半導體封裝的步驟之步驟順序圖。 參照第1 A圖的話，在具引線架或基板功用的單一半 導體晶片（即，沿外周緣設有複數主晶片腳位1 0 2的主半導 體晶片1 〇 〇)上，於既定部位處塗布供安裝副半導體晶片 1 3 0,1 5 0(參照第1C圖）用的黏著劑130a，l 50a。此時，黏著 -8- 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） 1243436 A7 B7 五、發明説明（） 劑1 3 0 a，1 5 0 a最好使用在1 7 5 °C以上的溫度條件，且5分鐘 至3 0分鐘以下硬化的樹脂。具體而言，最好為具優越散熱 性的非導電性聚合物，厚度最好在1 m i丨以下。 其中，主半導體晶片與副半導體晶片可舉例如：微處理 器與記憶體、微處理器與非記憶體、記憶體與非記憶體等。 第1 B圖所示係沿第1 A圖之A - A'線的切剖圖。以下， 配合說明上的方便與促進理解，特別根據沿第1 C圖之B - B | 線切剖圖，說明相關本發明的半導體封裝之製造步驟。 參照第1 C圖，在主半導體晶片1 0 0上既定部位處所塗 布的黏著劑1 30a，1 50a上，分別安裝有具複數副晶片腳位 1 3 2，1 5 2的副半導體晶片1 3 0,1 5 0。其中，副半導體晶片 1 3 0，1 5 0的大小，最好至少小於主半導體晶片1 〇 〇的大小， 且主半導體晶片100厚度最好為5mil至30mil程度，副半 導體晶片130,150厚度最好在lmil以下。 再者，形成於主半導體晶片1 0 0上之主晶片腳位1 0 2 的大小，與形成於副半導體晶片1 3 0，1 5 0上之副晶片腳位 1 3 2,1 5 2的大小，最好在25 " m〜150 " m程度。 其次，依主半導體晶片1 00上完全埋藏副半導體晶片 1 3 0,1 5 0之方式，形成樹脂（即，絕緣層104)，然後施行採 用罩幕圖案的蝕刻步驟，藉由選擇性的去除絕緣層其中一 部份，便如第1 D圖所示，使設置於主半導體晶片1 0 0上 的主晶片腳位1 0 2上部，及設置於副半導體晶片1 3 0上的 副晶片腳位1 3 2上部裸露出。其中，絕緣層1 0 4係可採用 -9- 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） (請先閲讀背面之注意事項再填寫本頁) %. 經濟部智慧財產局員工消費合作社印製 1243436 A7 B7 五、發明説明（） 非導電性聚醯亞胺、聚合物等。 (請先閲讀背面之注意事項再填寫本頁) 其次，藉由施行；賤鍍或蒸鑛（e v a ρ 〇 r a t i ο η)等步驟，便 如第IE圖所示，在主半導體晶片100整面上依序形成由 Ti/W所構成的下部阻障層1 〇6、與由純銅所構成的晶種層 1 0 8。其中，下部阻障層1 〇 6係供防止擴散與增加黏著力用 者。 其次’在主半導體晶片1 0 0指面上塗布光阻之後，利 用施行曝光與顯影步驟，而在主半導體晶片1 0 0上形成光 阻圖案1 1 0，然後如第1 F圖所示，形成具有使主半導體晶 片1 0 0之主晶片腳位1 0 2、副半導體晶片1 3 0，1 5 0之副晶 片腳位 1 3 2、及該等腳位間應依金屬圖案而連結之部分裸 露出的光阻圖案1 1 0。 經濟部智慧財產局員工消費合作社印製 參照第1 G圖所示，藉由施行電鍍步驟，對未形成光 阻圖案11 0的露出區域（即，主半導體晶片1 〇 〇上所設置主 晶片腳位1 02，與副半導體晶片1 3 0上所設置的副晶片腳 位1 3 2，以及連結該等腳位的部分），採用導電性優越的金 屬物質（譬如：銅、金等），電鍍至光阻圖案Π0高度之後， 在經由去光阻（strip)步驟而去除光阻圖案 110，俾在晶種 (s e e d)層 1 0 8上形成將主晶片腳位 1 0 2與副晶片腳位 1 3 2 予以電連結的金屬層1 1 2。 其次，在形成有金屬層112的主半導體晶片100整面 上，塗布光阻之後，藉由施行曝光與顯影步驟，而在主半 導體晶片1 00上形成罩幕圖案1 1 4，俾如第1 Η圖所示，形 -10- 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） 1243436 A7 B7 五、發明説明（） 成僅覆蓋金屬層112上方的罩幕圖案114。 其次’藉由施行以罩幕圖案1 1 4為姓刻罩幕的触刻步 驟，將金屬層1 1 2下方所形成的晶種層1 〇 8與下部阻障層 1 0 6以去除，並選擇性的去除殘餘部分，藉此使絕緣層1 〇 4 裸露出其中一部份，並藉由去光阻步驟而去除罩幕圖案 Π 4，便如第1 I圖所示，形成由下部阻障層1 0 6、晶種層 1 0 8及金屬層1 1 2所構成，且電連接著主晶片腳位1 〇 2與 副晶片腳位1 3 2,1 5 2的金屬圖案1 1 6。依此方式所形成金 屬圖案116的寬度，最好為25〜150/zm，厚度最好為 2000A 〜lOmil。 此外，在本發明較佳實施例中，金屬圖案1 1 6雖由 Ti/W + Cu + Cu或Ti/W + Cu + Au所形成，但是本發明並不僅 限於此實施例，亦可利用 C r + N i + A u、C r + N i + A u + C u、 Cr + Co + Ni + Au、Cr + Co + Ni + Cu + Au等組合而形成金屬圖案 116。 其次，將已形成金屬圖案116的主半導體晶片100整 面，塗布既定厚度（譬如1 0至1 0 0 μ m)的封裝材（譬如··軟焊 光阻Π 8)之後，藉由施行微影步驟與蝕刻步驟等，而如第 1J圖所示，選擇性的裸露出金屬圖案116上方的其中一部 份。 最後，如第1K圖所示，在金屬圖案1 1 6裸露出部分 處形成焊接端1 2 0之後，在經由安裝焊球1 2 2，便完成半 導體封裝之製造。其中，焊接端1 2 0係可為球形或四角形。 -11- 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） (請先閲讀背面之注意事項再填寫本頁) · 經濟部智慧財產局員工消費合作社印製 1243436 A7 B7 五 經濟部智慧財產局員工消費合作社印製 明説 月屬 發當 四 於 時 況 情 的 形 }角 X ο 為 好 最 寸 尺 Ο . 1 m m〜1 . 5 χ 1 . 5 m m程度。當屬於球形的情況時，最好p 0.1mm 〜φ 1.5mm 程度。 所以，經由如上述一連串步驟而所製得本發明之半導 體封裝，便如第2圖所示，具有：在主半導體晶片100上搭 載副半導體晶片1 3 0 , 1 5 0，在形成於主半導體晶片1 〇 〇夕卜 周緣的主晶片腳位1 0 2與形成於副半導體晶片1 3 0，1 5 0外 周緣的副晶片腳位 1 3 2，1 5 2之間，以及副半導體晶片 1 3 0,1 5 0的副晶片腳位1 3 2，1 5 2之間，透過金屬圖案1 1 6、 或金屬圖案116與焊接端120而電連接，然後金屬圖案 1 1 6、焊接端1 2 0及主晶片腳位1 0 2之外，將主半導體晶片 1 00上方部分利用封裝材的軟焊光阻1 1 8予以封裝的構造。 再者，在第2圖中雖未圖示，但是在各焊接端120中， 就由後續步驟而安裝焊球1 2 2。 【發明效果】 如以上說明，依照本發明的話，與採用打線接合、捲 帶接合、覆晶式接合等，而在金屬薄膜、陶瓷、基板等基 體上安裝多數個半導體晶片的習知半導體封裝有所不同， 因為乃在具引線架或基板功用的單一半導體晶片上，採用 金屬圖案直接安裝複數半導體晶片，因此可有效的達成半 導體封裝的小型輕量化與低成本化。因為採用金屬圖案直 接連結半導體晶片之間，因此可更增加半導體封裝之電特 性的可靠性。 -12- (請先閲讀背面之注意事項再填寫本頁) %· 、可· 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 1243436 A7 B7 五、發明説明（） 本發明在不脫逸本發明的技術思想前提下，可進行其 他各種形態。上述實施例，僅不過為瞭解本發明之技術内 容而所舉實施例而已，故不可狹隘的解釋為本發明僅限於 此實施例。在本發明之精神與申請專利範圍内，可施行各 種變化。 【圖式簡單說明】 第1圖之第1 A圖至第1 K圖係本發明較佳實施例之製 造半導體封裝的步驟之步驟順序圖。 第2圖係利用本發明較佳實施例所製得的半導體封裝 平面圖。 第3圖係習知多晶片模組（MCM)封裝剖面圖。 第4圖係習知多晶片封裝（MCP)剖面圖。 (請先閲讀背面之注意事項再填寫本頁) %· 經濟部智慧財產局員工消費合作社印製 【圖號對照說明】 100 主半導體晶片 102 主晶片腳位 104 絕緣層 106 下部阻障層 108 晶種層 110 光阻圖案 112 金屬層 114 罩幕圖案 116 金屬圖案 118 軟焊光阻 120 焊接端 122 焊球 130,150 副半導體晶片 30a, 150a 黏著劑 132,152 副晶片腳位 300 基體 302 第一半導體晶片 -13- 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 1243436 A7 B7 五、發明説明( 304 306 308 3 10 400 402 4〇4a,404b 406 408 第二半導體晶片 第三半導體晶片 PGA輸出入端子 BGA輸出入端子 環氧模組化合物 基板 半導體晶片 外接導線 絲線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -14- 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐)

Claims (1)

1243436 A8 B8 C8 D8 六、申請專利範圍 1. 一種半導體封裝，乃在含有相互電連接之複數半導體晶 片的半導體封裝中，具備有： 具有引線架或基板的機能，且在外周緣設有複數主 晶片腳位的主半導體晶片； 安裝於該主半導體晶片上的既定部位處，並在外周 緣處設有複數副晶片腳位之至少一個副半導體晶片； 依使該主晶片腳位及副晶片腳位裸露出的方式，於 埋藏該副半導體晶片的形態，形成於該主半導體晶片上 的絕緣層； 在該裸露出的任意主晶片腳位與副晶片腳位之 間，或任意副晶片腳位與其他副晶片腳位之間予以電連 接，並包含有形成於該主晶片腳位上的下部阻障層，與 形成於該下部阻障層上的晶種層，與形成於該晶種層上 的金屬層之複數金屬圖案；以及形成於複數金屬圖案上 既定部分上的複數焊接端。 2. 如申請專利範圍第1項所述之半導體封裝，其中該半導 體封裝係更具備有：除該複數焊接端之外，將該主半導體 晶片上部予以封裝的封裝材。 3 .如申請專利範圍第2項所述之半導體封裝，其中該封裝 材係軟焊光阻，厚度在10〜100 V m範圍内。 4. 如申請專利範圍第1項所述之半導體封裝，其中該黏著 劑係非導電性聚合物，厚度在1 m i 1以下。 5. 如申請專利範圍第1項所述之半導體封裝，其中該主晶 -15- 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) %. 、^1· 經濟部智慧財產局員工消費合作社印製 8 8 8 8 A B c D 1243436 六、申請專利範圍 片腳位大小係2 5〜1 5 0 // m ’厚度在5〜3 0 m i 1範圍内；該 副晶片腳位大小係25〜15〇e m，厚度在lmU以下。 (請先閱讀背面之注意事項再填寫本頁) 6.如申凊專利範圍第1項或第2項所述之半導體封裝，其 中该金屬圖案係由：Ti/W + Cu + Cu、 Ti/w + Cu + Au 、 Cr + Ni + Au 、 Cr + Ni + Au + Cu 、 Cr + Co + Ni + Au 、或 Cr + Co + Ni + Cu + Au等所構成的混合物。 7 ·如申請專利範圍第6項所述之半導體封裝，其中該金屬 圖案寬度係25〜15〇vm，厚度在200〇人〜1〇1^1範圍内。 8. 如申請專利範圍第1項所述之半導體封裝，其中該焊接 端係四角形或球形；當屬於四角形的情況時，具有〇. i X 0· 1mm〜1 .5 X 1 .5mm的尺寸；當屬於球形的情況時，具 有W 0.1mm〜p 1.5mm的尺寸。 9. 如申請專利範圍第丨項所述之半導體封裝，其中為在該 主半導體晶片上安裝副半導體晶片而使用黏著劑，該黏 著劑係非導電性聚合物，厚度在1 mil以下。 10·如申請專利範圍$ i項所述之半導體封裝，其中該絕緣 層係t 亞胺或聚合物。 經濟部智慧財產局員工消費合作社印製 種數 一.複 導 半 導 半 之 接 電 · 互有 相 備 有 具 含 •’ 造法 製方 乃 之 , 裝 法封 方體 造導 製 半 之的 裝片 封晶 體體 數 著 複 黏 有布 設塗 緣， 周 處 外 分 於部 且 定 ， 既 能 之 機上 的 片 板晶 基體 或導 架半 線主 引 的 有位 ； 具腳驟 在片步 晶 的 主 劑 1®« 個 1 少 至 之 位 腳 片 晶 laJ 數 複 有 設 處 緣 周 外 在 將 6- A S) N C 標 家 國 國 中 用 適 度 尺 張 紙 ¾) 公 97 2 X 10 21 1243436 B8 C8 D8 六、申請專利範圍 半導體晶片，安裝於該黏著劑上的步驟； 依埋藏該至少一個副半導體晶片，且使該主晶片腳 位及副晶片腳位裸露出的形態，而形成於絕緣層的步 驟； 形成將任意主晶片腳位與副晶片腳位之間，或任意 副晶片腳位與其他副晶片腳位之間予以電連接之複數 金屬圖案的步驟； 在已形成該複數金屬圖案的主半導體晶片整面 上，塗布封裝材之後，裸露出所選擇到各金屬圖案上部 其中一部份的步驟； 在該裸露出的金屬圖案上部形成焊接端的步驟；以 及在該各焊接端上部安裝焊球的步驟。 1 2.如申請專利範圍第1 1項所述之半導體封裝之製造方 法，其中該黏著劑係非導電性聚合物，厚度在1 mil以下。 1 3 .如申請專利範圍第1 1項所述之半導體封裝之製造方 法，其中該主晶片腳位大小係 2 5〜1 5 0 // m，厚度在 5〜3 0 m i 1範圍内；該副晶片腳位大小係2 5〜1 5 0 // m，厚 (請先閲讀背面之注意事項再填寫本頁) -訂- 經濟部智慧財產局員工消費合作社印製 下 以mi 11 在 度 第 圍 範 利 專 方 造 製 之 裝 封 體 。 導物 半合 之聚 述或 所胺 項亞Η酿 1—- 係 層 緣 絕 該 中 請 申 如 法 其 第 圍 範 利 專 請 申 如 法 方 與 造 層 製 障 之 阻 裝 部 封：下 體有成 導含形 半包序 之係依 述法，， 所方上 & 面 項 i 形 整 11的片 案晶 圖體 屬導 機半 該主 中該 其在 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ABCD 1243436 六、申請專利範圍 晶種（s e e d)層的步驟； (請先閲讀背面之注意事項再填寫本頁) 形成具有供使將該主晶片腳位、副晶片腳位、及各 自所對應腳位之間予以電連結用的部分，呈裸露出形態 之光阻圖案的步驟； 在該裸露出晶種層上形成金屬物質之後，去除上述 光阻圖案的步驟； 形成具有除上述金屬物質之外，裸露出殘餘部分之 形態的罩幕圖案的步驟；以及 藉由施行蝕刻步驟，對除該罩幕圖案下面之外所存 在的晶種層及下部阻障層施行蝕刻處理，然後經由去除 該罩幕圖案而形成該金屬圖案的步驟。 1 6.如申請專利範圍第1 1項或第1 5項所述之半導體封裝之 製造方法，其中該金屬圖案係由：Ti/W + Cu + Cu、 Ti/W + Cu + Au 、 Cr + Ni + Au 、 Cr + Ni + Au + Cu 、 Cr + Co + Ni + Au、或Cr + Co + Ni + Cu + Au等戶斤構成的混合物。 經濟部智慧財產局員工消費合作社印製 1 7.如申請專利範圍第1 6項所述之半導體封裝之製造方 法，其中該金屬圖案寬度係 25〜15〇em，厚度在 2000A〜1 Omil範圍内。 1 8 ·如申請專利範圍第1 1項所述之半導體封裝之製造方 法，其中該封裝材係軟焊光阻，厚度在1 0〜1 0 0 // m範圍 内。 1 9.如申請專利範圍第1 1項所述之半導體封裝之製造方 法，其中該焊接端係四角形或球形；當屬於四角形的情 -18- 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 8 8 8 8 A B CD 1243436 六、申請專利範圍 況時，具有 0.lx 0.1mm〜1.5x1.5mm的尺寸；當屬於球 形的情況時，具有p 0.1mm〜φ 1.5mm的尺寸。 (請先閱讀背面之注意事項再填寫本頁) •、^T· 線·: 經濟部智慧財產局員工消費合作社印製 9 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)
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