TWI240968B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
TWI240968B
TWI240968B TW092136961A TW92136961A TWI240968B TW I240968 B TWI240968 B TW I240968B TW 092136961 A TW092136961 A TW 092136961A TW 92136961 A TW92136961 A TW 92136961A TW I240968 B TWI240968 B TW I240968B
Authority
TW
Taiwan
Prior art keywords
insulating film
patent application
item
film
word lines
Prior art date
Application number
TW092136961A
Other languages
English (en)
Chinese (zh)
Other versions
TW200504871A (en
Inventor
Young-Taek Song
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200504871A publication Critical patent/TW200504871A/zh
Application granted granted Critical
Publication of TWI240968B publication Critical patent/TWI240968B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
TW092136961A 2003-06-30 2003-12-26 Method for manufacturing semiconductor device TWI240968B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030043686A KR20050002315A (ko) 2003-06-30 2003-06-30 반도체 소자의 제조 방법

Publications (2)

Publication Number Publication Date
TW200504871A TW200504871A (en) 2005-02-01
TWI240968B true TWI240968B (en) 2005-10-01

Family

ID=33536404

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092136961A TWI240968B (en) 2003-06-30 2003-12-26 Method for manufacturing semiconductor device

Country Status (4)

Country Link
US (1) US6927168B2 (ja)
JP (1) JP4401156B2 (ja)
KR (1) KR20050002315A (ja)
TW (1) TWI240968B (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100596834B1 (ko) * 2003-12-24 2006-07-04 주식회사 하이닉스반도체 반도체소자의 폴리실리콘 플러그 형성방법
KR100571655B1 (ko) * 2004-06-23 2006-04-17 주식회사 하이닉스반도체 랜딩 플러그 콘택 구조를 가진 반도체 소자 제조방법
US20070264829A1 (en) * 2006-05-12 2007-11-15 Hynix Semiconductor Inc. Slurry and method for chemical mechanical polishing
KR101185988B1 (ko) * 2009-12-30 2012-09-25 에스케이하이닉스 주식회사 반도체 메모리소자의 랜딩플러그컨택 형성방법
JP2013038095A (ja) * 2011-08-03 2013-02-21 Elpida Memory Inc 半導体装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100276387B1 (ko) * 1998-01-08 2000-12-15 윤종용 반도체 장치의 자기정렬 콘택 형성 방법
US6284660B1 (en) * 1999-09-02 2001-09-04 Micron Technology, Inc. Method for improving CMP processing
US6723655B2 (en) * 2001-06-29 2004-04-20 Hynix Semiconductor Inc. Methods for fabricating a semiconductor device

Also Published As

Publication number Publication date
TW200504871A (en) 2005-02-01
US20040266166A1 (en) 2004-12-30
US6927168B2 (en) 2005-08-09
JP2005026653A (ja) 2005-01-27
JP4401156B2 (ja) 2010-01-20
KR20050002315A (ko) 2005-01-07

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees