1238599 、、 * · 九、發明說明： 【發明所屬之技術領域】 本發明係關於輸入接受哭， 輸入接受哭，以接供於入二：丨其疋—種提供遲滞值予 及裝】 號適當的雜訊容受範圍的方法 【先前技術】 在早期積體電路的設計中，互補式氧 :⑽㈣出堪動器被規劃為推-挽式元件。結果 :溫度、供_及製造過程的差異，輪出匯流排的雜a 冒明顯波動’而雜關時㈣匯集在積體電路之裝置數旦 的函數。 =來’由於技術的進展，導致裝置尺寸及使 =的降低，設計者㈣更積積地在外部㈣鬆理雜訊 問通’以使系統内的電路運作速度能最大化。最近工業界 解決輸出驅動器問題的觀念為自挽式輸出轉而趨向： 使^動輸人接受器。差動輸人接受器的—側被提供—夫 考電壓’另-側則由開路汲極N通道裝置所驅動。: 開路汲極N-通道裝置係由晶片内提供，而匯流排拉^阻 則自晶片内或自外部提供，例如在系統主機板等。 上述類型的輸出驅動器盛行於工業界，由英代爾 _)所開發的奔騰(Pentium)X86系列的微處理器就是其 中一例。奔騰（Pentium)微處理器使用開路汲極队通=/中 裝置驅動—h5V匯流排，其參考閾值為1.0V。較新的^流 5 1238599 排規格則使用更低的電壓，例如參考閾值為0.83V的 1.25V匯流排。通常使用56歐姆拉昇終端，並且在拉降 阻抗則未指定時，開路汲極通道裝置被使用來符合匯流排 的切換及時序規格。工業界採用Assisted Gunning Transceiver Logic (AGTL，Assisted Gunning Transceiver Logic ，援助發身子接 收邏輯電路）這個名稱來廣泛描述這類連接這類匯流排之 裝置。這些裝置被習稱為AGTL裝置或AGTL邏輯或簡稱 AGTL。 然而習知的輸入接受器在輸入信號具有高雜訊的場合 有其缺點。具有局雜訊的輸入信號會在積體電路上導致錯 誤觸發及不當運作上。就該些接受器，其觸發或切換的門 才監是由鄰近設計切換閾值的一電壓範圍所界定。而此一電 壓範圍的限制大致是由製造過程、操作溫度及操作電壓所 決定。其他輸入裝置如施密特觸發裝置（Schmidt Trigger device)被設計成可為輸入信號提供遲滯值，但乃是以降低 速度、增加耗能及額外的匯流排負擔等做為代價。 若依據較新匯流排規格而降低電壓，會使雜訊的容受 度隨之降低，而使雜訊問題愈形嚴重。因此亟須提供一種 輸入接受器，可以容受更高的雜訊，而仍能在匯流排操作 電壓下維持正確邏輯運算，包含在較新規格下的較低電 壓。亦為所亟需者乃是提供一種輸入接受器，可以取代習 知輸入接受器，而具有較高的雜訊免疫力，而不會付出如 現今使用遲滯值之裝置，像施密特觸發裝置的代價。 1238599 【發明内容】 《所欲解決之問題》 本發明所欲解決之問題為：提供一種使用滯後變動參 ^值的輸入接受器，具有較高的雜訊免疫力，可以容受更 回的雜訊，而仍能在匯流排操作電壓維持正確邏輯運算， 且無習知使用遲滯值裝置的缺點。 《解決問題之手段》 本發明之一實施例提供一種具有遲滞值的輸入接受 器，其包括：一差動放大器；一參考電路，其具有一參考 ^點並產生-在標稱閾值電Μ的參考信號；以及—切換堆 宜衣置。此一放大器具有接受一輸入信號之一第一輸入 :二=接至參考節點之一第二輸入端，以及一輸出端以提 ，、-弟-輸出信號，該輸出信號具有第一及第二狀態以指 不上述輸人信號的狀態。此-切換堆㈣置，連接差動放 大器輪出端及參考節點，並根據位於上或下間值電壓 且與輪入信號相反方向的第一輪出信號，調整參考作號。 放大ίΓΓΓ:特定實施例中，輸入信號係提供給絲 放大♦反相輸入端’故而第一輸出信 相反的方向進行切換。在此實施例，還 以反相第-輸出信號，進而提供一第二輸出信號= 入信號的狀態。 儿从才日不輸 產生二=電料以是一分壓器’其可劃分電源電壓以 破。此一參考電路具有-令節點，做為產生參 1238599 考"ί§ 5虎用的茶考節點 古 ^ 口 、 即”、、占在一更明確的實施例中，此—分茂 器包含複數Ρ-通道梦晋，#必 、， ^ 、 Μ二-通道裝罝在電源電壓彳古號 及接地端間，以串遠方彳如$ — 口歲 連方式相連接。母一 通道裝罝具有遠 接在-起的-基體（bulk)和—源極（SGUrce)，及連接在 的閘極(gate)和-汲極恤ain)。就AGTL架構而言〜 中節點提供一來老作躲，兮会土江t ° 〜 亏“唬该苓考“號的標稱值約為電湄恭 壓信號的三分之二。 包愿电 此切換堆疊褒置可包含一 p_通道裝罝及一 n_通道裝 =°此-P_相I罝具有—源極連接至差動放大器輪出 端，及一閘極和一汲極都連接至參考節點。此一N_通道壯 罝具有-源極連接至差動放大器輸出端，—汲極連接至= 考節點’及-閘極連接至分壓器。在此一例子中，分壓“ 可包含-第二中節點’該第二中節點連接至N_通道裝置的 閘極:在AGTL架構中’第—中節點具有約為電源電壓作 分之二的標稱電壓’’第二中節點具有約為電源電 堊t號的二分之一的標稱電壓。 依本發明之一實施例，本發明提供一積體電路，並包 f : 一電源接腳及一接地接腳，二者共同接受一匯流排電 壓；一差動放大器，其由匯流排電壓提供電源；一參考^ 路；及一切換電路。該差動放大器，具有—反相輸二端S 接焚一輸入信號，一非反相輸入端以接受—參考信號，及 :輪出端以提供具有第一及第二狀態的一數位信號广用以 指示輸入信號的狀態。該參考電路橋接電源接腳及接地接 腳，並提供位於一標稱閾值電壓的參考信號。該切換電 Ϊ238599 路，連接至差動放大器的輸出端，並 能，調整灸者产咕e ·"· 豕數位k號的狀 i壓 考^虎至向或低於標稱閾值電壓的上或下閑值 卢：參考電路可以建構成—種電阻式分壓哭 一第一中節點，以提供參考信號。例如，此二; 器可包含複數P_通道裝置，該些 :田^刀昼 接腳及接地接腳之間。每—於電源 -基體和源極，及連接在—起的_==連接在:起的 致的電壓劃分。 °σ及極，以達成— 此一分壓器可包含一第二中節點. 包含一 Ρ诵、音壯$ 1 ’且此一切換電路可 、、衣置及一N-通道裝置。此_ρ_ 分別連接至第一中節點的一 、、衣置具有 放大器輸出端―、二=Γ 汲極，及連接至差動 第-中節點，-間極連接至第二中節極連接至 差動放大器輸出端。在胤架構二及：！極連接至 匯流排電壓的二分 中即具有約為 流排電壓的三分之—的標稱電壓。中^有約為匯 依本發明之一實施例，本發明 值的輸入接受器之方法，其包括:提供—= 具有遲滯 壓的參考銪 、， 捉仏具有標稱閾值電 入信號電壓，該差動放大器係在一較高；二“f與-輸 之間進行切拖.木、11 毕乂同甩壓及一較低電壓 考節點電壓至換至較高電壓時，增加參 包/土至一上閾值電壓；及當 電壓時，減少表考大㈣換至較低 夕 > 号即點电屋至一下閾值電壓。 1238599 提供參考節點的-可能方式是：在電愿來源的端點間 堆疊複數個第通道I置並形成-中節點。增加參考節 點電壓至上閾值電壓的一可能方式是：啟動連接至?·通道 堆疊裝置之其他P-通道裝置。減少參考節點電壓至一下閾 值電壓的一可能方式是：啟動連接p_通道堆疊裝置之一 N_ 通道裝置。以差動放大器比較參考節點電壓與一輸入信號 %【的可此方式疋.當輸入信號電壓低於下閾值電壓’ 差動放大器切換至較高電壓；及當輸入信號電壓高於上閾 值電壓，差動放大器切換至較低電壓。 《對於先前技術之效果》 本發明之具有遲滯值輸入接受器，具有較高的雜訊免 疫力，可以容受更高的雜訊，而仍能在匯流排操作電壓維 持正確邏輯運算，且無習知使用遲滯值裝置的降低速度、 增加耗能及額外的匯流排負擔等缺點。 【實施方式】 下述内容可使此領域中具有通常技術者得據以實施本 發明，就本發明之較佳實施例所做的各種變更修飾，或將 揭露於此的技術思想再應用於其他實施例，對習於此項技 術者而言，係屬明顯而可輕易完成者。因此發明人並無意 將本發明限制於該些被描述於此的實施例，而是在符合本 發明所揭露的技術思想及新穎特徵之下，賦予本發明最廣 之權利範圍。 1238599 ' ' 由於發明人認知到具有適當雜訊容受範圍的輸入接受 器的需求，於是開發出一種具有遲滯值且較習知輸入接受 器更大雜訊容受範圍的輸入接受器及方法，其將參照第一 至第四圖描於下。 第一圖為習知輸入接受器100的示意圖，其係使用於 AGTL架構開路汲極匯流排。習知輸入接受器100包括： 一差動放大器U1 ，其具有一反相輸入端以接受參考信號 REF，一非反相輸入端以接受輸入信號PDPADIN ;及一輸籲 出端以提供輸出信號OUT。參考信號REF是自匯流排電源 信號VTT衍生到一切換閾壓值，VTT及REF係晶片外產生 並經由pads(未示於圖中）提供給晶片。在一 AGTL架構 中，匯流排電源信號VTT約為1.5V，而切換閾壓值REF則 定為2/3 VTT—或約1.0V。當PDPADIN信號經REF信號， U1的轉換是被要求的。在所示構造中，當輸入信號 PDPADIN低於REF，輸出信號OUT在低值，而當輸入信號 PDPADIN高於REF，輸出信號OUT轉為高值。 < 當輸入信號PDPADIN具有高雜訊時，輸入接受器100 表現不佳。更且，依較新的匯流排規格，匯流排電源信號 VTT被降為1.25V ，參考信號REF則被降為約0.83V (1.25V 的2/3)閾壓值，雜訊容忍範圍亦被等比例的縮小，使得雜 訊的問題更難以被克服。如前所述，其他輸入裝置，例如 施密特觸發裝置（Schmidt Trigger device)，雖有提供一遲滯值 (hysteresis)予輸入信號，但此乃是以降低速度、增加耗能及 額外的匯流排負擔等做為代價。 1238599 β 、、 第二圖為本發明一實施例之輸入接受器2⑻的示意 圖，其依據AGTL架構開路使用於汲極匯流排構造。其包 括一差動放大器U1以接受輸入信號PDPADIN。但在此一 輸入接受器2⑻，輸入信號PDPADIN卻是提供給差動放大 器U1的反相輸入端，而另一個具遲滯值的參考信號 HREF則提供給非反相輸入端。差動放大器U1在其輸出 端顯示一 GRASS信號，此一 GRASS信號具有相對於輸入信 號PDPADIN狀態的反相狀態。輸入接受器200亦包括一反 相器U2 ，其具有一輸入端以接受GRASS信號及一輸出端 以提供OUT信號，OUT信號為一非反相版的PDPADIN信 號。 參考信號HREF衍生自匯流排電源信號VTT並具有一 如同習知差動輸入接受器100之REF信號的標稱閾值。依 AGTL架構，如果VTT為1.5V，貝1 HREF具有1.0V的標稱 閾值，如果VTT為125V ，則HREF具有0.83V的標稱閾 值。AGTL架構的實施例只是例示性的，其他的電壓值和 操作模式亦被考慮使用。此一 HREF信號並非來自於晶片 外，而是產自於晶片内。更且，此一 HREF信號具有兩個 操作電壓值，一個稍高於標稱閾值電壓，另一個稍低於標 稱閾值電壓，而使用那一個閾值電壓則取決於GRASS信號 的狀態。如此，HREF信號並非一單一電壓值，而是一具 有遲滯值的參考信號，其如下述。 一分壓器201 ，做為一參考電路，產生HREF信號的 標稱閾值電壓。此分壓器201係由三個實質相同的P_通道 12 1238599 、 · tr l 裝罝PI、P2及P3，在匯流排電源信號VTT及一參考端子或 接腳如接地端GND之間，以串連方式堆疊而成。P1的源極 連接VTT，其汲極及閘極在一第一中節點203相連，該第 一中節點203產生HREF信號。P2的源極連接中節點 203 ，其汲極及閘極在一第二中節點205相連。P3的源極 連接中節點205，其汲極及閘極在接地端GND相連。每 PI、P2及P3的基體（或N-井或井連接線（welltie))各自與其 源極連接。如此，P1的源極及基體與VTT等電位，而P3的_ 閘極及汲極則均接地。P1的閘極及汲極與P2的源極及基體 等電位，P2的閘極及汲極與P3的源極及基體等電位。如 · 此，分壓器201以一種對稱的組態形成，並將VTT電壓均 ·, 分為三等分。如此，節點203的標稱電壓值約為（2/3) , VTT，而節點205的電壓值約為（1/3) VTT。 輸入接受器200包括一“弱”堆疊裝置207 ，其具有 一 P-通道裝置P4及N-通道裝置N1 。GRASS信號被提供給 N1及P4的源極。N1及？4的汲極及P4的閘極在節點203 籲 連接。N1的閘極連接節點205，P4的基體連接VTT。在 另一種組態中，N1及P4基體節點可連接至GRASS信號。 堆疊裝置207做為一切換電路，依GRASS信號的變換，而 稍為增加或減少節點203參考信號HREF的閾值電壓。隨 著輸入信號PDPADIN與參考信號HREF比較的結果的變 換，差動放大器U1依高或低閾值電壓變換GRASS信號的 狀態。HREF信號以輸入信號PDPADIN變化方向的反方向 增加或減少，如此便可依GRASS信號變換提供遲滯值。在 13 1238599 、、 所示的電路構造中，P1到P3具有相等的大小，而相較於PI 到P3，N1及P4則為較“弱”的裝置。如將述於後者，滯 後變動的程度可用調整N1及P4對P1到P3的相對大小來調 整。 第三圖為輸入接受器200運作的時序圖，其中以輸入 信號PDPADIN及參考信號HREF的電壓值為縱軸，而時間 為橫軸。時間刻度並非特定，而是依個別的裝置或應用而 定。輸入信號PDPADIN以在0.0V至1.25V間振蕩或切換的 週期波呈現。匯流排電源信號VTT，依AGTL架構，以具 有約1.25V電壓的虛線呈現。HREF的標稱閾值電壓約為 0.83V ，以標有2/3 VTT的第一條點線呈現。在起始時間 T0(在非特定刻度時間座標二0.0)時，輸入信號PDPADIN在 其最低電壓值0V 。當輸入信號PDPADIN的電壓低於參考 信號HREF電壓值時，GRASS信號為高值；而當GRASS信 號為高值，N1為關而P4為開；而當N1為關而P4為開 時，在節點203的參考信號HREF電壓便被拉升而高於標 稱閾值電壓的2/3VTT。在所示的電路構造中，相較於P1到 P3，P4是相對較“弱”的裝置，所以如圖所示的上閾值電 壓HREF+，HREF電壓只增加到高出2/3 VTT約50mV ，即 0.88V。如此，當在輸入信號PDPADIN低於參考信號 HREF電壓的時間點T0，參考信號HREF電壓起先是在上 閾值電壓HREF+。 輸入信號PDPADIN電壓持續上升直到在T1時間超過上 閾值電壓HREF+，在此時點差動放大器U1進行切換動 14 1238599 . 、、 作，而將GRASS信號變為低值。而當GRASS信號為低值， P4為關而N1為開；而當P4為關而N1為開時，在節點 203的參考信號HREF電壓便被拉下而低於標稱閾值電壓 的2/3VTT。在所示的電路構造中，相較於P1到P3，N1是 相對較“弱”的裝置，所以如圖所示的下閾值電壓HREF —，HREF電壓只減少到低於2/3 VTT約50mV ，即 0.78V 。如此，當大約在輸入信號PDPADIN高於參考信號 HREF的上閾值電壓HREF+的時間點T1，參考信號HREF φ 電壓被拉低至下閾值電壓HREF —。輸入信號PDPADIN繼 續增加至以301標示的最高值，然後再下降，直到在T2時 間低於下閾值電壓HREF —。當輸入信號PDPADIN下降而 在T2時間低於下閾值電壓HREF —時，差放大器U1進行 切換動作，而將GRASS信號拉至高值。當GRASS信號變為 高值，N1關閉而P4再度開啟，而參考信號HREF也再切 換回上閾值電壓HREF+，並週而復始地重複相似的過程。 輸出信號OUT回應GRASS信號的轉換而轉換，並提供一 < PDPADIN信號的非反相表現。 輸入接受器2⑻及第三圖輸入接受器200運作的時序 圖所例示的實施例顯示：相對於2/3 VTT的標稱閎值電壓， HREF遲滯值的變化範圍約為100mV。100mV遲滯值的變 化範圍己足以在許多的應用上容受雜訊，且不會導致上述 習知遲滯值裝置-如施密特觸發裝置-的不良效果。為說 明的方便，輸入信號PDPADIN以一週期性的信號呈現，但 也可以是任何其他種類的信號，包括二位元或數位邏輯的 15 1238599 . 信號。雖然輸入信號PDPADIN在此是以一相對“乾淨”的 信號呈現，但即使輸入信號PDPADIN加入高達數十mV的 雜訊亦不會干擾切換動作的正球運作。尤其，當HREF遲 滯值防止GRASS信號被錯誤觸發或振蕩時，HREF遲滯值 就能使差動放大器U1正確的切換。如同習於此項技術者 所能領會者，遲滞值的範圍可藉由調整N1及P4相對於P-通道堆疊裝置P1至P3的大小而達成。 此P-通道裝置被規劃為相對精確且均勻的電阻裝置， 其分割匯流排電源信號VTT而得到2/3 VTT的電壓值，以做 為比較及切換之用。差動放大器U1直接或間接地接受來 自匯流排電源信號VTT的電源，並在該電源的範圍一VTT 電壓至GND接地電壓之間對進行對GRASS信號的切換。於 是，當N1關而P4開，P4實際上是處於與P1並聯的狀態， 在VTT及節點203之間的總電阻因而降低，HREF的電壓 值因此而提高到上閾值電壓HREF+。同時，當P4關而N1 開，N1實際上是處於與P2及P3並聯的狀態，在GND接地 端及節點203之間的總電阻因而降低，HREF的電壓值因 此而降低到下閾值電壓HREF —。其他替代性的構造亦可 被考慮，例如以電阻器或其他電阻性裝置建構分壓器 201 。在此替代性的構造中或在另外的情況，N1及P4可 被電阻式裝置及切換電路取代，以針對GRASS信號在 HREF+及HREF —間調整參考信號HREF 。 第四圖為根據本發明例示性實施例之建構差動輸入接 受器方法的流程圖。在第一方塊401 ，一標稱電壓值被提 16 1238599 . · · 供給一參考節點。在所示的實施例中，此是由在匯流排電 壓源VTT及GND之間堆疊具有一中節點的複數P-通道裝置 而達成。在次一方塊403 ，使用一差動放大器對一輸入信 號及參考節點電壓進行比較，該差動放大器在一電壓高值 及一電壓低值間進行切換。在一實施例中，當輸入信號電 壓低於一下閾值電壓時，差動放大器切換至電壓高值，而 當輸入信號電壓高於一上閾值電壓時，差動放大器切換至 電壓低值。同時，差動放大器接受匯流排電壓VTT，並在φ VTT電壓間進行切換。 在次一方塊405，當差動放大器切換至電壓高值，參 · 考節點電壓被增加至上閾值電壓。在所示的實施例中，此 . 是由啟動連至第一 P-通道堆疊裝置的一第二P-通道裝置而 達成。而在次一方塊407，當差動放大器切換至電壓低 值，參考節點電壓被減少至下閾值電壓。在所示的實施例 中，此是由啟動連至第一 P-通道堆疊裝置的一 N-通道裝置 而達成。 參 依本發明之實施例而實施之差動接受器有數個勝於習 知接受器的優點。本發明使設計者能在積體電路或晶片中 使用一種差動接受器，其雜訊容受範圍明顯高於習知差動 接受器迄今為止所能提供者。例如，差動輸入接受器200 可以實施於一積體電路，其接受的VTT匯流排電壓係來自 外部來源。在所示的實施例中，HREF信號是内生自VTT 信號。輸入信號PDPADIN可自外部或内部來源提供。 HREF信號的遲滯值可以對抗一高雜訊的輸入信號 17 1238599 PDPADIN。如同本說明所述，遲滯值的變化範圍可藉由調 整堆疊裝置的大小而增加。本發明對在低電壓操作的差動 輸入接受器具有顯著的優點，例如使用於較新的匯流排規 格的場合，其預期將會使用1·25Υ的匯流排且具有〇·83ν 的閾值電壓。 雖然在此本發明己參照一些較佳實施例做相當詳細的 描述，但其他實施例或變化亦在本發明的預期之内。例 如，分壓器201亦可以使用其他精密或一般的電阻器或電 阻式I置。同樣地，裝罝Ρ4及Ν1亦可以電阻式裝置及電 子式切換裝置或類似裝置取代。 $ 雖然本發明在此使用AGTL的匯流排規格及其相關輸· 入規範加以描述，但在此發明人亦要強調本發明之範圍係 超出AGTL而及於需要對輸入之雜訊免疫的任何應用。 ^ $於此技術者當應明瞭：以本發明所揭露之觀念及特 疋的貫施例為基礎而設計或修改成其他構造以達成與本發 明二標相同之功能，其均不脫離本發明之精神與由申請^ φ 利範圍所定之權利範圍。 【圖式簡單說明】 匯流排的習知 匯流排的本發 第一圖為依AGTL規範使用於開路汲極 接受器示意圖。 第一圖為依AGTL規範使用於開路汲極 明一實施例之例示性接受器的示意圖。 弟 圖為第二圖之本發明一實施例之例示 性輸入接受 18 1238599 、 器運作的時序圖。 第四圖為根據本發明例示性實施例之建構具有遲滯值 差動輸入接受器之方法的流程圖。 【主要元件符號說明】 元件及信號 100 習知輸入接受器 200 本發明一實施例之輸入接受器 201 分壓器 202 第一中節點 205 第二中節點 207 “弱”堆疊裝置 U1 差動放大器 REF 參考信號 PDPADIN 輸入信號 OUT 輸出信號 VTT 匯流排電源信號 HREF 具遲滯值的參考信號 GRASS 差動放大器輸出信號 PI P-通道裝罝 P2 P-通道裝罝 P3 P-通道裝罝 P4 P-通道裝置 N1 N-通道裝置 HREF + 上閾值電壓 19 1238599 HREF GND 步驟 401 403 405 407 下閾值電壓 接地端 一標稱電壓值被提供給一參考節點 使用一差動放大器對一輸入信號及參考節點電壓進 行比較 當差動放大器切換至電壓高值，參考節點電壓被增 加至上閾值電壓 當差動放大器切換至電壓低值，參考節點電壓被減 少至下閾值電壓 201238599, * * IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to input acceptance cry, input acceptance cry, in order to accept two: 丨 its 种-a kind of providing hysteresis value and equipment] No. Method of proper noise tolerance [prior art] In the design of early integrated circuits, the complementary oxygen: oscillating actuator was planned as a push-pull element. Result: The temperature, supply and manufacturing process are different, and the noise of the bus bars will fluctuate significantly, and when the noise is closed, it is a function of the number of devices assembled in the integrated circuit. = 来 ’As the technology progresses, the size of the device is reduced and the designer reduces the accumulation of external noise in order to maximize the circuit operation speed in the system. Recently, the industry's idea of solving the problem of output drivers has turned to self-pull output: to make people lose receivers. The -side of the differential input receiver is supplied-the test voltage 'and the other side is driven by an open-drain N-channel device. : The open-drain N-channel device is provided by the chip, and the bus pull-up resistor is provided from the chip or from the outside, such as the system motherboard. The above types of output drivers are prevalent in the industrial world. One example is the Pentium X86 series microprocessors developed by Intel. The Pentium microprocessor uses an open-circuit drain driver. The device is driven by the -5V bus, and its reference threshold is 1.0V. The newer ^ current 5 1238599 bus specification uses a lower voltage, such as a 1.25V bus with a reference threshold of 0.83V. A 56 ohm pull-up terminal is usually used, and when the pull-down impedance is not specified, an open-drain channel device is used to meet bus switching and timing specifications. The industry uses the name Assisted Gunning Transceiver Logic (AGTL, Assisted Gunning Transceiver Logic) to describe such devices that connect such buses extensively. These devices are known as AGTL devices or AGTL logic or AGTL for short. However, the conventional input receiver has disadvantages in the case where the input signal has high noise. Input signals with local noise can cause false triggering and improper operation on integrated circuits. For these receivers, the gates that trigger or switch are defined by a voltage range adjacent to the switching threshold of the design. The limitation of this voltage range is roughly determined by the manufacturing process, operating temperature, and operating voltage. Other input devices such as Schmidt Trigger devices are designed to provide hysteresis for input signals, but at the cost of reduced speed, increased energy consumption, and additional bus load. If the voltage is lowered according to the newer bus specifications, the noise tolerance will be reduced accordingly, and the noise problem will become more serious. It is therefore imperative to provide an input receiver that can tolerate higher noise while still maintaining correct logic operations at bus operating voltages, including lower voltages at newer specifications. It is also necessary to provide an input receiver that can replace the conventional input receiver and has a high noise immunity without paying for devices such as Schmitt triggering devices that use hysteresis values today. The price. 1238599 [Summary of the Invention] "Problems to be Solved" The problem to be solved by the present invention is to provide an input receiver that uses a hysteresis variable parameter value, which has higher noise immunity and can tolerate more noise. Information, while still maintaining the correct logic operation at the operating voltage of the bus, and without the disadvantages of using a hysteresis device. "Means for Solving Problems" An embodiment of the present invention provides an input receiver with a hysteresis value, which includes: a differential amplifier; a reference circuit, which has a reference point and generates-at a nominal threshold voltage. Reference signal; and-switch the pile should be placed. This amplifier has a first input that accepts an input signal: two = connected to a second input terminal of a reference node, and an output terminal to raise the output signal, the output signal has first and second State refers to the state of the input signal. This-switch the stack setting, connect the output end of the differential amplifier and the reference node, and adjust the reference number according to the first round output signal located at the upper or lower intermediate voltage and opposite to the input signal. Amplification ΓΓΓΓ: In a specific embodiment, the input signal is provided to the wire. Amplification ♦ Inverting input terminal ', so the first output signal is switched in the opposite direction. In this embodiment, the first output signal is also inverted to provide a second output signal = input signal state. The child never loses power. Two = electricity is a voltage divider. It can divide the power supply voltage to break. This reference circuit has a-order node, which is used to generate a reference to the 1238599 test " 5 tea test node used by the tiger, which is "," in a more specific embodiment, this-divider device contains The plural P-channel Mengjin, # 必 、, ^, Μ two-channel devices are connected between the power supply voltage and the ground terminal, and are connected in a series of distances such as $ — mouth-to-mouth connection. The female one-channel device has Remotely connected to the -bulk and -source (SGUrce), and connected to the gate and -drain (ain). As far as the AGTL architecture is concerned, the mid-node provides an old masterpiece to hide The nominal value of Xihui Tujiang t ° ~ is deficient. The nominal value of the "bluff the Lingkao" number is about two-thirds of the signal of the electricity pressure. It is hoped that the switch stacking device may include a p_channel device and An n_channel device = ° This-P_phase I 罝 has—the source is connected to the differential amplifier wheel output, and a gate and a drain are connected to the reference node. This N_channel is The source is connected to the output of the differential amplifier,-the drain is connected to the = test node 'and-the gate is connected to the voltage divider. In this example, the voltage divider can include-the second Middle node 'This second middle node is connected to the gate of the N-channel device: in the AGTL architecture, the' first-middle node has a nominal voltage of about two times the power supply voltage. ' One-half the nominal voltage of the chalk t. According to an embodiment of the present invention, the present invention provides an integrated circuit and includes f: a power pin and a ground pin, both of which jointly receive a bus voltage; a differential amplifier provided by the bus voltage Power supply; a reference circuit; and a switching circuit. The differential amplifier has an inverting input terminal S connected to an input signal, a non-inverting input terminal to receive a reference signal, and a round-out terminal to provide a digital signal with first and second states. Used to indicate the status of the input signal. This reference circuit bridges the power and ground pins and provides a reference signal at a nominal threshold voltage. The switching circuit 238599 is connected to the output of the differential amplifier, and can adjust the shape of the moxibustor. &Quot; · 豕 The shape of the digital k number is tested ^ tiger to or below the nominal threshold voltage. Or idle value Lu: The reference circuit can be constructed—a resistive voltage divider, a first middle node to provide a reference signal. For example, these two devices may include a plurality of P_channel devices, which are between the field pin and the ground pin. Every-from the power source-the base and the source, and connected at the _ = = connected at the same voltage division. ° σ and poles to achieve — this voltage divider can include a second middle node. Includes a verse, sound $ 1 ′ and this switching circuit can be, a clothing, and an N-channel device. This _ρ_ is connected to the first and the middle node of the first middle node, respectively, and the clothes have amplifier output terminals, two = Γ sink, and to the differential first-middle node, and the-intermediate pole is connected to the second middle node. Difference amplifier output. In the second framework and :! A pole connected to the bus voltage has a nominal voltage of about one-third of the bus voltage. According to an embodiment of the present invention, the method for inputting the value of the present invention includes: providing a reference signal having a hysteresis voltage, and a signal having a nominal threshold electrical input signal voltage. The difference amplifier is connected to a higher one; the two "f" and "-" are to be dragged and dropped. When the voltage is lowered and the voltage at a lower voltage test node is changed to a higher voltage, increase the reference package / soil. To the upper threshold voltage; and when the voltage is reduced, reduce the table test to a lower threshold voltage and click the electric house to the lower threshold voltage. 1238599 Provide a reference node-possible way is: at the endpoint of the electric source Multiple stacks of channel I are placed and formed into a -middle node. One possible way to increase the reference node voltage to the upper threshold voltage is to activate other P-channel devices connected to the? Channel stacking device. Reduce the reference node voltage to the lower threshold voltage One possible way is to start the N_ channel device connected to one of the p_channel stacking devices. Use a differential amplifier to compare the reference node voltage with an input signal% [This method can be used. When the input signal voltage is lower than the lower threshold voltage ' The differential amplifier is switched to a higher voltage; and when the input signal voltage is higher than the upper threshold voltage, the differential amplifier is switched to a lower voltage. "Effects of the Prior Art" The input receiver with hysteresis of the present invention has a higher Noise immunity, can tolerate higher noise, and still maintain the correct logic operation at the operating voltage of the bus, and has no habit of using the hysteresis device to reduce the speed, increase energy consumption, and additional bus burdens. [Embodiment] The following content can enable those skilled in the art to implement the present invention, make various changes and modifications to the preferred embodiments of the present invention, or reapply the technical ideas disclosed herein. Other embodiments are obvious to those skilled in the art and can be easily completed. Therefore, the inventor does not intend to limit the present invention to the embodiments described herein, but is in conformity with the present invention. Under the disclosed technical ideas and novel features, the invention has the broadest scope of rights. 1238599 '' As the inventor recognizes an input with a proper noise tolerance range The requirements of the receiver, so developed an input receiver and method with a hysteresis value and a larger noise tolerance range than the conventional input receiver, which will be described below with reference to the first to fourth figures. The first figure is The schematic diagram of the conventional input receiver 100 is used in the open-drain bus of the AGTL architecture. The conventional input receiver 100 includes: a differential amplifier U1 having an inverting input terminal for receiving the reference signal REF, a non- The inverting input terminal accepts the input signal PDPADIN; and an output terminal provides the output signal OUT. The reference signal REF is derived from the bus power signal VTT to a switching threshold voltage. VTT and REF are generated off-chip and pass through the pads (Not shown) provided to the chip. In an AGTL architecture, the bus power signal VTT is about 1.5V, and the switching threshold REF is set to 2/3 VTT—or about 1.0V. When the PDPADIN signal passes the REF signal, U1 conversion is required. In the configuration shown, when the input signal PDPADIN is lower than REF, the output signal OUT is at a low value, and when the input signal PDPADIN is higher than REF, the output signal OUT is turned to a high value. < When the input signal PDPADIN has high noise, the input receiver 100 performs poorly. Moreover, according to the newer bus specifications, the bus power signal VTT is reduced to 1.25V, and the reference signal REF is reduced to a threshold voltage of about 0.83V (2/3 of 1.25V). The noise tolerance range is also reduced. The reduction in proportion makes the problem of noise more difficult to overcome. As mentioned earlier, other input devices, such as Schmidt Trigger device, provide a hysteresis to the input signal, but this is to reduce speed, increase energy consumption, and extra busbars. Burden, etc. as a price. 1238599 β and 2 are schematic diagrams of an input receiver 2⑻ according to an embodiment of the present invention, which is used in an open circuit according to the AGTL architecture for a drain bus structure. It includes a differential amplifier U1 to accept the input signal PDPADIN. However, in this input receiver 2⑻, the input signal PDPADIN is provided to the inverting input of the differential amplifier U1, and another reference signal HREF with a hysteresis is provided to the non-inverting input. The differential amplifier U1 displays a GRASS signal at its output. This GRASS signal has an inverted state with respect to the state of the input signal PDPADIN. The input receiver 200 also includes an inverter U2, which has an input terminal to receive the GRASS signal and an output terminal to provide the OUT signal. The OUT signal is a non-inverted version of the PDPADIN signal. The reference signal HREF is derived from the bus power signal VTT and has a nominal threshold like the REF signal of the conventional differential input receiver 100. According to the AGTL architecture, if VTT is 1.5V, Bay 1 HREF has a nominal threshold of 1.0V, and if VTT is 125V, HREF has a nominal threshold of 0.83V. The embodiment of the AGTL architecture is only exemplary, and other voltage values and operation modes are also considered for use. This HREF signal does not come from outside the chip, but is produced inside the chip. Moreover, this HREF signal has two operating voltage values, one slightly above the nominal threshold voltage and the other slightly below the nominal threshold voltage, and which threshold voltage is used depends on the state of the GRASS signal. As such, the HREF signal is not a single voltage value, but a reference signal with a hysteresis value, which is as follows. A voltage divider 201 is used as a reference circuit to generate the nominal threshold voltage of the HREF signal. This voltage divider 201 is composed of three substantially identical P_channels 12 1238599, · tr l installed PI, P2 and P3, between the bus power signal VTT and a reference terminal or pin such as the ground terminal GND. Stacked in series. The source of P1 is connected to VTT, and its drain and gate are connected to a first middle node 203, which generates a HREF signal. The source of P2 is connected to the middle node 203, and its drain and gate are connected to a second middle node 205. The source of P3 is connected to the middle node 205, and its drain and gate are connected to the ground terminal GND. The matrix (or N-well or welltie) of each PI, P2, and P3 is connected to its source, respectively. In this way, the source and base of P1 are at the same potential as VTT, while the gate and drain of P3 are both grounded. The gate and drain of P1 are equipotential to the source and base of P2, and the gate and drain of P2 are equipotential to the source and base of P3. As such, the voltage divider 201 is formed in a symmetrical configuration, and the VTT voltage is evenly divided into three equal parts. In this way, the nominal voltage value of the node 203 is about (2/3) VTT, and the voltage value of the node 205 is about (1/3) VTT. The input receiver 200 includes a "weak" stacking device 207 having a P-channel device P4 and an N-channel device N1. The GRASS signal is provided to the sources of N1 and P4. N1 and? The drain of 4 and the gate of P4 are connected at node 203. The gate of N1 is connected to node 205, and the base of P4 is connected to VTT. In another configuration, N1 and P4 base nodes can be connected to GRASS signals. As a switching circuit, the stacking device 207 slightly increases or decreases the threshold voltage of the reference signal HREF of the node 203 according to the conversion of the GRASS signal. As the result of the comparison between the input signal PDPADIN and the reference signal HREF changes, the differential amplifier U1 changes the state of the GRASS signal by a high or low threshold voltage. The HREF signal increases or decreases in the opposite direction to the direction of change of the input signal PDPADIN, so that the hysteresis value can be provided according to the GRASS signal transformation. In the circuit structure shown in 13 1238599,, P1 to P3 are of equal size, and compared to PI to P3, N1 and P4 are more “weak” devices. As will be described in the latter, the degree of lag change can be adjusted by adjusting the relative sizes of N1 and P4 to P1 to P3. The third diagram is a timing diagram of the operation of the input receiver 200, where the voltage values of the input signal PDPADIN and the reference signal HREF are on the vertical axis and time is on the horizontal axis. The time scale is not specific but depends on the individual device or application. The input signal PDPADIN is presented as a periodic wave that oscillates or switches between 0.0V and 1.25V. The bus power signal VTT is represented by a dotted line with a voltage of about 1.25V according to the AGTL architecture. The nominal threshold voltage of HREF is about 0.83V, which is represented by the first dotted line labeled 2/3 VTT. At the start time T0 (the time coordinate is 0.0 at the non-specific scale), the input signal PDPADIN is at its lowest voltage value of 0V. When the voltage of the input signal PDPADIN is lower than the reference signal HREF voltage, the GRASS signal is high; and when the GRASS signal is high, N1 is off and P4 is on; and when N1 is off and P4 is on, The reference signal HREF voltage of 203 is pulled up above 2 / 3VTT of the nominal threshold voltage. In the circuit configuration shown, compared to P1 to P3, P4 is a relatively “weak” device, so the upper threshold voltage HREF + as shown in the figure, the HREF voltage only increases to about 50mV above the 2/3 VTT, That is 0.88V. In this way, when the input signal PDPADIN is lower than the reference signal HREF voltage at the time point T0, the reference signal HREF voltage is first at the upper threshold voltage HREF +. The input signal PDPADIN voltage continues to rise until the upper threshold voltage HREF + is exceeded at time T1, at which point the differential amplifier U1 switches to 14 1238599,, and the GRASS signal becomes a low value. When the GRASS signal is low, P4 is off and N1 is on; and when P4 is off and N1 is on, the reference signal HREF voltage at node 203 is pulled down and is lower than 2/3 VTT of the nominal threshold voltage. . In the circuit configuration shown, compared to P1 to P3, N1 is a relatively “weak” device, so the lower threshold voltage HREF — is shown in the figure, and the HREF voltage is only reduced to about 50mV below 2/3 VTT. , Which is 0.78V. In this way, when the input signal PDPADIN is higher than the upper threshold voltage HREF + of the reference signal HREF T1, the voltage of the reference signal HREF φ is pulled down to the lower threshold voltage HREF —. The input signal PDPADIN continues to increase to the highest value indicated by 301 and then decreases again until it falls below the lower threshold voltage HREF — at time T2. When the input signal PDPADIN falls and is lower than the lower threshold voltage HREF — at time T2, the difference amplifier U1 performs a switching action and pulls the GRASS signal to a high value. When the GRASS signal becomes high, N1 is turned off and P4 is turned on again, and the reference signal HREF is switched back to the upper threshold voltage HREF +, and the similar process is repeated again and again. The output signal OUT is converted in response to the conversion of the GRASS signal, and provides a non-inverted representation of the PDPADIN signal. The input receiver 2⑻ and the third timing diagram of the operation of the input receiver 200. The illustrated example shows that the range of the HREF hysteresis value is about 100mV relative to the nominal threshold voltage of 2/3 VTT. The range of the 100mV hysteresis value is sufficient to tolerate noise in many applications, and will not cause the above-mentioned conventional hysteresis devices, such as Schmitt trigger devices, to have the undesirable effect. For the convenience of explanation, the input signal PDPADIN is presented as a periodic signal, but it can also be any other kind of signal, including two-bit or digital logic 15 1238599. Although the input signal PDPADIN is presented here as a relatively "clean" signal, even if the input signal PDPADIN adds noise up to tens of mV, it will not interfere with the operation of the positive ball of the switching action. In particular, when the HREF hysteresis prevents the GRASS signal from being triggered or oscillated by mistake, the HREF hysteresis enables the differential amplifier U1 to switch correctly. As can be appreciated by those skilled in the art, the range of the hysteresis value can be achieved by adjusting the sizes of N1 and P4 relative to the P-channel stacking devices P1 to P3. This P-channel device is planned as a relatively accurate and uniform resistor device, which divides the bus power signal VTT to obtain a voltage value of 2/3 VTT for comparison and switching. The differential amplifier U1 directly or indirectly receives power from the bus power signal VTT, and switches the GRASS signal between the power source range VTT voltage and the GND ground voltage. Therefore, when N1 is off and P4 is on, P4 is actually in a parallel state with P1. The total resistance between VTT and node 203 is thus reduced, and the voltage value of HREF is increased to the upper threshold voltage HREF +. At the same time, when P4 is off and N1 is on, N1 is actually in a parallel state with P2 and P3. The total resistance between GND and node 203 is reduced, and the voltage value of HREF is reduced to the lower threshold voltage HREF — . Other alternative configurations are also contemplated, such as constructing the voltage divider 201 with a resistor or other resistive device. In this alternative configuration or in other cases, N1 and P4 can be replaced by resistive devices and switching circuits to adjust the reference signal HREF between HREF + and HREF — for GRASS signals. The fourth figure is a flowchart of a method of constructing a differential input receiver according to an exemplary embodiment of the present invention. In the first block 401, a nominal voltage value is raised 16 1238599. · · A reference node is supplied. In the embodiment shown, this is achieved by stacking a plurality of P-channel devices with a middle node between the bus voltage sources VTT and GND. At next block 403, a differential amplifier is used to compare an input signal and a reference node voltage, and the differential amplifier switches between a high voltage value and a low voltage value. In one embodiment, when the input signal voltage is lower than the lower threshold voltage, the differential amplifier is switched to a high voltage value, and when the input signal voltage is higher than an upper threshold voltage, the differential amplifier is switched to a low voltage value. At the same time, the differential amplifier accepts the bus voltage VTT and switches between φ VTT voltages. At next block 405, when the differential amplifier is switched to a high voltage value, the reference node voltage is increased to the upper threshold voltage. In the illustrated embodiment, this is achieved by activating a second P-channel device connected to the first P-channel stacking device. On the next block 407, when the differential amplifier is switched to a low voltage, the reference node voltage is reduced to a lower threshold voltage. In the illustrated embodiment, this is achieved by activating an N-channel device connected to the first P-channel stacking device. Differential receivers implemented in accordance with embodiments of the present invention have several advantages over conventional receivers. The present invention enables designers to use a differential receiver in an integrated circuit or chip, and its noise tolerance range is significantly higher than that of conventional differential receivers so far. For example, the differential input receiver 200 may be implemented in an integrated circuit, and the VTT bus voltage it receives is from an external source. In the embodiment shown, the HREF signal is an endogenous VTT signal. The input signal PDPADIN can be provided from an external or internal source. The hysteresis value of the HREF signal can counteract a noisy input signal. 17 1238599 PDPADIN. As described in this description, the range of the hysteresis value can be increased by adjusting the size of the stacking device. The present invention has significant advantages for differential input receivers operating at low voltages. For example, when it is used in newer bus bar specifications, it is expected that it will use a 1.25 Υ bus with a threshold voltage of 0.83 ν. Although the present invention has been described in some detail with reference to some preferred embodiments, other embodiments or variations are also contemplated by the present invention. For example, the voltage divider 201 can also use other precision or general resistors or resistors. Similarly, the devices P4 and N1 can also be replaced by resistive devices and electronic switching devices or similar devices. Although the present invention is described using the AGTL bus specification and its related input and input specifications, the inventor also emphasizes that the scope of the present invention is beyond the AGTL and for any application that needs immunity to input noise . ^ It should be clear to those skilled in the art: Designed or modified into other structures based on the concepts and specific implementation examples disclosed in the present invention to achieve the same function as the second standard of the present invention, all without departing from the present invention The spirit and scope of rights defined by the application ^ φ benefit scope. [Brief description of the diagram] The knowledge of the busbar The original picture of the busbar The first picture is a schematic diagram of the open-drain receiver used in accordance with AGTL specifications. The first figure is a schematic diagram of an exemplary receiver used in an open-drain electrode according to the AGTL specification. The figure is a timing chart of the operation of the exemplary input acceptor 18 1238599 according to an embodiment of the present invention in the second figure. The fourth figure is a flowchart of a method of constructing a differential input receiver with hysteresis according to an exemplary embodiment of the present invention. [Symbol description of main components] Component and signal 100 Known input receiver 200 Input receiver 201 Voltage divider 202 First middle node 205 Second middle node 207 “Weak” stacking device U1 Differential amplifier REF Reference signal PDPADIN Input signal OUT Output signal VTT Bus power signal HREF Reference signal with hysteresis GRASS Differential amplifier output signal PI P-channel device P2 P-channel device P3 P-channel device P4 P-channel device N1 N-channel device HREF + upper threshold voltage 19 1238599 HREF GND step 401 403 405 407 lower threshold voltage ground terminal A nominal voltage value is provided to a reference node. A differential amplifier is used to compare an input signal with the reference node voltage. The differential amplifier is switched to a high voltage value, and the reference node voltage is increased to an upper threshold voltage. When the differential amplifier is switched to a low voltage value, the reference node voltage is reduced to a lower threshold voltage of 20