CN100349166C - Input receiver with hysteresis and its construction method and integrated circuit - Google Patents
Input receiver with hysteresis and its construction method and integrated circuit Download PDFInfo
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- CN100349166C CN100349166C CNB2004101026081A CN200410102608A CN100349166C CN 100349166 C CN100349166 C CN 100349166C CN B2004101026081 A CNB2004101026081 A CN B2004101026081A CN 200410102608 A CN200410102608 A CN 200410102608A CN 100349166 C CN100349166 C CN 100349166C
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Abstract
An input receiver with hysteresis including a differential sense amplifier, a reference circuit having a reference node providing a reference signal at a nominal threshold voltage level, and a switching stack device. The amplifier has a first input which receives an input signal, a second input coupled to the reference node, and an output which provides an output signal having first and second states indicative of the input signal. The switching stack device operates to adjust the reference signal based on the output signal between upper and lower threshold levels in an opposite direction of the input signal. The reference circuit may be a voltage divider that divides a power voltage signal to develop the reference signal.
Description
Technical field
The present invention relates to input receiver, especially relate to and a kind ofly provide input receiver, with method and the device that provides suitable noise to hold scope to input signal to hysteresis.
Background technology
In the design of integrated circuit, complementary metal oxide semiconductor (CMOS) output driver is planned as and pushes away-draw the formula element in early days.As a result, look the difference of circuit temperature, supply voltage and manufacture process, the noise of output bus is fluctuation obviously, and noise also is the function that collects in the device quantity of integrated circuit simultaneously.
In recent years, because the continuous development of technology causes plant bulk and working voltage progressively to reduce, the deviser is forced to more energetically externally bus processing noise problem, so that intrasystem circuit running speed can maximize.The idea of the output driver of industry member solution recently problem is from pushing away-draw formula output then trends towards using differential input receiver.One side of differential input receiver connects a reference voltage, and opposite side is then driven by open drain N-CU channel unit.Typical open drain N-CU channel unit is provided by chip, and bus draws high resistance and then provides in chip or from the outside, for example at system host board etc.
The output driver of the above-mentioned type prevails in industry member, and the microprocessor of Pentium (Pentium) the X86 series of being developed by Intel (Intel) is exactly an example wherein.Pentium (Pentium) microprocessor uses open drain N-channel output unit to drive a 1.5V bus, and its reference threshold is 1.0V.Newer bus specification then uses lower voltage, and for example reference threshold is the 1.25V bus of 0.83V.Usually use 56 ohm and draw high terminal, and fall impedance when then not specifying drawing, the open drain CU channel unit is used and meets the switching and the sequential specification of bus.Industry member adopts this title of Assisted Gunning Transceiver Logic (AGTL, Assisted Gunning Transceiver Logic, Assisted Gunning Transceiver Logic) extensively to describe the device that connects this class bus.These devices are called as the AGTL device or the AGTL logical OR is called for short AGTL.
Yet existing input receiver has its shortcoming in the occasion that input signal has strong noise.Input signal with strong noise can be in lead to errors on the integrated circuit triggering and improper running.With regard to those receptacles, the threshold of its triggering or switching is defined by a contiguous voltage range that designs switching threshold.And the restriction of this voltage range is determined by manufacture process, operating temperature and operating voltage.Other input media such as schmidt trigger device (Schmidt Trigger device) are designed to can be input signal provides hysteresis, but to underspeed, to increase power consumption and extra bus burden etc. as its cost.
If reduce voltage according to new bus specification, the degree of holding of noise is decreased, and make noise problem more and more serious.Therefore suddenly must provide a kind of input receiver, can bear higher noise, and still can under bus operation voltage, keep correct logical operation, be included in than the low voltage under the new spec.Also, can replace existing input receiver, and have higher noise immunity, and can not pay, as the cost of schmidt trigger device as using the device of hysteresis now for urgent need person provides a kind of input receiver.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of input receiver that uses the change reference value that lags behind, has higher noise immunity, can bear higher noise, and still can under bus operation voltage, keep correct logical operation, and not have the existing shortcoming of using the hysteresis device.
To achieve these goals, the invention provides a kind of input receiver with hysteresis, its characteristics are, comprise: a differential amplifier, it has in order to accept a first input end of an input signal, be connected to one second input end of a reference mode, and the output terminal that one first output signal is provided, this first output signal has state first state and second state in order to indicate described input signal respectively; One reference circuit, it provides described reference mode and produces a reference signal in nominal threshold pressure value; An and storehouse device, the one receiving end is connected to the described output terminal of described first output signal that described differential amplifier provides, the described reference mode that one connecting end then is connected to described reference circuit and is provided, and according to described first output signal, the direction opposite with described input signal adjusted described reference signal between upper threshold voltage and threshold voltages.
Above-mentioned input receiver, its characteristics are that described reference circuit comprises a voltage divider, and this voltage divider has in first node with as described reference mode, and cuts apart a power supply voltage signal to produce described reference signal.
Above-mentioned input receiver, its characteristics are that described voltage divider comprises a plurality of P-CU channel unit, and these a plurality of P-CU channel unit are joined with serial arrangement between power supply voltage signal and earth terminal.
Above-mentioned input receiver, its characteristics are that each P-CU channel unit has a matrix and the one source pole that interconnects, and a grid that interconnects and a drain electrode.
Above-mentioned input receiver, its characteristics be, wherein node provides described reference signal in first, and the nominal value of this reference signal is about 2/3rds of described power supply voltage signal.
Above-mentioned input receiver, its characteristics are that described stack apparatus comprises: a P-CU channel unit has one source pole and is connected to described differential amplifier, and has a grid and a drain electrode is connected to described reference mode; And a N-CU channel unit, having the output terminal that one source pole is connected to described differential amplifier, a drain electrode is connected to described reference mode, and a grid is connected to described voltage divider.
Above-mentioned input receiver, its characteristics are that described voltage divider also comprises node in one second, and it connects the described grid of described N-CU channel unit.
Above-mentioned input receiver, its characteristics be, node has a nominal voltage value of 2/3rds that is about described power supply voltage signal in described first, and node has a nominal voltage value of 1/3rd that is about described power supply voltage signal in wherein said second.
Above-mentioned input receiver, its characteristics are, also comprise: described input signal is provided for an inverting input of described differential amplifier, and wherein said first output signal is switched with the reverse direction of the direction of described input signal; And a phase inverter, it has the described output terminal that an input end is connected to described differential amplifier, and an output terminal is in order to provide one second output signal to show the state of described input signal.
The present invention also provides a kind of integrated circuit, and its characteristics are, comprising: a power pin and a ground connection pin, and both accept a bus voltage jointly; One differential amplifier, it provides power supply by bus voltage, and tool one inverting input to be accepting an input signal, and a non-inverting input is accepting a reference signal, and an output terminal is indicated the state of described input signal so that the digital signal with first and second state to be provided; One reference circuit, it bridges between described power pin and the ground connection pin, and the described reference signal that is positioned at a nominal threshold voltage is provided; Reach one and switch circuit, it connects the described output terminal of described differential amplifier, and according to described digital signal state, the state of indicated input signal, the direction opposite with described input signal adjusted the threshold voltage of described reference signal between the upper threshold voltage of nominal threshold voltage and threshold voltages.
Said integrated circuit, its characteristics are that described reference circuit comprises a resistance divider, and this resistance divider has in one first node so that described reference signal to be provided.
Said integrated circuit, its characteristics are that described resistance divider comprises a plurality of P-CU channel unit, and these a plurality of P-CU channel unit are stacked between described power pin and the ground connection pin.
Said integrated circuit, its characteristics are, each of the P-CU channel unit of described a plurality of formation storehouses comprises the matrix and the source electrode that interconnect, and the grid and the drain electrode that interconnect.
Said integrated circuit, its characteristics are that described commutation circuit comprises: described voltage divider, and it comprises node in one second; One the one P-CU channel unit, it has a grid and a drain electrode that is connected to node in described first respectively, and the one source pole that is connected to the described output terminal of described differential amplifier; And a N-CU channel unit, it has a drain electrode that is connected to node in described first, is connected to a grid of node in described second, and the one source pole that is connected to the described output terminal of described differential amplifier.
Said integrated circuit, its characteristics be, node has a nominal voltage value of 2/3rds that is about described bus voltage in described first, and node has a nominal voltage value of 1/3rd that is about described bus voltage in wherein said second.
The method that the present invention also provides a kind of structure to have the input receiver of hysteresis, its characteristics are, comprising: the reference mode with nominal threshold voltage is provided; Compare reference mode voltage and applied signal voltage with differential amplifier, differential amplifier switches between a high voltage and a low voltage; When differential amplifier switches to high voltage, increase reference mode voltage to one upper threshold voltage; And when differential amplifier switches to low voltage, reduce reference mode voltage to one threshold voltages.
Above-mentioned structure has the method for the input receiver of hysteresis, and its characteristics are, the described step that reference mode is provided is included in a plurality of P-CU channel unit of storehouse between the terminal in voltage source, and the step of node in setting up.
Above-mentioned structure has the method for the input receiver of hysteresis, and its characteristics are that the step of described increase reference mode voltage comprises activation one the 2nd P-CU channel unit, and the 2nd P-CU channel unit is connected to the step of described a plurality of P-CU channel unit.
Above-mentioned structure has the method for the input receiver of hysteresis, and its characteristics are, the step of described minimizing reference mode voltage comprises and activates a N-CU channel unit, and this N-CU channel unit is connected to the step of described a plurality of P-CU channel unit.
Above-mentioned structure has the method for the input receiver of hysteresis, and its characteristics are, the step of described relatively reference mode voltage and applied signal voltage comprises when applied signal voltage and is lower than threshold voltages, and differential amplifier switches to high voltage; And being higher than upper threshold voltage when applied signal voltage, differential amplifier switches to the step of low voltage.
Effect of the present invention, be to have the hysteresis input receiver and have higher noise immunity, can bear higher noise, and still can keep correct logical operation at bus operation voltage, and do not have existing use the hysteresis device underspeed, increase power consumption and extra shortcomings such as bus burden.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is for being used in the existing receptacle synoptic diagram of open drain bus according to the AGTL standard;
Fig. 2 is for being used in the receptacle synoptic diagram of one embodiment of the invention of open drain bus according to the AGTL standard;
Fig. 3 is the sequential chart of the input receiver running of one embodiment of the invention among Fig. 2;
Fig. 4 is for making up the process flow diagram of the method with the differential input receiver of hysteresis in the embodiment of the invention.
Wherein, Reference numeral:
The 100-input receiver
The 200-input receiver, the 201-voltage divider
Node among the 203-first, node among the 205-second
207-" weak " stack apparatus
The U1-differential amplifier, the REF-reference signal
The PDPADIN-input signal, the OUT-output signal
VTT-bus source signal, the reference signal of HREF-tool hysteresis
GRASS-differential amplifier output signal
P1, P2, P3, P4-P-CU channel unit
The N1-N-CU channel unit
The HREF+-upper threshold voltage, HREF one-threshold voltages
The GND-earth terminal
Step 401-offers a reference mode with a nominal voltage value
Step 403-uses a differential amplifier that one input signal and reference mode voltage are compared
Step 405-works as differential amplifier and switches to the high value of voltage, and reference mode voltage is increased to upper threshold voltage
Step 407-works as differential amplifier and switches to the voltage low value, and reference mode voltage is reduced to threshold voltages
Embodiment
Fig. 1 is the synoptic diagram of existing input receiver 100, and it is used in AGTL structure open drain bus.Existing input receiver 100 comprises: a differential amplifier U1, and it has an inverting input to accept reference signal REF, and a non-inverting input is to accept input signal PDPADIN; And an output terminal is to provide output signal OUT.Reference signal REF derives to one from bus power source signal VTT to switch threshold pressure value, and VTT and REF are generations and offer chip by pads (not shown) chip outside.In an AGTL framework, bus power source signal VTT is about 1.5V, switches threshold pressure value REF and then is decided to be 2/3 VTT-or about 1.0V.When the PDPADIN signal through the REF signal, the conversion of U1 is required.Shown in the structure, PDPADIN is lower than REF when input signal, output signal OUT is at low value, and is higher than REF as input signal PDPADIN, output signal OUT transfers high value to.
When input signal PDPADIN had strong noise, input receiver 100 was performed poor.And according to newer bus specification, bus power source signal VTT is reduced to 1.25V, and reference signal REF is then reduced to about 0.83V (1.25V 2/3) threshold pressure value, and the noise tolerance is also dwindled by equal proportion ground, makes more to be difficult to overcome noise problem.As previously mentioned, other input media, schmidt trigger device (SchmidtTrigger device) for example, though provide a hysteresis (hysteresis) to give input signal, this is to underspeed, to increase power consumption and extra bus burden etc. as cost.
Fig. 2 is the synoptic diagram of the input receiver 200 of one embodiment of the invention, and it is used in the drain electrode bus structure according to AGTL framework open circuit.It comprises that a differential amplifier U1 is to accept input signal PDPADIN.But at this input receiver 200, input signal PDPADIN but provides the inverting input to differential amplifier U1, and the reference signal HREF of another tool hysteresis then offers non-inverting input.Differential amplifier U1 shows a GRASS signal at its output terminal, and this GRASS signal has the rp state with respect to input signal PDPADIN state.Input receiver 200 also comprises a phase inverter U2, and it has an input end to accept a GRASS signal and an output terminal so that OUT to be provided signal, and the OUT signal is the PDPADIN signal of a noninverting version.
Reference signal HREF is derived from bus power source signal VTT and have a nominal threshold value as the REF signal that has differential input receiver 100 now.According to the AGTL framework, if VTT is 1.5V, then HREF has the nominal threshold value of 1.0V, if VTT is 1.25V, then HREF has the nominal threshold value of 0.83V.The embodiment of AGTL framework is a most preferred embodiment, and other magnitude of voltage and operator scheme also can be considered to use.This HREF signal is not to come from outside the chip, but originates from chip.And this HREF signal has two operating voltage levels, an a little higher than nominal threshold voltage, and another is lower than nominal threshold voltage slightly, uses that threshold voltage then to depend on the state of GRASS signal.So, the HREF signal is not a single magnitude of voltage, but one have the reference signal of hysteresis, and it is as following.
One voltage divider 201 as a reference circuit, produces the nominal threshold voltage of HREF signal.This voltage divider 201, is formed with the serial arrangement storehouse between bus power source signal VTT and a reference terminal or pin such as earth terminal GND by three P-CU channel unit P1, P2 and P3 that essence is identical.The source electrode of P1 connects VTT, and its drain electrode links to each other with gate pole node 203 in one first, these node 203 generation HREF signals in first.Node 203 during the source electrode of P2 connects, its drain electrode links to each other with gate pole node 205 in one second.Node 205 during the source electrode of P3 connects, its drain electrode links to each other at earth terminal GND with gate pole.The matrix of every P1, P2 and P3 (or N-well or well connecting line (well tie)) is connected with its source electrode separately.So, the source electrode of P1 and matrix and VTT equipotential, the then equal ground connection of the grid of P3 and drain electrode.The source electrode of the grid of P1 and drain electrode and P2 and matrix equipotential, the source electrode of the grid of P2 and drain electrode and P3 and matrix equipotential.So, voltage divider 201 forms with a kind of configuration of symmetry, and VTT voltage is divided into trisection.So, the nominal voltage value of node 203 is about (2/3) VTT, and the magnitude of voltage of node 205 is about (1/3) VTT.
Input receiver 200 comprises one " weak " stack apparatus 207, and it has a P-CU channel unit P4 and N-CU channel unit N1.The GRASS signal is provided for the source electrode of N1 and P4.The drain electrode of N1 and P4 and the grid of P4 connect at node 203.The grid connected node 205 of N1, the matrix of P4 connects VTT.In another kind of configuration, N1 and P4 matrix node can be connected to the GRASS signal.Stack apparatus 207 switches circuit as one, according to the conversion of GRASS signal, and increases or reduce the threshold voltage of node 203 reference signal HREF a little.Along with input signal PDPADIN and reference signal HREF result's relatively conversion, differential amplifier U1 is according to the state of high or low threshold voltage conversion GRASS signal.The HREF signal increases or reduces with the opposite direction of input signal PDPADIN change direction, so just can provide hysteresis according to GRASS signal transformation.Shown in circuit structure in, P1 has equal size to P3, and compared to P1 to P3, N1 and P4 then be the device than " weak ".As being set forth in the latter, the degree of the change that lags behind can be adjusted to the relative size of P3 P1 with adjusting N1 and P4.
Fig. 3 is the sequential chart of input receiver 200 runnings, and wherein the magnitude of voltage with input signal PDPADIN and reference signal HREF is the longitudinal axis, and the time is transverse axis.Time scale is also nonspecific, but decides according to individual other device or application.Input signal PDPADIN presents with the periodic wave in vibration between 0.0V to 1.25V or switching.Bus power source signal VTT according to the AGTL framework, presents with the dotted line with about 1.25V voltage.The nominal threshold voltage of HREF is about 0.83V, presents with article one dotted line that indicates 2/3 VTT.When zero-time T0 (in nonspecific scale time coordinate=0.0), input signal PDPADIN is at its minimum voltage value 0V.When the voltage of input signal PDPADIN was lower than reference signal HREF magnitude of voltage, the GRASS signal was high value; And when the GRASS signal be high value, N1 for pass P4 for opening; And when N1 for pass P4 when opening, just drawn high at the reference signal HREF of node 203 voltage and be higher than the 2/3VTT of nominal threshold voltage.Shown in circuit structure in, to P3, P4 is the device of " weak " relatively compared to P1, so upper threshold voltage HREF+ as shown in the figure, HREF voltage only is increased to and exceeds the about 50mV of 2/3 VTT, i.e. 0.88V.So, as the time point T0 that is lower than reference signal HREF voltage at input signal PDPADIN, at first reference signal HREF voltage be at upper threshold voltage HREF+.
Input signal PDPADIN voltage continues to rise up to surpassing upper threshold voltage HREF+ in the T1 time, puts differential amplifier U1 at this moment and carries out change action, and the GRASS signal is become low value.And when the GRASS signal is low value, P4 for pass N1 for opening; And when P4 for pass N1 when opening, just left behind at the reference signal HREF of node 203 voltage and be lower than 2/3 VTT of nominal threshold voltage.Shown in circuit structure in, to P3, N1 is the device of " weak " relatively compared to P1, so threshold voltages HREF-as shown in the figure, HREF voltage only reduces to and is lower than the about 50mV of 2/3 VTT, i.e. 0.78V.So, as the time point T1 that is higher than the upper threshold voltage HREF+ of reference signal HREF greatly about input signal PDPADIN, reference signal HREF voltage is pulled low to threshold voltages HREF-.Input signal PDPADIN continues to increase to the mxm. that indicates with 301, and then descends, up to being lower than threshold voltages HREF-in the T2 time.When input signal PDPADIN descends and when the T2 time was lower than threshold voltages HREF-, difference amplifier U1 carried out change action, and the GRASS signal is pulled to high value.When the GRASS signal becomes high value, N1 closes and P4 opens once again, and reference signal HREF also switches back upper threshold voltage HREF+ again, and the process of duplication similarity again and again.Output signal OUT responds the conversion of GRASS signal and changes, and the noninverting performance of a PDPADIN signal is provided.
Embodiment shown in the sequential chart of input receiver 200 and 200 runnings of Fig. 3 input receiver shows: with respect to the nominal threshold voltage of 2/3 VTT, the variation range of HREF hysteresis is about 100mV.The variation range of 100mV hysteresis has been enough to the noise of holding in many application, and can not cause above-mentioned existing hysteresis device, as the ill effect of schmidt trigger device.Be the convenience of explanation, input signal PDPADIN presents with the signal of one-period property, but also can be the signal of any other kind, comprises the signal of two or Digital Logic.Though input signal PDPADIN is that signal with one relative " totally " presents at this, though input signal PDPADIN add can the disturbance switching action up to the noise of tens of mV yet correct running.Especially, when the HREF hysteresis prevented the GRASS signal by erroneous trigger or vibration, the HREF hysteresis just can make differential amplifier U1 correctly switch.Can understand as the technician in field herewith, the scope of hysteresis can realize with respect to the size of P-channel stack apparatus P1 to P3 by adjusting N1 and P4.
This P-CU channel unit is planned as accurate relatively and uniform resistance device, and its splitted bus power supply signal VTT and obtain the magnitude of voltage of 2/3 VTT is with as the usefulness that relatively reaches switching.Differential amplifier U1 accepts the power supply from bus power source signal VTT directly or indirectly, and at the scope-VTT voltage of this power supply to the switching of carrying out between the GND ground voltage the GRASS signal.So when N1 closes and P4 opens, P4 is actually the state in parallel with P1 that be in, all-in resistance thereby reduction between VTT and node 203, therefore the magnitude of voltage of HREF brings up to upper threshold voltage HREF+.Simultaneously, when P4 closes and N1 opens, N1 is actually the state in parallel with P2 and P3 that be in, all-in resistance thereby reduction between GND earth terminal and node 203, and therefore the magnitude of voltage of HREF is reduced to threshold voltages HREF-.Other substituting structure also can be considered, and for example makes up voltage divider 201 with resistor or other resistive device.In this substituting structure or in other situation, N1 and P4 can be replaced by resistance-type device and commutation circuit, to adjust reference signal HREF at the GRASS signal between HREF+ and HREF-.
Fig. 4 is the process flow diagram of the differential input receiver method of the structure of the exemplary embodiments according to the present invention.In step 401, a nominal voltage value is provided for a reference mode.In an illustrated embodiment, this is to be had a plurality of P-CU channel unit of node in one and reached by storehouse between source voltage bus VTT and GND.In step 403, use a differential amplifier that one input signal and reference mode voltage are compared, this differential amplifier switches between a high value of a voltage and a voltage low value.In one embodiment, when applied signal voltage was lower than a threshold voltages, differential amplifier switched to the high value of voltage, and when applied signal voltage was higher than a upper threshold voltage, differential amplifier switched to the voltage low value.Simultaneously, differential amplifier is accepted bus voltage VTT, and switches between VTT voltage.
In step 405, when differential amplifier switches to the high value of voltage, reference mode voltage is increased to upper threshold voltage.In an illustrated embodiment, this is to be connected to one the 2nd P-CU channel unit of a P-channel stack apparatus and to be realized by activation.And in step 407, when differential amplifier switches to the voltage low value, reference mode voltage is reduced to threshold voltages.In an illustrated embodiment, this is to be connected to a N-CU channel unit of a P-channel stack apparatus and to be realized by activation.
Implement the differential receptacle in ground according to embodiments of the invention a plurality of advantages that are better than existing receptacle are arranged.The present invention makes the deviser can use a kind of differential receptacle in integrated circuit or chip, the scope that its noise tolerance range can provide up to now apparently higher than existing differential receptacle.For example, differential input receiver 200 can be implemented on an integrated circuit, and the VTT bus voltage of its acceptance is from external source.In an illustrated embodiment, the HREF signal is conigenous the VTT signal in being.Input signal PDPADIN can provide from outside or inner source.The hysteresis of HREF signal can resist the input signal PDPADIN of a strong noise.Described as this explanation, the variation range of hysteresis can increase by the size of adjusting stack apparatus.The present invention has significant advantage to the differential input receiver at low voltage operating, for example is used in the occasion of newer bus specification, and its expection will be used the bus of 1.25V and have the threshold voltage of 0.83V.
Though do quite detailed description with reference to some preferred embodiments in this present invention, other embodiment or variation are also within expection of the present invention.For example, voltage divider 201 also can use other accurate or general resistor or resistance-type device.Similarly, device P4 and N1 also can resistance-type device and electronic type switching device shifter or similar device replacements.
Though the present invention uses the bus specification of AGTL and relevant input standard thereof to be described at this, to emphasize also that scope of the present invention exceeds AGTL and as required to any application of the noise immunity of input this inventor.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of claim of the present invention.
Claims (20)
1, a kind of input receiver with hysteresis is characterized in that, comprising:
One differential amplifier, it has in order to accept a first input end of an input signal, be connected to one second input end of a reference mode, and the output terminal that one first output signal is provided, this first output signal has state first state and second state in order to indicate described input signal respectively;
One reference circuit, it provides described reference mode and produces a reference signal in nominal threshold pressure value; And
One storehouse device, the one receiving end is connected to the described output terminal of described first output signal that described differential amplifier provides, the described reference mode that one connecting end then is connected to described reference circuit and is provided, and according to described first output signal, the direction opposite with described input signal adjusted described reference signal between upper threshold voltage and threshold voltages.
2, input receiver according to claim 1 is characterized in that, described reference circuit comprises a voltage divider, and this voltage divider has in first node with as described reference mode, and cuts apart a power supply voltage signal to produce described reference signal.
3, input receiver according to claim 2 is characterized in that, described voltage divider comprises a plurality of P-CU channel unit, and these a plurality of P-CU channel unit are joined with serial arrangement between power supply voltage signal and earth terminal.
4, input receiver according to claim 3 is characterized in that, each P-CU channel unit has a matrix and the one source pole that interconnects, and a grid that interconnects and a drain electrode.
5, input receiver according to claim 2 is characterized in that, wherein node provides described reference signal in first, and the nominal value of this reference signal is about 2/3rds of described power supply voltage signal.
6, input receiver according to claim 2 is characterized in that, described stack apparatus comprises:
One P-CU channel unit has one source pole and is connected to described differential amplifier, and has a grid and a drain electrode is connected to described reference mode; And
One N-CU channel unit has the output terminal that one source pole is connected to described differential amplifier, and a drain electrode is connected to described reference mode, and a grid is connected to described voltage divider.
7, input receiver according to claim 6 is characterized in that, described voltage divider also comprises node in one second, and it connects the described grid of described N-CU channel unit.
8, input receiver according to claim 7, it is characterized in that, node has a nominal voltage value of 2/3rds that is about described power supply voltage signal in described first, and node has a nominal voltage value of 1/3rd that is about described power supply voltage signal in wherein said second.
9, input receiver according to claim 1 is characterized in that, also comprises:
Described input signal is provided for an inverting input of described differential amplifier, and wherein said first output signal is switched with the reverse direction of the direction of described input signal; And
One phase inverter, it has the described output terminal that an input end is connected to described differential amplifier, and an output terminal is in order to provide one second output signal to show the state of described input signal.
10, an integrated circuit is characterized in that, comprising:
One power pin and a ground connection pin, both accept a bus voltage jointly;
One differential amplifier, it provides power supply by bus voltage, and tool one inverting input to be accepting an input signal, and a non-inverting input is accepting a reference signal, and an output terminal is indicated the state of described input signal so that the digital signal with first and second state to be provided;
One reference circuit, it bridges between described power pin and the ground connection pin, and the described reference signal that is positioned at a nominal threshold voltage is provided; And
One switches circuit, it connects the described output terminal of described differential amplifier, and according to the state of the indicated input signal of described digital signal, the direction opposite with described input signal adjusted the threshold voltage of described reference signal between the upper threshold voltage of described nominal threshold voltage and threshold voltages.
11, integrated circuit according to claim 10 is characterized in that, described reference circuit comprises a resistance divider, and this resistance divider has in one first node so that described reference signal to be provided.
12, integrated circuit according to claim 11 is characterized in that, described resistance divider comprises a plurality of P-CU channel unit, and these a plurality of P-CU channel unit are stacked between described power pin and the ground connection pin.
13, integrated circuit according to claim 12 is characterized in that, each of the P-CU channel unit of described a plurality of formation storehouses comprises the matrix and the source electrode that interconnect, and the grid and the drain electrode that interconnect.
14, integrated circuit according to claim 11 is characterized in that, described commutation circuit comprises:
Described voltage divider, it comprises node in one second;
One the one P-CU channel unit, it has a grid and a drain electrode that is connected to node in described first respectively, and the one source pole that is connected to the described output terminal of described differential amplifier; And
One N-CU channel unit, it has a drain electrode that is connected to node in described first, is connected to a grid of node in described second, and the one source pole that is connected to the described output terminal in described differential amplifier ground.
15, integrated circuit according to claim 14, it is characterized in that, node has a nominal voltage value of 2/3rds that is about described bus voltage in described first, and node has a nominal voltage value of 1/3rd that is about described bus voltage in wherein said second.
16, a kind of structure has the method for the input receiver of hysteresis, it is characterized in that, comprising:
Reference mode with nominal threshold voltage is provided;
Compare reference mode voltage and applied signal voltage with differential amplifier, differential amplifier switches between a high voltage and a low voltage;
When differential amplifier switches to high voltage, increase reference mode voltage to one upper threshold voltage; And
When differential amplifier switches to low voltage, reduce reference mode voltage to one threshold voltages.
17, structure according to claim 16 has the method for the input receiver of hysteresis, it is characterized in that, the described step that reference mode is provided is included in a plurality of P-CU channel unit of storehouse between the terminal in voltage source, and the step of node in setting up.
18, structure according to claim 16 has the method for the input receiver of hysteresis, it is characterized in that, the step of described increase reference mode voltage comprises activation one the 2nd P-CU channel unit, and the 2nd P-CU channel unit is connected to the step of described a plurality of P-CU channel unit.
19, structure according to claim 16 has the method for the input receiver of hysteresis, it is characterized in that, the step of described minimizing reference mode voltage comprises and activates a N-CU channel unit, and this N-CU channel unit is connected to the step of described a plurality of P-CU channel unit.
20, structure according to claim 16 has the method for the input receiver of hysteresis, it is characterized in that, the step of described relatively reference mode voltage and applied signal voltage comprises when applied signal voltage and is lower than threshold voltages, and differential amplifier switches to high voltage; And being higher than upper threshold voltage when applied signal voltage, differential amplifier switches to the step of low voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/833,806 | 2004-04-28 | ||
| US10/833,806 US6992518B2 (en) | 2003-04-28 | 2004-04-28 | Input receiver with hysteresis |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1691044A CN1691044A (en) | 2005-11-02 |
| CN100349166C true CN100349166C (en) | 2007-11-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004101026081A Active CN100349166C (en) | 2004-04-28 | 2004-12-24 | Input receiver with hysteresis and its construction method and integrated circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100349166C (en) |
| TW (1) | TWI238599B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4638939B2 (en) * | 2006-03-31 | 2011-02-23 | 富士通株式会社 | Threshold correction circuit, circuit and circuit board with threshold correction function |
| EP2963811B1 (en) * | 2014-06-30 | 2018-11-14 | Nxp B.V. | Driver for switched capacitor circuits |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5369319A (en) * | 1992-12-21 | 1994-11-29 | Delco Electronics Corporation | Comparator having temperature and process compensated hysteresis characteristic |
| US5973534A (en) * | 1998-01-29 | 1999-10-26 | Sun Microsystems, Inc. | Dynamic bias circuit for driving low voltage I/O transistors |
| US6249162B1 (en) * | 1993-05-17 | 2001-06-19 | Rohm Co., Ltd. | Hysteresis circuit |
| US6359485B1 (en) * | 1998-12-14 | 2002-03-19 | Ati International Srl | Differential input receiver and method for reducing noise |
-
2004
- 2004-08-18 TW TW93124897A patent/TWI238599B/en active
- 2004-12-24 CN CNB2004101026081A patent/CN100349166C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5369319A (en) * | 1992-12-21 | 1994-11-29 | Delco Electronics Corporation | Comparator having temperature and process compensated hysteresis characteristic |
| US6249162B1 (en) * | 1993-05-17 | 2001-06-19 | Rohm Co., Ltd. | Hysteresis circuit |
| US5973534A (en) * | 1998-01-29 | 1999-10-26 | Sun Microsystems, Inc. | Dynamic bias circuit for driving low voltage I/O transistors |
| US6359485B1 (en) * | 1998-12-14 | 2002-03-19 | Ati International Srl | Differential input receiver and method for reducing noise |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200536262A (en) | 2005-11-01 |
| CN1691044A (en) | 2005-11-02 |
| TWI238599B (en) | 2005-08-21 |
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