1237340 五、發明說明（1) 1. 本技藝所屬之技術領域 本技藝適用於晶片之金屬墊之重新佈局。 2. 先前技藝 圖1 先前技藝 顯示一個原始晶片1 0具有金屬墊A，圖中以八個金屬墊A 作為範例說明，八個金屬墊A分別安置在晶片的兩邊，實 際金屬墊數目可以增加也可以減少。 接著由於多晶片封裝技藝的興起，例如將兩片晶片靠在 一起封裝時’晶片與晶片之間的連線’為了要縮短打線 距離，便需要將金屬墊重新佈局，移位成為靠邊的一直 線排列。或是最近發展的「電路板在晶片上」（b 〇 a r d ο η chip)之技藝，也需要將原始金屬墊重新佈局，始成為單 排於晶片中間。 圖1顯示重新佈局之金屬墊B，為靠近晶片1 0的左邊，係 將原始金屬墊A以第一組導線1 1電性耦合至第二組金屬墊 B，金屬墊B成為一直線形狀，方便與左邊另外一片晶片 (圖中未表示）之打線用。 圖2 先前_藝-增加測試用金屬墊1237340 V. Description of the invention (1) 1. The technical field to which this technology belongs This technology is applicable to the rearrangement of metal pads of wafers. 2. Prior Art Figure 1 The previous art shows that an original wafer 10 has a metal pad A. The figure uses eight metal pads A as an example. The eight metal pads A are placed on both sides of the wafer. The actual number of metal pads can be increased. Can be reduced. Then, due to the rise of multi-chip packaging technology, for example, when the two chips are packaged next to each other, the 'connection between the chip and the chip', in order to shorten the wiring distance, the metal pads need to be re-arranged and shifted into a side-by-side line . Or the recently developed "circuit board on chip" (b 0 a r d ο η chip) technology also requires the original metal pads to be re-arranged to become a single row in the middle of the chip. Figure 1 shows the re-arranged metal pad B, which is close to the left side of the chip 10. The original metal pad A is electrically coupled to the second group of metal pads B with a first set of wires 11, and the metal pad B becomes a straight line, which is convenient For wiring with another chip (not shown) on the left. Figure 2 Previous_ 艺 -Add test metal pad
1237340 五、發明說明（2) 經過重新佈局以後之晶片如圖1所示，由於金屬墊B集中 成為一直線，且為了保有較小的晶片面積，所以金屬塾B 與金屬墊B之間的距離，顯得非常狹窄，這樣一來產生了 一個測試的問題，因為測試工具無法製作到如此精密， 所以，為了配合距離比較大的測試工具，必須再製作一 組金屬墊提供測試之用。圖2便顯示了金屬墊C'便是增加 的一組測試用金屬墊，金屬墊C被安置於金屬墊A與金屬 墊B的中間，提供測試之用，用以測試金屬墊A對於内部 電路之墊性耦合是否正常。 然而，圖2這種佈局的缺點便是：金屬墊C的存在，無法 確認導線1 1的正確性。換句話說，導線1 1如果在靠近金 屬墊B有斷路時無法測知，而會顯示晶片功能正常。本技 藝為了解決先前技藝的此一缺點，規劃了金屬墊D之佈 局，取代金屬塾C之佈局。 3.本技藝之内容 本技藝以金屬墊D，安置於晶片的上下兩邊（實際實施 時·可以安置在晶片無電路區域，使得金屬墊之間距離 夠大便可以），金屬墊D與金屬墊D之間的間隔拉大，便於 測試製具的製作與使用。金屬墊D藉導線1 2電性耦合至金 屬墊B。如此，當導線1 1有斷路時，本技藝之晶片單元便 可以在金屬墊D之墊性測試時，正確顯示產品為故障品。1237340 V. Description of the invention (2) The wafer after re-layout is shown in Figure 1. Since the metal pad B is concentrated into a straight line, and in order to maintain a small wafer area, the distance between the metal 塾 B and the metal pad B, It seems very narrow. This creates a test problem, because the test tool cannot be made so precise. Therefore, in order to match the test tool with a relatively large distance, a set of metal pads must be made for testing. Figure 2 shows that metal pad C 'is an additional set of test metal pads. Metal pad C is placed in the middle of metal pad A and metal pad B to provide testing for testing metal pad A for internal circuits. Whether the cushion coupling is normal. However, the disadvantage of the layout of FIG. 2 is that the existence of the metal pad C cannot confirm the correctness of the lead 11. In other words, if the wire 11 is not detected when there is a break near the metal pad B, it will indicate that the chip is functioning normally. In order to solve this shortcoming of the previous technology, this technology planned the layout of metal pad D instead of the layout of metal 塾 C. 3. Contents of this technique This technique uses metal pad D, which is placed on the upper and lower sides of the wafer (in actual implementation, it can be placed in the non-circuit area of the wafer so that the distance between the metal pads is large enough), metal pad D and metal pad D The interval between them is widened, which is convenient for making and using the test fixture. The metal pad D is electrically coupled to the metal pad B through the wires 12. In this way, when the wire 11 is broken, the wafer unit of this technology can correctly display the product as a defective product during the pad test of the metal pad D.
1237340 五、發明說明（3) 4.實施方式 圖3 .本技藝實施例 顯示一種具有原始金屬墊A之重新布局晶片，包含： 第一組金屬墊B，成一直線排列，作為連接至外部之端 點；藉著第一組導線1 1 ，電性耦合前述之第一組金屬墊B 至前述之原始金屬塾A，以及 ' 第二組金屬墊D，提供測試用；藉著第二組導線1 2，電性 搞合前述之第二組金屬整D至前述之第一組金屬塾B。 以上所述係利用較佳實施例詳細說明本技藝，惟，實施 例僅是代表說明本技藝，並非限制本技藝之權利範圍於 此一實施例，凡熟知此類技藝之人士皆能明瞭，適當而 作些微的改變及調整，仍將不失為本技藝所欲保護之範 圍。凡以下述申請專利範圍所述之範圍以及其均等技 藝、或是些微變化之技藝皆為本技藝之保護範圍。1237340 V. Description of the invention (3) 4. Implementation Figure 3. This technical example shows a rearranged wafer with original metal pad A, including: a first group of metal pads B arranged in a line as a connection to the outside Point; through the first group of wires 1 1, electrically couple the aforementioned first group of metal pads B to the aforementioned original metal 塾 A, and 'the second group of metal pads D, for testing purposes; by the second group of wires 1 2. Electrically couple the aforementioned second group of metals to the aforementioned first group of metals 塾 B. The above is a detailed description of the technique using a preferred embodiment. However, the embodiment is only a representative illustration of the technique and does not limit the scope of the right of the technique to this embodiment. Anyone who is familiar with this technique can understand it. And making minor changes and adjustments will still be within the scope of the protection of this technology. All the scopes described in the scope of patent application below and their equivalent technologies, or slightly changed technologies, are the protection scope of this technology.
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