JP2007103792A - Semiconductor device - Google Patents

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JP2007103792A
JP2007103792A JP2005293851A JP2005293851A JP2007103792A JP 2007103792 A JP2007103792 A JP 2007103792A JP 2005293851 A JP2005293851 A JP 2005293851A JP 2005293851 A JP2005293851 A JP 2005293851A JP 2007103792 A JP2007103792 A JP 2007103792A
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semiconductor device
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output
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internal circuit
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Miki Ikeda
幹 池田
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Kawasaki Microelectronics Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for which an ingenuity is exercised to eliminate an overhead of a chip's area while securing a pad's region with a required size. <P>SOLUTION: The semiconductor device has an internal circuit region 11 prepared at a central part of a semiconductor device 1, in which internal circuits are formed, a plurality of input/output cells 12 prepared such that one shorter side of their rectangular shape is lined up in order opposed to each side of the internal circuit region 11 and having a role of inputting and outputting signals to and from the external of the semiconductor device 1, a wire-bonding section 14 electrically connected through wires with the external of the semiconductor device 1, a probe section 15 with which an operation checking probe needle is brought into contact, and a plurality of pads overlapping the input/output cells 12 and arranged zigzag such that their longer side crosses the longer side of each input/output cell 12 perpendicularly. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に関し、特に入出力セル上にパットが形成された半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a pad is formed on an input / output cell.

近年、半導体装置は、微細加工技術の進歩に伴って集積度が向上するとともに、搭載される機能が増加されるに従いその回路規模も増大している。   In recent years, the degree of integration of semiconductor devices has improved with the progress of microfabrication technology, and the circuit scale has increased as the number of functions to be mounted has increased.

このように搭載される機能が増えるに従い、半導体装置の中央部に形成された内部回路と外部との間における信号数も増加し、入出力を担う入出力セルとパッドの数も増えてきている。このパッドには、ボンディングワイヤによりリードフレームと電気的に接続するワイヤボンディング部と動作確認用のプローブ針を当てるプローブ部とが備えられており、一般的に長方形の形状を有している。   As the functions mounted in this way increase, the number of signals between the internal circuit formed in the central part of the semiconductor device and the outside also increases, and the number of input / output cells and pads for input / output also increases. . The pad is provided with a wire bonding portion that is electrically connected to the lead frame by a bonding wire and a probe portion that abuts a probe needle for operation confirmation, and generally has a rectangular shape.

そのため、チップ面積の縮小化においては、配置される入出力セルやパッドによってチップサイズが決まらないよう半導体装置の限られた領域内に入出力セル、およびパッドを効率良く形成することが望まれる。   Therefore, in reducing the chip area, it is desired to efficiently form the input / output cells and pads in a limited region of the semiconductor device so that the chip size is not determined by the input / output cells and pads to be arranged.

そこで、入出力セル上にパッドを重ねて、そのパッドを千鳥状に配列することにより半導体チップを縮小する技術が提案されている（例えば、特許文献１参照。）。   Thus, a technique has been proposed in which a semiconductor chip is reduced by overlapping pads on input / output cells and arranging the pads in a staggered manner (see, for example, Patent Document 1).

特許文献１によれば、入出力セル上にパッドを重ねたことにより、チップ面積の縮小化が図られている。また、入出力セルの長辺に対してパッドの長辺が平行になるような千鳥状の配列を採用してパッドを入出力セル上から食み出さないように配置している。
特開平１１−３０７６０１号公報（第５頁、図５） According to Patent Document 1, the chip area is reduced by overlaying pads on input / output cells. Further, a staggered arrangement is adopted in which the long sides of the pads are parallel to the long sides of the input / output cells, and the pads are arranged so as not to protrude from the input / output cells.
Japanese Patent Laid-Open No. 11-307601 (5th page, FIG. 5)

上述の通り、このパッドにはワイヤボンディングを行うための領域と動作確認用のプローブ針を当てる領域が設けられている。ここで、パッドを縮小化した場合、ワイヤボンディングを行うための領域が狭められすぎると、電気的接続が不安定になるおそれが生じる。また、動作確認用のプローブ針が当てられる領域が狭められすぎると、プローブ針がパッドに当てられたときに生じるプローブ痕がパッドを食み出してしまうというおそれが生じる。   As described above, this pad is provided with a region for performing wire bonding and a region for applying a probe needle for operation confirmation. Here, when the pad is reduced, if the region for wire bonding is too narrow, the electrical connection may become unstable. In addition, if the region to which the probe needle for operation confirmation is applied is too narrow, there is a risk that the probe mark generated when the probe needle is applied to the pad will protrude the pad.

そこで、特許文献１に開示された技術を適用して必要なパッド領域を確保し、チップ面積の縮小化を試みようとすると、以下の問題が生じる。   Therefore, when the technique disclosed in Patent Document 1 is applied to secure a necessary pad area and attempt to reduce the chip area, the following problems occur.

例えば、チップ面積が縮小化するとともに、入出力セルの長辺に相当する入出力セル高も低くなる。ところが、パッド開口部のサイズはワイヤボンディング技術やプローブテスト技術で決まるため、パッドが入出力セルから食み出してしまい、これによるチップ面積のオーバヘッドの問題が生じてしまう。   For example, the chip area is reduced, and the input / output cell height corresponding to the long side of the input / output cell is also reduced. However, since the size of the pad opening is determined by the wire bonding technique or the probe test technique, the pad protrudes from the input / output cell, which causes a problem of chip area overhead.

従って、チップ面積の縮小化に伴って、必要な面積を持ったパッドの領域を確保しつつ、オーバヘッドの問題を解消することが望ましい。   Therefore, it is desirable to solve the overhead problem while securing a pad area having a necessary area as the chip area is reduced.

本発明は上記事情に鑑み、チップ面積の縮小化に対応するべく、必要な面積を持ったパッドの領域を確保しつつ、オーバヘッドの問題を解消する工夫が施された半導体装置を提供することを目的とする。   In view of the above circumstances, the present invention provides a semiconductor device that has been devised to solve the overhead problem while securing a pad area having a necessary area in order to cope with a reduction in chip area. Objective.

上記目的を達成する本発明の半導体装置は、
入出力セル上にパットが形成された半導体装置において、
上記半導体装置の中央部に設けられ、内部回路が形成された内部回路領域と、
長方形状の一方の短辺が上記内部回路領域の各辺と対向して順次並んで設けられた、上記内部回路と外部との間で信号の入出力を担う複数の入出力セルと、
上記半導体装置の外部との間でワイヤにより電気的に接続されるワイヤボンディング部と動作確認用のプローブ針が当てられるプローブ部とを有し、上記入出力セル上に重なり、かつその各入出力セルの長辺に対して長辺が垂直に交わるように千鳥配列された複数のパッドとを備えたことを特徴とする。 The semiconductor device of the present invention that achieves the above object provides:
In a semiconductor device in which a pad is formed on an input / output cell,
An internal circuit region provided in a central portion of the semiconductor device, in which an internal circuit is formed;
A plurality of input / output cells for inputting / outputting signals between the internal circuit and the outside, wherein one short side of the rectangular shape is sequentially arranged facing each side of the internal circuit region,
A wire bonding portion electrically connected to the outside of the semiconductor device by a wire, and a probe portion to which a probe needle for operation confirmation is applied, which overlaps with the input / output cell and each input / output thereof; And a plurality of pads arranged in a staggered manner so that the long sides intersect perpendicularly to the long sides of the cells.

本発明によれば、必要な面積を持ったパッドの領域を確保しつつ、チップ面積のオーバヘッドの解消が図られる。その結果、チップ面積の縮小化が実現される。   According to the present invention, it is possible to eliminate a chip area overhead while securing a pad area having a necessary area. As a result, the chip area can be reduced.

以下図面を参照して本発明の実施の形態を説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１は、本発明の第１の実施形態である半導体装置の平面図である。   FIG. 1 is a plan view of a semiconductor device according to the first embodiment of the present invention.

この半導体装置１は、半導体パッケージの基板上にその半導体チップが乗せられた後に内部配線として使われるリードフレームとワイヤボンディングされ、その半導体チップがモールド樹脂で包み込まれるなどして製造されるものである。   The semiconductor device 1 is manufactured by placing a semiconductor chip on a substrate of a semiconductor package, wire bonding with a lead frame used as an internal wiring, and wrapping the semiconductor chip with a mold resin. .

この半導体装置１の中央部には、内部回路が形成された内部回路領域１１が設けられている。また、この半導体装置１は半導体装置１の外部との間で信号の入出力を担う複数の入出力セル１２を備えており、長方形状の入出力セル１２の一方の短辺が、内部回路領域１１の各辺と対向して順次並んで設けられている。   In the central portion of the semiconductor device 1, an internal circuit region 11 in which an internal circuit is formed is provided. Further, the semiconductor device 1 includes a plurality of input / output cells 12 for inputting / outputting signals to / from the outside of the semiconductor device 1, and one short side of the rectangular input / output cell 12 is an internal circuit region. 11 are arranged side by side so as to face each side.

図２は、本発明の半導体装置の第１実施形態の部分拡大平面図である。   FIG. 2 is a partially enlarged plan view of the first embodiment of the semiconductor device of the present invention.

図２は、図１に示すＡの部分を拡大したものである。   FIG. 2 is an enlarged view of a portion A shown in FIG.

この入出力セル１２上には、入出力セル１２上に重なり、かつその各入出力セル１２の長辺に対して長辺が垂直に交わるように千鳥配列された複数のパッド１３が設けられている。   On this input / output cell 12, a plurality of pads 13 are provided which overlap with the input / output cell 12 and are arranged in a staggered manner so that the long side of the input / output cell 12 intersects the long side perpendicularly. Yes.

このパッド１３は、半導体装置１の外部に対して金線などのワイヤにより電気的に接続されるワイヤボンディング部１４と動作確認用のプローブ針が当てられるプローブ部１５とを備えている。また、このパッド１３は、入出力セル１２との間で信号をやり取りをする信号回線部１６も備えている。   The pad 13 includes a wire bonding portion 14 that is electrically connected to the outside of the semiconductor device 1 by a wire such as a gold wire and a probe portion 15 to which a probe needle for operation confirmation is applied. The pad 13 also includes a signal line unit 16 that exchanges signals with the input / output cell 12.

次に、本発明の一実施形態である半導体装置１について比較例を用いて説明する。
図３は、入出力セルの長辺に対して、パッドの長辺が平行になるように千鳥状に配列された場合の部分拡大図である。 Next, the semiconductor device 1 which is one embodiment of the present invention will be described using a comparative example.
FIG. 3 is a partially enlarged view when the long sides of the pads are arranged in a staggered manner so that the long sides of the pads are parallel to the long sides of the input / output cells.

なお、図２と比較して、入出力セルの大きさ、パッドの大きさは同じである。ただし、信号回線部１６はパッドの短辺側に備えられている。   Compared with FIG. 2, the size of the input / output cell and the size of the pad are the same. However, the signal line section 16 is provided on the short side of the pad.

図３に示されるように、入出力セルの長辺に対して、パッドの長辺が平行になるように千鳥状に配列すると、パッド１３は入出力セル１２から食み出し、オーバヘッドが生じてしまう。   As shown in FIG. 3, when the pads are arranged in a staggered manner so that the long sides of the pads are parallel to the long sides of the input / output cells, the pads 13 protrude from the input / output cells 12 and overhead is generated. End up.

一方、図２のように、入出力セル１２の長辺に対して、パッド１３の長辺が垂直に交わるように千鳥状に配列することによって、チップ面積のオーバヘッドを解消することができる。   On the other hand, as shown in FIG. 2, the chip area overhead can be eliminated by arranging the pads 13 in a zigzag manner so that the long sides of the pads 13 intersect perpendicularly to the long sides of the input / output cells 12.

従って、本発明の第１の実施形態である、図１、図２に示す半導体装置１によれば、必要な面積を持ったパッドの領域を確保しつつ、チップ面積のオーバヘッドを解消することができる。その結果、チップ面積の縮小化が実現される。   Therefore, according to the semiconductor device 1 shown in FIGS. 1 and 2, which is the first embodiment of the present invention, it is possible to eliminate the chip area overhead while securing the pad area having the necessary area. it can. As a result, the chip area can be reduced.

次に、本発明の第２の実施形態である半導体装置について説明する。   Next, a semiconductor device according to a second embodiment of the present invention will be described.

図４は、本発明の半導体装置の第２実施形態の部分拡大平面図である。   FIG. 4 is a partially enlarged plan view of the second embodiment of the semiconductor device of the present invention.

第２実施形態の半導体装置では、第１実施形態の半導体装置に比較して、入出力セルのピッチＬを狭めて、さらに入出力セルの数を増やすことを可能としている。なお、入出力セル１２と入出力セル１７とは、縦横の比率が異なるが面積は同じである。   In the semiconductor device of the second embodiment, as compared with the semiconductor device of the first embodiment, the pitch L of the input / output cells can be narrowed to further increase the number of input / output cells. The input / output cell 12 and the input / output cell 17 have the same area, although the aspect ratio is different.

この入出力セル１７の上には、図２と同様に、その入出力セル１７の上に重なり、かつその各入出力セル１７の長辺に対して長辺が垂直に交わるように千鳥配列された複数のパッド１３＿２が設けられている。   Similar to FIG. 2, the input / output cells 17 are overlapped on the input / output cells 17 and are arranged in a staggered manner so that the long sides of the input / output cells 17 intersect perpendicularly. A plurality of pads 13_2 are provided.

このパッド１３＿２は、パッド１３と同様に、半導体装置１の外部に対して金線などのワイヤにより電気的に接続されるワイヤボンディング部１４＿２と動作確認用のプローブ針が当てられるプローブ部１５＿２とを備えている。また、このパッド１３＿２は、入出力セル１７との間で信号をやり取りをする信号回線部１６＿２を備えている。   Like the pad 13, the pad 13_2 includes a wire bonding portion 14_2 electrically connected to the outside of the semiconductor device 1 by a wire such as a gold wire and a probe portion 15_2 to which a probe needle for operation confirmation is applied. I have. The pad 13_2 includes a signal line portion 16_2 for exchanging signals with the input / output cell 17.

第２の実施形態の半導体装置では、入出力セル１７のピッチＬを狭めて高密度化を図ったため、チップ面積がパッドにより決定されないようパッドの配置を最適化しなければならない。そこで、入出力セル１７の長辺に対して長辺が垂直に交わるように千鳥状にパッド１３＿２を３列に配列することで高密度化に対応させた構成としている。この結果、パッド１３＿２が入出力セル１７から食み出すおそれは取り除かれる。   In the semiconductor device of the second embodiment, the pitch L of the input / output cells 17 is narrowed to increase the density. Therefore, the arrangement of the pads must be optimized so that the chip area is not determined by the pads. Thus, the pads 13_2 are arranged in three rows in a staggered manner so that the long sides intersect perpendicularly with respect to the long sides of the input / output cell 17, thereby achieving a configuration corresponding to high density. As a result, the possibility that the pad 13_2 protrudes from the input / output cell 17 is eliminated.

従って、本発明の第２の実施形態である、この半導体装置によれば、必要な面積を持ったパッドの領域を確保しつつ、オーバヘッドの解消が図られる。その結果、チップ面積の縮小化が実現される。   Therefore, according to the semiconductor device according to the second embodiment of the present invention, overhead can be eliminated while securing a pad area having a necessary area. As a result, the chip area can be reduced.

以上説明したように、本発明によれば、必要な面積を持ったパッドの領域を確保しつつ、オーバヘッドを防ぐ工夫が施された半導体装置を提供することができる。   As described above, according to the present invention, it is possible to provide a semiconductor device that is devised to prevent overhead while securing a pad area having a necessary area.

本発明の第１の実施形態である半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment of the present invention. 本発明の半導体装置の第１実施形態の部分拡大平面図である。1 is a partially enlarged plan view of a first embodiment of a semiconductor device of the present invention. 入出力セルの長辺に対して、パッドの長辺が平行になるように千鳥状に配列された場合の部分拡大図である。It is the elements on larger scale at the time of arranging in a zigzag form so that the long side of a pad may become parallel to the long side of an input-output cell. 本発明の半導体装置の第２実施形態の部分拡大平面図である。It is the elements on larger scale of a 2nd embodiment of a semiconductor device of the present invention.

符号の説明Explanation of symbols

１ 半導体装置
１１ 内部回路領域
１２ 入出力セル
１３、１３＿２ パッド
１４、１４＿２ ワイヤボンディング部
１５、１５＿２ プローブ部
１６、１６＿２ 信号回線部
１７ 入出力セル
Ｌ ピッチ
DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Internal circuit area 12 Input / output cell 13, 13_2 Pad 14, 14_2 Wire bonding part 15, 15_2 Probe part 16, 16_2 Signal line part 17 Input / output cell L Pitch

Claims (1)

入出力セル上にパットが形成された半導体装置において、
前記半導体装置の中央部に設けられ、内部回路が形成された内部回路領域と、
長方形状の一方の短辺が前記内部回路領域の各辺と対向して順次並んで設けられた、前記内部回路と外部との間で信号の入出力を担う複数の入出力セルと、
前記半導体装置の外部との間でワイヤにより電気的に接続されるワイヤボンディング部と動作確認用のプローブ針が当てられるプローブ部とを有し、前記入出力セル上に重なり、かつ該各入出力セルの長辺に対して長辺が垂直に交わるように千鳥配列された複数のパッドとを備えたことを特徴とする半導体装置。 In a semiconductor device in which a pad is formed on an input / output cell,
An internal circuit region provided in a central portion of the semiconductor device, in which an internal circuit is formed;
A plurality of input / output cells for inputting / outputting signals between the internal circuit and the outside, wherein one short side of the rectangular shape is sequentially arranged to face each side of the internal circuit region,
A wire bonding portion electrically connected to the outside of the semiconductor device by a wire and a probe portion to which a probe needle for operation confirmation is applied, and overlaps the input / output cell, and the input / output A semiconductor device comprising a plurality of pads arranged in a staggered manner so that the long sides intersect perpendicularly to the long sides of the cells.
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WO2009075149A1 (en) * 2007-12-10 2009-06-18 Toyota Jidosha Kabushiki Kaisha Semiconductor device
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JP2019062243A (en) * 2019-01-28 2019-04-18 ルネサスエレクトロニクス株式会社 Semiconductor chip
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WO2009075149A1 (en) * 2007-12-10 2009-06-18 Toyota Jidosha Kabushiki Kaisha Semiconductor device
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