TWI236323B - Fabricating process of circuit board with embedded passive component - Google Patents

Abstract

A fabricating process of circuit board with embedded passive component is described. The process comprises few steps. First, a conductive layer including a first surface and a second surface opposing to the first surface is provided. Moreover, the conductive layer has first through holes, which are passing through the conductive layer, respectively. At least one material layer is forming on the first surface. A multi-layer circuit unit including second through holes is provided, and the locations of the second through holes are corresponding to the locations of the first through holes, respectively. The conductive layer and the multi-layer circuit unit are orientating with each other by the first through holes and the second through holes, while the first surface of the conductive layer is facing a surface of the multi-layer circuit unit, and the material layer is between the multi-layer circuit unit and the conductive layer. The conductive layer is laminated to the multi-layer circuit unit. The conductive layer is patterning to form a conductive pattern.

Description

1236323 五、發明說明（1) 【發明所屬之技術領域】 本發明是有關於一種電路板製程，且特別是有關於一 種具有埋入式被動元件(embedded passive component ) 之電路板製程。 【先前技術】 由於電子產品的積集度（integration)越來越高， 應用於高積集度之電子產品的電路板，其線路層也由單 層、2層而變為6層、8層，甚至到10層以上，以使電子元 件能夠更密集的裝設於印刷電路板上。一般而言，最常見 之電路板製程係為疊層法（lamination process)，當利 用疊層法來製作電路板時，各個線路層及絕緣層之間的對 位精度必須必須獲得良好的控制。因此，在電路板製程 中，通常是在各線路層所在之絕緣層上形成多個對位記 號，並利用這些對位記號來定位這些絕緣層及其表面之一 或兩層線路層，接著壓合這些絕緣層及這些線路層，使得 這些線路層及這些絕緣層成為多層電路板或電路板半成 品。 請參照圖1 A至圖1 B，其繪示習知的多層印刷電路板製 程之剖面示意圖。請參照圖1 A，首先提供一内層基板1 0， 而内層基板1 0包括一絕緣層1 2、二線路層1 4與一對位記號 1 6，其中二線路層1 4分別配置於絕緣層1 2之兩表面上，而 對位記號1 6係位於絕緣層1 2之一表面上。然後，於内層基 板1 0之兩側分別配置一第一基板2 0與一第二基板3 0，而第 一基板20與第二基板30分別具有絕緣層22與32、線路層241236323 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a circuit board process, and more particularly, to a circuit board process with embedded passive components. [Previous technology] As the integration of electronic products is getting higher and higher, the circuit layers used in high-integration electronic products' circuit boards have also been changed from single-layer and 2-layer to 6-layer and 8-layer. , Even to more than 10 layers, so that electronic components can be more densely mounted on printed circuit boards. In general, the most common circuit board manufacturing process is the lamination process. When the lamination method is used to make a circuit board, the alignment accuracy between each circuit layer and the insulation layer must be well controlled. Therefore, in the circuit board manufacturing process, multiple alignment marks are usually formed on the insulation layer where each circuit layer is located, and these alignment marks are used to locate these insulation layers and one or two circuit layers on their surfaces, and then press Combining these insulating layers and these circuit layers makes these circuit layers and these insulating layers a multilayer circuit board or a semi-finished circuit board. Please refer to FIG. 1A to FIG. 1B, which are schematic cross-sectional views of a conventional multilayer printed circuit board manufacturing process. Referring to FIG. 1A, an inner layer substrate 10 is first provided, and the inner layer substrate 10 includes an insulating layer 1, 2, two circuit layers 14, and a pair of bit marks 16, wherein two circuit layers 14 are respectively disposed on the insulating layer. 12 are on both surfaces, and the alignment mark 16 is on one of the surfaces of the insulating layer 12. Then, a first substrate 20 and a second substrate 30 are respectively disposed on both sides of the inner substrate 10, and the first substrate 20 and the second substrate 30 have insulating layers 22 and 32, and a circuit layer 24, respectively.

12914twf.ptd 第7頁 1236323 五、發明說明（2) 與3 4及第—對位記號 第一對位記號2 6與第一：第二對位記號3 6 (對位記號1 6、 示），而線路層^4與^ f位記號3 6之俯視圖如圓形區域所 之一表面上，且線^ ^ :對位記號26係配置於第一基板2〇 基板3 0之—表面上。q /與第二對位記號3 6係配置於第二 記號16、第一基板2〇 =後，藉由X光及内層基板1〇之對位 二對位記號36完成内眉第一對位記號26與第二基板30之第 之對位步驟。請參照^ ^板1 〇、第一基板20與第二基板3〇 第一基板20與第二基/ β ’對於完成對位之内層基板1 〇、 以形成一多層印刷ϋ30進行熱壓合與固化（curing )， 值得一提的是，對板或印刷電路板半成品。 對位記號3 6均是使用哚位圯號1 6、第一對位記號2 6與第二 號1 6與線路層丨4、第’一墨印刷的方式所形成，所以對位記 位§己^虎3 6與線路層3 4 子位°己號2 6與線路層2 4，及第二對 x光與對位記號1 6、第t間均分別具有一對位誤差。當使用 進行内層基板1〇、第一一對位記號26及第二對位記號36來 (如圖1 B之圓形區域亡板2 0與第二基板3 0之對位程序時 位誤差將不斷地累積。=),上述之對位記號所產生的對 些具有線路層之基柘μ f電路板的線路層數目增加，則這 加。 汉上的對位記號所累積的誤差也會增 另:屈隨著電路板層數的增加， (如RC延遲效應）也逐漸 =电性性為 被動元件，以改善電路板的電性性質。n jgj 性數值之規格化被動元件可能無法完全符合特別的電路設 12914twf.ptd 第8頁 1236323 五、發明說明（3) 計，故可將被動元件直接製作於電路板之内部，因此，在 電路板内部之被動元件係可隨著電路板之佈線設計及材料 選擇等來調整電路板電性數值。 【發明内容】 有鑒於此，本發明的目的就是在提供一種具有埋入式 被動元件之電路板製程，以增加多層電路板之對位精度。 基於上述目的或其他目的，本發明提出一種具有埋入 式被動元件之電路板製程，其係例如包括下列步驟。首 先，提供一導電層，其例如具有一第一面及對應之一第二 面，其中第一面例如具有至少一元件區域，且導電層例如 更具有多個第一貫孔，其係分別貫穿導電層。然後，形成 至少一材料層於第一面之元件區域上。之後，提供一多層 線路單元，其例如具有多個第二貫孔，其位置係分別對應 於這些第一貫孔之位置。經由這些第一貫孔及這些第二貫 孔來定位導電層與多層線路單元，而導電層之第一面係面 向多層線路單元之一表面，且材料層係位於多層線路單元 與導電層之間。接者，壓合導電層至多層線路單元。最 後，圖案化此導電層，以形成一第一導電圖案。 依照本發明較佳實施例所述之具有埋入式被動元件之 電路板製程，導電層例如為一銅馆層（c 〇 p p e r f 〇 i 1 )。 依照本發明較佳實施例所述之具有埋入式被動元件之 電路板製程，上述之形成材料層的方式例如包括網版印刷 (screen printing ) 〇 依照本發明較佳實施例所述之具有埋入式被動元件之12914twf.ptd Page 7 1236323 V. Description of the invention (2) and 3 4 and the first-registration mark The first registration mark 2 6 and the first: the second registration mark 3 6 (the registration mark 1 6) The top view of the circuit layer ^ 4 and ^ f bit mark 36 is like a surface of a circular area, and the line ^: registration mark 26 is arranged on the surface of the first substrate 20 and the substrate 30. q / with the second alignment mark 3 6 is arranged at the second mark 16 and the first substrate 20 =, then the first alignment of the inner eyebrow is completed by the X-ray and the second alignment mark 36 of the inner substrate 10 The alignment step between the mark 26 and the second substrate 30. Please refer to ^^ 1, the first substrate 20 and the second substrate 30, the first substrate 20 and the second substrate / β 'For the inner substrate 1 which has completed the alignment, to form a multi-layer printing ϋ30 for thermocompression bonding. With curing, it is worth mentioning that the board or the semi-finished product of the printed circuit board. The registration marks 3 6 are all formed by using the indole number 圯 16, the first registration mark 26 and the second number 16 and the circuit layer 丨 4, and the first ink printing method, so the registration § The sub-positions of the tiger 3 6 and the circuit layer 3 4 ° the number 2 6 and the circuit layer 2 4 and the second pair of x-rays and the alignment mark 16 and t each have a pair of bit errors. When using the alignment process of the inner substrate 10, the first pair of registration marks 26 and the second registration mark 36 (as shown in Figure 1B, the alignment error in the circular area of the dead plate 20 and the second substrate 30 will result in an alignment error. Accumulate continuously. =), The number of circuit layers for the base 柘 μ f circuit board with circuit layers generated by the above-mentioned alignment marks is increased, then this is added. The accumulative error of the alignment marks on the Chinese will also increase. In addition, with the increase of the number of circuit board layers, (such as the RC delay effect) gradually = electrical properties are passive components to improve the electrical properties of the circuit board. n jgj The normalized passive component of the numerical value may not fully meet the special circuit design. 12914twf.ptd Page 8 1236323 V. Description of the invention (3) Design, so the passive component can be made directly inside the circuit board. Therefore, in the circuit The passive components inside the board can be adjusted with the wiring design and material selection of the circuit board. [Summary of the Invention] In view of this, the object of the present invention is to provide a circuit board manufacturing process with embedded passive components to increase the alignment accuracy of a multilayer circuit board. Based on the foregoing or other objectives, the present invention provides a circuit board manufacturing process with embedded passive components, which includes, for example, the following steps. First, a conductive layer is provided, which has, for example, a first surface and a corresponding second surface, wherein the first surface has at least one element region, and the conductive layer further has a plurality of first through holes, respectively. Conductive layer. Then, at least one material layer is formed on the element area of the first surface. Thereafter, a multilayer circuit unit is provided, which has, for example, a plurality of second through holes, the positions of which correspond to the positions of the first through holes, respectively. The first through holes and the second through holes are used to locate the conductive layer and the multilayer circuit unit. The first side of the conductive layer faces a surface of the multilayer circuit unit, and the material layer is located between the multilayer circuit unit and the conductive layer. . Then, the conductive layer is laminated to the multilayer circuit unit. Finally, the conductive layer is patterned to form a first conductive pattern. According to the process for manufacturing a circuit board with an embedded passive component according to a preferred embodiment of the present invention, the conductive layer is, for example, a copper pavilion layer (c0 p p r r f oi i 1). According to the manufacturing process of the circuit board with embedded passive components according to the preferred embodiment of the present invention, the above-mentioned method for forming the material layer includes, for example, screen printing. Of passive components

12914twf.ptd 第9頁 1236323 五、發明說明（4) 電路板製程，第一導電圖案例如更具有一第一電極及相互 電性隔絕之一第二電極，其係分別連接至材料層，且材料 層之材質例如包括電容材料。 依照本發明較佳實施例所述之具有埋入式被動元件之 電路板製程，上述之在形成材料層之步驟後，例如更包括 形成至少一第一電極層於材料層及元件區域上，且第一導 電圖案例如更具有一第一電極與一第二電極，其中第一電 極係連接至電極層，而至少部分之電極層及至少部分之第 二電極係相互重疊，且材料層之材料例如包括介電材料。 此外，形成電極層之方式例如包括網版印刷。 依照本發明較佳實施例所述之具有埋入式被動元件之 電路板製程，上述之多層線路單元例如具有一第二導電圖 案，其配置於多層線路單元之表面，且在壓合導電層至多 層線路單元之步驟中，例如更包括提供一絕緣層，並將絕 緣層配置於導電層與多層線路單元之間，再將導電層經由 絕緣層而壓合至多層線路單元之表面。此外，絕緣層例如 為一半固化樹脂片（prepreg)。 基於上述，本發明之具有埋入式被動元件之電路板製 程直接採用第一貫孔作為第一電極與一第二電極於網板印 刷時對位之用，並且壓合時乃直接採用該貫孔作為各層之 對位記號，以進行各層之對位程序，因此本發明能夠減少 各層因對位記號所產生對位誤差的累積。此外，本發明更 可製作埋入式（embedded)之電阻元件、電感元件或電容 元件，以符合電路板的電路設計。12914twf.ptd Page 9 1236323 V. Description of the invention (4) The circuit board process, for example, the first conductive pattern has a first electrode and a second electrode which is electrically isolated from each other, which are respectively connected to the material layer, and the material The material of the layer includes, for example, a capacitor material. According to the manufacturing process of the circuit board with the embedded passive device according to the preferred embodiment of the present invention, after the step of forming the material layer, for example, the method further includes forming at least a first electrode layer on the material layer and the device region, and The first conductive pattern further has, for example, a first electrode and a second electrode, wherein the first electrode system is connected to the electrode layer, and at least part of the electrode layer and at least part of the second electrode system overlap each other, and the material of the material layer is, for example, Including dielectric materials. The method of forming the electrode layer includes, for example, screen printing. According to the process for manufacturing a circuit board with embedded passive components according to a preferred embodiment of the present invention, the above-mentioned multilayer circuit unit has, for example, a second conductive pattern, which is disposed on the surface of the multilayer circuit unit, and the conductive layer is laminated to The step of the multilayer circuit unit further includes, for example, providing an insulating layer, disposing the insulating layer between the conductive layer and the multilayer circuit unit, and pressing the conductive layer to the surface of the multilayer circuit unit through the insulating layer. In addition, the insulating layer is, for example, a prepreg. Based on the above, the manufacturing process of the circuit board with embedded passive components of the present invention directly uses the first through hole as the first electrode and a second electrode for alignment during screen printing, and directly uses the through hole during lamination. Holes are used as alignment marks of each layer to perform the alignment process of each layer. Therefore, the present invention can reduce the accumulation of alignment errors caused by the alignment marks in each layer. In addition, the present invention can also manufacture embedded resistance elements, inductance elements or capacitor elements to meet the circuit design of the circuit board.

12914twf.ptd 第10頁 1236323 五、發明說明（5) 易丨蓳；、讓本么明之上述和其他目的、特徵和優點能更明顯 說明如ί文特舉一較佳實施例，並配合所…，作詳細 【實施方式】 呈明參照圖2 Α至圖2 Ε，其繪示依照本發明較佳實施例之 ^ 2 Α埋^式巧動元件之電路板製程的剖面示意圖。請參照 三_ *首先提供一導電層1 1 0，而導電層1 1 0例如具有多個 ===孔UOd、一第一面110a及對應之一第二面110b，其 第一面U 0 a例如具有至少一元件區域丨丨〇 c，而這些第一 孔1 1 0 d係分別貫穿導電層1 1 0。然後，形成至少一材料 曰1/2〇於胃第一面110a之元件區域110c上（如圖2B所示）。 =後’提供一多層線路單元13〇 (如圖2C所示），而多層 ，路單元130例如具有多個第二貫孔13〇&，其中這些第二 =^13 0^之位置係分別對應於這些第一貫孔丨1〇d之位置。 此Ϊ 一 Ϊ '是’本實施例乃是經由這些第一貫孔1 i〇d及這 =f 一貝孔13 〇a來定位導電層110與多層線路單元130之間 線‘ ？位〇。此一外矣’導電層110之第一面11〇a係面向多層 單元之二ί面130b，且材料層120係位於多層線路 ，凡130之間。接者，壓合導電層"〇至多層線路單元i 3〇 』如圖2D所示）。最後，圖案化此導電層11〇，以一 第一導電圖案112 (如圖2E所示）。 請繼續參照圖2E，將這些第一貫孔丨丨“與這些 孔13〇a完成定位的方法例如是使用χ光或其他影像定位系 統。相較於習知技術之對位記號（如圖1β所示），本實施12914twf.ptd Page 10 1236323 V. Description of the invention (5) Yi 丨 蓳; Let the above and other objects, features and advantages of Benmeming be more clearly explained, such as a preferred embodiment, and cooperate with ... Detailed description [Embodiment] Referring to FIG. 2A to FIG. 2E, it shows a schematic cross-sectional schematic diagram of a circuit board manufacturing process of a 2A buried-type clever moving element according to a preferred embodiment of the present invention. Please refer to three_ * first provides a conductive layer 1 1 0, and the conductive layer 1 1 0 has, for example, a plurality of === holes UOd, a first surface 110a and a corresponding second surface 110b, the first surface U 0 of which a has, for example, at least one element region, and the first holes 1 1 0 d penetrate through the conductive layer 1 1 0, respectively. Then, at least one material, 1/20, is formed on the element region 110c of the first surface 110a of the stomach (as shown in FIG. 2B). = After 'provides a multi-layer circuit unit 13 (as shown in FIG. 2C), and a multi-layer, circuit unit 130, for example, has a plurality of second through-holes 130 & Corresponding to the positions of the first through holes 10d. This Ϊ Ϊ 'Yes' In this embodiment, the line between the conductive layer 110 and the multi-layer circuit unit 130 is located via the first through holes 1 iod and this = f y hole 13 oa. Bit 0. The first surface 11a of the outer conductive layer 110 is facing the second surface 130b of the multilayer unit, and the material layer 120 is located between the multiple lines 130 and 130. Then, the laminated conductive layer " 0 to the multilayer circuit unit i3o " is shown in FIG. 2D). Finally, the conductive layer 110 is patterned with a first conductive pattern 112 (as shown in FIG. 2E). Please continue to refer to FIG. 2E. The method of positioning the first through holes 丨 丨 with these holes 13a is, for example, using χ light or other image positioning systems. Compared to the alignment marks of the conventional technology (see FIG. 1β) Shown), this implementation

第11頁 12914twf.ptd 1236323 五 發明說明（6) ，广n\直夕接藉由第一貫孔110d及第二貫孔1 ^ ‘誤差的夕累層藉線路單元13〇之間的對位，'其結0果β ί進行導電 導電材料声'，、而此：二=電層110例如為-麵夠減少對 exponent )的配設區。值得注意的是破動^件（passive f $ =如網版印刷。另外，多層線路單元料層120之 ，電路板之半成品。再者，形成第如是多層 f疋採用機械鑽孔（drill )或是雷射鐵孔，d的方法例 在形成材料層120之方式例如網版印亡，f且鑽孔乃 :第-貫孔1 1 Od為網版印刷對位孔。而在别進行〜版入印刷皆 業之前，這些第二貫孔丨3 〇a就已經 =a對位作 二：，1 3 0a能夠電性連接至少二層位於多)吏Ί第 之内部的線路層（未繪示）。 、、路早7G 1 3 0 請參照圖3，其繪示依照本發明較佳 入式被動元件之電路板製程的剖面 A _ 有埋 2C内容相似，其不同之處在於‘ I 7° j f内容與圖 tl32， =面13Gb ’且在壓合導電層11()至多層線路單元i3〇 驟中，例如更包括提供一絕緣層丨4〇，並將絕 於導電層⑴與多層線料元13()之間，㈣導a = =層140而壓合至多層線路單元13〇之表面曰二 付注意的是，在壓合的步驟中，本實施例同樣使用第一# 孔ll〇d及對應之第二貫孔i30a來定位導電層11〇與多層線Page 1112914twf.ptd 1236323 Explanation of the five inventions (6), Guang n \ Zhi Xi is connected by the first through hole 110d and the second through hole 1 ^ 'The error of the Xilei layer borrow line unit 13 Alignment "Its result 0 is the result of conducting conductive material sound", and this: two = the electrical layer 110 is, for example,-the surface is enough to reduce the provision area for exponent). It is worth noting that the broken pieces (passive f $ = such as screen printing. In addition, the multilayer circuit unit material layer 120, the semi-finished product of the circuit board. Furthermore, the formation of such a multilayer f is using mechanical drilling (drill) or It is a laser iron hole. The method of d is the method of forming the material layer 120 such as screen printing, and f is drilling: the first through hole 1 1 Od is a screen printing registration hole. Before entering the printing industry, these second through holes 丨 3 〇a = a counter-position two: 1, 3 0a can be electrically connected to at least two layers located in more than one) the internal circuit layer (not shown) ). 。, Road early 7G 1 3 0 Please refer to FIG. 3, which shows the cross-section A of the circuit board manufacturing process of the preferred passive component according to the present invention. The content of 2C is similar, the difference is in the content of 'I 7 ° jf And FIG. T132, = plane 13Gb 'and in the step of laminating the conductive layer 11 () to the multilayer circuit unit i30, for example, it further includes providing an insulating layer 丨 40, and will be insulated from the conductive layer 多层 and the multilayer wire material element 13 Between (), ㈣a == layer 140 and the second surface of the multilayer circuit unit 13 is laminated. Note that in the step of lamination, the first embodiment also uses the first #hole 110d and Corresponding to the second through hole i30a to locate the conductive layer 11 and the multilayer line

1236323 五、發明說明（7) 路單元1 3 0之間的相對位置。此外，本圖與圖2 c之元件區 域1 1 0 c例如是電阻、電感或電容元件區域，复八另】日月士 請參照圖4，其繪示依照本發明較佳實施例之且 入式被動元件之電路板製程應用於電阻元件的却丨/\立 圖。本圖内容與圖2E内容相似，其不同之處在於· 之 第一導電圖案112例如更具有一第一導線u 及相·互電"性 隔絕之一第二導線1 1 2 b，其係分別連接至材料層丨3 〇。另 外，材料層1 2 0之材質例如包括電阻材料。所以' 二 線112a、第二導線11 2b與材料層120能夠構成一電 =二同理請參照圖4 ’依其相同原理而改採電感材料兀則 月匕夠構成一電感元件。 、 請參照圖5 A至圖5B，其繪示依照本發明較佳 入ίί:元件t電路&製程應用㈣容元：的剖面 =料層12…驟後，例如更包括形成门至之/一在電於桎= L材B料rVV件區域⑴以（如圖以所示）I來日 ，第一導電圖案112 / :，、、、 而至少部分之電i I第一電極1 12a係連接至電極層150， 互重疊，用以形;層=及//部分之第二電極112b係相 包括網版印刷，Ϊ，。此外、，形成電極層丨5〇之方式例如 因此，電極層15 η 乂第貫通孔11 〇 d為網版印刷對位孔。 、第一電極112a、第二電極1121)與材科1236323 V. Description of the invention (7) The relative position between the road units 1 3 0. In addition, the element area 1 1 0 c of this figure and FIG. 2 c is, for example, a resistance, inductance, or capacitance element area. For more details, please refer to FIG. 4, which shows a preferred embodiment according to the present invention. The circuit board process of the passive components is applied to the resistive components. The content of this figure is similar to that of FIG. 2E. The difference is that the first conductive pattern 112 has, for example, a first wire u and a second wire 1 1 2 b which is isolated from each other. Connected to the material layers 丨 30 respectively. The material of the material layer 120 includes, for example, a resistive material. Therefore, the second wire 112a, the second wire 11 2b, and the material layer 120 can form an electric circuit = the same reason, please refer to FIG. 4 ′ According to the same principle, the inductive material is changed. Therefore, the moon can be used to form an inductive element. Please refer to FIG. 5A to FIG. 5B, which illustrate a preferred embodiment of the present invention: the element t circuit & process application: capacity section: section = material layer 12 ... After the step, for example, it also includes forming a gate to / First, in the area of electricity 桎 = L material B material rVV parts (as shown in the figure) I, the first conductive pattern 112 /: ,,,, and at least part of the electricity i I the first electrode 1 12a series The second electrode 112b connected to the electrode layer 150 overlaps each other to form a layer; and the phase of the second electrode 112b includes screen printing. In addition, the method of forming the electrode layer 5o is, for example, the electrode layer 15 η through the first through hole 11 d is a screen printing registration hole. , First electrode 112a, second electrode 1121) and Materials Division

1236323 五、發明說明（8) 層1 2 0能夠構成一電容元件。 綜上所述，本發明之具有埋入式被動元件之電路板製 程具有下列優點： 一、 相較於習知技術所採用之對位記號的方法，本發 明之具有埋入式被動元件之電路板製程直接採用各層上之 貫孔作為各層之對位記號，以進行各層之對位程序，因此 本發明之具有埋入式被動元件之電路板製程能夠減少對位 誤差的累積。 二、 本發明之具有埋入式被動元件之電路板製程更可 形成埋入式（embedded)之電阻元件、電感元件或電容元 件，以符合電路板的電路設計。 三、 在埋入式之電阻元件、電感元件或電容元件中， 形成電阻元件、電感元件或電容元件材料層之方法為網版 印刷，採先鑽（第一貫通孔）後印法，即網版印刷前已鑽 完第一貫通孔，作為各層網版印刷之對位孔，因此本發明 之具有埋入式被動元件之電路板製程能夠減少網版印刷對 位誤差的累積。所以本發明將可降低具有埋入式被動元件 之印刷電路板的製作成本。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。1236323 V. Description of the invention (8) The layer 1 2 0 can constitute a capacitive element. In summary, the circuit board manufacturing process with embedded passive components of the present invention has the following advantages: 1. Compared with the alignment mark method used in the conventional technology, the circuit with embedded passive components of the present invention The board process directly uses the through holes on each layer as the alignment marks of each layer to perform the alignment process of each layer. Therefore, the circuit board process with embedded passive components of the present invention can reduce the accumulation of alignment errors. 2. The manufacturing process of the circuit board with embedded passive components of the present invention can form embedded resistance components, inductance components, or capacitor components to meet the circuit design of the circuit board. 3. In the embedded resistance element, inductance element or capacitance element, the method of forming the material layer of the resistance element, inductance element or capacitance element is screen printing, which is firstly drilled (first through hole) and then printed, that is, the screen The first through hole has been drilled before the lithographic printing, as the alignment holes for the screen printing of each layer. Therefore, the circuit board manufacturing process with embedded passive components of the present invention can reduce the accumulation of screen printing alignment errors. Therefore, the present invention can reduce the manufacturing cost of printed circuit boards with embedded passive components. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

12914twf.ptd 第14頁 1236323 圖式簡單說明 圖1 A至圖1 B繪示習知的多層印刷電路板製程之剖面示 意圖。 圖2 A至圖2 E繪示依照本發明較佳實施例之具有埋入式 被動元件之電路板製程的剖面示意圖。 圖3繪示依照本發明較佳實施例之具有埋入式被動元 件之電路板製程的剖面示意圖。 圖4繪示依照本發明較佳實施例之具有埋入式被動元 件之電路板製程應用於電阻元件的剖面示意圖。 圖5 A至圖5 B繪示依照本發明較佳實施例之具有埋入式 被動元件之電路板製程應用於電容元件的剖面示意圖。 【圖式標示說明】 1 0 :内層基板 12、22、32、40、140 :絕緣層 1 4、2 4、3 4 :線路層 1 6 :對位記號 2 0 :第一基板 2 6 :第一對位記號 3 0 :第二基板 3 6 :第二對位記號 1 1 0 :導電層 1 1 0 a :第一面 1 1 0 b ··第二面 1 1 0 c :元件區域 1 1 0 d :第一貫孔12914twf.ptd Page 14 1236323 Brief Description of Drawings Figures 1A to 1B are schematic cross-sectional views of a conventional multilayer printed circuit board manufacturing process. 2A to 2E are schematic cross-sectional views illustrating a process of manufacturing a circuit board with an embedded passive component according to a preferred embodiment of the present invention. FIG. 3 is a schematic cross-sectional view illustrating a manufacturing process of a circuit board with embedded passive components according to a preferred embodiment of the present invention. FIG. 4 is a schematic cross-sectional view illustrating a process of applying a circuit board process with embedded passive elements to a resistive element according to a preferred embodiment of the present invention. 5A to 5B are schematic cross-sectional views showing a process of applying a circuit board with embedded passive elements to a capacitor element according to a preferred embodiment of the present invention. [Illustration of Graphical Symbols] 10: Inner substrates 12, 22, 32, 40, 140: Insulating layers 1, 2, 4, 3, 4: Circuit layers 1 6: Registration mark 2 0: First substrate 2 6: No. Pair mark 3 0: Second substrate 36 6: Second mark 1 1 0: Conductive layer 1 1 a: First surface 1 1 0 b · Second surface 1 1 0 c: Element area 1 1 0 d: first through hole

12914twf.ptd 第15頁 1236323 圖式簡單說明 112： 1 12a 1 12b 120 130 132 130a 130b 150 第一導電圖案 :第一電極 :第二電極 材料層 多層線路單元 第二導電圖案 :第二貫孔 :表面 電極層12914twf.ptd Page 15 1236323 Brief description of the drawing 112: 1 12a 1 12b 120 130 132 130a 130b 150 First conductive pattern: first electrode: second electrode material layer multilayer circuit unit second conductive pattern: second through hole: Surface electrode layer

12914twf.ptd 第16頁12914twf.ptd Page 16

Claims (1)

1236323 _案號 93103594_年月日__ 六、申請專利範圍 之電路板製程，其中在形成該材料層之步驟後，更包括形 成至少一電極層於該材料層及該元件區域上，且該第一導 電圖案更具有一第一電極與一第二電極，其中該第一電極 係連接至該電極層，而至少部分之該電極層及至少部分之 該第二電極係相互重疊，且該材料層之材料包括介電材 料。 6 .如申請專利範圍第5項所述之具有埋入式被動元件 之電路板製程，其中形成該電極層之方式包括網版印刷。 7 .如申請專利範圍第1項所述之具有埋入式被動元件 之電路板製程，其中該多層線路單元具有一第二導電圖 案，其配置於該多層線路單元之該表面，且在壓合該導電 層至該多層線路單元之步驟中，更包括提供一絕緣層，並 將該絕緣層配置於該導電層與該多層線路單元之間，再將 該導電層經由該絕緣層而壓合至該多層線路單元之該表 面。 8 .如申請專利範圍第7項所述之具有埋入式被動元件 之電路板製程，其中該絕緣層係為一半固化樹脂片。1236323 _ Case number 93103594_ 年月 日 __ VI. The patented circuit board process, wherein after the step of forming the material layer, it further includes forming at least one electrode layer on the material layer and the element area, and the The first conductive pattern further has a first electrode and a second electrode, wherein the first electrode system is connected to the electrode layer, and at least part of the electrode layer and at least part of the second electrode system overlap each other, and the material The material of the layer includes a dielectric material. 6. The process for manufacturing a circuit board with an embedded passive component as described in item 5 of the scope of patent application, wherein the method of forming the electrode layer includes screen printing. 7. The process for manufacturing a circuit board with an embedded passive component as described in item 1 of the scope of the patent application, wherein the multilayer circuit unit has a second conductive pattern, which is disposed on the surface of the multilayer circuit unit, and is laminated. The step from the conductive layer to the multilayer circuit unit further includes providing an insulating layer, disposing the insulating layer between the conductive layer and the multilayer circuit unit, and pressing the conductive layer to the conductive layer via the insulating layer. The surface of the multilayer circuit unit. 8. The process for manufacturing a circuit board with embedded passive components as described in item 7 of the scope of the patent application, wherein the insulating layer is a semi-cured resin sheet. 12914twf1.ptc 第18頁12914twf1.ptc Page 18