JP2722451B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2722451B2 JP2722451B2 JP62093519A JP9351987A JP2722451B2 JP 2722451 B2 JP2722451 B2 JP 2722451B2 JP 62093519 A JP62093519 A JP 62093519A JP 9351987 A JP9351987 A JP 9351987A JP 2722451 B2 JP2722451 B2 JP 2722451B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor chip
- bump
- wiring
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、パッケージによって封止する半導体チップ
を備えた半導体装置に関する。
〔従来の技術〕
近年、半導体装置の微細化ならびに多機能化に伴い、
電気信号の入出力端子（リード）数が増加している。
従来、この種の半導体装置は第４図に示すように構成
されている。これを同図に基づいて概略説明すると、同
図において、符号１で示すものは電極２を有し上方に開
口する箱状のピングリッドアレイ（以下、PGAと呼称す
る）パッケージ、３はこのPGAパッケージ１内に収納さ
れ周縁に多数の電極パッド４を有する半導体チップ、５
はこの半導体チップ３の電極パッド４とPGAGパッケージ
１の電極２とを接続する例えばA1等のワイヤである。ま
た、６は入出力信号を外部に取り出す外部端子としての
ピン、７は前記PGAパッケージ１の開口部を閉塞する蓋
体である。なお、前記PGAパッケージ１はセラミック製
の多層基板によって構成されている。
このように構成された半導体装置を第５図に示すプリ
ント基板８上に実装するには、ピン６をスルーホール8a
に挿通させた後、ランドパターン8bに半田付けすること
により行われる。
〔発明が解決しようとする課題〕
ところで、この種の半導体装置においては、ピン６が
スルーホール8aに挿通する構造であるため、ピン６のピ
ッチＰをスルーホール8aの最小ピッチ（1.8mm）以下の
寸法に設定することができず、PGAパッケージ１の小型
化ならびにプリント基板８の配線高密度化を図ることが
できないという問題があった。
本発明はこのような事情に鑑みなされたもので、パッ
ケージの小型化を図ることができると共に、回路基板の
配線密度を高めることができる半導体装置を提供するも
のである。
〔課題を解決するための手段〕
この発明にかかる半導体装置は、互いに反対側に位置
する第１及び第２の表面を有し、有機材料からなる積層
構造の回路基板と、前記第１の表面上に設けられた半導
体チップと、前記第２の表面上に設けられたバンプと前
記第１の表面上に設けられ、前記半導体チップに電気的
に接続された接続導体と、前記回路基板を貫通して設け
られ、前記接続導体と前記バンプとを電気的に接続する
内部配線とを備える。そして、前記内部配線の少くとも
一つが、第１乃至第３の部分を有する。前記第１の部分
は前記接続導体に接続された一端と、他端とを有し、前
記第１の表面側で前記回路基板の内部を前記回路基板の
厚み方向に延びる。前記第２の部分は前記バンプに接続
された一端と、他端とを有し、前記第２の表面近傍で前
記回路基板の内部を前記厚み方向に延びる。前記第３の
部分は前記第１の部分の前記他端と前記第２の部分の前
記他端とを接続する。そして前記第２の部分は前記第１
の部分よりも前記厚み方向と直交する方向において前記
半導体チップに近く設けられ、前記第１の部分及び前記
第２の部分が中実構造である。
〔作用〕
内部配線のうち、第１の表面に表れる第１の部分と、
第２の表面に表れる第２の部分とを、第１及び第２の表
面に平行な方向でずらせることができる。
第３の部分を設けることで、内部配線の第１及び第２
の部分の各々の長さは回路基板の厚さよりも短くするこ
とができる。
バンプが受ける機械的衝撃は、直接的にではなく、屈
曲した内部配線を介して接続導体に伝わる。
第１の部分及び第２の部分が中実構造であることで、
内部配線のヒートサイクル耐性は向上する。
〔実施例〕
第１図および第２図は本発明に係る半導体装置を示す
断面図と斜視図、第３図は第１図のＡ部分を拡大して示
す断面図である。これらの図において、符号11で示され
るものはチップ実装用の回路基板で、複数のセラミック
基板が積層されて形成されている。なお、この回路基板
11における図１および図３において上側となる表面を以
下において第１の表面といい、この第１の表面とは反対
側となる裏面を以下において第２の表面という。
そして、この第１の表面上には表面配線11aが設けら
れ、第２の表面上には外部端子としての多数のバンプ12
が設けられている。これらの表面配線11aとバンプ12と
は、回路基板11を貫通するように設けられた内部配線11
bによって電気的に接続されている。この内部配線11bは
第３図に示すように回路基板11の第１の表面から第２の
表面へとステップ状に形成されている。
詳述すると、内部配線11bはその何れもが、一端が表
面配線11aに接続されつつ回路基板11の上方（第１の表
面側）で厚み方向に延びる第１の部分と、一端がバンプ
12に接続されつつ回路基板11の下方（第２の表面側）で
厚み方向に延びる第２の部分と、第１の部分の他端と第
２の部分の他端とを厚み方向と垂直な方向（第１及び第
２の表面と平行な方向）に接続する第３の部分とで構成
されている。第２の部分の一端はバンプ設置部として第
２の表面に露呈し、このバンプ設置部上にバンプ12が設
けられている。第３の部分は、積層された回路基板11に
おいて、隣接する層の境界に設けることができる。
13はAu等のバンプ13aをの非接合側であって周辺部に
有する半導体チップで、回路基板11の第１の表面上に接
合されている。このバンプ13aは半導体チップ13の電極
として機能する。また、表面配線11aの接続部はバンプ1
3aより外側に距離をおいて位置するように形成されてい
る。
14はその中央部に窓14aを有するフィルム（TABテー
プ）で、回路基板11および半導体チップ13に接合されて
おり、一側にはバンプ13a,表面配線11aの接続部に各々
接続するインナーリード15aとアウターリード15bからな
る配線パターン15が接続導体として形成されている。
そして、フィルム14および半導体チップ13は保護部材
としてのパッケージ16によって樹脂封止されている。
このように構成された半導体装置においては、積層構
造の回路基板11の第１の表面上に半導体チップ13が設け
られ、第２の表面上にバンプ12が設けられ、半導体チッ
プ13と電気的に接続された配線パターン15が設けられ、
配線パターン15とバンプ12とを電気的に接続する内部配
線11bが回路基板11を貫通して設けられている。そして
内部配線11bの何れもが、第１乃至第３の部分を有す
る。第１の部分は配線パターン15に接続された一端と、
他端とを有し、第１の表面近傍で回路基板11の内部をそ
の厚み方向に延びる。第２の部分はバンプ12に接続され
た一端と、他端とを有し、第２の表面近傍で回路基板の
内部をその厚み方向に延びる。第３の部分は第１の部分
の他端と第２の部分の他端とを第１の表面と平行な方向
に延びて接続する。
そのため、内部配線11bのうち、第１の表面に表れる
第１の部鵜分と、第２の表面に表れる第２の部分とを、
第１及び第２の表面に平行な方向でずらせることができ
る。従ってアウターリード15bが半導体チップから遠く
離れたとしても、第２の部分を第１の部分よりも半導体
チップに近く設け、バンプ12間の寸法を1.8mmより小さ
く設定することができる。
第３の部分を設けることなく内部配線11bを構成した
場合にはその長さは回路基板11の厚さとなる。一方、第
３の部分を設けることで、内部配線11bの第１及び第２
の部分の各々の長さは、より短くすることができる。従
って、回路基板11と内部配線11bとの熱膨張差に起因す
る熱疲労（ヒートサイクル）に対してその耐性（ヒート
サイクル特性）を向上することができる。内部配線11b
の何れもがこのように耐性の向上した構成を有している
ので内部配線11bによる電気的接続の信頼性が非常に高
い。
さらにバンプ12が受ける機械的衝撃は、直接的にでは
なく、上述のように屈曲した内部配線11bを介して配線
パターン15に伝わる。そのため、配線パターン15に伝わ
る機械的衝撃は緩和され、半導体チップ13とバンプ12と
の電気的接続不良が抑制される。
次に、本発明における半導体装置の製造方法について
説明する。
先ず、回路基板11上に半導体チップ13をろう材あるい
は樹脂によって接合する。この場合、予め多数のバンプ
13aが設けたれたICウエハ（図示せず）から半導体チッ
プ13が切断されている。次いで、半導体チップ13をフィ
ルム14に接合し、これを回路基板11実装する。このと
き、インナーリード15a,アウターリード15bが半導体チ
ップ13のバンプ13aと表面配線11aとに各々接続されてい
る。しかる後、パッケージ16によってフィルム14および
半導体チップ13を樹脂封止する。このようにして半導体
装置を製造することができる。
なお、回路基板11のバンプ12を形成するには、例えば
Au,Cu,Pb−Sn等によるめっきやPb−Sn系半田槽へのディ
ッピングあるいはPb−Sn系半田ペーストの印刷・リフロ
ーによって行うことができる。また、パッケージ16はト
ランスファモールド法によって成形することができる。
また、本発明における回路基板11の材料は前述した実
施例に限定されず、例えば有機材料でもよく、その材料
は適宜変更することが自由である。この他、本発明にお
ける封止方法が樹脂ポッテイング法によるものでもよい
ことはいうまでもない。実施例で示したように、封止方
法としてトランスファモールド法を採用してパッケージ
16をモールド樹脂によって変形すると、半導体装置の製
造をきわめて簡単に行うことができる。
なお回路基板11の材料としては、一般に、有機材料を
用いれば安価であり、誘電率が低くて電気的特性に優れ
るという点で望ましい一方、セラミック系の材料と比較
して線膨張係数が金属（例えば銅）と大きく異なるとい
う短所をも有していることが知られている。
かかる短所を補償するため、第３図に示されるよう
に、内部配線11bのうち回路基板11を貫通する部分は、
その内部を配線材料等で充填することが望ましい。当該
貫通部分が中空状態では、体積の大きな有機材料と、薄
膜状の金属とが隣り合わせになっているだけとなり、両
者の線膨張係数の相違に起因してヒートサイクル耐性が
悪くなる。しかし、理由は詳らかではないが、金属であ
れ、他の材質であれ、当該貫通部分を充填することによ
って、配線のための金属は回路基板と充填物質との間に
挟まれて内部配線のヒートサイクル耐性が向上する。
〔発明の効果〕
以上に説明したように本発明によれば、第１の部分の
位置に拘らずに、バンプ間の寸法を従来のピン挿通方式
と比較して小さく設定することができる。
また回路基板と内部配線との熱膨張差に起因する熱疲
労（ヒートサイクル）に対してその耐性（ヒートサイク
ル特性）を向上することができ、内部配線の電気的接続
の信頼性が非常に高まる。
更に接続導体に伝わる機械的衝撃は緩和され、半導体
チップとバンプとの電気的接続不良が抑制される。
しかもヒートサイクル耐性の悪化を抑制しつつ、回路
基板に安価で誘電率の小さな有機材料を用いて電気的特
性を向上させることができる。Description: TECHNICAL FIELD The present invention relates to a semiconductor device having a semiconductor chip sealed by a package. [Prior Art] In recent years, with the miniaturization and multifunctionalization of semiconductor devices,
The number of input / output terminals (leads) for electric signals is increasing. Conventionally, this type of semiconductor device is configured as shown in FIG. This will be briefly described with reference to FIG. 1. In FIG. 1, a reference numeral 1 denotes a box-shaped pin grid array (hereinafter referred to as PGA) package having electrodes 2 and opening upward, and 3 denotes the PGA. A semiconductor chip 5 housed in a package 1 and having a large number of electrode pads 4 around its periphery;
A wire such as A1 connects the electrode pad 4 of the semiconductor chip 3 to the electrode 2 of the PGAG package 1. Reference numeral 6 denotes a pin as an external terminal for extracting input / output signals to the outside, and reference numeral 7 denotes a lid for closing an opening of the PGA package 1. The PGA package 1 is formed of a ceramic multilayer substrate. In order to mount the semiconductor device thus configured on the printed circuit board 8 shown in FIG.
After that, it is performed by soldering to the land pattern 8b. [Problems to be Solved by the Invention] In this type of semiconductor device, the pitch P of the pins 6 is equal to or less than the minimum pitch (1.8 mm) of the through holes 8a because the pins 6 are inserted through the through holes 8a. Therefore, there is a problem that the size of the PGA package 1 cannot be reduced and the wiring density of the printed circuit board 8 cannot be increased. The present invention has been made in view of such circumstances, and provides a semiconductor device that can reduce the size of a package and increase the wiring density of a circuit board. [Means for Solving the Problems] A semiconductor device according to the present invention has first and second surfaces located on opposite sides of each other, a circuit board having a laminated structure made of an organic material, and the first surface. A semiconductor chip provided thereon, a bump provided on the second surface, and a connection conductor provided on the first surface and electrically connected to the semiconductor chip, penetrating the circuit board. And an internal wiring for electrically connecting the connection conductor and the bump. At least one of the internal wirings has first to third portions. The first portion has one end connected to the connection conductor and the other end, and extends inside the circuit board in the thickness direction of the circuit board on the first surface side. The second portion has one end connected to the bump and the other end, and extends inside the circuit board in the thickness direction near the second surface. The third portion connects the other end of the first portion and the other end of the second portion. And the second part is the first part
The first portion and the second portion are provided closer to the semiconductor chip in a direction perpendicular to the thickness direction than the portion, and the first portion and the second portion have a solid structure. [Operation] A first portion of the internal wiring, which appears on the first surface,
The second portion appearing on the second surface can be shifted in a direction parallel to the first and second surfaces. By providing the third portion, the first and second internal wirings can be formed.
Can be shorter than the thickness of the circuit board. The mechanical shock received by the bump is transmitted to the connection conductor not directly but via the bent internal wiring. That the first part and the second part are solid structures,
The heat cycle resistance of the internal wiring is improved. Embodiments FIGS. 1 and 2 are cross-sectional views and perspective views showing a semiconductor device according to the present invention, and FIG. 3 is an enlarged cross-sectional view of a portion A in FIG. In these figures, what is indicated by reference numeral 11 is a circuit board for chip mounting, which is formed by laminating a plurality of ceramic substrates. Note that this circuit board
The upper surface in FIGS. 1 and 3 in FIG. 11 is hereinafter referred to as a first surface, and the rear surface opposite to the first surface is hereinafter referred to as a second surface. A surface wiring 11a is provided on the first surface, and a number of bumps 12 as external terminals are provided on the second surface.
Is provided. The surface wiring 11a and the bump 12 are connected to the internal wiring 11 provided so as to penetrate the circuit board 11.
It is electrically connected by b. The internal wiring 11b is formed in a step shape from the first surface to the second surface of the circuit board 11, as shown in FIG. More specifically, each of the internal wirings 11b has a first portion extending in the thickness direction above the circuit board 11 (on the first surface side) while one end is connected to the surface wiring 11a, and one end having a bump.
A second portion connected to the second portion and extending in a thickness direction below the circuit board 11 (second surface side), and the other end of the first portion and the other end of the second portion are perpendicular to the thickness direction. And a third portion connected in a direction (a direction parallel to the first and second surfaces). One end of the second portion is exposed as a bump setting portion on the second surface, and a bump 12 is provided on the bump setting portion. The third portion can be provided at a boundary between adjacent layers in the stacked circuit boards 11. Reference numeral 13 denotes a semiconductor chip having a bump 13a such as Au on a non-bonding side and a peripheral portion thereof, and is bonded to the first surface of the circuit board 11. The bump 13a functions as an electrode of the semiconductor chip 13. The connection part of the surface wiring 11a is bump 1
It is formed so as to be located at a distance outside of 3a. Reference numeral 14 denotes a film (TAB tape) having a window 14a at the center thereof, which is bonded to the circuit board 11 and the semiconductor chip 13, and has on one side inner leads 15a connected to the connection portions of the bump 13a and the surface wiring 11a. And a wiring pattern 15 including outer leads 15b is formed as a connection conductor. The film 14 and the semiconductor chip 13 are resin-sealed by a package 16 as a protection member. In the semiconductor device configured as described above, the semiconductor chip 13 is provided on the first surface of the circuit board 11 having a laminated structure, the bump 12 is provided on the second surface, and the semiconductor chip 13 is electrically connected to the semiconductor chip 13. A connected wiring pattern 15 is provided,
An internal wiring 11b for electrically connecting the wiring pattern 15 and the bump 12 is provided to penetrate the circuit board 11. Each of the internal wirings 11b has first to third portions. The first part has one end connected to the wiring pattern 15,
It has the other end and extends inside the circuit board 11 in the thickness direction near the first surface. The second portion has one end connected to the bump 12 and the other end, and extends inside the circuit board in the thickness direction near the second surface. The third portion extends and connects the other end of the first portion and the other end of the second portion in a direction parallel to the first surface. Therefore, of the internal wiring 11b, the first portion appearing on the first surface and the second portion appearing on the second surface are:
It can be shifted in a direction parallel to the first and second surfaces. Therefore, even if the outer lead 15b is far away from the semiconductor chip, the second portion can be provided closer to the semiconductor chip than the first portion, and the dimension between the bumps 12 can be set smaller than 1.8 mm. When the internal wiring 11b is formed without providing the third portion, the length becomes the thickness of the circuit board 11. On the other hand, by providing the third portion, the first and second internal wirings 11b are provided.
The length of each of the portions can be shorter. Therefore, resistance (heat cycle characteristics) against thermal fatigue (heat cycle) caused by a difference in thermal expansion between the circuit board 11 and the internal wiring 11b can be improved. Internal wiring 11b
All have a configuration with improved resistance in this way, and therefore, the reliability of the electrical connection by the internal wiring 11b is extremely high. Further, the mechanical shock received by the bumps 12 is transmitted not directly but to the wiring pattern 15 via the bent internal wiring 11b as described above. Therefore, the mechanical shock transmitted to the wiring pattern 15 is reduced, and the poor electrical connection between the semiconductor chip 13 and the bump 12 is suppressed. Next, a method for manufacturing a semiconductor device according to the present invention will be described. First, the semiconductor chip 13 is joined on the circuit board 11 by a brazing material or a resin. In this case, a large number of bumps
A semiconductor chip 13 is cut from an IC wafer (not shown) provided with 13a. Next, the semiconductor chip 13 is bonded to the film 14, and this is mounted on the circuit board 11. At this time, the inner lead 15a and the outer lead 15b are connected to the bump 13a and the surface wiring 11a of the semiconductor chip 13, respectively. Thereafter, the film 14 and the semiconductor chip 13 are resin-sealed by the package 16. Thus, a semiconductor device can be manufactured. In order to form the bumps 12 on the circuit board 11, for example,
It can be performed by plating with Au, Cu, Pb-Sn or the like, dipping in a Pb-Sn-based solder tank, or printing / reflowing a Pb-Sn-based solder paste. The package 16 can be formed by a transfer molding method. Further, the material of the circuit board 11 in the present invention is not limited to the above-described embodiment, and may be, for example, an organic material, and the material may be appropriately changed. In addition, it goes without saying that the sealing method in the present invention may be based on a resin potting method. As shown in the embodiment, the transfer molding method is adopted as the sealing method to package
By deforming 16 with a mold resin, the manufacture of a semiconductor device can be performed extremely easily. As a material for the circuit board 11, it is generally preferable to use an organic material because it is inexpensive and has a low dielectric constant and excellent electrical characteristics. On the other hand, a linear expansion coefficient is higher than that of a ceramic material. (For example, copper). In order to compensate for such a disadvantage, as shown in FIG. 3, a portion of the internal wiring 11b that penetrates the circuit board 11,
It is desirable to fill the inside with a wiring material or the like. When the penetrating portion is in a hollow state, the organic material having a large volume and the metal in the form of a thin film are only adjacent to each other, and the heat cycle resistance is deteriorated due to the difference in the coefficient of linear expansion between the two. However, although the reason is not clear, the metal for wiring is sandwiched between the circuit board and the filling material by filling the penetrating portion, whether it is metal or another material, so that the internal wiring heats up. Cycle resistance is improved. [Effects of the Invention] As described above, according to the present invention, the dimension between bumps can be set smaller than that of the conventional pin insertion method, regardless of the position of the first portion. Further, the resistance (heat cycle characteristic) to thermal fatigue (heat cycle) caused by the difference in thermal expansion between the circuit board and the internal wiring can be improved, and the reliability of the electrical connection of the internal wiring is greatly increased. . Further, the mechanical shock transmitted to the connection conductor is reduced, and the poor electrical connection between the semiconductor chip and the bump is suppressed. In addition, the electrical characteristics can be improved by using an inexpensive organic material having a small dielectric constant for the circuit board while suppressing the deterioration of the heat cycle resistance.
【図面の簡単な説明】
第１図および第２図は本発明に係る半導体装置を示す断
面図と斜視図、第３図は第１図のＡ部分を拡大して示す
断面図、第４図は従来の半導体装置を示す斜視図、第５
図はその回路基板への取付状態を示す断面図である。
11…回路基板、11a…配線パターン、11b…配線パター
ン、12…バンプ、13…半導体チップ、13a…バンプ、14
…フィルム、15…配線パターン、15a…インナーリー
ド、15b…アウターリード、16…パッケージ。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are a cross-sectional view and a perspective view showing a semiconductor device according to the present invention, FIG. 3 is an enlarged cross-sectional view of a portion A in FIG. 1, and FIG. Is a perspective view showing a conventional semiconductor device, and FIG.
The figure is a sectional view showing the state of attachment to the circuit board. 11: circuit board, 11a: wiring pattern, 11b: wiring pattern, 12: bump, 13: semiconductor chip, 13a: bump, 14
... film, 15 ... wiring pattern, 15a ... inner lead, 15b ... outer lead, 16 ... package.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 御秡如 英也 伊丹市瑞原４丁目１番地 三菱電機株式 会社北伊丹製作所内 (72)発明者 上田 哲也 伊丹市瑞原４丁目１番地 三菱電機株式 会社北伊丹製作所内 (72)発明者 寺岡 康宏 伊丹市瑞原４丁目１番地 三菱電機株式 会社北伊丹製作所内 (72)発明者 関 博司 伊丹市瑞原４丁目１番地 三菱電機株式 会社北伊丹製作所内 (56)参考文献 特開 昭58−39037（ＪＰ，Ａ) 特開 昭61−59848（ＪＰ，Ａ) 特開 昭62−277753（ＪＰ，Ａ) ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hideya Mikaru 4-1-1 Mizuhara, Itami City Mitsubishi Electric Stock Inside the Kita Itami Works (72) Inventor Tetsuya Ueda 4-1-1 Mizuhara, Itami City Mitsubishi Electric Stock Inside the Kita Itami Works (72) Inventor Yasuhiro Teraoka 4-1-1 Mizuhara, Itami City Mitsubishi Electric Stock Inside the Kita Itami Works (72) Inventor Hiroshi Seki 4-1-1 Mizuhara, Itami City Mitsubishi Electric Stock Inside the Kita Itami Works (56) References JP-A-58-39037 (JP, A) JP-A-61-59848 (JP, A) JP-A-62-277753 (JP, A)
Claims (1)
し、有機材料からなる積層構造の回路基板と、 前記第１の表面上に設けられた半導体チップと、 前記第２の表面上に設けられたバンプと、 前記第１の表面上に設けられ、前記半導体チップに電気
的に接続された接続導体と、 前記回路基板を貫通して設けられ、前記接続導体と前記
バンプとを電気的に接続する内部配線と を備え、 前記内部配線の少なくとも一つが、 前記接続導体に接続された一端と、他端とを有し、前記
第１の表面側で前記回路基板の内部を前記回路基板の厚
み方向に延びる第１の部分と、 前記バンプに接続された一端と、他端とを有し、前記第
２の表面側で前記回路基板の内部を前記厚み方向に延び
る第２の部分と、 前記第１および第２の表面とほぼ平行に延びる平行部分
を含み前記第１部分の前記他端と前記第２の部分の前記
他端とを接続する第３の部分と を有し、 前記第２の部分は前記第１の部分よりも前記厚み方向と
直交する方向において前記半導体チップに近く設けら
れ、 前記第１の部分及び前記第２の部分が中実構造である半
導体装置。(57) [Claims] A circuit board having a stacked structure made of an organic material having first and second surfaces located on opposite sides of each other, a semiconductor chip provided on the first surface, and provided on the second surface And a connection conductor provided on the first surface and electrically connected to the semiconductor chip, and provided through the circuit board to electrically connect the connection conductor and the bump. An internal wiring to be connected, at least one of the internal wirings has one end connected to the connection conductor, and the other end, and the inside of the circuit board on the first surface side of the circuit board. A first portion extending in the thickness direction, a second portion having one end connected to the bump, and the other end, and extending in the thickness direction inside the circuit board on the second surface side; A parallel extending substantially parallel to the first and second surfaces And a third portion connecting the other end of the first portion and the other end of the second portion, the second portion including the second portion, the second portion being more in the thickness direction than the first portion. A semiconductor device provided near the semiconductor chip in a direction orthogonal to the first direction, wherein the first portion and the second portion have a solid structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62093519A JP2722451B2 (en) | 1987-04-15 | 1987-04-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62093519A JP2722451B2 (en) | 1987-04-15 | 1987-04-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63258048A JPS63258048A (en) | 1988-10-25 |
| JP2722451B2 true JP2722451B2 (en) | 1998-03-04 |
Family
ID=14084579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62093519A Expired - Fee Related JP2722451B2 (en) | 1987-04-15 | 1987-04-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2722451B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0394436A (en) * | 1989-09-06 | 1991-04-19 | Toshiba Corp | Manufacture of semiconductor device |
| JP2760627B2 (en) * | 1990-04-12 | 1998-06-04 | 株式会社東芝 | Semiconductor device |
| KR100191853B1 (en) * | 1995-12-20 | 1999-06-15 | 윤종용 | Semiconductor package having an opening part on the solder resister |
| JP3538290B2 (en) * | 1997-01-09 | 2004-06-14 | 株式会社ルネサステクノロジ | Wiring member and lead frame having the same |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49123271A (en) * | 1973-03-28 | 1974-11-26 | ||
| JPS5243364A (en) * | 1975-10-01 | 1977-04-05 | Hitachi Ltd | Power semiconductor device and process for production of same |
| JPS56137659A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device and its manufacture |
| JPS5839037A (en) * | 1981-09-01 | 1983-03-07 | Nec Corp | Chip carrier |
| JPS58207657A (en) * | 1982-05-28 | 1983-12-03 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS598361A (en) * | 1982-07-06 | 1984-01-17 | Nec Corp | Package of semiconductor integrated circuit device |
| JPS6159848A (en) * | 1984-08-31 | 1986-03-27 | Fujitsu Ltd | Flip chip mounting method using leadless chip carrier |
| JPS61134045A (en) * | 1984-12-05 | 1986-06-21 | Nec Corp | Resin-sealed semiconductor device |
| JPS61226937A (en) * | 1985-03-30 | 1986-10-08 | Toshiba Corp | Semiconductor device |
| JPS62277753A (en) * | 1986-05-27 | 1987-12-02 | Sumitomo Electric Ind Ltd | Semiconductor package |
-
1987
- 1987-04-15 JP JP62093519A patent/JP2722451B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63258048A (en) | 1988-10-25 |
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