TWI224372B - Field-effect-controllable semiconductor component and fabricating method thereof - Google Patents

Field-effect-controllable semiconductor component and fabricating method thereof Download PDF

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TWI224372B
TWI224372B TW092103250A TW92103250A TWI224372B TW I224372 B TWI224372 B TW I224372B TW 092103250 A TW092103250 A TW 092103250A TW 92103250 A TW92103250 A TW 92103250A TW I224372 B TWI224372 B TW I224372B
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TW200304188A (en
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Oliver Haeberlen
Franz Hirler
Manfred Kotek
Andreas Rupp
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Infineon Technologies Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0869—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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Abstract

The present invention relates to a field-effect-controllable, vertical semiconductor component with deep trenches and to two methods for fabricating such a semiconductor component, in which, for the fabrication, the body regions and source regions are implanted into the semiconductor body by inclined implantation via the inner walls of the trenches.

Description

1224372 五、發明說明（l) 本發明的内容包括兩種製造可經由場效應控制的半導體 組件的方法，以及具有申請專利範圍第丨6項之特徵的這種 導體組件。 對於設計新一代的垂直式大功率半導體組件而言，縮小 艮大的重要性。經由縮小比接通電阻-方面 流密度。因此可以將體積及製造成本均小 良夕的+ ν體組件用於相同總電流的情況。 縮 組件取 體組件 向的閘 寬度較 導體組 當高。 使用具 本體區 的内部 厚度遠 半部的 槽内上 下半部 電阻R。"的一種方法是以溝槽式結構的半導 ΐ千結構的半導體組件。在溝槽式結構的半1224372 V. Description of the invention (l) The content of the present invention includes two methods for manufacturing a semiconductor component that can be controlled by field effect, and such a conductor component having the characteristics of the scope of patent application No. 6. For designing a new generation of vertical high-power semiconductor components, it is important to reduce the size. Turn on the resistance-reduction aspect via the reduction ratio. Therefore, it is possible to use a + ν body component with good volume and manufacturing cost for the same total current. The width of the brake in the direction of the shrinking component and the body component is higher than that of the conductor group. Use the upper and lower resistors R in the tank with the thickness of the inner half of the body and the far half. " One method is a semiconductor device with a semiconductor structure with a trench structure. Half in trench structure

m設置於半導體基體内，也就是設置於垂 電極内。由於這種半導體組件每一 I 大，因此可以使比接通電阻Ron大幅面積上的通 件而言’漂移區造成的電阻佔整個接：二 有較深的溝槽的半導體結；電；匕最好 及/或通道區，下半部則深入漂移區内、的、汔:緊 二有階梯狀的電介質，由於電介質在y半冓指 厚度自然會大於在溝槽内上半部的厚槽内 +部形成通道控制用的閘極氧化物。“。、:在: 形成的埸氧化物的作用是使閑電極與半^基體^m is disposed in the semiconductor substrate, that is, in the vertical electrode. Because this semiconductor device has a large I, it can make the resistance caused by the 'drift region account for the entire connection than the pass piece on a large area of the on-resistance Ron: two semiconductor junctions with deep trenches; electricity; The best and / or the channel area, the lower half is deeper into the drift area, 汔: Tight two stepped dielectric, because the dielectric in the y-half finger thickness is naturally larger than the thick groove in the upper half of the trench The inner + part forms a gate oxide for channel control. ". ::: The role of the formed hafnium oxide is to make the free electrode and the semi-substrate ^

第5頁 1224372Page 5 1224372

五、發明說明（2) 緣0 這種具有較深的溝槽、以及溝槽内具有階梯狀的閘 和氧化物的半導體組件係屬於已知的技術，例如在德 D〜=二IΓ有提及。在wo 0 1 /0 1 484 A2則：出製造 攻種半導體組件的方法。 這種半 被再充電的 因此會產生 關次數頻繁 由一個閘源 Ba 1 i ga所著 組件），PWS 中有關於金 的說明。閘 之間的重疊 層形成的電 汲電容Q主 導體組件的 定0 導體組件 寄生輸入 開關損耗 的情況下 電容Ces及 的 π P 〇 w e r Publish 屬氧化物 源電容Q 部分電容 容部分所 要是由閘 閘極氧化 均含有一個在每一次開關過程中都必男 電容。由於這個再充電過程需要電流， ，尤其是在使用低電壓半導體組件及 的開關損耗會特別大。這個寄生 θ 一個閘汲電容Cgd所構成。在Β. Semiconductor Devices"(功率半 mg Company，381 —383 頁及圖 f導體結構的閘源電容Cgs及開汲電容 是由一個介於閘極的多晶矽層及源電1 I以及-個由通道區及閘電極 構成。又稱為反饋電容或密勒電容：: 極氧化物電容構成，而具有深溝样 物電容是由閘電極上半部較寬區； 在目前已知的製造這種半 國專利DE 19935442 C1提出的 導體組件的方法中（例如 衣造方法），通常都是經 •待 由通V. Description of the invention (2) Edge 0 This semiconductor device with deep trenches and stepped gates and oxides in the trenches is a known technology. For example, there is an improvement in Germany D ~ = 二 IΓ. and. In Wo 0 1/0 1 484 A2, there is a method for manufacturing semiconductor devices. This kind of semi-recharged will therefore produce frequent closings by a gate source (Ba 1 i ga). The PWS has a description of gold. The capacitor Ces and π P in the case of parasitic input switching loss of the conductive component Q formed by the overlapping layer between the gates of the conductor assembly are the capacitors Ces and π P 〇wer Publish belong to the oxide source capacitor Q part of the capacitance and capacity of the gate Gate oxidation contains a capacitor that must be male during each switching process. Since this recharging process requires current, especially when using low-voltage semiconductor components, the switching losses will be particularly large. This parasitic θ is formed by a gate-drain capacitor Cgd. In Β. Semiconductor Devices " (power half mg Company, pages 381-383 and Figure f, the gate-source capacitance Cgs and open-drain capacitance are composed of a polycrystalline silicon layer between the gate and the source 1 I and-a channel Area and gate electrode. Also known as feedback capacitor or Miller capacitor :: An electrode oxide capacitor, and a capacitor with a deep trench sample is a wider area of the upper half of the gate electrode; In the method of the conductor assembly proposed in the patent DE 19935442 C1 (such as the clothing manufacturing method), it is usually

第6頁 1224372 五、發明說明（3) 過晶片正面 精確控制多 極將溝槽式 閘電極至少 能夠到達足 半部應深入 之間的梯級 過這樣做無 之上，造成 的離子 晶$夕閘 半導體 要到達 夠的深 溝槽内 位於本 可避免 閘 >及電 注入來 電極的 組件接 十分接 度，需 部，以 體區下 的會造 容佔總 產生本體區及源極區。 溝槽餘刻深度。為了能 通及切斷，從晶片正面 近漂移區的深度。為了 要運用適當的提前量。 便使介於閘極氧化物及 方，也就是被設置在漂 成閘電極會重疊在一部 輸入電容很大比例的結 問題是彳艮難 夠通過閘電 伸入溝槽的 確保閘電極 閘電極的上 場極氧化物 移區内。不 分的漂移區 果。 :此本發明的目的在於提出一種具有較低之輸入電容备 运種半導體組件，以及製造這種半導體組件的方法。 採用具有申請專利範圍第i及第3項之特徵的製造方法， 1 ΐ具有申請專利範圍第16項之特徵的半導體組件即可達至 本發明的目的。 I < > 2發明的製造方法中，還可另外經由溝槽的側壁對4 “ i ΐ ϊ區進行離子注入及必$的向外擴散作業。經由也 抑4工/▲的本體區及源極區的通道輪廓可以在溝槽内經d 行校正（第一種情況），或是經由兩個不同合 Μ Λ二正一種情況）。第一種情況是經由同一個邊（例如 個、軎^的—個邊或是在溝槽内被向下餘刻的場極氧化物的— :用於本體區及源極區的離子注入，然後再將用於本 1224372Page 6 1224372 V. Explanation of the invention (3) Passing the front of the wafer to precisely control the multi-pole The grooved gate electrode can reach at least the step between the half of the foot. Doing so does not cause the ion crystal. The semiconductor needs to reach deep enough trenches to be located in the avoidable gates, and the components of the electrodes injected by the electrical connection are very close, and the total volume of the body area and the source area is occupied by the capacity under the body area. Trench remaining depth. In order to be able to pass and cut off, the depth of the drift region is approached from the front side of the wafer. In order to use the appropriate amount of advance. Therefore, the junction between the gate oxide and the square, that is, the gate electrode that is set to drift so that the gate electrode overlaps with a large proportion of the input capacitance. The upper field of the electrode is within the oxide transition region. Indistinguishable drift region. : The purpose of the present invention is to propose a semiconductor device with low input capacitance for backup operation and a method for manufacturing the semiconductor device. By adopting the manufacturing method having the features of the scope of application for items i and 3, a semiconductor device having the features of the scope of application for patent can achieve the object of the present invention. I < > In the manufacturing method of the second invention, ion implantation and necessary outward diffusion of the 4 "i ΐ ϊ region can also be performed through the side wall of the trench. The channel contour of the source region can be corrected in the trench by d (the first case) or by two different combinations (M Λ two positive one). The first case is through the same edge (for example,軎 ^ —one side or field oxide etched down in the trench—for ion implantation in the body and source regions, and then used in this 1224372

五、發明說明（4) 體區的離子擴散出來 經由輔助層或場極氧 或場極氧化物的向下 個輔助層或場極氧化 極電容調整至最低， 。第二種情況是先 化物的一個邊注入 蝕刻後，再將用於 物注入。第二種情 以及將通道長度調 將用於源極區的離子 ’然後在完成辅助層 本體區的離子經由這 況最好是將源極—一閘 整至彳艮小。 在德國專利DE 1 9 72 0 2 1 5 Μ的公開說明書中公開的製造 方法是通過一個溝槽的側壁將摻雜材料注入而製造出半導體 組件，以達到調整半導體組件的門限電壓的目的。由於這種 方法僅注入一次摻雜材料，因此只能形成源極區，而不能形 、美國專利US 6274437 Β1提出的方法也只有通過溝槽側 壁進行一次離子注入作業。因此，不論是美國專利us B1或是德國專利DE 1 972〇215 A1提出的方法都不能-解決前面說明過的問題（也就是本發明所要解決的問題）。 在形成本體區後，最好是將設置在溝槽側壁上的場極氧 化物略為向下蝕刻，以便使介於場極氧化物及閘極氧化物之 間的被向下蝕刻的梯級處於略低於出現在溝槽側壁上的位於 本體區及漂移區之間的pn結的位置。將場極氧化物向下蝕刻 屬於種可以精確控制的技術，也就是說，可以非常精確的 疋出梯級的位置。在能夠經由離子注入參數確定pn結緊靠在 /冓槽側壁上的位置後，就可以經由適當的向下餘刻使介於場V. Description of the invention (4) The ions in the body region diffuse out and the capacitance of the next auxiliary layer or field oxide via the auxiliary layer or field oxide or field oxide is adjusted to the lowest level. In the second case, one side of the compound is etched and then used for implantation. In the second case, the channel length is adjusted to use the ions for the source region, and then the ions in the body region of the auxiliary layer are completed. In this case, it is best to set the source to a gate to be small. The manufacturing method disclosed in the published specification of German Patent DE 197 2 0 2 1 5 M is to manufacture a semiconductor device by injecting a dopant material through the side wall of a trench to achieve the purpose of adjusting the threshold voltage of the semiconductor device. Because this method implants the dopant material only once, it can only form the source region, and it cannot be shaped. The method proposed in US Patent No. 6,274,437 B1 also only performs an ion implantation operation through the trench sidewall. Therefore, neither the US patent US B1 nor the German patent DE 1 972201 215 A1 can solve the problem described above (that is, the problem to be solved by the present invention). After the body region is formed, it is better to etch the field oxide disposed on the sidewall of the trench slightly downward, so that the step etched down between the field oxide and the gate oxide is slightly etched. Lower than the position of the pn junction between the body region and the drift region appearing on the sidewall of the trench. Etching the field oxide down is a technique that can be precisely controlled, that is, the position of the steps can be pinpointed very accurately. After the position of the pn junction abutting on the side wall of the trench can be determined through the ion implantation parameters, the intervening field

1224372 五、發明說明（5) 極氧化物及閘極氧化物之間的梯級位於pn結下方。這樣就可1 以使問電極和漂移區的重疊部分降至最低，達到將閘汲電容 降至最低的目的。 曰_ 面提到的梯級並不需要剛好是一個水平的梯級，也就 二Πΐ個梯級可以是一個階段狀的結構，其位置係介於閘極 士 M f電介質（場極氧化物）之間。出於製造技術的考量， 少有點傾斜。在角洛處和稜邊處要製作成倒圓，而且或多或 的方區及本體區的步驟是經由斜向離子注入 層很薄的電介晰/费二内的輔助層去除。接下來的步驟是將一 電介質的作用是二溝槽上半部露空的溝槽侧壁上，這層 為了形成閘電極應：導ί 閘極氧化物。然後 及本體區的接觸區。電材枓將溝槽填滿，同時形成源極區 進行離子注入 子，要报士 , 守’要形成11型摻雜區诵堂9、士 λ r山 于要形成p型摻雜嘑匕通吊疋注入砷離 錄等亦可作為η型摻雜=吊：:主入爛離子。但是磷、硫、 料。注入第-種及第材稽科"而/呂、銦等亦可作為Ρ型摻雜材 的先決條件是(特別是—在種:田的離子(例如石申及删離子） 所注入的件的摻々量在，使，：-個… 大，因此硼合以+ 里逖兩於硼。由於硼的擴鸯尨I 、 快彳"的速度擴散至半匕並 第9頁 1224372 五、發明說明（6) ------ 形成--個僅換·-JL. ^ ”有领離子的摻雜層。雖然在源極區内也含有· 少量的硼離子，也丄^ ^ 仁由於蝴離子的濃度遠低於珅的濃度，故可 離子注入诵誉H + y Λ k $疋在一個大於ο的注入角度下進行，這個 兩的么ΐ 將為避免穿隧效應（Channel ing—Ef fekten)所 二二計算進去。注入角度最好是45度(與第-個表 為可不過只要是介於30度至60度之間的注入角度均 坦及/或非常w度太如广是要在溝槽側壁區形成輪廓非常平 間的注入角Α -區及源極區時，則介於15度至75度之 壁的卜^ 1 斜向離子注入，以確保所有溝槽側 土的上+部都有離子注入。 |另屏h w 光列2在溝槽内的輔助層通常是由-層光刻膠構成。除了 九刻膠外，也可以使用其他偁成除了 構成這個輔助層。#丨& γ σ作為離子注入掩膜的材料來 稍助㉟例如可以用閘電極作為輔助層。 在=的：種有利的實施方式中，問 二而疋在沉積出閘電極材料後被略為向下未= 電極就不會將源極區整個覆蓋住， d。廷樣閘 源電容的目的。 同樣可以達到縮小閘1224372 V. Description of the invention (5) The step between the pole oxide and the gate oxide is located below the pn junction. In this way, the overlap between the interrogation electrode and the drift region can be minimized, and the gate-drain capacitance can be minimized. The step mentioned above does not need to be exactly a horizontal step, that is, the two steps can be a stage-like structure, and its position is between the gate M f dielectric (field oxide) . Due to manufacturing technology considerations, it is less inclined. The steps to make rounds at the corners and edges, and more or less square and body regions, are removed by a thin dielectric / facilitative auxiliary layer with a thin oblique ion implantation layer. The next step is to apply a dielectric on the side wall of the trench exposed in the upper half of the trench. In order to form the gate electrode, the gate oxide should be conducted. Then contact the body area. The electric material fills the trench, and at the same time, the source region is formed for ion implantation. It is necessary to report, and it is necessary to form an 11-type doped region. 9. The λr mountain is to form a p-type doped dagger. Tritium implanted arsenic ionization can also be used as η-type doping = hang :: main rot ion. But phosphorus, sulfur, and materials. Implantation of the first species and the second material " and / Lu, indium, etc. can also be used as the prerequisite for P-type dopants (especially-ions in the species: field (such as Shishen and deleted ions) The amount of erbium doped is so that:-one ... So boron combined with + ri is equal to boron. Due to the expansion of boron I, the rate of rapid diffusion " spreads to half a dagger and page 9 1224372 5 、 Explanation of the invention (6) ------ Formation of a doped layer with only a change of -JL. ^ "With a leading ion. Although it contains a small amount of boron ions in the source region, it is also ^^ ^ Since the concentration of butterfly ions is much lower than that of 珅, ion implantation can be performed at an implantation angle greater than ο. The two 的 ΐ will be used to avoid the tunneling effect. —Ef fekten) is calculated. The injection angle is preferably 45 degrees (but the first table is OK, but as long as it is between 30 degrees and 60 degrees, the injection angle is frank and / or very w degrees too In order to form an implantation angle A-region and a source region with a very flat profile in the sidewall region of the trench, an oblique ion implantation of a wall between 15 degrees and 75 degrees is performed to ensure that The upper + part of all trench side soils has ion implantation. | Another screen hw The auxiliary layer of light column 2 in the trench is usually composed of -layer photoresist. In addition to nine-layer resist, other formations can also be used. In addition to forming this auxiliary layer. # 丨 & γ σ is used as a material for the ion implantation mask to assist a little. For example, a gate electrode can be used as an auxiliary layer. In =: In an advantageous embodiment, the second and third layers are deposited. After the gate electrode material is slightly downward, the electrode will not cover the entire source region, d. The purpose of the gate-like gate source capacitor. The gate can also be reduced.

溝槽的斷面形狀通常為 四方形或梯形 但也可以採用UThe cross-sectional shape of the groove is usually square or trapezoidal, but U can also be used.

第10頁 1224372 五、發明說明（7) 形或V形的斷面。溝槽係以 一個表面上，或是以正方相可狀或格閘狀的形狀設置在第 形狀設置在半導體基體内r本：匕、圓形、或是橢圓形的 從第-個表面伸入半導體基：：或極區最好是經由 形成導電觸點接通。在一錄^的本體接觸區及/或源接觸區 3槽的方式將本體接觸區置入式中，可以垂直於 製造方法能夠提供這種可；：矩巧：只有本發明提出的 側壁離子注入形&的源極區;^=經由對表面進行的 係。因此按照本發明的方式(倒㈣狀）的關 必對條帶狀的溝槽進行校正，^的接觸離子注入可以不 垂直於溝槽的方式，並；留半：：7以將本體接觸區設置成 量可以使胞元閘變小很多。 入之離子注入邊緣的前置 接艏2一種可行方式是可以在沒有4膜遮蔽的情況下對本體 =區進行離子注人，在這種情況下，在溝槽上半部介於源 f區及〜1電極之間的絕緣層必須，皮向下蝕刻i溝槽的位置。 隹此處源極區的源極引線連接可經由溝槽側壁來進行。 由於二氧化矽（Si〇2)不但易於製造，而且生產成本又 低，故此處係以二氧化矽（Si 〇2 )作為製作絕緣層及/ 介質 的材料。 /Page 10 1224372 V. Description of the invention (7) Shaped or V-shaped section. The groove is provided on a surface, or in a square shape or a grid shape. The groove is provided in the semiconductor substrate. The shape: dagger, circular, or elliptical extends from the first surface. Semiconductor-based: The pole region is preferably switched on by forming a conductive contact. The main body contact area and / or the source contact area are arranged in a three-slot manner in the recorded body, and the body contact area can be provided perpendicularly to the manufacturing method. This can be provided: only the side wall ion implantation proposed by the present invention The source region of the shape & ^ = via the line to the surface. Therefore, according to the method of the invention (inverted shape), it is necessary to correct the strip-shaped groove, and the contact ion implantation of ^ may not be perpendicular to the groove, and leave half :: 7 to place the body contact area Setting the amount can make the cell gate much smaller. A possible way to pre-connect the edge of the implanted ion implantation is to implant the body = region without the 4 film mask. In this case, the upper half of the trench is between the source f region And the insulating layer between ~ 1 electrodes must be etched down to the position of the i-groove. Here, the source wiring of the source region can be performed through the trench sidewall. Since silicon dioxide (SiO2) is not only easy to manufacture, but also has low production costs, it is here used silicon dioxide (SiO2) as the material for the insulating layer and / or the dielectric. /

第11頁 II _ 1224372 五、發明說明（8) 理論上設置在溝槽内的雷八晰 腐氧化物層除了以二氧化矽=二，以及設置在表面上的防 緣材料或方式來製作， ”、、材料外，也可以採用其他絕 化石夕及氮化石夕製成的薄膜，；=(，、真空、或是二氧 法製成的二氧化矽作為閘極氧貝而言，仍以經熱處理 建議以二氧化矽作為 2所獲得的效果最佳，因此 1电Μ貝及防腐氧化物層。 溝槽的下半部诵I女 Τ呆該處的間汲電容能^氧化物’ =掉’而且可以用來使漂移區的電 π除掉，就像在所謂的償半 的載Μ子相互 摻雜層一樣。ά補1貝牛¥體、、且件中的不同電導類型的 本發明的半導體組件會具有較高的擊穿電ζ的ί ί體組件’ 處理的最好在溝槽侧壁上設有-層經過敎 2。⑽至2一二：二：置在溝槽下半部的絕緣層的厚度通常Ϊ 數十⑽至^⑽ 在溝槽上半部的絕緣層的厚度則通常為 其他作為製作閑電極的材料，不過亦可使用 ν電材枓來製作閘電極，如金屬矽化物、金 電』二面雖然這些材料就製造技術、物理特性、：：導 寺方面而言均不如使用高摻雜的多晶矽有利。 1224372 五、發明說明（9) 一種有利的實施方式係將半導體組件製作成垂直式的半 導體組件。不過也可以將半導體組件製作成其他形狀，例如 製作成種所明的上汲式（U p - D r a i η )半導體組件。上沒式半 導體組件的源極區、汲極區、以及閘電極都是從半導體基體 的同一邊形成觸點接通。電流主要是沿著垂直方向流動，但 是在漂移區下方則是從側面流出至表面。 本發明的其他有利的實施方式及進一步改良請參見從屬 於主申請專利範圍的其他申請範圍及關於以下圖式的說明文 字中。 除非另有說明，否則在以上所有圖式中相同的標號均代 表完全相同及/或作用相同的構件。 第一圖顯不本發明之構成溝槽式金屬氧化物半導體場效 應電晶體（MOSFET)的半導體組件的部分斷面圖。第一圖中的 =導體基體（1 )可以是一個單晶的矽晶片。半導體基體（丨）的 第一個表/面（2)被稱為晶片正面。半導體基體（〇的第二個表 面（3)被稱為晶片背面。半導體基體（1)具有一個緊鄰晶片背 面（3)的強η型摻雜的汲極區（4)。在朝晶片正面（2)的方向上 有一個弱η型摻雜的漂移區（5 )緊接在汲極區（4 )上。漂移區 (5)通常是經由外延法被置於汲極區（4)之上，但是外延、去並 非唯一的可行方法，也可以用其他方法將漂移區（5)置於、及’ ==技Ϊ朝晶片正面⑺的方向上有一_型摻雜的 本體£(6)緊接在漂移區（5)上，介於漂移區（5)及本體區（6)Page 11 II _ 1224372 V. Description of the invention (8) In principle, the Rabata rot oxide layer provided in the trench is made of silicon dioxide = two, and the edge protection material or method provided on the surface. In addition to materials, thin films made of other fossilized and nitrided stones can also be used; = (, vacuum, or silicon dioxide made by the dioxin method is still used as the gate oxygen shell. After heat treatment, it is recommended to use silicon dioxide as 2. The best effect is obtained, so 1 ohms and anti-corrosive oxide layer. The lower part of the trench is called d. The capacitance of the drain capacitor ^ oxide '= It can also be used to remove the electric π in the drift region, just like the so-called half-doped carriers mutually doped with each other. The supplementary conductivity is different from that of the conductivity type. The semiconductor device of the invention will have a high breakdown voltage, and it is best to treat the light-emitting device on the side wall of the trench with a layer of 敎 2. ⑽ to 21-2: two: placed under the trench The thickness of the insulating layer in the half is usually tens of ⑽ to ^ ⑽ The thickness of the insulating layer in the upper half of the groove is usually He is used as a material for making leisure electrodes, but ν electric materials can also be used to make gate electrodes, such as metal silicide and gold electricity. Although these materials are not as good as the manufacturing technology, physical characteristics, and guides: Highly doped polycrystalline silicon is advantageous. 1224372 V. Description of the invention (9) An advantageous embodiment is that the semiconductor device is made into a vertical semiconductor device. However, the semiconductor device can also be made into other shapes, such as the known Up-drain (U p-D rai η) semiconductor components. The source region, the drain region, and the gate electrode of the top-submerged semiconductor device are all contacted from the same side of the semiconductor substrate. The current is mainly along the It flows in the vertical direction, but flows from the side to the surface below the drift zone. For other advantageous embodiments and further improvements of the present invention, please refer to the other application scopes subordinate to the main application patent scope and the description of the following drawings. Unless otherwise noted, the same reference numerals in all the above drawings represent identical and / or identical structures. The first figure shows a partial cross-sectional view of a semiconductor component constituting a trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) according to the present invention. The first figure = the conductor matrix (1) may be a single crystal The first surface / surface (2) of the semiconductor substrate (丨) is called the front side of the wafer. The second surface (3) of the semiconductor substrate (0) is called the back side of the wafer. The semiconductor substrate (1) has one A strongly n-type doped drain region (4) next to the back surface (3) of the wafer. There is a weak n-type doped drift region (5) in the direction toward the front side (2) of the wafer, which is immediately adjacent to the drain region ( 4). The drift region (5) is usually placed on the drain region (4) by epitaxy, but epitaxy and removal are not the only feasible method, and the drift region (5) can also be placed in other regions by other methods. And '== technology has a _-type doped body in the direction of the front surface of the wafer. (6) is directly next to the drift region (5), between the drift region (5) and the body region (6).

第13頁 1224372 五、發明說明（10) 之間的父界面定義出一個pn結（21)。在晶片正面（2)及本體 區（5 )還設有一個強η型摻雜的源極區（7 )。 以溝槽技術製造的金屬氧化物半導體組件具有溝槽 (8) °溝槽（8)位於半導體基體（1)内，其範圍起自晶片正面 (2 ) ’經過源極區（7 )及本體區（6 )，並伸入漂移區（& )。另外 還设有自晶片正面（2 )起垂直伸入溝槽（8 )内的閘電極（9 )。 閘電極（9)經由電介質（18，19)與溝槽側壁（10)及溝槽底部 (11 )絕緣。 此處的溝槽（8)係德國專利DE 1 9935442 C1所稱的深溝 槽，其範圍延伸至漂移區（5)。為了易於觀察及說明，故將 一個溝槽的斷面放大繪製於圖式（la)。由於溝槽（8)内的閘 電極（9 )及電介質（1 8 ’ 1 9 )具有一個梯級（1 5 )，使得位於溝 槽下半部（16)的電介質厚度遠大於位於溝槽上半部（17)的電 介=厚度。相反的，位於溝槽上半部（17)的閘電極（9)厚度 則遠大於位於溝槽下半部（丨6 )的閘電極（9 )厚度。 又 如果將閘電極（9 )接上一個正閘極電位，在本體區（6 )緊 鄰溝槽（8 )的部分會因為載流子的侵入而形成通道（2 〇 )。如、 果在引出線（D，S)之間接上一個汲源電壓，就會產生一個從· 源極區（9)流出，經過通道（20)、漂移區（5)、汲極區（4) 最後抵達汲極引出線（D)的電流。不過要產生這種情況需具 備的一個前提是，梯級（1 5)的位置需位於本體區（6)及漂矛多Page 13 1224372 V. Description of Invention (10) The parent interface between (10) defines a pn junction (21). A strongly n-doped source region (7) is also provided on the front surface (2) and the body region (5) of the wafer. The metal oxide semiconductor component manufactured by the trench technology has a trench (8). The trench (8) is located in the semiconductor substrate (1), and its range starts from the front side of the wafer (2) and passes through the source region (7) and the body. Zone (6), and extends into the drift zone (&). In addition, a gate electrode (9) extending vertically from the front side (2) of the wafer into the groove (8) is provided. The gate electrode (9) is insulated from the trench sidewall (10) and the trench bottom (11) via a dielectric (18, 19). The groove (8) here is a deep groove referred to in German patent DE 1 9935442 C1, and its range extends to the drift region (5). For easy observation and explanation, the cross section of a groove is enlarged and drawn in the figure (la). Since the gate electrode (9) and the dielectric (1 8 '1 9) in the trench (8) have a step (1 5), the thickness of the dielectric located in the lower half (16) of the trench is much larger than that in the upper half The dielectric of the part (17) = thickness. In contrast, the thickness of the gate electrode (9) located in the upper half (17) of the trench is much larger than the thickness of the gate electrode (9) located in the lower half (6) of the trench. If the gate electrode (9) is connected to a positive gate potential, a portion of the body region (6) next to the trench (8) will form a channel (20) due to carrier intrusion. For example, if a drain-source voltage is connected between the lead-out lines (D, S), an outflow from the source region (9) will pass through the channel (20), drift region (5), and drain region (4). ) The current that finally reaches the drain pin (D). However, a prerequisite for this situation is that the position of the step (1 5) must be located in the body area (6) and more

第14頁 1224372 五、發明說明（π) 區（5)之間的pn結（21)的下方、或是略高於pn結上方的位 置。 在本發明的半導體組件中，梯級（1 5 )的位置被校正至剛 好與pn結（21)位於同一個平面的位置，或是略低於(21) 的位置。這個校正動作可以利用自動校正或是在製造本體區 (6)及/或源極區（7)時經由梯級（15)導出的場極氧化物 的上緣所進行的校正來完成。 沒極區（4 )是經由設置在晶片背面（3 )上的大面積汲極金 屬化層（12)與没極引出線（D)連接。在晶片正面（2)上有一個 源極金屬化層（1 3 )。源極金屬化層（丨3 )經由一個分路與源極 區（7)及本體區（6)形成導電觸點接通。金屬化層（is)與閘電 極（9 )之間隔著將二者絕緣的防腐氧化物層（1 & )。有多種材 料可用來製作防腐氧化物層（1 4 )，例如蝴麟石夕玻璃（b p $ g )。 源極金屬化層（1 3 )在晶片正面（2 )上與源極引出線（s )連接， 閘電極（9)則是與閘極引出線（G)連接。 在半導體基體（1)的配置方式中，閘電極（9)、本體 (6)、以及源極區（7)覆蓋的區域是溝槽式金屬氧化物半導體 場效應電晶體（MOSFET)的由許多胞元構成的胞元場（ZF)，而 第一圖的斷面圖僅顯示兩個胞元。每一個胞元都含有一個單 電晶體。並聯的許多單電晶體的負載線路即形成金屬氧化物 半導體場效應電晶體（MOSFET)。除了胞元場（ZF)之外，第一Page 14 1224372 V. Description of the invention The position below the pn junction (21) or slightly above the pn junction between the (π) regions (5). In the semiconductor device of the present invention, the position of the step (1 5) is corrected to a position that is exactly on the same plane as the pn junction (21), or a position slightly lower than (21). This correcting action can be performed by automatic correction or by the upper edge of the field oxide derived through the step (15) when the body region (6) and / or the source region (7) are manufactured. The electrodeless region (4) is connected to the electrodeless lead (D) via a large-area drain metallization layer (12) provided on the back surface (3) of the wafer. There is a source metallization layer (1 3) on the front side (2) of the wafer. The source metallization layer (丨 3) forms a conductive contact with the source region (7) and the body region (6) through a shunt. The metallization layer (is) and the gate electrode (9) are separated by an anticorrosive oxide layer (1 &) which insulates the two. There are various materials that can be used to make the anticorrosive oxide layer (1 4), such as butterfly stone glass (b p $ g). The source metallization layer (1 3) is connected to the source lead (s) on the front side (2) of the wafer, and the gate electrode (9) is connected to the gate lead (G). In the arrangement of the semiconductor substrate (1), the area covered by the gate electrode (9), the body (6), and the source region (7) is a trench metal oxide semiconductor field effect transistor (MOSFET). The cell field (ZF) consists of cells, while the cross section of the first image shows only two cells. Each cell contains a single transistor. The load lines of many single transistors in parallel form metal oxide semiconductor field effect transistors (MOSFETs). In addition to the cell field (ZF), the first

第15頁 1224372 五、發明說明（12) 圖运顯不金屬氧化物半導， 包 / 、 f J琢效應電曰辦Mimeι?γτ、 邊緣區（RB)。邊緣區（RB)内雖然也=B曰體（MOSFET)的一部分 内的胞元對於總電流量並無任飼:貢^溝槽，不過邊緣區（RB) 以下以兩個實例說明本發 組件的兩種方法。 的^造第一圖之半導體 第一種製造方法（第二圖）·· 第 的標號與 這種製造方法包括以下的步驟 弟一圖相同。 片 ⑷首先準備一個以摻雜的半導體基體。 正面（2)起向下在半導體基體〇)内蝕刻出溝槽$者自曰 (b)利用沉積方式在晶片正面（2)的整個,二 場極氧化物(18)。 的整個路空表面加上一層 (〇利用沉積方式在溝槽（8)内形成一個將溝槽 輔助層（22)，例如由光刻膠構成的輔助層。接著 样Page 15 1224372 V. Description of the invention (12) The picture shows the non-metal oxide semiconducting, including the /, J, and 效应, and the edge region (RB). Although the cells in the edge region (RB) are also part of the B-body (MOSFET), there is no feed for the total current: Gong ^ trench, but the edge region (RB) will be described below with two examples Two methods. The first figure of the semiconductor manufacturing method (the second figure) is the same as that of the first figure. This manufacturing method includes the following steps. The wafer first prepares a semiconductor substrate for doping. From the front side (2), a trench is etched down in the semiconductor substrate (0). (B) The entire field of the wafer front side (2) is deposited by a deposition method, a two-field electrode oxide (18). Add a layer of the entire empty surface of the road (0 by using a deposition method to form a trench auxiliary layer (22) in the trench (8), for example, an auxiliary layer composed of a photoresist.

底部對輔助層向下蝕刻使其只剩下一段位 / S 短柱（22)。 奴位於溝槽内的光刻膠 (d) 向下蝕刻場極氧化物（8)，使場極氧化物 (1 5 )與光刻膠短柱（2 2 )的頂部處於同一高度。 、’ (e) 接著經由離子注入將硼離子及砷離子注入半導體基體 (1 )。離子注入的步驟是以注入角度45度的斜6、士 士二、佳 $二進T離子注人時，設置在溝槽（8)内的光刻膠=柱二2) 及％極氧化物（18)係作為注入掩膜之用，因此石申子及/或硼 第16頁 1224372 五、發明說明（13) f子會破注入第一個表面（2)及溝槽（8)的侧壁（10)。在太〇 中，珅的摻雜劑#、約為5 χ 1〇14 cm_2，二1ϋ i在本例 使溝槽側壁（1G)能夠均勾的被注人離子，故 種所謂的象限離子注人方式來進行離子注人工作/ ，主入硼離子後接著進行一個擴散步驟，其目的是使棚 離子進一步擴散到丰墓 吏硼 面Ο) β+體基體（）内。這樣就形成緊接在表 '曰貝，壁（1 0 )上的強η型摻雜的源極區（7 )，以及緊 源極區（7 )及溝槽側壁（丨〇 )上的弱ρ型摻雜的本體” C b ) ° (g)待離子注入步驟及擴散步驟完成後， ”光刻膠短柱(22)。接著向下韻刻場極氧化物(l8)= m:4:)的上緣(15)位置低於緊接在溝槽⑻上的。n (h )經由加熱氧化在溝槽（8)内形成閘極氧化物，並以古 的多晶矽將溝槽（8)填滿。接著利用蝕刻方式將溢出到晶" ^晶秒去除，只留下位於溝槽⑻内作為閘電極 由於源極金屬化層（13)、汲極金屬化層（12)、以及 f (14)的製造方法均屬於已知的技術，因此無需在此處加 說明。 第二種製造方法（第三圖）： 本發明提出的第二種製造方法有一部分的製造步驟與第The auxiliary layer is etched down at the bottom so that only a single bit / S stub is left (22). The photoresist (d) in the trench etches the field oxide (8) downward so that the field oxide (1 5) is at the same height as the top of the photoresist stub (2 2). (') Then, a boron ion and an arsenic ion are implanted into the semiconductor substrate (1) by ion implantation. The step of ion implantation is to implant the photoresist in the trench (8) = column 2) and% pole oxide when the T, T, T, and T 2 ions are implanted at an implantation angle of 45 degrees. (18) It is used as an implantation mask, so Shi Shenzi and / or Boron Page 16 1224372 V. Description of the invention (13) The f will break the side of the first surface (2) and the groove (8). Wall (10). In Tai 0, the dopant of yttrium is about 5 x 1014 cm_2, and 2 ϋ i in this example enables the trench sidewall (1G) to be uniformly implanted with ions, so the so-called quadrant ion implantation The ion implantation work is performed in a human way. After the main boron ions are introduced, a diffusion step is performed, the purpose of which is to diffuse the shed ions into the boron surface of the tomb cemetery. In this way, a strongly n-doped source region (7) immediately adjacent to the surface, wall (1 0), and weak regions on the source region (7) and the trench sidewall (丨 0) are formed. After the ion implantation step and the diffusion step are completed, the "p-type doped body" "Cb) °" (g) is a "photoresist stub" (22). Then, the position of the upper edge (15) of the field polar oxide (18) = m: 4 :) is lower than that immediately next to the trench ⑻. n (h) forms a gate oxide in the trench (8) through thermal oxidation, and fills the trench (8) with ancient polycrystalline silicon. Then, the overflowing crystal is removed by etching, and only the gate electrode is located in the trench 由于 due to the source metallization layer (13), the drain metallization layer (12), and f (14). The manufacturing methods are known techniques, so they need not be explained here. Second manufacturing method (third picture): The second manufacturing method proposed by the present invention has a part of manufacturing steps and

第17頁 1224372 發明說明（14) 一種製造方法相同，也就是說這兩種方法一直到形成光刻膠 短柱（22)及場極氧化物（18)的部分（相當於第一種方法的（/) --(b)部分）都是相同的。到這個步驟為止，在溝槽（8)内形 f的光刻膠短柱（22)與溝槽（8)的側壁（10)及底部（n)均隔 著具有絕緣作用的場極氧化物（丨8 )。以下是接下來的步驟。 (A)將換雜劑2：為5 X 1〇14 — — lxl〇16 cm_2的砷離子以適當的 注入角度（通常是45度）注入半導體基體（1)，且最好是採用· 象限離子注入方式。這樣就可以形成一個緊鄰表面（2)及側 壁（1 0 )的強η型摻雜的源極區（7)。 (Β)接著向下蝕刻在接下來的場極氧化物蝕刻步驟中作為掩 膜，用的光刻膠短柱（22)。待在接下來的離子注入步驟中作 為_子/主入掩膜之用的場極氧化物（1 8 )被向下钱刻至與被向 下蝕刻過的光刻膠短柱（22)相同的高度後，將摻雜劑量約為 1013 cm2的硼離子以適當的注入角度（通常是45度）注入半導 胜基體（1 )。這樣就可以形成一個緊鄰源極區（γ )及溝槽（8 ) 的弱Ρ型摻雜的本體區（6 )。 (C)接著將場極氧化物梯級（丨5 )向下蝕刻至低於緊靠在溝槽 側壁（1 0 )上的ρη結（21 )的邊緣的位置。由於這個向下钱刻的 作業可以進行的十分精確，因此一定能夠將場極氧化物（丨8) 的上緣（1 5 )向下蝕刻至低於ρη結（2丨）的位置。這樣就可以將 上緣（1 5 )與pn結（2 1 )的邊緣之間所需的最小間距縮小至最低 的程度，達到減少閘汲電容的目的。Page 1224372 Description of the invention (14) One manufacturing method is the same, that is to say, these two methods are until the formation of the photoresist pillars (22) and the field oxide (18) (equivalent to the first method) (/)-(B)) are the same. Up to this step, the photoresist stub (22) in the shape of f in the trench (8) and the sidewall (10) and bottom (n) of the trench (8) are separated by a field oxide having an insulating effect. (丨 8). Here are the next steps. (A) Doping agent 2: 5 X 1104-1x1016 cm_2 of arsenic ions is implanted into the semiconductor substrate (1) at an appropriate implantation angle (usually 45 degrees), preferably using quadrant ions Way of injection. In this way, a strongly n-doped source region (7) can be formed next to the surface (2) and the side walls (1 0). (B) Next, the photoresist stubs (22) used as a mask in the subsequent field oxide etching step are etched downward. The field oxide (18) to be used as a sub-sub / main mask in the next ion implantation step is etched down to the same length as the photoresist stub (22) etched down. After implanting the boron ions at a doping dose of about 1013 cm2 at a proper implantation angle (usually 45 degrees), the semiconductive substrate (1) is implanted. In this way, a weak P-type doped body region (6) can be formed next to the source region (γ) and the trench (8). (C) Next, the field oxide step (5) is etched down to a position lower than the edge of the ρn junction (21) abutting on the sidewall (1 0) of the trench. Since this down-cut operation can be performed very accurately, the upper edge (15) of the field oxide (丨 8) must be etched down to a position below the ρη junction (2 丨). In this way, the minimum required distance between the upper edge (1 5) and the edge of the pn junction (2 1) can be reduced to a minimum, so as to reduce the gate-drain capacitance.

1224372 五、發明說明（15) 接下來的步驟又與第一猶繫i告太 (22)你、婆祕,〇、 裡衣化方法相同，就是將光刻膠 點接ΐ 了 =源極區（7)及本體區（6)能夠對源電極（13)形成觸 是直i將？：接通區必須具有很高的摻雜濃度。通常的作法 入Ϊ if 域。完成經由溝槽側壁進行的斜向離子注 向呈门==(7)及本體區⑷就會具有一個朝表面⑺的方 通所ίΓ本體=)「的摻雜分布。將本體區⑷為形成觸點接 本體Hi方向""。在現有的半導體組件的製造方法中， 上，0 π I 23)都教育設置在對準胞元及/或溝槽（8)的方向 距。口此本體接觸區（8)與溝槽（8)之間必須相隔一個最小間 有利ϋ顯7" m之+導體組件中本冑區（6)的一種 = f觸方式。為了形成本體接觸區⑵），應在使用 产报言的=Σ狀溝槽（8)，的離子注入掩膜的情況下將摻雜濃 二二二子合注人半導體基體（1)内，被注人半導體（1)内 r ® π ^ I?變源極區（7)在該處從表面到本體區（6)之間的 參雜分佈，但先決條件是，注入…子的摻 f f 7 =々形成的的ρ型摻雜需明顯大於該處原有之源極 &⑺的Π型摻雜。源極區接片(24)處於含有本體接觸區⑵) 1224372 五、發明說明（16) 逼(2°)上方緊靠溝槽(8)的位置。這些源極區接 ⑺彼此連接n 盍住的源極區 (3)對也太可:垃在沒有掩膜遮蔽的情況下經由表面⑺向源極區 觸：接觸 (23)進行離子注入。為了形成源極區⑺的 =妾觸’必須將位於溝槽⑻内的閘極氧化物⑴）及閘電 J 一直向下蝕刻，直到源極區（7)能夠從側面經由溝槽側 土（ 1 〇)形成觸點接通為止。不過這種實 中繪出。 、、禋Μ鈿方式亚未在第四圖 本發明的製造方法的應用 的實施方式，而是可以透過導 改變摻雜濃度等方式，製造出 雖然在前面說明的實施方式均 場效應電晶體（MOSFET)的半導 法的應用範圍並不僅限於此種 以應用於溝槽式IGBT的製造。 綜上所述可知，利用本發 化物作為遮蔽掩膜的情況下， 料經由溝槽側壁注入，即可十 電極梯級的位置控制在略低於 位置。 範圍並不限於第一圖——4顯示 電型（η型及p型）的互換，以及 其他多種不同的半導體組件。 屬於溝槽式金屬氧化物半導體 體組件，但是本發明的製造方 半導體組件的製造，而是也可 明的方法，也就是在以場極氧 以斜向離子注入方式將摻雜材 分簡單、但卻非常有效的將閘 本體區及漂移區之間的ρη結的1224372 V. Description of the invention (15) The next step is the same as that of the first report (22) You, mystery, and lining. The method is to connect the photoresist dots to the source region. (7) and the body area (6) can contact the source electrode (13). : The turn-on region must have a high doping concentration. The usual practice is to enter the if field. After the oblique ion implantation through the trench sidewall is completed, the gate == (7) and the body region ⑷ will have a doping distribution toward the surface ί, the body =) ". The body region is formed to form a contact Tap the body in the Hi direction " ". In the existing method of manufacturing a semiconductor device, 0 π I 23) is educated and set in a direction distance aligned with the cell and / or the groove (8). This body There must be a minimum space between the contact area (8) and the groove (8). A “f” contact method of the local area (6) in the + m + conductor assembly. In order to form the body contact area (⑵), In the case of using the ion implantation mask of the = Σ-shaped trench (8), the dopant should be implanted into the semiconductor substrate (1) and into the semiconductor (1). r ® π ^ I? The heterogeneous distribution of the source region (7) from the surface to the bulk region (6), but the prerequisite is that the implanted… The doping needs to be significantly larger than the original type & ⑺-type doping of the source. The source region tab (24) contains the body contact region ⑵) 1224372 V. Description of the invention (16) Close to the trench (8) above (2 °). These source regions are connected to each other and the source region (3) held by the pair is also too good: in the case of no masking Downward contact through the surface ⑺ toward the source area: contact (23) for ion implantation. In order to form the source area 妾 = 妾 contact ', the gate oxide ⑴ in the trench ⑻) and the gate current J must be directed downwards. Etching until the source region (7) can be contacted from the side through the trench side soil (10). However, this is actually drawn. The method is not shown in the fourth figure. The application method of the manufacturing method is to change the doping concentration through conduction, and the method of manufacturing the semiconductor field-effect transistor (MOSFET) of the embodiment described above is not limited to this application. It is applied to the manufacture of trench IGBTs. In summary, it can be known that in the case of using the present compound as a mask, the material is injected through the trench sidewall, and the position of the ten-electrode step can be controlled to be slightly lower than the range. Not limited to the first figure-4 shows electrical type (n-type and p-type And other various semiconductor components. It belongs to the trench metal oxide semiconductor body component, but the manufacturing method of the semiconductor component of the present invention is also a clear method, that is, the field electrode oxygen is used to obliquely. Diffusion of dopants into the ion implantation method is simple, but it is very effective in separating the ρη junction between the gate body region and the drift region.

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1224372 圖式簡單說明 第一圖：係本發明之構成溝槽式金屬氧化物半導體場效應 電晶體（MOSFET)的半導體組件的部分斷面圖。 第一圖（a ):係一個溝槽的部分放大圖（a )。 第二圖（a)至（h):係說明如何以本發明的第一種製造方法 製造第一圖之半導體組件之部份斷面（a)--(h)。 第三圖（a)至（c):係說明如何以本發明的第二種製造方法 製造第一圖之半導體組件之部分斷面（A)--(C)。 第四圖：係製造本體--源極接觸的第一種有利的方法的部 分斷面圖。 1 4防腐氧化物層 1 5梯級 元件符號說明 1半導體組件 4 >及極區 7 源極區 1 0溝槽側壁 1 3源極金屬化層 1 6溝槽下半部 1 9閘極氧化物 2 2光刻膠短柱 2 晶片正面 5 漂移區 8溝槽 11溝槽底部 1 7溝槽上半部 20通道 2 3本體接觸區 3晶片背面 6 本體區 9 閘電極 1 2沒極金屬化層 1 8場極氧化物 2 1 ρ η 結 24源極區接片1224372 Brief description of the drawings The first diagram: a partial cross-sectional view of a semiconductor device constituting a trench type metal oxide semiconductor field effect transistor (MOSFET) of the present invention. The first picture (a): a partial enlarged view of a groove (a). The second diagrams (a) to (h): Partial cross-sections (a)-(h) illustrating how to manufacture the semiconductor device of the first diagram by the first manufacturing method of the present invention. The third figures (a) to (c) are diagrams (A)-(C) of the semiconductor device of the first figure, which illustrate how to manufacture the semiconductor device of the first figure by the second manufacturing method of the present invention. Figure 4: Partial cross-sectional view of the first advantageous method of manufacturing the body-source contact. 1 4 Anticorrosive oxide layer 1 5 Symbol description of step elements 1 Semiconductor device 4 > and 7 electrode regions 1 0 trench sidewall 1 3 source metallization layer 6 6 lower half of trench 1 9 gate oxide 2 2 Photoresist post 2 Front side of the wafer 5 Drift region 8 Trench 11 Trench bottom 1 7 Upper half of the trench 20 channels 2 3 Body contact area 3 Back side of the wafer 6 Body area 9 Gate electrode 1 2 Electrodeless metallization layer 1 8 field oxide 2 1 ρ η junction 24 source region tab

第22頁 1224372 圖式簡單說明 D汲極引出線 S 源極引出線 G 閘極引出線 ZF胞元場 RB邊緣區 第23頁Page 22 1224372 Brief description of the diagram D Drain lead S Source lead G Gate lead ZF cell field RB edge area

Claims (1)

1224372 _案號92103250_年月日_«__ 六、申請專利範圍 1 . 一種製造可經由場效應控制的半導體組件的方法，半 導體組件的閘電極（（9 )設置在溝槽（8 )内，並經由電介質 (1 8，1 9 )與其他部位絕緣，此種製造方法的步驟如下： (a)準備一個第一種導電型的半導體基體（1)，接著自第 一個表面面（2)起向下在半導體基體（1)内至少蝕刻出一個 溝槽（8 ); (b )在溝槽（8 )的側壁（1 0 )及底部（1 1 )覆蓋上一個絕緣層 (18)； (c )用一個輔助層（2 2 )將溝槽（8 )的下半部（1 6 )填滿； (d )將絕緣層（1 8 )未被輔助層（2 2 )覆蓋住的部分去除； (e )以仍留在溝槽（8 )内的絕緣層（1 8 )及/或輔助層（2 2 )作 為離子注入掩膜，將第一種及第二種導電型離子經由溝槽 側壁（1 0 )注入半導體基體（1 )内為源極區（7 )保留的區域 内。 2. 如申請專利範圍第1項的製造方法，其特徵為：以熱處 理方式使第二種導電型離子自本體區（6 )被向外擴散以形 成本體區（6)。 3. 一種製造可經由場效應控制的半導體組件的方法，半 導體組件的閘電極（（9 )設置在溝槽（8 )内，並經由電介質 (1 8，1 9 )與其他部位絕緣，此種製造方法的步驟如下： (A)準備一個第一種導電型的半導體基體（1)，接著自第 一個表面（2)起向下在半導體基體（1)内至少蝕刻出一個溝1224372 _Case No. 92103250_Year Month _ «__ VI. Patent Application Scope 1. A method for manufacturing a semiconductor device that can be controlled by field effect, the gate electrode ((9) of the semiconductor device is arranged in the trench (8), It is insulated from other parts through dielectrics (18, 19). The steps of this manufacturing method are as follows: (a) Prepare a semiconductor substrate of the first conductivity type (1), and then from the first surface (2) At least one trench (8) is etched from the semiconductor substrate (1) upward and downward; (b) a sidewall (1 0) and a bottom (1 1) of the trench (8) are covered with an insulating layer (18); (c) filling the lower half (1 6) of the trench (8) with an auxiliary layer (2 2); (d) the part of the insulating layer (1 8) not covered by the auxiliary layer (2 2) Removing; (e) using the insulating layer (1 8) and / or the auxiliary layer (2 2) remaining in the trench (8) as an ion implantation mask to pass the first and second conductive ions through the trench The trench sidewall (1 0) is implanted into the semiconductor substrate (1) in a region reserved for the source region (7). 2. If the manufacturing method according to item 1 of the patent application scope is characterized in that The second conductive type ion is diffused outward from the body region (6) to form a body region (6) by heat treatment. 3. A method of manufacturing a semiconductor device controllable by field effect, a gate electrode of the semiconductor device (( 9) It is arranged in the trench (8) and insulated from other parts through the dielectric (18, 19). The steps of this manufacturing method are as follows: (A) Prepare a semiconductor substrate of the first conductivity type (1) , And then etch at least one groove in the semiconductor substrate (1) downward from the first surface (2) 第24頁 1224372 92103250 修正 曰 六、申請專利範圍 槽（8 ); (B) 在溝槽（8)的側壁（10)及底 (18); - 4 ( 1 1 )覆盍上一個絕緣層 (C) 1 一個輔助層（22)將溝槽（8)的下 將ff層(18)未被輔助層(⑵覆蓋住的部分真去V. 為離：溝槽(8)内的絕緣層（18)及/或輔助層(于22)作 為離子注入掩膜，將第一種曰（22)作 注入半導體基體⑴内，以形成△離區子(「)由溝槽側壁(1〇) (F )向下蝕刻殘留的絕緣層（丨8 ); =仍留在溝槽（8)内的絕緣層（18)及/或輔助層 ^子注入掩膜，將第二種導電型離子經由溝；j*二@ n ^ ;主入半導體基體⑴内，以形成緊鄰源極區(?=;(1。) (6 )。 、〖J的本體區 ’、,其特徵為：在步驟 並將未被輔助層 4·如申請專利範圍第3項的製造方法 (G)之前進一步向下蝕刻輔助層（22)， (2 2 )覆蓋的絕緣層（1 8 )部分去除。 5 ·如申請專利範圍第1項至第4項的製造方法， 馬·在形成本體區（7 )之後，將絕緣層（1 8 )向下钱 到絕緣層（1 8 )的上緣（1 5 )略低於或略高於本體區（* 導體基體（1 )之間的pn結（2 1 )觸及溝槽備壁（丨〇 )的 f半 止。 置為 6·如申請專利範圍第1項至第4項的製造方Page 24 1224372 92103250 Amendment VI. Patent Application Slot (8); (B) Cover the side wall (10) and bottom (18) of the groove (8);-4 (1 1) with an insulation layer ( C) 1 An auxiliary layer (22) removes the lower layer ff layer (18) of the trench (8) without the auxiliary layer (the part covered by 真 really goes to V. is away: the insulating layer in the trench (8) ( 18) and / or the auxiliary layer (at 22) as an ion implantation mask, and the first type (22) is implanted into the semiconductor substrate ⑴ to form a delta ion region (") from the trench sidewall (1〇) ( F) Etching the remaining insulating layer (丨 8) downwards; = the insulating layer (18) and / or the auxiliary layer remaining in the trench (8) are implanted into the mask, and the second conductive ion is passed through the trench ; J * 二 @ n ^; Mainly into the semiconductor substrate ⑴ to form a source region (? =; (1.) (6)., "The body region of J '," characterized in that in the step and Unassisted layer 4. If the manufacturing method (G) of item 3 of the patent application is applied, the auxiliary layer (22) is further etched downward, and the insulating layer (1 8) covered by (2 2) is partially removed. 5 • If applied for a patent Manufacturing methods in the range of items 1 to 4, · After forming the body area (7), lower the insulating layer (1 8) down to the upper edge (1 5) of the insulation layer (1 8) slightly lower than or slightly higher than the body area (* conductor base (1) The pn junction (2 1) between them touches the f-half of the trench preparation wall (丨 〇). Set to 6 · If the manufacturer of the patent application ranges from item 1 to item 4, 第25頁 1224372 _案號 92103250_年月日__ 六、申請專利範圍 法，其特徵為：在完成離子注入的步驟後，進行以下的步 驟： --去除輔助層（22); --在溝槽（8 )的露空的側壁（1 0 )上設置另外一個厚度比絕 緣層（1 8 )薄的絕緣層（1 9 ); --用一種適當的導電材料將溝槽（8 )填滿以形成閘電極 (9)； --形成本體接觸區（23)以產生本體區（6)的觸點接通，形 成本體接觸區（23)的方式是將第二種導電型離子經由第一 個表面（2)注入半導體基體（1)内。 7 ·如申請專利範圍第1項至第4項的製造方法，其特徵 為：輔助層（2 2 )是由一種光刻膠所構成。 8. 如申請專利範圍第1項至第4項的製造方法，其特徵 為：為輔助層（2 2 )設置一個以導電材料形成閘電極（9 )。 9. 如申請專利範圍第5項的製造方法，其特徵為：為輔助 層（2 2 )設置一個以導電材料形成閘電極（9 )。 1 0.如申請專利範圍第1項至第4項的製造方法，其特徵 為：以砷離子作為被注入的第一種導電型離子。Page 25 1224372 _Case No. 92103250_Year Month Date__ VI. The patent application method is characterized in that after completing the ion implantation step, the following steps are performed:-removing the auxiliary layer (22);-in On the exposed side wall (1 0) of the trench (8), another insulating layer (19) having a thickness smaller than that of the insulating layer (18) is provided;-the trench (8) is filled with a suitable conductive material Full to form the gate electrode (9);-forming the body contact area (23) to generate the contact of the body area (6), and the way to form the body contact area (23) is to pass the second conductive type ion through the first A surface (2) is injected into the semiconductor substrate (1). 7. The manufacturing method according to claims 1 to 4 of the scope of patent application, characterized in that the auxiliary layer (2 2) is made of a photoresist. 8. The manufacturing method according to the scope of claims 1 to 4 of the patent application, which is characterized in that: the auxiliary layer (2 2) is provided with a conductive material to form the gate electrode (9). 9. The manufacturing method according to item 5 of the scope of patent application, characterized in that a gate electrode (9) is formed of a conductive material for the auxiliary layer (2 2). 10. The manufacturing method according to claims 1 to 4 of the scope of patent application, characterized in that arsenic ions are used as the first conductive type ions to be implanted. 第26頁 1224372 _案號921Q3250_年月日_«_ 六、申請專利範圍 1 1 ·如申請專利範圍第1項至第4項的製造方法，其特徵 為：以硼離子作為被注入的第二種導電型離子。 1 2.如申請專利範圍第1項至第4項的製造方法，其特徵 為：第一種導電型離子的注入劑量至少比第二種導電型離 子的注入劑量高出一個數量級。 1 3.如申請專利範圍第1項至第4項的製造方法，其特徵 為：第一種導電型離子及/或第二種導電型離子是以和第 一個表面（2)呈15--75度（尤其是3 0 — 6 0度，且最好是45 度）的注入角度的方式注入。 1 4 ·如申請專利範圍第1項至第4項的製造方法，其特徵 為：離子注入步驟係以象限離子注入的方式進行。 15.如前述申請專利範圍第1項至第4項的製造方法，其特 徵為：將第二種導電型離子經由被掩膜遮蔽的第一個表面 (2 )注入半導體組件（1 ))内，以形成本體接觸區（2 3 )，此 處之掩膜是由垂直並對齊於溝槽（8)的本體接觸區（23)所 形成。Page 26 1224372 _Case No. 921Q3250_Year Month Date _ «_ VI. Application for Patent Scope 1 1 · If the manufacturing method for the scope of patent applications Nos. 1 to 4, it is characterized by using boron ions as the implanted No. Two conductive ions. 1 2. The manufacturing method of items 1 to 4 of the scope of patent application, characterized in that the implantation dose of the first conductivity type ions is at least an order of magnitude higher than the implant dose of the second conductivity type ions. 1 3. The manufacturing method according to claims 1 to 4 of the scope of patent application, characterized in that the first conductivity type ions and / or the second conductivity type ions are 15- to the first surface (2). -75 degrees (especially 30-60 degrees, and preferably 45 degrees). 1 4 · The manufacturing method according to claims 1 to 4 of the scope of patent application, characterized in that the ion implantation step is performed by means of quadrant ion implantation. 15. The manufacturing method according to items 1 to 4 of the aforementioned patent application range, characterized in that: the second conductive type ion is implanted into the semiconductor device (1) via the first surface (2) masked by the mask. To form a body contact area (2 3), and the mask here is formed by the body contact area (23) that is vertical and aligned with the groove (8). 第27頁 1224372 六 案號 92103250 申讀專利範圍 曰 修正 16•如珂述申請專利範圍第i項至第4項的製造方法，其特 徵為：為形成本體接觸區（23)，將第二種導電型離子以大 面積立沒有被掩膜遮蔽的方式經由第一個表面（2 )注入半 導體耝件（1 ))内，並將形成閘電極（9 )的材料向下蝕刻至 溝槽（8 )内源極區（7 )與溝槽側壁（丨〇 )交界之處。 ι7· /種設置在半導體基體内且可經由 體組件： 一一矣少具有一個汲極區（4, 5)及至少一個第—種導電型 的源極區（7 ) ’ 一一矣少///個設置在汲極區（4, 5)及源極區（7)之間的 第二種導笔型的本體區（6)， 一一灵少具有一個從第一個表面（2)通過源極區（7)、本體 區（6)、一直伸入汲極區（4，5)的溝槽（8)， 一一奚少具有一個閘電極（9 )，此閘電極（9 )係設置在溝槽 場效應控制的半導 (8)内，並以電介質（18，19)與半導體基體（1)絕緣，其中 位於溝槽上半部（1 7)的電介質是較薄的閘極氧化物（1 9)， 位於溝槽下半部（1 6)的電介質則是較厚的場極氧化物 (1 8 )，且在閘極氧化物（1 9 )及場極氧化物（1 8 )的交界處有 一個梯級（1 5 )， 此種半導體組件的特徵為··本體區（6 ) i少有一部分從溝 槽側壁（10)起埋入半導體基體（1)内，形成於本體區（6)及 汲極區（4，5 )之間的p n結（2 1 )與溝槽側壁（1 0 )的接觸位置Page 27 1224372 Six cases No. 92103250 Application scope of the patent is amended 16 • Ru Keshu applied for the scope of patent application for items i to 4 of the manufacturing method, which is characterized by: in order to form the body contact area (23), the second The conductive ions are implanted into the semiconductor element (1) through the first surface (2) in a large area without being masked by the mask, and the material forming the gate electrode (9) is etched down to the trench (8) ) Where the inner source region (7) intersects with the trench sidewall (丨 0). ι7 · / types are arranged in the semiconductor substrate and can pass through the body component:-one has at least one drain region (4, 5) and at least one source region (7) of the first conductivity type-one by one / // A second guide-type body region (6) disposed between the drain region (4, 5) and the source region (7). One spirit has one from the first surface (2) Through the source region (7), the body region (6), and the trenches (8) extending straight into the drain region (4, 5), one gate electrode (9) is provided at a time, and the gate electrode (9) It is arranged in the semiconductor field-conductor (8) controlled by the trench field effect, and is insulated from the semiconductor substrate (1) by dielectrics (18, 19). The dielectric located in the upper half of the trench (1 7) is a thin gate. The electrode oxide (1 9), the dielectric located in the lower half (1 6) of the trench is a thicker field oxide (1 8), and the gate oxide (1 9) and the field oxide ( There is a step (1 5) at the junction of 18). This type of semiconductor component is characterized by the body region (6) i. A small part is buried in the semiconductor substrate (1) from the trench sidewall (10) to form In the body area (6) and drain Contact position of the pn junction (2 1) between the regions (4, 5) and the trench sidewall (1 0) 第28頁Page 28 1224372 _案號92103250_年月日_修正 六、申請專利範圍 是以階梯狀的梯級（1 5 )為準。 1 8.如申請專利範圍第1 7項的半導體組件，其特徵為：整 個閘電極（9 )都位於溝槽（8 )内，且源極區（7 )只有緊鄰溝 槽側壁（1 0 )的部分會被閘電極（9)覆蓋住。 1 9 .如申請專利範圍第1 7項或第1 8項的半導體組件，其特 徵為：在第一個表面（2 )的配置設計中，溝槽（8 )係製作成 條帶狀、格間狀、或是矩形波狀。 2 0 .如申請專利範圍第1 7項或第1 8項的半導體組件，其特 徵為：為形成本體區（6)的觸點接通故設置本體接觸區 (23)，本體接觸區（23)的方向與溝槽（8)垂直，並與溝槽 (8 )緊鄰在一起。 2 1 ·如申請專利範圍第1 7項或第1 8項的半導體組件，其特 徵為：場極氧化物（1 8 )的厚度是2 0 nm到2 //之間，閘極氧 化物（1 9 )的厚度是數nm到1 0 Onm之間。 2 2 .如申請專利範圍第1 7項或第1 8項的半導體組件，其特 徵為：閘電極（9 )含有多晶矽，絕緣層（1 8，1 9 )含有二氧 化矽（S i 0 2 )。1224372 _ Case No. 92103250_ Year Month Date_ Amendment 6. The scope of patent application is based on the step-like steps (1 5). 1 8. The semiconductor device according to item 17 of the scope of patent application, characterized in that the entire gate electrode (9) is located in the trench (8), and the source region (7) is only adjacent to the trench sidewall (1 0) The part will be covered by the gate electrode (9). 19. If the semiconductor component of item 17 or item 18 in the scope of patent application is characterized in that in the configuration design of the first surface (2), the groove (8) is made into a strip-like, grid-like structure. Intermittent or rectangular wavy. 20. If the semiconductor component of the 17th or 18th in the scope of patent application is applied, it is characterized in that a body contact area (23) and a body contact area (23) are provided for the contacts forming the body area (6) to be connected. The direction of) is perpendicular to the groove (8) and is close to the groove (8). 2 1 · If the semiconductor device under item 17 or item 18 of the patent application scope is characterized in that the thickness of the field oxide (1 8) is between 20 nm and 2 //, the gate oxide ( 19) The thickness is between a few nm and 10 Onm. 2 2. The semiconductor device according to item 17 or item 18 of the scope of patent application, characterized in that the gate electrode (9) contains polycrystalline silicon, and the insulating layer (18, 19) contains silicon dioxide (S i 0 2 ). 第29頁 1224372 _案號9210325Q_年月日_«_ 六、申請專利範圍 2 3 .如申請專利範圍第1 7項或第1 8項的半導體組件，其特 徵為：將半導體組件製作成垂直式半導體組件。 2 4.如申請專利範圍第1 7項或第1 8項的半導體組件，其特 徵為··將半導體組件製作成上汲式（Up-Dr a in)式半導體組 件0Page 29 1224372 _Case No. 9210325Q_Year Month Day _ «_ VI. Application for Patent Scope 2 3. For the semiconductor components with the scope of patent application No. 17 or No. 18, it is characterized by making the semiconductor components vertical Semiconductor device. 2 4. If the semiconductor component of the 17th or 18th in the scope of the patent application, the characteristics of the semiconductor component are made into an up-dr ain type semiconductor component. 0 第30頁Page 30
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