TWI222106B - Semiconductor substrate, field-effect transistor, and their production methods - Google Patents

Semiconductor substrate, field-effect transistor, and their production methods Download PDF

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Publication number
TWI222106B
TWI222106B TW092102412A TW92102412A TWI222106B TW I222106 B TWI222106 B TW I222106B TW 092102412 A TW092102412 A TW 092102412A TW 92102412 A TW92102412 A TW 92102412A TW I222106 B TWI222106 B TW I222106B
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Taiwan
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layer
sige layer
sige
composition ratio
semiconductor substrate
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TW092102412A
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Chinese (zh)
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TW200415707A (en
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Ichiro Shiono
Masaharu Ninomiya
Hazumu Kougami
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Sumitomo Mitsubishi Silicon
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Abstract

There is a first layer formation step, second layer formation step, heat treatment step and polishing step; the first layer formation step sets the thickness of the first SiGe layer to be thinner than twice the critical thickness, which is the thickness at which increasing the thickness produces dislocations and lattice relaxation does not occur; and the second layer formation step makes the Ge compositional ratio of the second SiGe layer lower than the highest value in the layer of the Ge compositional ratio in at least the first SiGe layer, or the Ge compositional ratio of the SiGe layer at the contact surface with Si, and moreover, at least partially forms a sloping composition region in which the Ge compositional ratio gradually increases toward the surface. As a result, along with the threading dislocation density being low and surface roughness being small, deterioration of the surface and boundary roughness during heat treatment in a device manufacturing process or the like is prevented.

Description

1222106 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於一種使用在高速度MOSFET等之半導 體基板及場效型電晶體以及此等之製造方法。 【先前技術】 近年來，提議在Si (矽）基板上透過SiGe (矽鍺） 層而將進行磊晶成長之歪斜Si層使用在通道區域上之高 速度 MOSFET、MODFET、HEMT。在該歪斜 Si_FET，藉 由格子常數大於Si之SiGe，而在Si層，進行拉伸，產生 歪斜，因此，Si之頻帶構造發生變化，解除退縮而提高 載體遷移率。因此，可以藉由使用該歪斜Si層，作爲通 道區域，而達到通常之1 . 3〜8倍左右之高速度化。此外 ，作爲製程係可以使用藉由CZ法所造成之通常之Si基板 ，作爲基板，能夠藉由習知之CMOS作業而實現高速度 CMOS 〇 但是，爲了作爲FET之通道區域而使得所要求之前 述歪斜Si層進行磊晶成長，因此，必須在Si基板上，使 得良質之SiGe層進行磊晶成長，但是，由於Si和SiGe 間之格子常數之不同，因此，因爲錯位等而造成結晶性之 問題產生。所以，向來係進行以下各種之提議。 例如提議：使用以一定之緩和傾斜而改變SiGe之Ge 組成比之緩衝層之方法、使用呈台階狀（階梯狀）地改變 Ge (鍺）組成比之緩衝層之方法、使用呈超格子狀地改變 -6 - (2) (2)12221061222106 (1) Description of the invention [Technical field to which the invention belongs] The present invention relates to a semiconductor substrate, a field-effect transistor, and a method for manufacturing the same, which are used in a high-speed MOSFET and the like. [Previous technology] In recent years, it has been proposed to use a high-speed MOSFET, MODFET, and HEMT on the channel region by using a skewed Si layer for epitaxial growth through a SiGe (silicon germanium) layer on a Si (silicon) substrate. In this skewed Si_FET, SiGe having a lattice constant larger than that of Si is stretched in the Si layer to cause distortion. Therefore, the band structure of Si is changed, and the shrinkage is cancelled to improve the carrier mobility. Therefore, by using the skewed Si layer as a channel region, it is possible to achieve a high speed of about 1.3 to 8 times. In addition, as the process system, a normal Si substrate caused by the CZ method can be used. As the substrate, a high-speed CMOS can be realized by a conventional CMOS operation. However, the above-mentioned skew is required in order to serve as a channel region of the FET. The Si layer is epitaxially grown. Therefore, a good SiGe layer must be epitaxially grown on the Si substrate. However, due to the difference in lattice constants between Si and SiGe, crystallinity problems arise due to misalignment and the like. . Therefore, the following various proposals have been made. For example, it is proposed to use a buffer layer that changes the Ge composition ratio of SiGe with a certain gentle slope, a buffer layer that changes the Ge (germanium) composition ratio in a stepped (stepped) manner, and use a superlattice pattern. Change -6-(2) (2) 1222106

Ge (鍺）組成比之緩衝層之方法、以及使用Si (矽）之 切斷晶圓而以一定之傾斜而改變Ge組成比之緩衝層之方 法等。 以下，列舉文獻。 專利文獻1 :美國專利第6，1 0 7，6 5 3號說明書 專利文獻2 :美國專利第5，442，205號說明書 專利文獻3 :美國專利第5，22 1，4 1 3號說明書 專利文獻4:國際公開第98/00857號簡介小冊子 專利文獻5:日本特開平6-2 5 2 046號公報 但是，在前述習知技術，殘留以下之課題。 也就是說，使用前述習知技術而進行成膜之SiGe層 係成爲貫通錯位密度或表面粗糙無法達到作爲元件及製造 製程所要求之水準之狀態。 例如在使用使得Ge組成比呈傾斜之緩衝層之狀態下 ，可以使得貫通錯位密度，變得比較低，但是，會有表面 粗糙呈惡化之意外發生，相反地，在使用使得Ge組成比 成爲階梯狀之緩衝層之狀態下，可以使得表面粗糙，變得 比較小，但是，會有貫通錯位密度變大之意外發生。此外 ，在使用切斷晶圓之狀態下，錯位係不是在成膜方向而是 容易脫離於橫向，但是，還無法達到充分之低錯位化。即 使是就表面粗糙而言’也還無法達到近年來之LSI (大型 積體電路）等之光微影製程所要求之程度。 【發明內容】 (3) (3)1222106 【發明之揭示】 本發明係有鑒於前述課題而完成的；其目的係提供〜 種能夠使得貫通錯位密度變低且表面粗糙也變小至實用程 度爲止之半導體基板及場效型電晶體以及此等之製造方法 〇 本發明之半導體基板之製造方法，係藉由在Si基板 上而對於SiGe層進行磊晶成長的半導體基板之製造方法 ，具有：在前述Si基板上而對於第一 SiGe層進行磊晶成 長之第一層形成作業、在前述第一 SiGe層上直接或透過 磊晶成長之Si層而對於第二SiGe層進行磊晶成長之第二 層形成作業、在藉由磊晶成長而形成前述SiGe層之途中 或形成後、於超過該磊晶成長溫度之溫度而施加熱處理之 熱處理作業、以及在前述SiGe層形成後藉由硏磨而除去 在前述熱處理所產生之表面凹凸之硏磨作業；此外’前述 第一層形成作業係設定前述第一 SiGe層之膜厚更加薄於 成爲藉由膜厚之增加來產生錯位而產生晶格鬆弛之膜厚之 臨界膜厚之2倍，前述第二層形成作業係形成使得前述第 二SiGe層之Ge組成比至少在和前述第一 SiGe層或前述 Si間之接觸面而更加低於第一 SiGe層之Ge組成比之層 中最大値並且至少一部分之Ge組成比朝向表面而逐漸地 增加的傾斜組成區域，以便於解決前述課題。 最好是在本發明中，前述第一層形成作業係前述第一 SiGe層之Ge組成比X成爲一定，使得第一 SiGe層’成 爲滿足下列關係式： -8- (4) (4)1222106 tc ( nm ) = ( 1 . 9x 1 〇·3/ 5 ( χ ) 2 ) · In ( tc/ 0.4 ) e ( x ) = ( a〇 + 0.2003 26x + 〇. 026 1 74x2/ a〇 ) a〇 = 0.543nm ( aG係Si之格子常數） 之臨界膜厚t。之2倍未滿之厚度。 此外，最好是在本發明中，前述第二SiGe層係直接 配置在前述第一 SiGe層上，並且，成爲層整體之Ge組成 比朝向表面而逐漸增加的傾斜組成層。 本發明之前述第一 SiGe層係也可以採用Ge組成比χ 成爲0.05以上及0.3以下之手段。 本發明係在Si基板上透過SiGe層而形成歪斜Si層 的半導體基板之製造方法，可以在藉由前述半導體基板之 製造方法所製作之半導體基板之前述第二SiGe層上，直 接或透過其他SiGe層，而對於前述歪斜Si層，進行磊晶 成長。 本發明之半導體基板之製造方法，係藉由在Si基板 上而對於SiGe層進行磊晶成長的半導體基板之製造方法 ’具有：在前述Si基板上而對於第一 SiGe層進行磊晶成 長之第一層形成作業、在前述第一 SiGe層上直接或透過 磊晶成長之Si層而對於第二SiGe層進行磊晶成長之第二 層形成作業、在藉由磊晶成長而形成前述SiGe層之途中 或形成後、於超過該磊晶成長溫度之溫度而施加熱處理之 熱處理作業、以及在前述SiGe層形成後藉由硏磨而除去 -9- (5) (5)1222106 在前述熱處理所產生之表面凹凸之硏磨作業；此外’前述 第一層形成作業係設定前述第一 Si Ge層之膜厚更加薄於 成爲藉由膜厚之增加來產生錯位而產生晶格鬆弛之膜厚之 臨界膜厚之2倍，前述第二層形成作業係以連續之Ge組 成比而重複地進行複數次之對於朝向表面而逐漸地增加 Ge組成比之SiGe傾斜組成層來進行磊晶成長之作業以及 藉由前述傾斜組成層之最後Ge組成比而在傾斜組成層上 來對於SiGe —定組成層進行磊晶成長之作業，形成Ge組 成比沿著成膜方向具有傾斜而呈階梯狀地進行變化之前述 第二SiGe層之薄膜，使得該第二SiGe層下面之Ge組成 比，更加低於前述第一 SiGe層之Ge組成比之層中之最大 値，以便於解決前述課題。 最好是在(本發明中，前述第一層形成作業係前述第一 SiGe層之Ge組成比X成爲一定，使得第一 SiGe層，成 爲滿足下列關係式： tc(nm) = ( 1.9x 1 Ο*3/ ε ( χ ) 2 ) · In ( tc/ 0.4 ) £ (x)二（a〇 + 0.2003 26x + 0.026 1 74x2/ a〇 ) a〇= 0.5 43 nm ( a〇係Si之格子常數） 之臨界膜厚t。之2倍未滿之厚度。 此外，在本發明中，前述第一 SiGe層係也可以採用 Ge組成比χ成爲〇 . 〇 5以上及〇 . 3以下之手段。 本發明係在Si基板上透過SiGe層而形成歪斜Si層 -10- (6) (6)1222106 的半導體基板之製造方法，可以在藉由前述任一項所記載 之半導體基板之製造方法所製作之半導體基板之前述第二 SiGe層上，直接或透過其他SiGe層，而對於前述歪斜Si 層，進行磊晶成長。 本發明之半導體基板，係藉由具有Si基板、該Si基 板上之第一 SiGe層以及直接或透過Si層而配置在該第一 SiGe層上之第二SiGe層，前述第一 SiGe層係成爲更加 薄於藉由膜厚之增加來產生錯位而產生晶格鬆弛之膜厚之 臨界膜厚之2倍之膜厚，前述第二SiGe層係具有使得其 Ge組成比至少在和前述第一 SiGe層或前述Si間之接觸 面而更加低於第一 SiGe層之Ge組成比之層中最大値並且 至少一部分之Ge組成比朝向表面而逐漸地增加的傾斜組 成區域，藉由前述半導體基板之製造方法而進行製作，以 便於解決前述課題。 最好是在本發明中，前述第一 SiGe層，係Ge組成比 X成爲一定，成爲滿足下列關係式： t c ( nm ) = (1·9χ10-3/ε ( χ ) 2 ) ·1η(ΐ<；/0.4) £ ( χ ) = ( a〇 + 0.200326χ + 0·026174χ2 / a〇) a〇 = 0.543nm ( aG係Si之格子常數） 之臨界膜厚t。之2倍未滿之厚度。 此外，在本發明中，前述第一 S i G e層係也可以採用 Ge組成比χ成爲0.05以上及0.3以下之手段。 -11 - (7) (7)1222106 本發明之前述第二SiGe層係可以直接配置在前述第 一 SiGe層上，並且，成爲層整體之Ge組成比朝向表面而 逐漸增加的傾斜組成層。 最好是在本發明中，具有直接或透過其他SiGe層而 配置在前述半導體基板之前述第二SiGe層上之歪斜Si層 〇 本發明之半導體基板，係藉由具有Si基板、該Si基 板上之第一 SiGe層以及直接或透過Si層而配置在該第一 SiGe層上之第二SiGe層，前述第一 SiGe層係成爲更加 薄於藉由膜厚之增加來產生錯位而產生晶格鬆弛之膜厚之 臨界膜厚之2倍之膜厚，前述第二SiGe層係交互地且以 連續之Ge組成比，來構成朝向表面而使得Ge組成比逐 漸地增加之SiGe傾斜組成層和以該傾斜組成層上面之Ge 組成比而配置在傾斜組成層上之S i Ge —定組成層，成爲 複數層層積狀態，前述第二SiGe層下面之Ge組成比係構 成爲更加低於前述第一 SiGe層之Ge組成比之層中最大値 ，藉由前述半導體基板之製造方法而進行製作，以便於解 決前述課題。 最好是在本發明中，前述第一 SiGe層，係Ge組成比 X成爲一定，成爲滿足下列關係式： tc(nm) = ( 1 .9x ΙΟ-3/ ε ( χ ) 2 ) · In ( tc/ 0.4 ) ε (χ) ~ ( a〇 + 0.200326χ + 0.026174x2/a〇) a〇= 〇.5 43 nm ( a〇係Si之格子常數） -12- (8) (8)1222106 之臨界膜厚t。之2倍未滿之厚度。 此外，在本發明中，前述第一 SiGe層係也可以採用 Ge組成比X成爲0,05以上及0.3以下之手段。 可以在本發明中，具有直接或透過其他SiGe層而配 置在前述半導體基板之前述第二SiGe層上之歪斜Si層。 本發明之場效型電晶體之製造方法，係藉由在SiGe 層上之進行磊晶成長之歪斜Si層而形成通道區域之場效 型電晶體之製造方法，在藉由前述半導體基板之製造方法 所製作之半導體基板之前述歪斜Si層上，形成前述通道 區域，以便於解決前述課題。 本發明之場效型電晶體，係藉由在SiGe層上之進行 磊晶成長之歪斜S i層而形成通道區域之場效型電晶體， 藉由前述場效型電晶體之製造方法而進行製作，以便於解 決前述課題。 本發明之半導體基板之製造方法，係藉由具有第一層 形成作業、第二層形成作業、熱處理作業和硏磨作業，而 設定第一 SiGe層之膜厚更加薄於成爲藉由膜厚之增加來 產生錯位而產生晶格鬆驰之膜厚之臨界膜厚之2倍，使得 第二SiGe層之Ge組成比至少在和第一 SiGe層或前述Si 間之接觸面而更加低於第一 SiGe層之Ge組成比之層中最 大値，並且，第二SiGe層具有至少一部分之Ge組成比朝 向表面而逐漸地增加的傾斜組成區域，因此，能夠在Si 基板和第一 SiGe層間之界面以及第一 SiGe層和第二 -13- (9) (9)1222106A method for buffer layer of Ge (germanium) composition ratio, and a method of changing the buffer layer of Ge composition ratio with a certain inclination by using Si (silicon) cut wafer. The literature is listed below. Patent Document 1: U.S. Patent No. 6,107,6,5 3 Patent Document 2: U.S. Patent No. 5,442,205, Patent Document 3: U.S. Patent No. 5,22,1,4,13 Patent Specification Document 4: International Publication No. 98/00857 Brief Booklet Patent Document 5: Japanese Patent Application Laid-Open No. 6-2 5 2 046 However, in the conventional technique described above, the following problems remain. That is, the SiGe layer formed using the conventional techniques described above is in a state where penetration dislocation density or surface roughness cannot reach the level required as a component and manufacturing process. For example, in the case of using a buffer layer having a tilted Ge composition ratio, the penetration dislocation density can be made relatively low, but the surface roughness may be deteriorated accidentally. On the contrary, the Ge composition ratio is made into a step when used. In the state of the state of the buffer layer, the surface can be roughened and become relatively small, but accidental increase of the through-dislocation density may occur. In addition, in a state where a cut wafer is used, the misalignment is not in the film-forming direction but is easily separated from the lateral direction. However, sufficient misalignment cannot be achieved. Even if the surface is rough, it cannot reach the level required for photolithography processes such as LSI (Large-Scale Integrated Circuit) in recent years. [Summary of the Invention] (3) (3) 1222106 [Disclosure of the Invention] The present invention has been made in view of the foregoing problems; its purpose is to provide ~ species that can reduce the penetration dislocation density and surface roughness to a practical level Semiconductor substrate, field-effect transistor, and manufacturing method thereof. The manufacturing method of the semiconductor substrate of the present invention is a method for manufacturing a semiconductor substrate by epitaxial growth of a SiGe layer on a Si substrate. A first layer forming operation for epitaxial growth of the first SiGe layer on the Si substrate, a second layer of epitaxial growth for the second SiGe layer on the first SiGe layer directly or through the epitaxial growth of the Si layer A layer forming operation, a heat treatment operation in which a heat treatment is performed at a temperature exceeding the epitaxial growth temperature during or after the formation of the SiGe layer by epitaxial growth, and removal by honing after the formation of the SiGe layer The honing operation of the surface unevenness caused by the foregoing heat treatment; in addition, the foregoing first layer forming operation is to set the film thickness of the first SiGe layer to be thinner than In order to generate a dislocation and increase the critical film thickness of the film with a lattice relaxation by increasing the film thickness, the second layer forming operation is performed so that the Ge composition ratio of the second SiGe layer is at least equal to that of the first The SiGe layer or the contact surface between the Si and the Si composition layer is lower than the largest Ge composition ratio in the first SiGe layer, and at least a part of the Ge composition ratio gradually increases toward the surface, so as to solve the aforementioned problem. Preferably, in the present invention, the first layer forming operation is performed such that the Ge composition ratio X of the first SiGe layer becomes constant, so that the first SiGe layer becomes a relation satisfying the following relationship: -8- (4) (4) 1222106 tc (nm) = (1.9x 1 0.3 / 5 (χ) 2) In (tc / 0.4) e (x) = (a〇 + 0.2003 26x + 〇.026 1 74x2 / a〇) a〇 The critical film thickness t of 0.543 nm (lattice constant of aG-based Si). 2 times less than full thickness. In addition, in the present invention, it is preferable that the second SiGe layer is directly disposed on the first SiGe layer, and that the Ge composition ratio of the entire layer gradually increases toward the surface and is an inclined composition layer. In the aforementioned first SiGe layer system of the present invention, a method may be adopted in which the Ge composition ratio χ becomes 0.05 or more and 0.3 or less. The present invention relates to a method for manufacturing a semiconductor substrate having a skewed Si layer through a SiGe layer on a Si substrate. The method can directly or through other SiGe layers on the second SiGe layer of a semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate. And epitaxial growth is performed for the aforementioned skewed Si layer. The method for manufacturing a semiconductor substrate of the present invention is a method for manufacturing a semiconductor substrate by epitaxial growth of a SiGe layer on a Si substrate. The method includes: a method of epitaxial growth of a first SiGe layer on the Si substrate; One layer forming operation, the second layer forming operation for epitaxial growth of the second SiGe layer on the first SiGe layer directly or through epitaxial growth of the Si layer, and the formation of the aforementioned SiGe layer by epitaxial growth The heat treatment operation of applying heat treatment at a temperature exceeding the epitaxial growth temperature on the way or after formation, and removing it by honing after the formation of the aforementioned SiGe layer.-9- (5) (5) 1222106 Honing operation of surface unevenness; In addition, the aforementioned first layer forming operation is to set the film thickness of the aforementioned first Si Ge layer to be thinner than a critical film having a film thickness that causes dislocation and lattice relaxation due to an increase in film thickness. 2 times thicker, the aforementioned second layer forming operation is repeated a plurality of times with a continuous Ge composition ratio, and the SiGe inclined composition layer that gradually increases the Ge composition ratio toward the surface is subjected to an epitaxy. The operation of crystal growth and the epitaxial growth of the SiGe-definite composition layer on the inclined composition layer by the last Ge composition ratio of the aforementioned inclined composition layer, forming the Ge composition ratio is inclined along the film-forming direction and has a step shape. The thin film of the aforementioned second SiGe layer is changed so that the Ge composition ratio under the second SiGe layer is lower than the maximum 値 in the Ge composition ratio of the first SiGe layer in order to solve the aforementioned problem. It is preferable that (in the present invention, the first layer forming operation is that the Ge composition ratio X of the first SiGe layer is constant, so that the first SiGe layer becomes the following relationship: tc (nm) = (1.9x 1 〇 * 3 / ε (χ) 2) · In (tc / 0.4) £ (x) two (a〇 + 0.2003 26x + 0.026 1 74x2 / a〇) a〇 = 0.5 43 nm (a〇 is the lattice constant of Si The critical film thickness t. Is less than 2 times the thickness. In addition, in the present invention, the aforementioned first SiGe layer system may also adopt a method in which the Ge composition ratio χ is 0.05 or more and 0.3 or less. The invention is a manufacturing method of a semiconductor substrate in which a skewed Si layer is formed through a SiGe layer on a Si substrate. (6) (6) 1222106, which can be manufactured by the method for manufacturing a semiconductor substrate described in any one of the foregoing. On the aforementioned second SiGe layer of the semiconductor substrate, the epitaxial growth of the skewed Si layer is performed directly or through other SiGe layers. The semiconductor substrate of the present invention has a Si substrate and a first SiGe on the Si substrate. Layer and a second SiGe layer disposed directly or through the Si layer on the first SiGe layer, the aforementioned first The SiGe layer is thinner than the critical film thickness which is twice as critical as the film thickness caused by dislocation and lattice relaxation caused by the increase in film thickness. The second SiGe layer has a Ge composition ratio at least The first SiGe layer or the contact surface between the Sis is lower than the largest Ge in the first SiGe layer, and at least a part of the Ge composition ratio gradually increases toward the surface. The semiconductor substrate is manufactured by a method for manufacturing the semiconductor substrate in order to solve the aforementioned problems. Preferably, in the present invention, the first SiGe layer has a constant Ge composition ratio X and satisfies the following relationship: tc (nm) = (1 · 9χ10-3 / ε (χ) 2) · 1η (ΐ <; / 0.4) £ (χ) = (a〇 + 0.200326χ + 0 · 026174χ2 / a〇) a〇 = 0.543nm (aG Si lattice (Constant) critical film thickness t. 2 times less than the full thickness. In addition, in the present invention, the aforementioned first SiGe layer system may also adopt a method in which the Ge composition ratio χ becomes 0.05 or more and 0.3 or less. -11 -(7) (7) 1222106 The aforementioned second SiGe layer system of the present invention can be directly arranged in front The first SiGe layer is an inclined composition layer in which the Ge composition ratio of the entire layer gradually increases toward the surface. Preferably, in the present invention, the second SiGe layer is provided with the second second semiconductor substrate directly or through another SiGe layer. Skewed Si layer on SiGe layer. The semiconductor substrate of the present invention has a Si substrate, a first SiGe layer on the Si substrate, and a second SiGe layer disposed on the first SiGe layer directly or through the Si layer. The aforementioned first SiGe layer is thinner than the critical film thickness which is twice as critical as the film thickness caused by dislocation and lattice relaxation caused by the increase of the film thickness. The aforementioned second SiGe layer is alternately and continuously The Ge composition ratio constitutes a SiGe inclined composition layer facing the surface so that the Ge composition ratio gradually increases, and a SiGe-constant composition layer arranged on the inclined composition layer based on the Ge composition ratio above the inclined composition layer, becomes In the multilayered state, the Ge composition ratio below the second SiGe layer is configured to be lower than the largest in the Ge composition ratio of the first SiGe layer, and is advanced by the method for manufacturing the semiconductor substrate. Production in order to solve the aforementioned problems. Preferably, in the present invention, the first SiGe layer has a constant Ge composition ratio X and satisfies the following relationship: tc (nm) = (1.99xIO-3 / ε (χ) 2) · In ( tc / 0.4) ε (χ) ~ (a〇 + 0.200326χ + 0.026174x2 / a〇) a〇 = 0.55 43 nm (a〇 is the lattice constant of Si) -12- (8) (8) 1222106 of Critical film thickness t. 2 times less than full thickness. Further, in the present invention, the first SiGe layer system may adopt a method in which the Ge composition ratio X is equal to or greater than 0,05 and equal to or less than 0.3. In the present invention, there may be a skewed Si layer disposed on the second SiGe layer of the semiconductor substrate directly or through another SiGe layer. The method for manufacturing a field-effect transistor of the present invention is a method for manufacturing a field-effect transistor in which a channel region is formed by using a skewed Si layer for epitaxial growth on a SiGe layer. The aforementioned channel region is formed on the aforementioned skewed Si layer of the semiconductor substrate manufactured by the method, so as to solve the aforementioned problem. The field-effect transistor of the present invention is a field-effect transistor in which a channel region is formed by a skewed Si layer that is epitaxially grown on a SiGe layer, and is performed by the aforementioned method for manufacturing a field-effect transistor. Made in order to solve the aforementioned problems. The method for manufacturing a semiconductor substrate of the present invention is to set the film thickness of the first SiGe layer to be thinner than the film thickness by using a first layer forming operation, a second layer forming operation, a heat treatment operation, and a honing operation. Increasing the critical film thickness by 2 times to produce a dislocation and produce a lattice relaxation film thickness, so that the Ge composition ratio of the second SiGe layer is at least lower than that of the first SiGe layer or the aforementioned Si The Ge composition ratio of the SiGe layer is the largest, and the second SiGe layer has an inclined composition region where at least a part of the Ge composition ratio gradually increases toward the surface. Therefore, the interface between the Si substrate and the first SiGe layer and First SiGe layer and second -13- (9) (9) 1222106

SiGe層間之界面附近，有效率地集中錯位，可以減低第 二SiGe層表面之貫通錯位密度及表面粗糙，此外，在藉 由磊晶成長而形成SiGe層之途中或形成後，於超過該磊 晶成長溫度之溫度，施加熱處理，在SiGe層形成後，藉 由硏磨而除去在熱處理所產生之表面凹凸，因此，在基板 ，配合事前熱履歷而預先產生由於晶格鬆弛或錯位之運動 所造成之表面粗糙之惡化，對於由於表面粗糙之惡化所產 生之凹凸，進行硏磨除去，而使得表面成爲平坦化。因此 ，即使是在該基板，藉由元件製造作業等而施加熱處理， 也能夠防止表面或界面之粗糙惡化再一次地發生。 前述熱處理作業及硏磨作業係可以在第一層形成作業 和第二層形成作業之其中某一個作業途中或形成後而進行 〇 在此，由於第一 SiGe層係形成爲更加薄於臨界膜厚 之2倍之薄膜，因此，在第一 SiGe層之成膜中，配合膜 厚而使得歪斜能量變大，但是，幾乎無生成錯位。接著， 在開始第二SiGe層之磊晶成長時，已經在第一 SiGe層， 積存歪斜能量，因此，在第二SiGe層之膜厚變薄之階段 ，錯位之生成和成長係由第一 SiGe層兩側之界面及第二 SiGe層內之第一 SiGe層側開始進行，第一 SiGe層及第 二SiGe層之晶格鬆弛係開始進行。此時，第二SiGe層之 Ge組成比’係在和第一 SiGe層或前述Si層間之接觸面 ，更加低於第一 SiGe層之Ge組成比之層中最大値，因此 ’錯位係沿著第一 SiGe層兩側之界面而進行集中及生成 -14- (10)1222106 ，第一 SiGe層兩側之界面之錯位生成 SiGe層之晶格鬆弛，抑制在第二SiGe層 或成長，同時，也抑制第二SiGe層表面 化。 此外，在第二SiGe層之傾斜組成區 地生成錯位、發生錯位間之相互纒繞、減 中之錯位密度、同時、藉由沿著橫方向而 、以便於減少表面區域之貫通錯位密度、 之惡化之效果。 在習知之並無第一 SiGe層之狀態下 ，於傾斜組成區域之膜厚成爲既定之膜厚 膜厚時，開始進行錯位之生成，一旦在經 加後，還在形成傾斜組成區域之狀態下， 也就是說，在習知構造中，僅在傾斜組成 分區域，得到前述效果。 另一方面，在具有第一 SiGe層之本 經在第一 SiGe層，積存歪斜能量，因此， 之膜厚變薄之階段，錯位之生成係在第二 進行，所以，在第二SiGe層內之傾斜組 到前述效果，減少第二SiGe層之表面區 度，也抑制表面粗糙之惡化。 此外，第一 SiGe層係發揮作爲除去月 之水分或氧成分或者碳成分之不純物之層 制起因於S i基板表面污染所造成之缺陷之 ，係有助於第二 •內之錯位之生成 之表面粗糙之惡 域，也具有均等 少傾斜組成區域 導引錯位之成長 也抑制表面粗糙 之傾斜組成區域 以上而超過臨界 過錯位密度之增 得到前述效果。 區域上側之一部 發明構造中，已 在第二SiGe層 SiGe層內開始 成區域整體，得 域之貫通錯位密 干謂Si基板表面 之功能，具有抑 :效果。 -15- (11) (11)1222106 此外’在第一 SiGe層之成膜中而開始生成錯位時， 錯位係沿著多方向而開始成長，因此，不容易抑制錯位成 長之方向’不容易減低貫通錯位或表面粗糙。因此，第一 Si Ge層之膜厚係必須在不超過臨界膜厚2倍之範圍內， 設定膜厚更加薄於實際錯位之生成或晶格鬆弛顯著地開始 進行之膜厚。同時，第一 SiGe層之膜厚係膜厚越成爲接 近實際錯位之生成或晶格鬆弛顯著地開始進行之膜厚，則 效果越好。實際錯位之生成或晶格鬆弛顯著地開始進行之 膜厚係隨著成膜之溫度條件而不同。因此，可以在各個成 膜條件，於不超過臨界膜厚2倍之範圍內，在實際錯位之 生成或晶格鬆弛顯著地開始進行之膜厚附近，選擇有效地 得到本發明效果之膜厚。 此外，在本發明之半導體基板及半導體基板之製造方 法，正如前面敘述，第一 SiGe層之Ge組成比係成爲一定 ，因此，在相同之Ge組成比，實際錯位之生成或晶格鬆 弛顯著地開始進行之膜厚係變得最薄，在最薄之膜厚，得 到本發明之效果，具有所謂成膜所需時間短之優點。此外 ，在這些半導體基板及半導體基板之製造方法，可以藉由 使得第一 SiGe層，成爲滿足前述關係式之臨界膜厚（係 指不論成膜溫度而僅由Ge組成比和格子常數所算出之產 生錯位及產生晶格鬆弛之膜厚）te之2倍未滿之厚度，以 便於容易設定第一 SiGe層之膜厚，成爲在實際錯位之生 成或晶格鬆弛顯著地開始進行之膜厚內。 也就是說，藉由成膜溫度而改變前述實際錯位之生成 -16- (12) (12)1222106 或晶格鬆弛顯著地開始進行之膜厚，因此，如果成爲僅由 Ge組成比X和格子常數而理論上所求出之理想之臨界膜 厚te之2倍未滿的話，則可以變得更加薄於實際錯位之 生成或晶格鬆弛顯著地開始進行之膜厚，得到本發明之效 果。此外，前述臨界膜厚係以在平衡狀態而進行成膜，來 作爲前提，因此，不論成膜溫度，而僅由Ge組成比和格 子常數來決定，但是，實際錯位之生成或晶格鬆弛顯著地 開始進行之膜厚，係不僅是在平衡狀態，也包含在低溫成 長等之非平衡狀態而進行成膜之狀態，配合成膜溫度而進 行決定。 此外’正如前面敘述，在本發明之半導體基板及半導 體基板之製造方法，前述第一 Si Ge層之Ge組成比X係成 爲〇.〇5以上及〇.3以下，因此，實際錯位之生成或晶格 鬆弛顯著地開始進行之膜厚係不會變得過薄或過厚，在適 當厚度之第一 SiGe層，有效地得到本發明之效果。 也就是說，在第一 SiGe層之Ge組成比X小於0.05 之狀態下，實際錯位之生成或晶格鬆弛顯著地開始進行之 膜厚係變得過厚，因此，第一 SiGe層之成膜所需要之時 間變長，並且，使得第一 SiGe層之表面粗糙惡化。 另一方面，在第一 SiGe層之Ge組成比X大於0.3之 狀態下，以非常薄之膜厚而使得實際錯位之生成或晶格鬆 弛顯著地開始進行，因此，不容易控制性良好地形成第一 S i Ge 層。 此外，如果前述第一 SiGe層之Ge組成比X成爲 •17- (13) (13)1222106 0.0 5以上及0 · 3以下的話，則實際錯位之生成或晶格鬆弛 顯著地開始進行之膜厚係成爲適當厚度，沿著第一 SiGe 層兩側之界面而集中及生成錯位，第一 SiGe層兩側界面 之錯位生成，係有效地得到有助於第二Si Ge層之晶格鬆 弛之效果。 在這些半導體基板及半導體基板之製造方法，前述第 二SiGe層係直接配置在前述第一 SiGe層上，並且，成爲 層整體之Ge組成比朝向表面而逐漸增加的傾斜組成層， 因此，具有所謂在不浪費之狀態下而配置用以得到本發明 效果之必要層、以最薄之膜厚而得到本發明之效果、以及 成膜所需要之時間短之優點。 在本發明之半導體基板及半導體基板之製造方法，設 定第一 SiGe層之膜厚更加薄於成爲藉由膜厚之增加來產 生錯位而產生晶格鬆驰之膜厚之臨界膜厚之2倍，使得第 二SiGe層下面之Ge組成比，更加低於第一 SiGe層之Ge 組成比之層中最大値，因此，能夠在Si基板和第一 SiGe 層間之界面以及第一 SiGe層和第二SiGe層間之界面附近 ，有效率地集中錯位，可以減低第二SiGe層表面之貫通 錯位密度及表面粗糙，此外，在藉由磊晶成長而形成 SiGe層之途中或形成後，於超過磊晶成長溫度之溫度， 施加熱處理，在SiGe層形成後，藉由硏磨而除去在熱處 理所產生之表面凹凸，因此，在基板，配合事前熱履歷而 預先產生由於晶格鬆弛或錯位之運動所造成之表面粗糙之 惡化，對於由於表面粗糙之惡化所產生之凹凸，進行硏磨 -18- (14) (14)1222106 除去，而使得表面成爲平坦化。因此，即使是在該基板， 藉由元件製造作業等而施加熱處理，也能夠防止表面或界 面之粗糙惡化再一次地發生。 在此，由於第一 SiGe層係形成爲更加薄於臨界膜厚 之2倍之薄膜，因此，在第一 Si Ge層之成膜中，配合膜 厚而使得歪斜能量變大，但是，幾乎無生成錯位。接著， 在開始％ 一 SiGe層之嘉晶成長時，已經在第一* SiGe層， 積存歪斜能量，因此，在第二SiGe層之膜厚變薄之階段 ，錯位之生成和成長係由第一 SiGe層兩側之界面及第二 SiGe層內之第一 SiGe層側開始進行，第一 SiGe層及第 二SiGe層之晶格鬆弛係開始進行。此時，第二SiGe層之 Ge組成比，係在和第一 SiGe層或前述Si層間之接觸面 ，更加低於第一 SiGe層之Ge組成比之層中最大値，因此 ，錯位係沿著第一 SiGe層兩側之界面而進行集中及生成 ’第一 SiGe層兩側之界面之錯位生成，係有助於第二 SiGe層之晶格鬆弛，抑制在第二SiGe層內之錯位之生成 或成長，同時，也抑制第二SiGe層表面之表面粗糙之惡 化。 此外’第一 SiGe層係發揮作爲除去所謂Si基板表面 之水分或氧成分或者碳成分之不純物之層之功能，具有抑 制起因於Si基板表面污染所造成之缺陷之效果。 此外，在第一 SiGe層之成膜中而開始生成錯位時， 錯位係沿著多方向而開始成長，因此，不容易抑制錯位成 長之方向’不容易減低貫通錯位或表面粗糙。因此，第一 -19- (15) (15)1222106 S i G e層之膜厚係必須在不超過臨界膜厚2倍之範圍內， 設定膜厚更加薄於實際錯位之生成或晶格鬆弛顯著地開始 進行之膜厚。同時，第一 SiGe層之膜厚係膜厚越成爲接 近實際錯位之生成或晶格鬆弛顯著地開始進行之膜厚，則 效果越好。實際錯位之生成或晶格鬆弛顯著地開始進行之 膜厚係隨著成膜之溫度條件而不同。因此，可以在各個成 膜條件，於不超過臨界膜厚2倍之範圍內，在實際錯位之 生成或晶格鬆驰顯著地開始進行之膜厚附近，選擇有效地 得到本發明效果之膜厚。 此外，交互地且以連續之Ge組成比，使得朝向表面 而Ge組成比逐漸地增加之SiGe傾斜組成層和以該傾斜組 成層上面之Ge組成比而配置在傾斜組成層上之s i Ge —定 組成層，成爲複數層層積狀態，作爲第二SiGe層，因此 ’作爲第二SiGe層整體，係成爲Ge組成比之傾斜階梯狀 之層，容易在界面，使得錯位沿著橫方向移動，不容易產 生貫通錯位，同時，在界面之組成變化小，因此，可以抑 制在界面之錯位產生，在傾斜組成層之層內，均等地產生 錯位，抑制表面粗糙之惡化。 本發明人們係就SiGe之成膜技術而進行硏究，結果 ’得知結晶中之錯位具有以下傾向。 也就是說，在形成SiGe層之薄膜時，在成膜中所產 生之錯位，係具有容易運動在相對於成膜方向之傾斜方向 或橫方向（垂直於成膜方向之方向·· <110>方向）之其 中某一個之特性。此外，錯位係在層之界面，容易運動在 -20- (16) (16)1222106 橫方向上，但是，認爲在組成急劇地發生變化之界面，容 易運動在前述傾斜方向上，同時，許多錯位係高密度地產 生。 因此’認爲在Ge組成比成爲單純之階梯狀而進行成 膜時，則在成爲急劇之組成變化之界面部分，呈高密度地 產生許多錯位’同時，錯位容易運動在成膜方向之傾斜方 向上，恐怕成爲貫通錯位之可能性高。此外，認爲在Ge 組成比呈單純緩慢地進行傾斜而進行成膜時，則並無成爲 運動於前述傾斜方向之錯位散逸至橫方向之機會之部分（ 界面等）產生，貫通至表面爲止。 相對於這些，在本發明之半導體基板之製造方法，以 連續之Ge組成比而重複地進行複數次之對於朝向表面而 逐漸地增加Ge組成比之SiGe傾斜組成層來進行磊晶成長 之作業以及藉由前述傾斜組成層之最後Ge組成比而在傾 斜組成層上來對於SiGe —定組成層進行磊晶成長之作業 ，形成Ge組成比沿著成膜方向具有傾斜而呈階梯狀地進 行變化之前述第二SiGe層之薄膜，因此，可以交互地形 成複數段之傾斜組成層和一定組成層而成爲Ge組成比之 傾斜階梯狀之層，形成錯位密度小且表面粗糙小之 SiGe 層。 也就是說，在界面，錯位容易運動在橫方向上，不容 易產生貫通錯位。此外，在界面之組成變化小，因此，可 以抑制在界面之錯位產生，在傾斜組成層之層內，均等地 產生錯位，抑制表面粗糙之惡化。 -21 - (17) (17)1222106 此外，在第二SiGe層之傾斜組成區域，也具有均等 地生成錯位、發生錯位間之相互纏繞、減少傾斜組成區域 中之錯位密度、同時、藉由沿著橫方向而導引錯位之成長 、以便於減少表面區域之貫通錯位密度、也抑制表面粗糙 之惡化之效果。 在習知之並無第一 SiGe層之狀態下之傾斜組成區域 ，於傾斜組成區域之膜厚成爲既定之膜厚以上而超過臨界 膜厚時，開始進行錯位之生成，一旦在經過錯位密度之增 加後，還在形成傾斜組成區域之狀態下，得到前述效果。 也就是說，在習知構造中，僅在傾斜組成區域上側之一部 分區域，得到前述效果。 另一方面，在具有第一 SiGe層之本發明構造中，已 經在第一 SiGe層，積存歪斜能量，因此，在第二SiGe層 之膜厚變薄之階段，錯位之生成係在第二SiGe層內開始 進行，所以，在第二SiGe層內之傾斜組成區域整體，得 到前述效果，減少第二SiGe層之表面區域之貫通錯位密 度，也抑制表面粗糙之惡化。 在這些半導體基板及半導體基板之製造方法，於前述 SiGe層上，直接或透過其他SiGe層，而對於歪斜Si層 ，進行磊晶成長，因此，得到缺陷少且表面粗糙小之良質 之歪斜Si層，並且，在硏磨作業後，在SiGe層上，直接 或透過其他SiGe層，而使得歪斜Si層’進行磊晶成長， 所以，可以在表面狀態良好之SiGe層上’形成Si層之薄 膜，具有良質之歪斜Si層，結果，適合作爲例如使用以 -22- (18) (18)1222106 歪斜Si層成爲通道區域之MOSFET等之積體電路用之半 導體基板及其製造方法。 在這些場效型電晶體及場效型電晶體之製造方法，於 藉由前述本發明之半導體基板或前述本發明之半導體基板 之製造方法所製作之半導體基板之前述歪斜Si層，具有 通道區域’因此，即使是在元件製造時，施加熱處理，也 能夠在表面狀態良好之SiGe層上，得到良質之歪斜Si層 ’以高良品率而得到高性能之場效型電晶體。 【實施方式】 [發明之最佳實施形態】 以下，根據圖式而說明本發明之第一實施形態。 第一圖係顯示具有本發明之歪斜Si層之半導體晶圓 (體基板）W之剖面構造；在一起對照說明該半導體 晶圓 W之構造和其製造製程時，首先，正如第一圖及第 二圖所示，在Si基板1上，藉由減壓CVD法，而對於成 爲Ge組成比X由〇開始至0.3爲止而在成膜方向（朝向 $胃）具有傾斜且逐漸增加之傾斜組成層之第一 SiGe層 2 ’進行磊晶成長。此外，藉由前述減壓CVD法所造成之 成膜’係使用H2作爲載體氣體，使用SiH4及GeH4作爲 來源氣體。 接著，在第一 SiGe層2上，對於以該第一 SiGe層2 之最後Ge組成比（〇. 3 )而成爲一定組成層及緩和層之第 一 SiGe層3，進行磊晶成長。這些第一 SiGe層2及第二 -23- (19) (19)1222106Near the interface between the SiGe layers, efficient dislocations can reduce the through dislocation density and surface roughness of the surface of the second SiGe layer. In addition, during or after the formation of the SiGe layer through epitaxial growth, the epitaxial layer is exceeded. At the temperature of the growth temperature, heat treatment is applied. After the SiGe layer is formed, the surface unevenness caused by the heat treatment is removed by honing. Therefore, the substrate is pre-generated due to lattice relaxation or dislocation movement in accordance with the previous thermal history. The surface roughness is deteriorated, and the unevenness caused by the deterioration of the surface roughness is removed by honing to make the surface flat. Therefore, even if the substrate is subjected to a heat treatment by an element manufacturing operation or the like, it is possible to prevent the surface or interface from being deteriorated again and again. The aforementioned heat treatment operation and honing operation may be performed during or after the formation of one of the first layer forming operation and the second layer forming operation. Here, the first SiGe layer system is formed to be thinner than the critical film thickness. It is twice as thin as the film. Therefore, in the film formation of the first SiGe layer, the skew energy is increased in accordance with the film thickness, but almost no dislocation is generated. Then, when the epitaxial growth of the second SiGe layer is started, the distortion energy is already accumulated in the first SiGe layer. Therefore, at the stage where the film thickness of the second SiGe layer is thinned, the generation and growth of the dislocation is caused by the first SiGe layer. The interface on both sides of the layer and the first SiGe layer side in the second SiGe layer begin, and the lattice relaxation system of the first SiGe layer and the second SiGe layer begins. At this time, the Ge composition ratio of the second SiGe layer is at the contact surface with the first SiGe layer or the aforementioned Si layer, which is even lower than that of the first SiGe layer. Therefore, the 'dislocation system is along the The interface on both sides of the first SiGe layer is concentrated and generated -14- (10) 1222106, and the dislocation of the interface on both sides of the first SiGe layer generates the lattice relaxation of the SiGe layer, which inhibits or grows in the second SiGe layer. Surface formation of the second SiGe layer is also suppressed. In addition, dislocations are generated in the tilted composition region of the second SiGe layer, mutual entanglement between dislocations occurs, and the dislocation density is reduced, and at the same time, by reducing the dislocation density in the surface area along the horizontal direction, Deterioration effect. In the state where the first SiGe layer is not known, when the film thickness of the inclined composition region becomes the predetermined film thickness and film thickness, the generation of the misalignment is started. Once added, the inclined composition region is still formed. That is, in the conventional structure, the aforementioned effects are obtained only in the sub-area of the oblique composition. On the other hand, since the distortion energy is accumulated in the first SiGe layer with the first SiGe layer, the generation of dislocation is performed in the second stage when the film thickness becomes thin. Therefore, in the second SiGe layer, The oblique set to the aforementioned effect reduces the surface area of the second SiGe layer and also suppresses the deterioration of the surface roughness. In addition, the first SiGe layer functions as a layer that removes impurities such as moisture, oxygen, or carbon from the moon. Defects caused by the surface contamination of the Si substrate contribute to the generation of misalignment within the second substrate. The evil domain of surface roughness also has the growth of evenly-inclined composition regions to guide the growth of dislocations, and also suppresses the increase of the surface roughness of the inclined composition regions above the critical over-dislocation density to obtain the aforementioned effects. The upper part of the area In the invention structure, the entire area of the SiGe layer has begun to form a whole area in the second SiGe layer, and the function of the through-dislocation of the area is closely related to the function of the surface of the Si substrate. -15- (11) (11) 1222106 In addition, when the dislocation starts to form in the formation of the first SiGe layer, the dislocation starts to grow in multiple directions, so it is not easy to suppress the direction of dislocation growth. It is not easy to reduce Dislocation through or rough surface. Therefore, the film thickness of the first Si Ge layer must be within a range not exceeding twice the critical film thickness, and the film thickness must be set to be thinner than the actual dislocation generation or lattice relaxation to start significantly. At the same time, the more the film thickness of the first SiGe layer is, the more the film thickness becomes closer to the actual dislocation generation or the lattice relaxation starts significantly, the better the effect. The generation of the actual dislocation or the start of the lattice relaxation significantly changes the film thickness depending on the temperature conditions of the film formation. Therefore, it is possible to select a film thickness at which the effects of the present invention can be effectively obtained in the vicinity of the film thickness at which the actual generation of dislocations or the start of lattice relaxation occurs within the range of not more than twice the critical film thickness under each film formation condition. In addition, in the manufacturing method of the semiconductor substrate and the semiconductor substrate of the present invention, as described above, the Ge composition ratio of the first SiGe layer becomes constant. Therefore, at the same Ge composition ratio, the generation of actual misalignment or lattice relaxation is significantly The film thickness at the beginning is the thinnest. At the thinnest film thickness, the effect of the present invention is obtained. This has the advantage that the time required for film formation is short. In addition, in these semiconductor substrates and semiconductor substrate manufacturing methods, the first SiGe layer can be made to have a critical film thickness that satisfies the aforementioned relationship (referred to as being calculated from the Ge composition ratio and the lattice constant regardless of the film formation temperature). Film thickness causing dislocations and lattice relaxation) 2 times less than te, in order to easily set the film thickness of the first SiGe layer, and become within the film thickness where the actual generation of dislocations or lattice relaxation begins significantly . In other words, the formation of the aforementioned actual dislocation is changed by the film-forming temperature -16- (12) (12) 1222106 or the film thickness at which lattice relaxation starts significantly. Therefore, if it is only composed of Ge composition ratio X and lattice If the theoretical critical film thickness te which is constant and less than 2 times is theoretically full, the film thickness can be made thinner than the film thickness at which the actual generation of dislocations or lattice relaxation begins significantly, and the effect of the present invention can be obtained. In addition, the aforementioned critical film thickness is based on the premise that the film is formed in an equilibrium state. Therefore, regardless of the film formation temperature, it is determined only by the Ge composition ratio and the lattice constant. However, the generation of actual dislocation or the lattice relaxation is significant The film thickness at the start of the film formation is determined not only in the equilibrium state but also in the non-equilibrium state such as low-temperature growth, and the film formation temperature is determined. In addition, as described above, in the semiconductor substrate and the manufacturing method of the semiconductor substrate of the present invention, the Ge composition ratio X of the first Si Ge layer is greater than or equal to 0.05 and less than or equal to 0.3. Therefore, the actual displacement or The film thickness at which the lattice relaxation starts significantly does not become too thin or too thick, and the effect of the present invention is effectively obtained in the first SiGe layer of an appropriate thickness. That is to say, in a state where the Ge composition ratio X of the first SiGe layer is less than 0.05, the film thickness of the actual generation of dislocation or the start of lattice relaxation significantly becomes too thick. Therefore, the film formation of the first SiGe layer The required time becomes longer and the surface roughness of the first SiGe layer is deteriorated. On the other hand, in a state where the Ge composition ratio X of the first SiGe layer is greater than 0.3, the generation of the actual dislocation or the relaxation of the lattice is significantly started with a very thin film thickness, and therefore, it is not easy to form with good controllability. The first Si Ge layer. In addition, if the Ge composition ratio X of the first SiGe layer is • 17- (13) (13) 1222106 0.0 5 or more and 0 · 3 or less, the film thickness at which the generation of actual misalignment or the relaxation of the crystal lattice begins to proceed markedly It is a proper thickness, and dislocations are concentrated and generated along the interface on both sides of the first SiGe layer. The generation of dislocations on the interface on both sides of the first SiGe layer is effective to obtain the effect of helping the lattice relaxation of the second SiGe layer. . In these semiconductor substrates and manufacturing methods of the semiconductor substrate, the second SiGe layer is directly disposed on the first SiGe layer, and it has an inclined composition layer in which the Ge composition ratio of the entire layer gradually increases toward the surface. The necessary layers for obtaining the effect of the present invention are arranged without waste, the effect of the present invention is obtained with the thinnest film thickness, and the time required for film formation is short. In the semiconductor substrate and the manufacturing method of the semiconductor substrate of the present invention, the film thickness of the first SiGe layer is set to be thinner than a critical film thickness that is a film thickness that causes dislocation due to an increase in film thickness and a lattice relaxation. So that the Ge composition ratio under the second SiGe layer is even lower than the largest in the Ge composition ratio of the first SiGe layer. Therefore, the interface between the Si substrate and the first SiGe layer and the first SiGe layer and the second Near the interface between SiGe layers, efficient dislocations can reduce the through dislocation density and surface roughness of the surface of the second SiGe layer. In addition, during or after the formation of the SiGe layer by epitaxial growth, it exceeds the epitaxial growth. After the SiGe layer is formed, the surface unevenness caused by the heat treatment is removed by honing after the formation of the SiGe layer. Therefore, the substrate may be caused in advance by lattice relaxation or dislocation movement in accordance with the previous thermal history. Deterioration of the surface roughness is performed by honing-18- (14) (14) 1222106 to remove the unevenness caused by the deterioration of the surface roughness to make the surface flat. Therefore, even if heat treatment is applied to the substrate by a component manufacturing operation or the like, it is possible to prevent the surface or the interface from being deteriorated from being deteriorated again. Here, the first SiGe layer is formed as a thinner film that is twice thinner than the critical film thickness. Therefore, in the film formation of the first SiGe layer, the thickness of the film is adjusted to increase the skew energy. However, almost no Generate misalignment. Then, at the beginning of the growth of the Jiajing of the% SiGe layer, the distortion energy has been accumulated in the first * SiGe layer. Therefore, at the stage where the film thickness of the second SiGe layer becomes thinner, the generation and growth of the dislocation is performed by the first The interface on both sides of the SiGe layer and the first SiGe layer side in the second SiGe layer begin to proceed, and the lattice relaxation system of the first SiGe layer and the second SiGe layer begins. At this time, the Ge composition ratio of the second SiGe layer is at the contact surface with the first SiGe layer or the aforementioned Si layer, which is even lower than that of the Ge composition ratio of the first SiGe layer. Therefore, the dislocation is along the Concentration and generation of interfaces on both sides of the first SiGe layer to generate dislocations at the interfaces on both sides of the first SiGe layer help to relax the lattice of the second SiGe layer and suppress the generation of dislocations in the second SiGe layer Or growth, at the same time, the deterioration of the surface roughness of the surface of the second SiGe layer is also suppressed. In addition, the first SiGe layer functions as a layer for removing impurities such as moisture or oxygen components or carbon components on the surface of the Si substrate, and has an effect of suppressing defects caused by the surface contamination of the Si substrate. In addition, when dislocations are started to form during the formation of the first SiGe layer, the dislocations start to grow in multiple directions. Therefore, it is not easy to suppress the direction in which dislocations grow, and it is not easy to reduce through-dislocations or surface roughness. Therefore, the film thickness of the first -19- (15) (15) 1222106 S i Ge layer must be within 2 times the critical film thickness, and the film thickness must be set to be thinner than the actual dislocation generation or lattice relaxation. The film thickness started significantly. At the same time, the more the film thickness of the first SiGe layer is, the more the film thickness becomes closer to the actual dislocation generation or the lattice relaxation starts significantly, the better the effect. The generation of the actual dislocation or the start of the lattice relaxation significantly changes the film thickness depending on the temperature conditions of the film formation. Therefore, it is possible to select a film thickness that effectively obtains the effect of the present invention under each film formation condition within a range not exceeding 2 times the critical film thickness, in the vicinity of the film thickness at which the actual generation of the dislocation or the lattice relaxation begins significantly. . In addition, the SiGe inclined composition layer alternately and continuously with the Ge composition ratio such that the Ge composition ratio gradually increases toward the surface and the si Ge arranged on the inclined composition layer with the Ge composition ratio above the inclined composition layer are determined. The composition layer is in a multilayered state, as the second SiGe layer, so 'as the second SiGe layer as a whole, it is an inclined stepped layer with a Ge composition ratio, and it is easy to cause the dislocation to move in the horizontal direction at the interface. Dislocation is easy to occur, and at the same time, the composition change at the interface is small. Therefore, it is possible to suppress the occurrence of dislocation at the interface, and uniformly generate dislocation in the layer of the inclined composition layer to suppress the deterioration of the surface roughness. The present inventors have studied the film formation technology of SiGe, and as a result, it has been found that the dislocation in the crystal has the following tendency. In other words, when forming a thin film of the SiGe layer, the dislocation generated during the film formation has a tendency to move in an oblique direction or a lateral direction (a direction perpendicular to the film formation direction) with respect to the film formation direction. ≪ 110 > Direction) one of the characteristics. In addition, the dislocation is at the interface of the layer, and it is easy to move in the horizontal direction of -20- (16) (16) 1222106. However, it is considered that at the interface where the composition changes sharply, it is easy to move in the aforementioned oblique direction. At the same time, many Dislocations occur at high density. Therefore, "When the Ge composition ratio is formed into a simple step-like film, it is considered that a large number of dislocations are generated at a high density at the interface portion where the composition changes sharply." At the same time, the dislocations easily move in the oblique direction of the film formation direction There is a high possibility that it may become a through dislocation. In addition, it is considered that when the Ge composition ratio is simply slowly inclined to form a film, no portion (interface, etc.) that has a chance of moving in the above-mentioned oblique direction and dissipates to the horizontal direction is generated and penetrates to the surface. In contrast, in the method for manufacturing a semiconductor substrate of the present invention, the operation of epitaxial growth is performed repeatedly with a continuous Ge composition ratio a plurality of times, and for the SiGe inclined composition layer that gradually increases the Ge composition ratio toward the surface, and The epitaxial growth of the SiGe-definite composition layer is performed on the inclined composition layer by the last Ge composition ratio of the aforementioned inclined composition layer to form the aforementioned Ge composition ratio which is inclined along the film-forming direction and changes stepwise. The thin film of the second SiGe layer can therefore alternately form a plurality of inclined composition layers and a certain composition layer to form an inclined stepped layer with a Ge composition ratio, forming a SiGe layer with a small dislocation density and a small surface roughness. In other words, at the interface, the dislocation is easy to move in the horizontal direction, and it is not easy to produce through-dislocation. In addition, since the composition change at the interface is small, the occurrence of misalignment at the interface can be suppressed, and the misalignment can be generated uniformly in the layer of the inclined composition layer to suppress the deterioration of the surface roughness. -21-(17) (17) 1222106 In addition, in the tilted composition region of the second SiGe layer, there are evenly generated dislocations, intertwining between dislocations, reduction of dislocation density in the tilted composition region, and simultaneously, by The effect of guiding the growth of misalignment in the horizontal direction is to reduce the density of penetration misalignment in the surface area and to suppress the deterioration of surface roughness. In the known state where the first SiGe layer does not have a tilted composition region, when the film thickness of the tilted composition region becomes greater than a predetermined film thickness and exceeds a critical film thickness, the generation of misalignment is started. Once the misalignment density increases, After that, the aforementioned effect is obtained in a state where the inclined composition region is formed. That is, in the conventional structure, the aforementioned effect is obtained only in a part of the region on the upper side of the inclined composition region. On the other hand, in the structure of the present invention having the first SiGe layer, the skew energy has been accumulated in the first SiGe layer. Therefore, at the stage where the film thickness of the second SiGe layer becomes thin, the generation of the dislocation is in the second SiGe layer. The layer starts to work. Therefore, in the entire inclined composition region in the second SiGe layer, the aforementioned effect is obtained, the penetration dislocation density in the surface region of the second SiGe layer is reduced, and the deterioration of the surface roughness is also suppressed. In these semiconductor substrates and semiconductor substrate manufacturing methods, epitaxial growth is performed on the distorted Si layer directly or through other SiGe layers on the aforementioned SiGe layer. Therefore, a good distorted Si layer with few defects and small surface roughness is obtained. Moreover, after the honing operation, the distorted Si layer is 'epitaxially grown' on the SiGe layer directly or through other SiGe layers, so a thin film of the Si layer can be formed on the SiGe layer with a good surface state. It has a good quality skewed Si layer, and as a result, it is suitable for use as a semiconductor substrate for integrated circuits using -22- (18) (18) 1222106 skewed Si layer as a channel region, and a method for manufacturing the same. The field-effect transistor and the method for manufacturing the field-effect transistor have a channel region in the skewed Si layer of the semiconductor substrate produced by the semiconductor substrate of the present invention or the semiconductor substrate manufacturing method of the present invention. 'Therefore, even when heat treatment is applied during element manufacture, a good skewed Si layer can be obtained on a SiGe layer having a good surface state' and a high-performance field-effect transistor can be obtained with a high yield. [Embodiment] [Best Embodiment of the Invention] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The first diagram is a cross-sectional structure of a semiconductor wafer (body substrate) W having a skewed Si layer according to the present invention. When the structure of the semiconductor wafer W and its manufacturing process are explained together, first, as shown in the first diagram and the first diagram, As shown in the two figures, the Si substrate 1 has a sloped composition layer that is inclined and gradually increases in the film-forming direction (toward the stomach) by a reduced-pressure CVD method for forming the Ge composition ratio X from 0 to 0.3. The first SiGe layer 2 'is epitaxially grown. In addition, the film formation 'by the aforementioned reduced pressure CVD method uses H2 as a carrier gas and SiH4 and GeH4 as a source gas. Next, on the first SiGe layer 2, epitaxial growth is performed on the first SiGe layer 3 that becomes a certain composition layer and a relaxation layer based on the final Ge composition ratio (0.3) of the first SiGe layer 2. These first SiGe layers 2 and second -23- (19) (19) 1222106

SiGe層3，係發揮作爲用以形成歪斜si層之薄膜之SiGe 緩衝層之功能。 接著’在這些第一 SiGe層2及第二SiGe層3之形成 途中或形成後，正如第三（a)圖所示，施加熱處理，而 預先在SiGe層，產生表面粗糙之惡化。該熱處理條件， 係設定在例如所謂8 0 0 °C〜1 1 0 0 °C之溫度、於超過S i Ge 層之磊晶成長溫度之溫度和所謂1分鐘〜200分鐘之熱處 理時間。此外，在本實施形態，於第二SiGe層3之成膜 途中，一旦停止來源氣體之供應，停止進行成膜，則在該 狀態下，以升溫至l〇〇〇°C爲止之狀態而進行10分鐘之退 火。在該退火處理後，降溫至第二SiGe層3之成膜溫度 爲止，再一次地供應來源氣體而進行殘餘之成膜。 接著，正如第三（b )圖所示，藉由 CMP ( Chemical Mechanical Polishing :化學機械式拋光）等，以便對於由 於熱處理而在表面產生因爲表面粗糙之惡化所造成之凹凸 之第二SiGe層3之表面，進行硏磨，成爲平坦化，除去 由於表面粗糙之惡化所產生之凹凸。 此外，前述第一 SiGe層2及第二SiGe層3之膜厚， 係分別例如成爲1 . 5 // m及0.7 5 // m。 此外，正如第三（c)涵所示，在硏磨之第二SiGe層 3上，使得Si層，進彳了嘉晶成長’形成歪斜Si層5’製 作半導體晶圓W。 在本實施形態，於藉由磊晶成長而形成第二s i Ge層 3之途中或形成後，在超過該磊晶成長溫度之溫度，施加 -24- (20) (20)1222106 熱處理，在第二SiGe層3形成後，藉由硏磨而除去在熱 處理所產生之表面凹凸，因此，在基板上，配合事前熱履 歷而預先產生由於晶格鬆弛或錯位之運動所造成之表面粗 糙之惡化，結果，在藉由元件製造作業等而施加熱處理時 ，能夠防止表面或界面之粗糙惡化再一次地產生。 此外，第一 S i G e層2係G e組成比朝向表面而逐漸地 增加之傾斜組成區域，因此，能夠在SiGe層中之特別是 表面側，抑制錯位密度。 接著，將使用本發明之前述實施形態之半導體基板之 場效型電晶體（MOSFET )及其製造製程，一起參照第四 圖而進行說明。 第四圖係顯示本發明之場效型電晶體之槪略構造；爲 了製造該場效型電晶體，因此，在具有藉由前述製造作業 所製作之歪斜Si層之半導體晶圓W表面之歪斜Si層5上 ，按照順序地堆積Si02之閘極氧化膜6及閘極多結晶矽 膜7。接著，在成爲通道區域之部分上之閘極多結晶矽膜 7上，進行圖案化，形成閘極電極（省略圖示）。 接著，閘極氧化膜6也進行圖案化，除去閘極電極下 以外之部分。此外，藉由在罩幕使用閘極電極之離子注入 ，而在歪斜Si層5及第二SiGe層3，自行整合地形成η 型或Ρ型源極區域S及汲極區域D。然後，分別在源極區 域S及汲極區域D上，形成源極電極及汲極電極（省略 圖示），製造歪斜Si層5成爲通道區域之η型或ρ型 MOSFET 〇 -25- (21) (21)1222106 在這樣所製作之mosfet，於具有藉由前述製法所製 作之歪斜Si層之半導體晶圓w上之歪斜Si層5，形成通 道區域，因此，在元件製造時，即使施加熱處理，也不會 產生表面或界面之粗糙惡化，可以藉由良質之歪斜Si層 5，而以高良品率，得到動作特性良好之MOSFET。例如 在形成前述閘極氧化膜6時，爲了形成熱氧化膜，因此， 加熱半導體晶圓W，但是，半導體晶圓W係預先承受事 前熱履歷，在熱氧化膜形成時，並無在Si Ge層或歪斜Si 層，產生表面或界面之粗糙惡化。 此外，本發明之技術範圍係並非限定於前述實施形態 ，可以在不脫離本發明主旨之範圍內，加入各種之變化。 例如在前述實施形態，於第二SiGe層之形成途中， 進行Si Ge層之熱處理，但是，也可以在第一 Si Ge層之形 成途中或第二SiGe層之形成後，進行熱處理。 此外，在具有前述實施形態之歪斜Si層之半導體晶 圓W上之歪斜Si層5上，甚至具有SiGe層之半導體晶 圓，也包含在本發明中。此外，在第二SiGe層上，直接 地形成歪斜Si層之薄膜，但是，也可以在第二SiGe層上 ，還形成其他SiGe層之薄膜，透過該SiGe層而使得該歪 斜Si層，進行磊晶成長。 此外，在本實施形態，作爲MOSFET用之基板，係 製作具有SiGe層之半導體晶圓，但是，也可以成爲適用 在其他用途之基板。例如本發明之半導體基板係可以適用 在太陽能電池用基板上。也就是說，可以藉由在前述各個 -26- (22) (22)1222106 實施形態之Si基板上，形成成爲逐漸地增加Ge組成比而 在最表面成爲l〇〇%Ge之傾斜組成區域之SiGe層之薄膜 ，並且，在該上面，形成Ga As (鎵砷）薄膜，以便於製 作太陽能電池用基板。在該狀態下，得到低錯位密度且高 性能之太陽能電池用基板。 以下，根據圖式而說明本發明之第二實施形態。 在本實施形態，第一、第二SiGe層係不同於前述實 施形態。 第五圖係顯示本發明之半導體晶圓（半導體基板）W 之剖面構造；在一起參照及說明該半導體晶圓之構造時， 首先，在藉由CZ法等而進行上拉成長所製作之p型或η 型Si基板1上，正如第五圖及第六圖所示，例如藉由減 壓CVD法，而對於Ge組成比X成爲一定（例如x = 〇. 1 5 )並且厚度更加薄於前述實際錯位之生成或晶格鬆弛開始 顯著地進行之膜厚之厚度（例如3 00nm)之第一 SiGe層 2，進行磊晶成長。 此時，由於第一 SiGe層2成膜更加薄於實際錯位之 生成或晶格鬆弛開始顯著地進行之膜厚，因此，在第一 SiGe層2之成膜中，配合膜厚而使得歪斜能量變大，但 是，幾乎不產生錯位或晶格鬆弛。 此外，第一 SiGe層2之厚度，係成爲滿足下列關係 式： tc ( nm ) = ( 1.9χ ΙΟ'3/ £ (χ)2) · In ( y 0.4) -27- (23) (23)1222106 e ( x ) = ( a〇 + 0.200326x + 0.026174x2//a〇) a〇= 0·5 43 ηπι ( aG係Si之格子常數） 之臨界膜厚U之2倍未滿之厚度。 接著，在第一 Si Ge層2上，對於第二Si Ge層3，進 行磊晶成長。該第二SiGe層3，係設定其Ge組成比y至 少在和第一 SiGe層2間之接觸面而更加低於第一 SiGe層 2之Ge組成比X之層中最大値。此外，第二SiGe層3， 係其Ge組成比y朝向表面而逐漸地增加的傾斜組成層（ 例如Ge組成比y由0開始增加至0.3爲止之層）（傾斜 組成區域），例如成膜至1 . 1 // m之厚度爲止。 在此，在這些第一 SiGe層2及第二SiGe層3之形成 途中或形成後，施加相同於前述第一實施形態之第三（a )圖所示之熱處理之同樣熱處理，預先在SiGe層，產生 表面粗糙之惡化，同時，正如在前述第一實施形態之第三 (b )圖所示，藉由CMP等，以便於硏磨由於熱處理而在 表面產生因爲表面粗糙之惡化所造成之凹凸之第二 SiGe 層3之表面，成爲平坦化，除去由於表面粗糙之惡化所產 生之凹凸。 在開始第一 SiGe層3之晶晶成長時’已經在第一 SiGe層2，積存歪斜能量，因此，在第二SiGe層3之膜 厚變薄之階段，錯位之生成和成長係由第一 SiGe層2兩 側之界面及第二SiGe層3內之第一 SiGe層2側而開始進 行，並且，第一 SiGe層2及第二SiGe層3之晶格鬆弛係 -28- (24) (24)1222106 開始進行。此時，由於第二SiGe層3之Ge組成比，係在 第一 SiGe層2之接觸面，更加低於第一 SiGe層2之Ge 組成比之層中最大値，因此，錯位係沿著第一 SiGe層2 兩側之界面2a、2b，進行集中及生成，第一 SiGe層2兩 側之界面2a、2b之錯位生成，係有助於第二SiGe層3之 晶格鬆弛，抑制在第二SiGe層3內之錯位之生成或成長 ，同時，也抑制第二SiGe層3表面之表面粗糙之惡化。 此外，藉由Ge組成比z相同於第二SiGe層3之最後 Ge組成比（例如z爲0.3 )，僅以既定厚度（例如0.4// m )而對於一定組成比之SiGe緩和層4，進行磊晶成長， 接著，在該SiGe緩和層4上，對於單結晶Si，進行磊晶 成長，形成歪斜Si層5，而在硏磨後，成爲既定厚度（ 例如20nm )，以便於製作本實施形態之半導體晶圓W。 此外，藉由前述減壓CVD法所造成之成膜，係使用 H2作爲載體氣體，使用SiH4及GeH4作爲來源氣體。 像這樣，在本實施形態之半導體晶圓W，相同於前述 第一實施形態，在藉由磊晶成長而形成第二SiGe層3之 途中或形成後，於超過該磊晶成長溫度之溫度，施加熱處 理，在第二SiGe層3形成後，藉由硏磨而除去在熱處理 所產生之表面凹凸，因此，在基板上，配合事前熱履歷而 預先產生由於晶格鬆弛或錯位之運動所造成之表面粗糙之 惡化’結果’在藉由兀件製造作業等而施加熱處理時，能 夠防止表面或界面之粗糙惡化再一次地產生，同時，設定 第一 SiGe層2之膜厚更加薄於實際錯位之生成或晶格鬆 -29 - (25)1222106 弛顯著地開始進行之膜厚，使得第二SiGe層3之Ge 比y至少在和第一 SiGe層2間之接觸面而更加低於 SiGe層2之Ge組成比X之層中最大値，因此，能夠 基板1和第一 SiGe層2間之界面2a以及第一 SiGe 和第二SiGe層3間之界面2b，有效率地集中錯位， 減低貫通錯位密度及表面粗糙等。 此外，由於第一 SiGe層2之Ge組成比係成爲一 因此，具有所謂以相同之Ge組成比而使得實際錯位 成或晶格鬆弛顯著地開始進行之膜厚變得最薄、以最 膜厚而得到本發明之效果、以及成膜所需要之時間短 點。 此外，可以藉由使得第一 SiGe層2成爲滿足前 係式之臨界膜厚U之2倍未滿之厚度，而根據後面 之實驗結果，設定第一 SiGe層2之膜厚，容易成爲 錯位之生成或晶格鬆弛顯著地開始進行之膜厚內。 此外，在本實施形態，具有藉由第二SiGe層3 逐漸增加Ge組成比之傾斜組成層（傾斜組成區域） 等地生成錯位、發生錯位間之相互纏繞及減少第二 層3中之錯位密度同時藉由錯位之成長導引至橫方向 少表面區域之貫通錯位密度，抑制表面粗糙之惡化的 〇 此外，在本實施形態，由於在第二SiGe層3之 前，已經在第一 SiGe層2，積存歪斜能量，因此， 二SiGe層3之膜厚變薄之階段，錯位之生成係在 組成 第一 在Si 層2 可以 定， 之生 薄之 之優 述關 敘述 實際 成爲 而均 SiGe 而減 效果 成膜 在第 第二 -30- (26) (26)1222106The SiGe layer 3 functions as a SiGe buffer layer as a thin film for forming a skewed si layer. Next, during the formation of the first SiGe layer 2 and the second SiGe layer 3, heat treatment is applied as shown in FIG. 3 (a), and the surface of the SiGe layer is deteriorated in advance. The heat treatment conditions are set at, for example, a temperature of so-called 800 ° C to 110 ° C, a temperature exceeding the epitaxial growth temperature of the SiGe layer, and a heat treatment time of 1 minute to 200 minutes. In addition, in this embodiment, once the supply of the source gas is stopped and the film formation is stopped during the film formation of the second SiGe layer 3, in this state, the film is heated to a temperature of 1000 ° C. 10 minutes annealing. After this annealing treatment, the temperature is lowered to the film-forming temperature of the second SiGe layer 3, and the source gas is supplied again to perform the remaining film-forming. Next, as shown in FIG. 3 (b), the second SiGe layer 3 is subjected to CMP (Chemical Mechanical Polishing), etc., so as to generate unevenness on the surface due to deterioration of surface roughness due to heat treatment. The surface is honed to be flattened to remove unevenness caused by deterioration of the surface roughness. In addition, the film thicknesses of the first SiGe layer 2 and the second SiGe layer 3 are, for example, 1.5 m / m and 0.7 5 m / m. In addition, as shown in the third (c), a semiconductor wafer W is formed on the second SiGe layer 3 by honing so that the Si layer is grown to form a skewed Si layer 5 '. In this embodiment, during or after forming the second si Ge layer 3 by epitaxial growth, a heat treatment of -24- (20) (20) 1222106 is applied at a temperature exceeding the epitaxial growth temperature. After the formation of the two SiGe layers 3, the surface unevenness caused by the heat treatment is removed by honing. Therefore, on the substrate, the deterioration of the surface roughness due to the relaxation of the lattice or the movement of the dislocation is generated in advance on the basis of the previous thermal history. As a result, when heat treatment is performed by a device manufacturing operation or the like, it is possible to prevent the occurrence of the roughening of the surface or the interface again. In addition, since the first SiGe layer 2 is a sloped composition region where the Ge composition ratio gradually increases toward the surface, the dislocation density can be suppressed particularly on the surface side in the SiGe layer. Next, the field-effect transistor (MOSFET) using the semiconductor substrate of the aforementioned embodiment of the present invention and its manufacturing process will be described with reference to the fourth figure. The fourth figure shows a schematic structure of a field-effect transistor of the present invention; in order to manufacture the field-effect transistor, the distortion on the surface of a semiconductor wafer W having a skewed Si layer produced by the aforementioned manufacturing operation On the Si layer 5, a gate oxide film 6 and a gate polycrystalline silicon film 7 of SiO2 are sequentially deposited. Next, the gate polycrystalline silicon film 7 on the portion that becomes the channel region is patterned to form a gate electrode (not shown). Next, the gate oxide film 6 is also patterned to remove portions other than the gate electrode. In addition, by using ion implantation of the gate electrode in the mask, the n-type or p-type source region S and the drain region D are formed on the skewed Si layer 5 and the second SiGe layer 3 by themselves. Then, a source electrode and a drain electrode (not shown) are formed on the source region S and the drain region D, respectively, and an n-type or p-type MOSFET with a skewed Si layer 5 as a channel region is manufactured. -25-25 (21 (21) 1222106 In the mosfet produced in this way, the channel region is formed on the skewed Si layer 5 on the semiconductor wafer w having the skewed Si layer produced by the aforementioned manufacturing method. Therefore, even when heat treatment is applied during element manufacturing, No rough deterioration of the surface or interface will occur, and the MOSFET with good operating characteristics can be obtained with a high yield rate by distorting the Si layer 5 with good quality. For example, when the gate oxide film 6 is formed, in order to form a thermal oxide film, the semiconductor wafer W is heated. However, the semiconductor wafer W is subjected to a prior thermal history in advance. Layer or skewed Si layer, causing rough deterioration of the surface or interface. In addition, the technical scope of the present invention is not limited to the foregoing embodiments, and various changes can be added without departing from the spirit of the present invention. For example, in the foregoing embodiment, the heat treatment of the Si Ge layer is performed during the formation of the second SiGe layer. However, the heat treatment may be performed during the formation of the first Si Ge layer or after the formation of the second SiGe layer. Further, on the skewed Si layer 5 on the semiconductor wafer W having the skewed Si layer of the foregoing embodiment, even a semiconductor wafer having a SiGe layer is included in the present invention. In addition, a thin film of a skewed Si layer is directly formed on the second SiGe layer, but a thin film of another SiGe layer may also be formed on the second SiGe layer, and the skewed Si layer may be passed through the SiGe layer to perform epitaxial Crystal growth. In addition, in this embodiment, as the substrate for the MOSFET, a semiconductor wafer having a SiGe layer is manufactured, but it may be a substrate suitable for other applications. For example, the semiconductor substrate of the present invention can be applied to a substrate for a solar cell. In other words, it is possible to form an inclined composition region that gradually increases the Ge composition ratio and becomes 100% Ge on the Si substrate of each of the aforementioned -26- (22) (22) 1222106 embodiments. A thin film of a SiGe layer, and a Ga As (gallium arsenide) film is formed on the thin film to facilitate the production of a substrate for a solar cell. In this state, a substrate with low dislocation density and high performance is obtained for a solar cell. Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In this embodiment, the first and second SiGe layers are different from the foregoing embodiment. The fifth figure shows the cross-sectional structure of the semiconductor wafer (semiconductor substrate) W of the present invention. When referring to and describing the structure of the semiconductor wafer together, first, p is produced by pull-up growth by the CZ method or the like. On the n-type or n-type Si substrate 1, as shown in the fifth and sixth figures, for example, by a reduced pressure CVD method, the composition ratio X for Ge becomes constant (for example, x = 0.15) and the thickness is thinner than The first SiGe layer 2 with a film thickness (for example, 300 nm) where the generation of the aforementioned actual dislocation or the relaxation of the lattice begins to proceed significantly, undergoes epitaxial growth. At this time, since the film formation of the first SiGe layer 2 is thinner than the film thickness at which the generation of the actual dislocation or the lattice relaxation begins to proceed significantly, the film thickness in the film formation of the first SiGe layer 2 is matched to the skew energy. It becomes larger, but hardly causes dislocation or lattice relaxation. In addition, the thickness of the first SiGe layer 2 satisfies the following relationship: tc (nm) = (1.9χ ΙΟ'3 / £ (χ) 2) · In (y 0.4) -27- (23) (23) 1222106 e (x) = (a〇 + 0.200326x + 0.026174x2 // a〇) a〇 = 0. 5 43 ηπ (aG-based lattice constant) is less than 2 times the critical film thickness U. Next, epitaxial growth is performed on the first Si Ge layer 2 and the second Si Ge layer 3. The second SiGe layer 3 is set such that its Ge composition ratio y is at least the largest in the contact surface with the first SiGe layer 2 and lower than the Ge composition ratio X of the first SiGe layer 2. In addition, the second SiGe layer 3 is an inclined composition layer whose Ge composition ratio y gradually increases toward the surface (for example, a layer whose Ge composition ratio y increases from 0 to 0.3) (inclined composition region), such as film formation to 1. 1 // m thickness. Here, during or after the formation of the first SiGe layer 2 and the second SiGe layer 3, the same heat treatment as that shown in the third (a) of the first embodiment is applied, and the SiGe layer is previously applied. In addition, as shown in the third (b) of the aforementioned first embodiment, the surface roughness is deteriorated. At the same time, CMP or the like is used to facilitate the honing of the surface due to the deterioration of the surface roughness due to the heat treatment. The surface of the second SiGe layer 3 is flattened to remove unevenness caused by the deterioration of the surface roughness. At the beginning of the crystal growth of the first SiGe layer 3, the distortion energy is already accumulated in the first SiGe layer 2. Therefore, at the stage where the film thickness of the second SiGe layer 3 becomes thin, the generation and growth of the dislocation is controlled by the first The interface on both sides of the SiGe layer 2 and the first SiGe layer 2 side in the second SiGe layer 3 started, and the lattice relaxation system of the first SiGe layer 2 and the second SiGe layer 3 was -28- (24) ( 24) 1222106 started. At this time, since the Ge composition ratio of the second SiGe layer 3 is on the contact surface of the first SiGe layer 2 and is even lower than the largest 値 in the Ge composition ratio of the first SiGe layer 2, the dislocation is along the first The interfaces 2a, 2b on both sides of a SiGe layer 2 are concentrated and generated, and the dislocation generation of the interfaces 2a, 2b on both sides of the first SiGe layer 2 helps to relax the lattice of the second SiGe layer 3 and suppress the The generation or growth of the misalignment in the second SiGe layer 3 also suppresses the deterioration of the surface roughness of the surface of the second SiGe layer 3. In addition, with the Ge composition ratio z being the same as the final Ge composition ratio of the second SiGe layer 3 (for example, z is 0.3), only a predetermined thickness (for example, 0.4 // m) is used for the SiGe relaxation layer 4 with a certain composition ratio. Epitaxial growth. Next, on this SiGe easing layer 4, epitaxial growth is performed on single-crystal Si to form a skewed Si layer 5. After honing, it has a predetermined thickness (for example, 20 nm) to facilitate the production of this embodiment. Of semiconductor wafers W. In addition, the film formation by the aforementioned reduced-pressure CVD method uses H2 as a carrier gas and SiH4 and GeH4 as source gases. As such, the semiconductor wafer W in this embodiment is the same as the first embodiment described above, and during the formation of the second SiGe layer 3 by epitaxial growth or after formation, at a temperature exceeding the epitaxial growth temperature, After heat treatment is applied, after the second SiGe layer 3 is formed, the surface unevenness caused by the heat treatment is removed by honing. Therefore, the substrate is caused in advance due to lattice relaxation or dislocation movement in accordance with the previous thermal history. The 'result' of the deterioration of the surface roughness can be prevented from occurring again when the surface or interface is deteriorated when heat treatment is performed by a manufacturing process or the like, and at the same time, the film thickness of the first SiGe layer 2 is set to be thinner than the actual dislocation. The film thickness at which the formation or lattice loose -29-(25) 1222106 begins to occur significantly makes the Ge ratio of the second SiGe layer 3 at least at the contact surface with the first SiGe layer 2 lower than that of the SiGe layer 2 The Ge ratio is the largest in the X layer. Therefore, the interface 2a between the substrate 1 and the first SiGe layer 2 and the interface 2b between the first SiGe and the second SiGe layer 3 can be efficiently concentrated and the through-dislocation can be reduced. dense Surface roughness and the like. In addition, since the Ge composition ratio of the first SiGe layer 2 is one, the so-called film composition with the same Ge composition ratio so that the actual dislocation formation or lattice relaxation begins significantly becomes the thinnest and the film thickness is the thinnest. The time required to obtain the effects of the present invention and film formation is short. In addition, the first SiGe layer 2 can be made to have a thickness less than twice the critical film thickness U that satisfies the previous formula, and according to subsequent experimental results, the film thickness of the first SiGe layer 2 can be set to easily become dislocated. Generation or lattice relaxation begins significantly within the film thickness. In addition, in this embodiment, the second SiGe layer 3 has a tilted composition layer (inclined composition region) in which the Ge composition ratio is gradually increased, dislocations are entangled with each other, and the dislocation density in the second layer 3 is reduced. At the same time, through the growth of the dislocation, the penetration dislocation density in the small surface area in the horizontal direction is guided to suppress the deterioration of the surface roughness. In addition, in this embodiment, since the second SiGe layer 3 is already in the first SiGe layer 2, The skew energy is accumulated. Therefore, at the stage when the film thickness of the two SiGe layers 3 becomes thin, the generation of the dislocation is determined in the first composition in the Si layer 2. The best description of the thinness of the thin film actually becomes the SiGe and reduces the effect. Film formation in the second -30- (26) (26) 1222106

SiGe層3內開始進彳了，結果，在第二SiGe層3內之傾斜 組成區域整體，得到前述效果，減少第二SiGe層3表@ 區域之貫通錯位密度，也抑制表面粗糙之惡化。 此外，第一 SiGe層2係發揮作爲除去所謂在Si基板 1表面之水分或氧成分或者碳成分之不純物之層之功能， 具有抑制起因於Si基板1表面污染之缺陷之效果。 此外，即使是在本實施形態，也能夠正如前述第~實 施形態之第四圖，製造使用前述半導體晶圓W之場效型 電晶體（MOSFET )。 接著，根據第七圖而說明本發明之第三實施形態。 本實施形態不同於第三實施形態之不同點，係在第二 實施形態之第一 SiGe層2，設定Ge組成比，成爲一定， 相對地，在本實施形態，正如第七圖所示，在和S i基板 1間之接觸面，使得第一 S i G e層1 2之G e組成比X，成爲 層中最大値，逐漸地減少Ge組成比X之方面。 也就是說，在本實施形態，於第一 S i Ge層1 2之形成 作業，在成膜開始時，使得Ge組成比X，成爲0.3，然後 ，逐漸地減少，最後改變Ge組成比X，幾乎成爲0爲止 ，成爲僅成長至更加薄於實際錯位之生成或晶格鬆弛顯著 地開始進行之膜厚之既定厚度（例如35 Onm )之傾斜組成 層。 在本實施形態，可以藉由在和Si基板1間之接觸面 ，使得第一 SiGe層12之Ge組成比X，成爲層中最大値 ，而使得成膜時之歪斜能量，集中在和S i基板1間之界 -31 - (27) (27)1222106 面側，在第二SiGe層3成膜開始時之所產生之晶格鬆弛 之際，比起和第二SiGe層3間之界面，還更加在和Si基 板1間之界面，產生許多錯位。可以藉此，而在離開第二 SiGe層3表面側之位置，集中錯位，相同於前述實施形 態，也能夠減低貫通錯位或表面粗糙。 接著，根據第八圖而說明本發明之第四實施形態。 本實施形態不同於第二實施形態之不同點，係第三實 施形態之第二SiGe層12成爲逐漸減少Ge組成比之傾斜 組成層，相對地，在第三實施形態，正如第八圖所示，在 第一 SiGe層22之形成作業，在成膜開始時，使得Ge組 成比X，成爲0.3，然後，逐漸地減少，最後改變Ge組成 比X，幾乎成爲〇爲止，進行既定厚度（例如3 5 0nm)之 成膜後，接著，還逐漸地增加Ge組成比X，最後成爲0.3 爲止之既定厚度（例如3 5 0nm)成膜之組成變化層之方面 此外，設定該第一 SiGe層22之厚度，更加薄於實際 錯位之生成或晶格鬆弛顯著地開始進行之膜厚。 即使是在該第四實施形態，第一 SiGe層22之Ge組 成比X，係在Si基板1和第二SiGe層3間之接觸面，成 爲層中最大値，因此，相同於第二實施形態，可以在Si 基板1和第二SiGe層3間之界面，產生許多錯位。 接著，根據第九圖及第十圖而說明本發明之第五及第 六實施形態。 第五實施形態不同於第二實施形態之不同點，係在第 -32- (28) (28)1222106 二實施形態之第一 SiGe層2，設定Ge組成比，成爲一定 ，相對地，在第五實施形態，正如第九圖所示，使得第一 SiGe層32之Ge組成比X，幾乎由〇開始而逐漸地增力[]， 最後一直到〇 . 3爲止，進行更加薄於實際錯位之生成或晶 格鬆弛顯著地開始進行之膜厚之既定厚度（例如3 5 0 n m ) 之成膜之方面。 此外，第六實施形態不同於第二實施形態之不同點， 係在第二實施形態之第一 SiGe層2，設定Ge組成比，成 爲一定，相對地，在第六實施形態，正如第十圖所示，使 得第一 SiGe層42之Ge組成比X，幾乎由0開始而逐漸 地增加，一直到0.3爲止，進行既定厚度（例如3 5 0nm) 之成膜，並且，然後還使得Ge組成比X，由0.3開始而 逐漸地減少，一直到幾乎0爲止，進行既定厚度（例如 3 5 0nm)之成膜之方面。此外，設定第一 S i Ge層4 2之厚 度，更加薄於實際錯位之生成或晶格鬆弛顯著地開始進行 之膜厚。 在這些第五及第六實施形態，能夠得到相同於前述實 施形態之同樣效果，同時，皆以更加薄於實際錯位之生成 或晶格鬆弛顯著地開始進行之膜厚之厚度而形成第一 SiGe層32、42之任何一個，因此，可以在第二SiGe層3 之成膜時，於第一 SiGe層32、42兩側之界面，集中地產 生錯位，減低貫通錯位或表面粗糙。此外，在第五及第六 實施形態，由於第一 SiGe層32、42層中之Ge組成比之 最大値，並無位處在和S i基板1間之界面側，因此，第 -33- (29) (29)1222106 二及第三實施形態係比較能夠得到貫通錯位和表面粗糙之 改善效果。 此外，在前述第二〜第六實施形態，於第一 SiGe層 中，對於膜厚之Ge組成比之分布係成爲正如5個之分布 ，但是，也可以成爲其他分布。例如也可以使得第一 SiGe層，成爲由不同Ge組成比之複數個SiGe層所構成 之多層膜。此外，也可以在成爲前述多層膜而包含Si層 之多層膜。 此外，在前述各個實施形態，於第一 SiGe層內而改 變Ge組成比之狀態下，對於膜厚而以一定比例，改變組 成，但是，也可以成爲其比例不一定之構造。此外，第一 SiGe層係可以是包含Ge之層，能夠積存歪斜能量，也可 以是這些以外之任何一種Ge組成比之分布。此外，在前 述各個實施形態，於第二SiGe層內使得Ge組成比朝向表 面而逐漸增加之傾斜組成區域，對於膜厚而以一定比例， 改變組成，但是，也可以成爲其比例不一定之構造。此外 ，可以使得其組成傾斜，成爲階梯狀之Ge組成比之變化 。此外，在前述各個實施形態，於第一 SiGe層上，直接 地配置第二SiGe層，但是，也可以透過Si層而配置第二 SiGe層。此外，也可以在前述各個實施形態之半導體晶 圓W之歪斜Si層上，還形成SiGe層之薄膜。 接著，根據圖式而說明本發明之第七實施形態。The SiGe layer 3 began to penetrate. As a result, the entire tilted composition region in the second SiGe layer 3 achieved the aforementioned effect, reducing the penetration dislocation density in the surface region of the second SiGe layer 3, and suppressing the deterioration of the surface roughness. In addition, the first SiGe layer 2 functions as a layer for removing so-called impurities such as moisture or oxygen components or carbon components on the surface of the Si substrate 1, and has the effect of suppressing defects caused by the surface contamination of the Si substrate 1. In addition, even in this embodiment, a field-effect transistor (MOSFET) using the semiconductor wafer W described above can be manufactured as in the fourth diagram of the first to the embodiment. Next, a third embodiment of the present invention will be described with reference to the seventh figure. This embodiment is different from the third embodiment in that the first SiGe layer 2 in the second embodiment has a Ge composition ratio set to be constant. In contrast, in this embodiment, as shown in the seventh figure, The contact surface with the Si substrate 1 makes the Ge composition ratio X of the first Si Ge layer 12 the largest 値 in the layer, and gradually decreases the Ge composition ratio X. That is, in this embodiment, in the formation operation of the first Si Ge layer 12 at the beginning of film formation, the Ge composition ratio X becomes 0.3, and then gradually decreases, and finally the Ge composition ratio X is changed. Until it becomes almost zero, it becomes a sloped composition layer that grows only to a predetermined thickness (for example, 35 Onm) that is thinner than the actual generation of dislocation or the beginning of lattice relaxation. In this embodiment, the contact ratio between the Si substrate 1 and the Si substrate 1 can make the Ge composition ratio X of the first SiGe layer 12 the largest in the layer, so that the skew energy during film formation can be concentrated on S i The boundary between the substrate 1 and the -31-(27) (27) 1222106 side, when the crystal lattice at the beginning of the formation of the second SiGe layer 3 is relaxed, compared with the interface with the second SiGe layer 3, Furthermore, many dislocations occur at the interface with the Si substrate 1. This allows the dislocation to be concentrated away from the surface side of the second SiGe layer 3, which is the same as the aforementioned embodiment, and can also reduce through-dislocation or surface roughness. Next, a fourth embodiment of the present invention will be described with reference to the eighth figure. This embodiment is different from the second embodiment in that the second SiGe layer 12 of the third embodiment becomes a tilted composition layer that gradually decreases the Ge composition ratio. In contrast, in the third embodiment, as shown in FIG. 8 In the formation operation of the first SiGe layer 22, at the beginning of film formation, the Ge composition ratio X becomes 0.3, and then gradually decreases. Finally, the Ge composition ratio X is changed to almost 0, and a predetermined thickness (for example, 3) is performed. After forming a film of 50 nm), the composition ratio X of Ge is gradually increased, and finally it becomes a composition changing layer of a predetermined thickness (for example, 350 nm) formed by 0.3. In addition, the first SiGe layer 22 is set to The thickness is thinner than the film thickness at which the generation of the actual dislocation or the relaxation of the lattice starts significantly. Even in this fourth embodiment, the Ge composition ratio X of the first SiGe layer 22 is the contact surface between the Si substrate 1 and the second SiGe layer 3, and it is the largest in the layer. Therefore, it is the same as the second embodiment. Many dislocations can occur at the interface between the Si substrate 1 and the second SiGe layer 3. Next, the fifth and sixth embodiments of the present invention will be described with reference to the ninth and tenth drawings. The fifth embodiment is different from the second embodiment in that it is -32- (28) (28) 1222106 The first SiGe layer 2 of the second embodiment, the Ge composition ratio is set to be constant. In contrast, in the first In the fifth embodiment, as shown in the ninth figure, the Ge composition ratio X of the first SiGe layer 32 is gradually increased from almost 0 [], and finally until 0.3, it is thinner than the actual dislocation. Formation or formation of a film of a given thickness (for example, 350 nm) where film relaxation begins significantly. In addition, the sixth embodiment is different from the second embodiment in that the first SiGe layer 2 in the second embodiment has a Ge composition ratio set to be constant. In contrast, in the sixth embodiment, as shown in FIG. As shown, the Ge composition ratio X of the first SiGe layer 42 is gradually increased from almost 0 to 0.3, and a film of a predetermined thickness (for example, 350 nm) is formed, and then the Ge composition ratio is also made. X is gradually decreased from 0.3 to almost 0, and the film formation with a predetermined thickness (for example, 350 nm) is performed. In addition, the thickness of the first SiGe layer 42 is set to be thinner than the film thickness at which the generation of the actual dislocation or the lattice relaxation starts significantly. In these fifth and sixth embodiments, it is possible to obtain the same effect as in the previous embodiment, and at the same time, the first SiGe is formed with a thickness that is thinner than the film thickness at which the generation of the actual dislocation or the lattice relaxation starts significantly. Either of the layers 32 and 42 can be concentrated at the interface between the two sides of the first SiGe layer 32 and 42 during the film formation of the second SiGe layer 3 to reduce through-dislocation or surface roughness. In addition, in the fifth and sixth embodiments, since the Ge composition ratio in the first SiGe layers 32 and 42 is the largest, and there is no position on the interface side with the Si substrate 1, the -33- (29) (29) 1222106 Compared with the second and third embodiments, it is possible to obtain the improvement effect of through-dislocation and surface roughness. In addition, in the second to sixth embodiments, the distribution of the Ge composition ratio with respect to the film thickness in the first SiGe layer is as small as five, but other distributions may also be used. For example, the first SiGe layer may be a multilayer film composed of a plurality of SiGe layers with different Ge composition ratios. Alternatively, a multilayer film including a Si layer as the multilayer film may be used. In addition, in each of the foregoing embodiments, in a state where the Ge composition ratio is changed in the first SiGe layer, the composition is changed in a certain ratio with respect to the film thickness, but it may have a structure in which the ratio is not constant. In addition, the first SiGe layer system may be a layer containing Ge, capable of accumulating distortion energy, or a distribution of any other Ge composition ratio than these. In addition, in each of the foregoing embodiments, in the second SiGe layer, the inclined composition region in which the Ge composition ratio gradually increases toward the surface changes the composition with a certain ratio for the film thickness, but it may also have a structure in which the proportion is not necessarily . In addition, its composition can be tilted to change the stepwise Ge composition ratio. In each of the foregoing embodiments, the second SiGe layer is directly disposed on the first SiGe layer. However, the second SiGe layer may be disposed through the Si layer. In addition, a thin film of a SiGe layer may be formed on the skewed Si layer of the semiconductor wafer W in each of the foregoing embodiments. Next, a seventh embodiment of the present invention will be described with reference to the drawings.

第十一圖係顯示本實施形態之半導體晶圓（半導體基 板）W之剖面構造；在，在一起對照說明該半導體晶圓W -34- (30) (30)1222106 之構造和其製造製程時，首先，正如第十一圖及第十二圖 所示，在藉由CZ法等而進行上拉成長所製作之p型或η 型之Si基板1上，例如藉由減壓CVD法，而對於Ge組 成比X成爲一定（例如X = 0. 1 5 )並且更加薄於前述實際 錯位之生成或晶格鬆弛顯著地開始進行之膜厚之厚度（例 如3 00nm )之第一 SiGe層2，進行磊晶成長。 此時，第一 SiGe層2係形成更加薄於實際錯位之生 成或晶格鬆弛顯著地開始進行之膜厚之薄膜，因此，雖然 在第一 SiGe層2之成膜中，配合膜厚而使得歪斜能量變 大，但是，幾乎不產生錯位或晶格鬆弛。 此外’第一 SiGe層2之厚度，係成爲滿足下列關係 式： tc ( nm ) = (1.9χ1(Γ3/ε ( χ ) 2 ) · In ( tC// 〇. 4 ) ε (χ) = ( a〇 + 0.200326x + 0.026174x2/a〇) a〇= 0.543 nm ( a〇係Si之格子常數） 之臨界膜厚U之2倍未滿之厚度。 接著，在第一 SiGe層2上，對於第二SiGe層3，進 行晶晶成長。設定該第二SiGe層3，使得其Ge組成比y 至少在和第一 SiGe層2間之接觸面而更加低於第一 SiGe 層2之Ge組成比χ之層中最大値。此外，第二SiGe層3 ’係使得Ge組成比χ由0開始至y (例如y = 0.3 )爲止 而沿著成膜方向具有傾斜並且呈階梯狀地進行變化之Sh- -35- (31)1222106 xGex之台階狀傾斜層。 接著，在第二SiGe層3上，對於Ge組成比成爲 之Si ^Gey之緩和層4，進行磊晶成長。此外，藉由 組成比z(在本實施形態z=y)而在Sii.zGez之緩禾[ 上，對於S i進行磊晶成長，形成歪斜S i層5，以便 作具有本實施形態之歪斜Si層之半導體晶圓W。此 各層之膜厚係例如第二Si Ge層3爲1.5 // m、緩和層 0.7〜0.8//111、歪斜81層5爲15〜2211111。 前述第二SiGe層3之成膜，係正如由第十二圖 十四圖所示，以連續之Ge組成比而重複地進行複數 對於朝向表面而逐漸地增加Ge組成比至既定値爲 SiGe傾斜組成層3a來進行磊晶成長之作業以及藉由 組成層3 a之最後Ge組成比而在傾斜組成層3 a上來 SiGe —定組成層3b進行磊晶成長之作業。此外， SiGe層3下面之Ge組成比，係設定成爲第一 SiGe 上面之Ge組成比以下。此外，在本實施形態，由0 而逐漸地增加第二SiGe層3之Ge組成比。 例如在本實施形態，重複地進行5次之傾斜組 3a和一定組成層3b之磊晶成長作業，而形成第二 層3。也就是說，在〗次之傾斜組成層3 a和一定組 3 b之磊晶成長作業成爲1個步驟時，首先作爲最初 ，係使得第一傾斜組成層3 a，在S i基板1上，由〇 至〇. 〇 6爲止而逐漸地增加Ge組成比，進行成長，在 面，形成Ge組成比爲〇.〇6之第——定組成層3b。 ;一定 以Ge ]層4 :於製 丨外， 4爲 至第 次之 止之 傾斜 對於 第二 層2 開始 成層 SiGe 成層 步驟 開始 其上 接著 -36- (32) (32)1222106 ，作爲第二步驟，係在Ge組成比爲0.06之第——定組成 層3b上，使得第二傾斜組成層3a，由0.06開始至0.12 爲止而逐漸地增加Ge組成比，進行成長，在其上面，形 成Ge組成比爲0.12之第二一定組成層3b。 接著，作爲第三步驟，係在Ge組成比爲0.1 2之第二 一定組成層3b上，使得第三傾斜組成層3a，由0.12開始 至〇. 1 8爲止而逐漸地增加Ge組成比，進行成長，在其上 面，形成Ge組成比爲〇. 18之第三一定組成層3b。接著 ，作爲第四步驟，係在Ge組成比爲0. 1 8之第三一定組成 層3b上，使得第四傾斜組成層3a，由0.18開始至0.24 爲止而逐漸地增加Ge組成比，進行成長，在其上面，形 成Ge組成比爲0.24之第四一定組成層3b。此外，作爲 最後步驟，係在Ge組成比爲0.24之第四一定組成層3b 上’使得第五傾斜組成層3 a，由0.2 4開始至0.3爲止而 逐漸地增加Ge組成比，進行成長，在其上面，形成Ge 組成比爲0.3之第五一定組成層3b。此外，在本實施形態 ，各個傾斜組成層3 a及各個一定組成層3 b之膜厚，係皆 設定成爲相同。 在開始前述第二SiGe層3之嘉晶成長時，已經在第 一 SiGe層2，積存歪斜能量，因此，在第二SiGe層3之 膜厚變薄之階段，錯位之生成和成長係由第一 SiGe層2 兩側之界面及第二SiGe層3內之第一 SiGe層2側而開始 進行，並且，第一 SiGe層2及第二SiGe層3之晶格鬆弛 係開始進行。此時，第二SiGe層3之Ge組成比，係在第 -37- (33) (33)Ϊ222106 一 SiGe層2之接觸面，更加低於第一 SiGe層2之Ge組 成比之層中最大値，因此，錯位係沿著第一 s丨Ge層2兩 側之界面2a、2b而集中及生成，第一 SiGe層2兩側之界 面2a、2b之錯位生成，係有助於第二SiGe層3之晶格鬆 弛，抑制在第二SiGe層3內之錯位之生成或成長，同時 ，也抑制第二SiGe層3表面之表面粗糙之惡化。 在此，在這些第一 SiGe層2及第二SiGe層3之途中 或形成後，施加相同於前述第一實施形態之第三（a )圖 所示之熱處理之同樣熱處理，預先在SiGe層，產生表面 粗糙之惡化，同時，正如在前述第一實施形態之第三（b )圖所示，藉由CMP等，以便於硏磨由於熱處理而在表 面產生因爲表面粗糙之惡化所造成之凹凸之第二SiGe層 3之表面，成爲平坦化，除去由於表面粗糙之惡化所產生 之凹凸。 此外，藉由僅以既定厚度（例如0.75 // m )而對於 Ge組成比z相同於第二SiGe層3之最後Ge組成比（例 如z爲0.3 )之一定組成比之SiGe緩和層4，進行磊晶成 長，接著，在該SiGe緩和層4上，對於單結晶Si，進行 磊晶成長，僅以既定厚度（例如20nm)而形成歪斜Si層 5，以便於製作本實施形態之半導體晶圓W。 此外，藉由前述減壓CVD法所造成之成膜，係例如 使用H2作爲載體氣體，使用SiH4及GeH4作爲來源氣體 〇 像這樣，在本實施形態之半導體晶圓W，相同於前述 -38- (34) (34)1222106 第一實施形態，在藉由裔晶成長而形成第二SiGe層3之 途中或形成後，於超過該磊晶成長溫度之溫度，施加熱處 理，在第二SiGe層3形成後，藉由硏磨而除去在熱處理 所產生之表面凹凸，因此，在基板上，配合事前熱履歷而 預先產生由於晶格鬆弛或錯位之運動所造成之表面粗糙之 惡化，結果，在藉由元件製造作業等而施加熱處理時，能 夠防止表面或界面之粗糙惡化再一次地產生，同時，設定 第一 SiGe層2之膜厚更加薄於實際錯位之生成或晶格鬆 弛顯著地開始進行之膜厚，使得第二SiGe層3之Ge組成 比y至少在和第一 SiGe層2間之接觸面而更加低於第一 SiGe層2之Ge組成比X之層中最大値，因此，能夠在Si 基板1和第一* SiGe層2間之界面2a以及第一 SiGe層2 和第二SiGe層3間之界面2b，有效率地集中錯位，可以 減低貫通錯位密度及表面粗糙等。 此外，由於第一 S i G e層2之G e組成比係成爲一定， 因此’具有所謂以相同之Ge組成比而使得實際錯位之生 成或晶格鬆弛顯著地開始進行之膜厚變得最薄、以最薄之 膜厚而得到本發明之效果、以及成膜所需要之時間短之優 點。 此外，可以藉由使得第一 SiGe層2成爲滿足前述關 係式之臨界膜厚t。之2倍未滿之厚度，而根據後面敘述 之實驗結果，設定第一 SiGe層2之膜厚，容易成爲實際 錯位之生成或晶格鬆弛顯著地開始進行之膜厚內。 此外，在本實施形態，由於在第二SiGe層3之成膜 -39- (35) (35)1222106 前，已經在第一 SiGe層2，積存歪斜能量，因此，在第 二SiGe層3之膜厚變薄之階段，錯位之生成係在第二 SiGe層3內開始進行，結果，在第二SiGe層3內之傾斜 組成區域整體，得到前述效果，減少第二SiGe層3表面 區域之貫通錯位密度，也抑制表面粗糙之惡化。 此外，第一 SiGe層2係發揮作爲除去所謂在Si基板 1表面之水分或氧成分或者碳成分之不純物之層之功能， 具有抑制起因於Si基板1表面污染之缺陷之效果。 此外，在本實施形態，於第二S i Ge層3之形成，以 連續之Ge組成比而重複地進行複數次之對於朝向表面而 逐漸地增加Ge組成比之SiGe傾斜組成層3a來進行磊晶 成長之作業以及藉由傾斜組成層3 a之最後Ge組成比而在 傾斜組成層3a上來對於SiGe —定組成層3b進行磊晶成 長之作業，因此，可以交互地形成複數段之傾斜組成層 3 a和一定組成層3 b而成爲Ge組成比之傾斜階梯狀之層 ，正如前面敘述，能夠形成錯位密度小且表面粗糙小之 SiGe 層。 也就是說，在本實施形態，能夠均等地產生晶格鬆驰 所需要之錯位，同時，形成SiGe層之薄膜，以便於使得 錯位儘可能地運動在橫方向上而不貫通及超出於表面上， 因此，能夠得到良好之表面狀態。 此外，即使是在本實施形態，也能夠正如前述第一實 施形態之第四圖所示，製造使用前述半導體晶圓W之場 效型電晶體（Μ Ο S F E T )。 -40- (36)1222106 接著，根據第十五圖及第十六圖而說明本發明 實施形態。 本實施形態和第七實施形態間之不同點，係在 施形態之第二SiGe層3，傾斜組成層3a及一定組 之膜厚係分別相同地進行設定，相對地，在第八實 ，正如第十五圖及第十六圖所示，在對於傾斜組成 及一定組成層13b進行磊晶成長之作業中，分別在 之重複中，使得傾斜組成層1 3 a及一定組成層1 3 b 逐漸地變薄而形成第二SiGe層13之方面。此外， 施形態，重複地進行5次之傾斜組成層3 a及一定 3 b之嘉晶成長作業，但是，在本實施形態，即使 複地進行4次之傾斜組成層1 3 a及一定組成層1 3 b 成長作業而形成第二SiGe層13之方面，也是不同 也就是說，在本實施形態，於傾斜組成層1 3 a 組成層1 3 b之晶晶成長作業，在成長第一傾斜組成 及第——定組成層1 3 b後，成長更加薄於第一傾斜 1 3 a及第--定組成層1 3 b的第二傾斜組成層1 3 a 一定組成層1 3 b。此外，同樣地成長更加薄於第二 成層13a及第二一定組成層13b的第三傾斜組成層 第三一定組成層1 3 b，最後成長更加薄於第三傾斜 1 3 a及第三一定組成層1 3 b的第四傾斜組成層1 3 a 一定組成層13b，而形成第二SiGe層13。 在此，在這些第四一定組成層13b之形成途中 後，施加相同於前述實施形態之同樣熱處理，3 之第八 第七實 成層3b 施形態 層 13a 每一次 之厚度 在本實 組成層 是在重 之嘉晶 的。 及一定 層13a 組成層 及第二 傾斜組 13a及 組成層 及第四 或形成 頃先在 -41 - (37) (37)1222106The eleventh figure shows the cross-sectional structure of the semiconductor wafer (semiconductor substrate) W according to this embodiment; when the structure of the semiconductor wafer W -34- (30) (30) 1222106 and its manufacturing process are explained in comparison with each other First, as shown in FIG. 11 and FIG. 12, on a p-type or η-type Si substrate 1 produced by pull-up growth by a CZ method or the like, for example, by a reduced pressure CVD method, For the first SiGe layer 2 whose Ge composition ratio is constant (for example, X = 0. 1 5) and is thinner than the film thickness (for example, 300 nm) where the generation of the actual dislocation or lattice relaxation begins significantly, Perform epitaxial growth. At this time, the first SiGe layer 2 is formed to be thinner than the film thickness at which the generation of the actual dislocation or the lattice relaxation starts significantly. Therefore, although the film thickness of the first SiGe layer 2 is adjusted to match the film thickness, The skew energy becomes large, but almost no dislocation or lattice relaxation occurs. In addition, the thickness of the first SiGe layer 2 satisfies the following relationship: tc (nm) = (1.9χ1 (Γ3 / ε (χ) 2) · In (tC // 0.4.) Ε (χ) = ( a〇 + 0.200326x + 0.026174x2 / a〇) a〇 = 0.543 nm (a 〇 lattice constant of Si) critical film thickness U is less than twice the thickness. Next, on the first SiGe layer 2, for The second SiGe layer 3 undergoes crystal growth. The second SiGe layer 3 is set so that its Ge composition ratio y is at least at the contact surface with the first SiGe layer 2 and is lower than the Ge composition ratio of the first SiGe layer 2. The largest 値 in the layer of χ. In addition, the second SiGe layer 3 ′ is such that Sh, which has a composition ratio χ from 0 to y (for example, y = 0.3), is inclined along the film formation direction and changes stepwise. --35- (31) 1222106 xGex stepped inclined layer. Next, on the second SiGe layer 3, epitaxial growth is performed on the Si ^ Gey relaxation layer 4 whose Ge composition ratio becomes. In addition, the composition ratio z (in this embodiment z = y), and in Sii.zGez, the epitaxial growth of Si is performed to form a skewed Si layer 5 so as to form a semiconductor having a skewed Si layer in this embodiment. Wafer W. The film thickness of each layer is, for example, the second Si Ge layer 3 is 1.5 // m, the relaxation layer 0.7 to 0.8 // 111, and the skew 81 layer 5 is 15 to 2211111. The film formation of the aforementioned second SiGe layer 3 As shown in the twelfth figure and the fourteenth figure, the complex number is repeatedly repeated at a continuous Ge composition ratio. For the surface, the Ge composition ratio is gradually increased to a predetermined level of SiGe inclined composition layer 3a for epitaxial growth. The operation and the operation of epitaxial growth of SiGe-fixed composition layer 3b on the inclined composition layer 3a by the final Ge composition ratio of the composition layer 3a. In addition, the Ge composition ratio under the SiGe layer 3 is set to be the first The Ge composition ratio above SiGe is below. In this embodiment, the Ge composition ratio of the second SiGe layer 3 is gradually increased from 0. For example, in this embodiment, the tilt group 3a and a certain composition layer are repeated five times. The epitaxial growth operation of 3b forms the second layer 3. In other words, when the epitaxial growth operation of the inclined composition layer 3a and a certain group 3b becomes a step, it is first used as the first step to make the first A tilted composition layer 3 a, on the Si substrate 1, from 〇 to 〇. 〇 The composition ratio of Ge is gradually increased up to 6 and growth is performed. On the surface, the third-constant composition layer 3b with a composition ratio of Ge of 0.06 is formed. The layer must be Ge]. The second stop of the tilt is for the second layer 2 to start the SiGe layering step, which is followed by -36- (32) (32) 1222106. As the second step, the Ge composition ratio is 0.06-the fixed composition layer. On 3b, the second oblique composition layer 3a is gradually increased from 0.06 to 0.12, and the Ge composition ratio is gradually increased, and a second certain composition layer 3b having a Ge composition ratio of 0.12 is formed thereon. Next, as a third step, it is on the second certain composition layer 3b with a Ge composition ratio of 0.1 2 so that the third inclined composition layer 3a gradually increases the Ge composition ratio from 0.12 to 0.18, Growth is performed, and a third constant composition layer 3b having a Ge composition ratio of 0.18 is formed thereon. Next, as a fourth step, the third certain composition layer 3b having a Ge composition ratio of 0.1 8 is formed, so that the fourth inclined composition layer 3a gradually increases the Ge composition ratio from 0.18 to 0.24. Grow, and a fourth certain composition layer 3b having a Ge composition ratio of 0.24 is formed thereon. In addition, as a final step, the fourth certain composition layer 3b having a Ge composition ratio of 0.24 is formed so that the fifth inclined composition layer 3a gradually increases the Ge composition ratio from 0.24 to 0.3 and grows. A fifth certain composition layer 3b having a Ge composition ratio of 0.3 is formed thereon. In addition, in this embodiment, the film thicknesses of each of the inclined composition layers 3a and each of the constant composition layers 3b are set to be the same. At the beginning of the growth of the Jiajing of the second SiGe layer 3, the distortion energy has been accumulated in the first SiGe layer 2. Therefore, at the stage where the film thickness of the second SiGe layer 3 becomes thin, the generation and growth of the dislocations are initiated by the first The interface on both sides of a SiGe layer 2 and the first SiGe layer 2 side in the second SiGe layer 3 begin, and the lattice relaxation system of the first SiGe layer 2 and the second SiGe layer 3 begins. At this time, the Ge composition ratio of the second SiGe layer 3 is at the -37- (33) (33) Ϊ222106 contact surface of the SiGe layer 2, which is even lower than the largest Ge composition ratio of the first SiGe layer 2 Alas, therefore, the dislocations are concentrated and generated along the interfaces 2a, 2b on both sides of the first SiGe layer 2, and the dislocations generated on the interfaces 2a, 2b on both sides of the first SiGe layer 2 contribute to the second SiGe The lattice of the layer 3 is relaxed, and the generation or growth of dislocations in the second SiGe layer 3 is suppressed, and at the same time, the deterioration of the surface roughness of the surface of the second SiGe layer 3 is also suppressed. Here, during or after the formation of the first SiGe layer 2 and the second SiGe layer 3, the same heat treatment as the heat treatment shown in the third (a) of the first embodiment is applied, and the SiGe layer is previously applied. Deterioration of surface roughness occurs, and at the same time, as shown in the third (b) diagram of the aforementioned first embodiment, CMP and the like are used to facilitate honing to generate unevenness on the surface due to deterioration of surface roughness due to heat treatment. The surface of the second SiGe layer 3 is flattened to remove unevenness caused by deterioration of the surface roughness. In addition, by using a predetermined thickness (eg, 0.75 // m) for the SiGe moderating layer 4 with a certain composition ratio of the Ge composition ratio z being the same as the final Ge composition ratio of the second SiGe layer 3 (eg, z is 0.3), Epitaxial growth, and then, on the SiGe relaxation layer 4, epitaxial growth is performed on single-crystal Si, and a skewed Si layer 5 is formed only with a predetermined thickness (for example, 20 nm) to facilitate the fabrication of the semiconductor wafer W of this embodiment. . In addition, the film formation by the aforementioned reduced-pressure CVD method uses, for example, H2 as a carrier gas and SiH4 and GeH4 as a source gas. As such, the semiconductor wafer W in this embodiment is the same as the above-38- (34) (34) 1222106 In the first embodiment, during or after forming the second SiGe layer 3 by crystal growth, heat treatment is applied at a temperature exceeding the epitaxial growth temperature, and the second SiGe layer 3 is applied. After the formation, the surface unevenness caused by the heat treatment is removed by honing. Therefore, on the substrate, the deterioration of the surface roughness due to the loosening or dislocation of the lattice is preliminarily combined with the previous thermal history. As a result, When heat treatment is applied during element manufacturing, etc., it is possible to prevent the deterioration of the surface or interface from occurring again. At the same time, the film thickness of the first SiGe layer 2 is set to be thinner than the actual generation of dislocation or lattice relaxation. The film thickness is such that the Ge composition ratio y of the second SiGe layer 3 is at least at the contact surface with the first SiGe layer 2 and is lower than that of the first SiGe layer 2 with the largest Ge composition ratio. Therefore, The interface 2a between the Si substrate 1 and the first * SiGe layer 2 and the interface 2b between the first SiGe layer 2 and the second SiGe layer 3 can efficiently concentrate dislocations, which can reduce penetration dislocation density and surface roughness. In addition, since the G e composition ratio of the first S i G e layer 2 is constant, the thickness of the film having the so-called Ge composition ratio that substantially starts the actual dislocation generation or lattice relaxation significantly becomes the largest. It is thin, and the effect of the present invention is obtained with the thinnest film thickness, and the time required for film formation is short. In addition, the first SiGe layer 2 can be made to have a critical film thickness t that satisfies the aforementioned relationship. It is less than twice the thickness, and based on the experimental results described later, setting the film thickness of the first SiGe layer 2 is likely to be within the film thickness where the generation of actual misalignment or lattice relaxation begins significantly. In addition, in this embodiment, since the first SiGe layer 2 has stored skew energy before the film formation of -39- (35) (35) 1222106 in the second SiGe layer 3, the second SiGe layer 3 At the stage where the film thickness becomes thinner, the generation of dislocation starts in the second SiGe layer 3, as a result, the entire tilted composition region in the second SiGe layer 3 achieves the aforementioned effect and reduces the penetration of the surface region of the second SiGe layer 3. Dislocation density also suppresses deterioration of surface roughness. In addition, the first SiGe layer 2 functions as a layer for removing so-called impurities such as moisture or oxygen components or carbon components on the surface of the Si substrate 1, and has the effect of suppressing defects caused by the surface contamination of the Si substrate 1. In addition, in the present embodiment, in the formation of the second Si Ge layer 3, the continuous Ge composition ratio is repeatedly performed a plurality of times, and the SiGe inclined composition layer 3a that gradually increases the Ge composition ratio toward the surface is subjected to epitaxy. The operation of crystal growth and the epitaxial growth of the SiGe-constant composition layer 3b on the inclined composition layer 3a by the final Ge composition ratio of the inclined composition layer 3a. Therefore, a plurality of inclined composition layers can be formed alternately. 3 a and a certain composition layer 3 b become an inclined stepped layer having a Ge composition ratio. As described above, a SiGe layer with a small dislocation density and a small surface roughness can be formed. That is, in this embodiment, it is possible to uniformly generate the dislocations required for lattice relaxation, and at the same time, form a thin film of the SiGe layer so that the dislocations can move in the horizontal direction as much as possible without penetrating and exceeding the surface. Therefore, a good surface state can be obtained. In addition, even in this embodiment, a field-effect transistor (M S F E T) using the semiconductor wafer W can be manufactured as shown in the fourth figure of the first embodiment. -40- (36) 1222106 Next, an embodiment of the present invention will be described with reference to Figs. 15 and 16. The difference between this embodiment and the seventh embodiment is that the second SiGe layer 3, the inclined composition layer 3a, and a certain group of film thicknesses are set the same in the applied embodiment. In contrast, in the eighth embodiment, as in As shown in Figs. 15 and 16, in the operation of epitaxial growth of the inclined composition and a certain composition layer 13b, the operations of the inclined composition layer 1 3a and the certain composition layer 1 3 b are gradually repeated respectively. The ground is thinned to form the second SiGe layer 13. In addition, in the application form, the tilted composition layer 3 a and constant 3 b are repeatedly performed for 5 times. However, in this embodiment, even if the inclined composition layer 1 3 a and constant composition layer are performed four times, 1 3 b The second SiGe layer 13 is also different in the growth operation. That is, in this embodiment, the crystal growth operation on the inclined composition layer 1 3 a and the composition layer 1 3 b is performed on the first inclined composition. After the first-definite composition layer 1 3 b, the growth is thinner than the first inclined composition layer 1 3 a and the second-inclined composition layer 1 3 b of the first-definite composition layer 1 3 b and the certain composition layer 1 3 b. In addition, the third oblique composition layer 1 3 b, which is thinner than the second formation layer 13 a and the second certain composition layer 13 b, is similarly grown, and finally grows thinner than the third oblique composition 1 3 a and the third The fourth inclined composition layer 1 3 a with a certain composition layer 1 3 b has a certain composition layer 13 b, and a second SiGe layer 13 is formed. Here, after the formation of these fourth certain composition layers 13b, the same heat treatment as that of the previous embodiment is applied, and the eighth and seventh actual formation layers 3b of 3b each time the thickness of the formation layer 13a is Jiaying in the heavy. And a certain layer 13a, a component layer, and a second inclined group 13a, a component layer, and a fourth or formation are in -41-(37) (37) 1222106

SiGe層，產生表面粗糙之惡化，同時，藉由CMP等，以 便於硏磨由於熱處理而在表面產生因爲表面粗糙之惡化所 造成之凹凸之第四一定組成層13b之表面，成爲平坦化， 除去由於表面粗縫之惡化所產生之凹凸。 也就是說，在第一傾斜組成層1 3 a及第——定組成層 13b成爲li、％ 一傾斜組成層13a及第二一定組成層13b 成爲I2、第二傾斜組成層13a及第二一定組成層13b成爲 h以及第四傾斜組成層13a及第四一定組成層13b成爲14 時，則進行層積而成爲h > 12 > 13 > 14。在此，第四傾斜 組成層1 3 a及第四一定組成層1 3 b之14係顯示硏磨後。 此外，產生錯位之臨界膜厚係隨著Ge組成比而改變 ’但是’前述各層係設定更加厚於該臨界膜厚，在各層， 均等地產生晶格鬆弛所需要之錯位。 此外，各個傾斜組成層1 3 a之Ge組成比之傾斜，係 分別設定成爲相同。 正如前面敘述，Ge組成比越高，則越容易產生錯位 ，因此，在正如第七實施形態而以相同厚度來重複地進行 成膜之狀態下，像上層一樣而產生許多錯位，相對地，正 如本實施形態一樣，可以藉由在每一次重複，使得傾斜組 成層13a及一定組成層13b之厚度逐漸地變薄，而在各層 ，更加均等地產生錯位。 接著，根據第十七圖而說明本發明之第九實施形態。 本實施形態和第七實施形態間之不同點，係在第七實 施形態之第一 SiGe層2，設定Ge組成比成爲一定，相對 -42- (38) (38)1222106 地，在本實施形態，正如第十七圖所示，第一 Si Ge層之 G e組成比X不成爲一定之方面。例如本實施形態之第一 例子，係正如第十七（a )圖所示，使得第一 S i Ge層12 之Ge組成比X，在和S i基板1間之接觸面，成爲層中最 大値，逐漸地減少Ge組成比X。 也就是說，在本實施形態之第一例子，於第一 siGe 層1 2之形成作業，在成膜開始時，使得Ge組成比X成爲 〇. 3，然後，逐漸地減少，最後使得Ge組成比X，幾乎變 化至〇爲止，成爲僅以既定厚度（例如350nm)成長爲更 加薄於實際錯位之生成或晶格鬆弛顯著地開始進行之膜厚 之傾斜組成層。 在本實施形態，可以藉由使得第一 SiGe層12之Ge 組成比X，在和Si基板1間之接觸面，成爲層中最大値 ，而使得成膜時之歪斜能量，集中在和S i基板1間之界 面側，能夠在第二SiGe層3成膜開始時之所產生之晶格 鬆弛之際，比起和第二SiGe層3間之界面，還更加在和 Si基板1間之界面，產生許多錯位。可以藉此而在離開 第二SiGe層3表面側之位置，集中錯位，也可以相同於 第七實施形態，減低貫通錯位或表面粗糙。 此外，本實施形態之第二例子，係正如第十七（a ) 圖所示，在第一 SiGe層22之形成作業中，於成膜開始時 ，使得Ge組成比X成爲0.3，然後，逐漸地減少，使得 Ge組成比X，幾乎變化至0爲止，以既定厚度（例如 3 5 Onm )而進行成膜後，接著，還再一次地逐漸增加Ge -43- (39) (39)1222106 組成比x，成爲最後進行至〇·3爲止之既定厚度（例如 3 5 0nm)成膜之組成變化層。 此外，該第一 SiGe層22之厚度，係也設定成爲更加 薄於實際錯位之生成或晶格鬆弛顯著地開始進行之膜厚。 即使是在該第二例子中，第一 SiGe層22之Ge組成 比X，係在Si基板1和第二SiGe層3間之接觸面，成爲 層中最大値，因此，相同於第一實施形態，可以在Si基 板1和第二SiGe層3間之界面，產生許多錯位。 此外，本實施形態之第三例子，係正如第十七（c ) 圖所示，使得第一 SiGe層32之Ge組成比X，幾乎由〇 開始而逐漸地增加，進行最後至0.3爲止之更加薄於實際 錯位之生成或晶格鬆弛顯著地開始進行之膜厚之既定厚度 (例如3 5 0 n m )之成膜。 此外，本實施形態之第四例子，係正如第十七（d ) 圖所示，使得第一 SiGe層42之Ge組成比X，幾乎由〇 開始而逐漸地增加，進行至〇. 3爲止之既定厚度（例如 3 5 Onm)之成膜，並且，然後由0.3開始而逐漸地減少Ge 組成比X，進行幾乎至〇爲止之既定厚度（例如3 5 0nm) 之成膜。此外，第一 SiGe層42之厚度係設定更加薄於實 際錯位之生成或晶格鬆弛顯著地開始進行之膜厚。 在這些第四及第五例子，第一 SiGe層32、42之厚度 係皆形成爲更加薄於實際錯位之生成或晶格鬆弛顯著地開 始進行之膜厚，因此，可以在第二SiGe層3之成膜時， 於第一 SiGe層32、42兩側之界面，集中地產生錯位，減 -44- (40) (40)1222106 低貫通錯位或表面粗糙。此外，在第四及第五例子，第一 SiGe層32、42層中之Ge組成比之最大値’並無存在於 和Si基板1間之界面側，因此，第一及第二實施形態係 比較能夠更加得到貫通錯位和表面粗糙之改善效果。 此外，本發明之技術範圍係並非限定於前述實施形態 ，可以在不脫離本發明意思之範圍內，加入各種變化。 例如在前述各個實施形態，於第一 SiGe層中，作爲 Ge組成比對於膜厚之分布，係成爲正如5個之分布，但 是，也可以成爲其他分布。例如也可以使得第一 SiGe層 ，成爲由不同Ge組成比之複數個SiGe層所構成之多層膜 。此外，也可以在成爲前述多層膜而包含Si層之多層膜 〇 此外，在前述各個實施形態，於第一 S i Ge層內而改 變Ge組成比之狀態下，對於膜厚而以一定比例，改變組 成，但是，也可以成爲其比例不一定之構造。 此外，第一 SiGe層係可以是包含Ge之層，能夠積存 歪斜能量，也可以是這些以外之任何一種Ge組成比之分 布。 此外，在前述各個實施形態，於第二S i Ge層內使得 Ge組成比朝向表面而逐漸增加之傾斜組成區域，對於膜 厚而以一定比例，改變組成，但是，也可以成爲其比例不 一定之構造。 此外，在前述各個實施形態，於第一 SiGe層上，直 接地配置第二SiGe層，但是，也可以透過Si層而配置第 -45- (41)1222106 __* S i G e 層。 此外’也可以在前述各個實施形態之半導體晶圓 斜Si層上，還形成SiGe層之薄膜。 此外’在前述各個實施形態，作爲MOSFET用 ，係製作具有SiGe層之半導體晶圓，但是，也可以 適用在其他用途之基板。例如也可以將本發明之半導 板之製造方法及半導體基板，適用在太陽能電池或光 用之基板上。也就是說，可以藉由在前述各個實施形 形成第二SiGe層及第三SiGe層之薄膜，而在最表面 爲由65%開始至l〇〇%Ge或100%Ge，並且，在其 ，形成InGaP (銦鎵磷）、GaAs (鎵石申）或 AlGaAs 鎵砷）之薄膜，以便於製作太陽能電池或光元件用基 在該狀態下，得到低錯位密度且高性能之太陽能電池 板0 【實施例】 接著，參照第十八圖及第十九圖，具體地說明根 述實施形態而進行硏磨前熱處理之狀態下之表面或界 粗糙惡化。 根據前述第七實施形態，作爲實施例及比較例， 使用直徑200mm之Si基板1，藉由扇葉式減壓型磊 膜裝置，而在載體氫’混合SiH4及GeH4，於壓力（ 〜15000Pa)及溫度680〜850°C之範圍，進行成膜。 十八圖，顯示這些實施例及比較例之製作流程圖。 之歪 基板 作爲 體基 元件 態， ，成 上面 (鋁 板。 用基 據前 面之 係皆 晶成 5 000 在第 •46- (42) (42) 1222106 在該狀態下，於退火處理及硏磨處理前，正如第十九 圖所示，分別使得第一 SiGe層2、第二SiGe層3、緩和 層4及歪斜Si層5，成膜爲30nm、2.0//m、1.0#m、 2〇nm。此外，第一 SiGe層2之Ge組成比係成爲0. 15， 同時，第二SiGe層3係傾斜組成層3a形成爲3層，使得 在最表面之傾斜組成層3 a之最後Ge組成比係成爲0.3。 硏磨前之退火處理，係藉由扇葉式減壓型磊晶成膜裝 置，而在氮氣流中、1100 °C，實施30分鐘。 此外，退火處理後之硏磨處理（CMP處理），係使 得硏磨料，成爲0.5 // m，在該硏磨處理後，實施一般之 SCI洗淨。 接著，在SCI洗淨後，以相同於當初之同樣成膜條件 而對於第二SiGe層3，進行0.5//m之再成膜，並且，對 於歪斜Si層4，進行20nm之成膜。 最後作爲元件製造作業中之熱處理之模擬測試，係爲 了比較本實施例及比較例之耐熱性，因此，使用模型熱處 理爐，還在氮氣流中、1100 °C，實施30分鐘之熱處理。 就前述所製作之本實施例及比較例而言，進行藉由表 面粗度計所造成之測定。此外，爲了進行比較，因此，在 硏磨前及元件熱處理之模擬測試之前後，分別進行測定。 此外，在表面粗度計之測定，係藉由掃描線長度 1mm、切斷長度〇. 1mm、測定步驟0.2 // m而進行。 這些測定結果係正如以下。 -47 - (43) <粗度測定 :1 >(本實施例及比較例：硏磨前晶圓） RMS ： 1 . 7 5 nm <粗度測定 :2-1 >(本實施例：硏磨後之再成膜後馬上 之晶圓） RMS ： 0.2 4 nm <粗度測定 :2-2 >(比較例：硏磨後之再成膜後馬上之 晶圓） RMS : 0.7 5 n m <粗度測定 :3 - 1 > (本實施例：熱處理之模擬測試後之 晶圓） RMS · 0.30nm 1222106 <粗度測定：3 -2 > (比較例：熱處理之模擬測試後之晶 圓） RM S : 0 · 8 5 nm 由前述結果而得知：本實施例係比起比較例，熱處理 之模擬測試後之RMS之變化非常小，成爲良好之表面狀 肯巨。 【產業上之可利用性】 如果藉由本發明的話，則達到以下效果。 -48- (44) (44)1222106 (1) 如果藉由本發明之半導體基板及半導體基板之 製造方法的話，則設定第一 SiGe層之膜厚更加薄於成爲 藉由膜厚之增加來產生錯位而產生晶格鬆弛之膜厚之臨界 膜厚之2倍，使得第二siGe層之Ge組成比至少在和第一 SiGe層或前述Si間之接觸面而更加低於第一 SiGe層之 Ge組成比之層中最大値，並且，第二Si Ge層具有至少一 部分之Ge組成比朝向表面而逐漸地增加的傾斜組成區域 ，因此，能夠在Si基板和第一 SiGe層間之界面以及第一 SiGe層和第二SiGe層間之界面附近，有效率地集中錯位 ，可以減低第二SiGe層表面之貫通錯位密度及表面粗糙 〇 (2) 如果藉由本發明之半導體基板及半導體基板之 製造方法的話，則在藉由磊晶成長而形成SiGe層之途中 或形成後，於超過該磊晶成長溫度之溫度，施加熱處理， 在SiGe層形成後，藉由硏磨而除去在熱處理所產生之表 面凹凸，因此，即使是在對於由於事前熱履歷所造成之表 面凹凸而進行硏磨除去之基板上，藉由元件製造作業等而 施加熱處理，也能夠防止表面或界面之粗糙再一次地惡化 〇 (3) 如果藉由本發明之半導體基板及半導體基板之 製造方法的話，則設定第一 SiGe層之膜厚更加薄於成爲 藉由膜厚之增加來產生錯位而產生晶格鬆弛之膜厚之臨界 膜厚之2倍，交互地且以連續之Ge組成比’來使得朝向 表面而使得Ge組成比逐漸地增加之SiGe傾斜組成層和以 -49- (46)1222106 第5圖係顯示本發明之第二實施形態之半導體基板之 剖面圖。 第6圖係顯示G e組成比相對於本發明之第二實施形 態之半導體基板膜厚之圖形。 第7圖係顯示Ge組成比相對於本發明之第三實施形 態之半導體基板膜厚之圖形。The SiGe layer causes the deterioration of the surface roughness, and at the same time, the surface of the fourth certain composition layer 13b, which is embossed due to the deterioration of the surface roughness due to the heat treatment, is flattened by CMP, etc., to be flattened. Removal of unevenness caused by deterioration of rough seams on the surface. In other words, the first inclined composition layer 13a and the first-definite composition layer 13b become li,%, the first inclined composition layer 13a and the second constant composition layer 13b become I2, the second inclined composition layer 13a, and the second When the constant composition layer 13b becomes h and the fourth inclined composition layer 13a and the fourth constant composition layer 13b become 14, they are laminated to h > 12 > 13 > 14. Here, 14 of the fourth inclined composition layer 1 3 a and the fourth constant composition layer 1 3 b is shown after honing. In addition, the critical film thickness that causes dislocations varies depending on the Ge composition ratio. However, the aforementioned layer systems are set to be thicker than this critical film thickness, and the dislocations required for lattice relaxation are uniformly generated in each layer. In addition, the inclination of the Ge composition ratio of each of the inclined composition layers 13a is set to be the same. As described above, the higher the Ge composition ratio, the more easily dislocations occur. Therefore, in the state where the film is repeatedly formed with the same thickness as in the seventh embodiment, many dislocations are generated like the upper layer. As in this embodiment, the thickness of the inclined composition layer 13a and the constant composition layer 13b can be gradually reduced by repeating each time, and the dislocations can be more evenly generated in each layer. Next, a ninth embodiment of the present invention will be described with reference to the seventeenth figure. The difference between this embodiment and the seventh embodiment lies in the first SiGe layer 2 of the seventh embodiment, and the Ge composition ratio is set to be constant. Relative to -42- (38) (38) 1222106, in this embodiment As shown in the seventeenth figure, the Ge composition ratio X of the first Si Ge layer does not become a certain aspect. For example, the first example of this embodiment is as shown in the seventeenth (a) diagram, so that the Ge composition ratio X of the first Si Ge layer 12 becomes the largest in the layer at the contact surface with the Si substrate 1. Alas, the Ge composition ratio X is gradually reduced. That is, in the first example of this embodiment, in the formation operation of the first siGe layer 12, at the beginning of film formation, the Ge composition ratio X becomes 0.3, and then gradually decreases, and finally the Ge composition The ratio X almost changes to 0, and becomes a sloped composition layer that grows only at a predetermined thickness (for example, 350 nm) to a thickness that is thinner than the actual generation of dislocation formation or lattice relaxation. In this embodiment, by making the Ge composition ratio X of the first SiGe layer 12 the largest surface in the layer at the contact surface with the Si substrate 1, the skew energy during film formation can be concentrated on S i On the interface side between the substrate 1 and the second SiGe layer 3, when the lattice formed at the beginning of film formation is relaxed, the interface with the second SiGe layer 3 can be more at the interface with the Si substrate 1 , Resulting in many dislocations. By doing so, it is possible to concentrate the dislocation at a position away from the surface side of the second SiGe layer 3, or it may be the same as that of the seventh embodiment to reduce the through dislocation or the surface roughness. In addition, as shown in the seventeenth (a) diagram in the second example of this embodiment, in the formation operation of the first SiGe layer 22, at the beginning of film formation, the Ge composition ratio X is 0.3, and then gradually Ground, so that the Ge composition ratio X changes almost to 0, and after forming the film with a predetermined thickness (for example, 3 5 Onm), the composition of Ge -43- (39) (39) 1222106 is gradually increased again. The ratio x is a composition change layer having a film thickness of a predetermined thickness (for example, 350 nm) which is finally performed until 0.3. In addition, the thickness of the first SiGe layer 22 is also set to be thinner than the film thickness at which the generation of the actual dislocation or the lattice relaxation starts significantly. Even in this second example, the Ge composition ratio X of the first SiGe layer 22 is at the contact surface between the Si substrate 1 and the second SiGe layer 3 and becomes the largest 値 in the layer. Therefore, it is the same as the first embodiment. Many dislocations can occur at the interface between the Si substrate 1 and the second SiGe layer 3. In addition, the third example of this embodiment is as shown in the seventeenth (c) diagram, so that the Ge composition ratio X of the first SiGe layer 32 gradually increases from almost 0, and finally increases to 0.3. Film formation of a predetermined thickness (for example, 350 nm), which is thinner than the actual generation of dislocation or lattice relaxation begins significantly. In addition, the fourth example of this embodiment is, as shown in the seventeenth (d) diagram, the Ge composition ratio X of the first SiGe layer 42 gradually increases from almost 0 to 0.3. A film having a predetermined thickness (for example, 3 Onm) is formed, and then a Ge composition ratio X is gradually reduced from 0.3 to form a film having a predetermined thickness (for example, 350 nm) to almost zero. In addition, the thickness of the first SiGe layer 42 is set to be thinner than the film thickness at which the generation of the actual dislocation or the lattice relaxation starts significantly. In these fourth and fifth examples, the thicknesses of the first SiGe layers 32 and 42 are all formed to be thinner than the film thickness at which the generation of the actual dislocation or the lattice relaxation starts significantly. During the film formation, dislocations are concentrated at the interfaces on both sides of the first SiGe layers 32 and 42 to reduce -44- (40) (40) 1222106 low-through dislocations or surface roughness. In addition, in the fourth and fifth examples, the largest Ge composition ratio 値 ′ in the first SiGe layers 32 and 42 is not present on the interface side with the Si substrate 1. Therefore, the first and second embodiments are The improvement effect of through-dislocation and surface roughness can be more obtained. In addition, the technical scope of the present invention is not limited to the foregoing embodiments, and various changes can be added without departing from the meaning of the present invention. For example, in each of the foregoing embodiments, the distribution of the Ge composition ratio to the film thickness in the first SiGe layer is as small as five, but it may be other distributions. For example, the first SiGe layer can also be made into a multilayer film composed of a plurality of SiGe layers with different Ge composition ratios. In addition, the multilayer film including the Si layer as the multilayer film may be used. In addition, in each of the foregoing embodiments, in a state where the Ge composition ratio is changed in the first Si Ge layer, the film thickness is a certain ratio. The composition is changed, but it may be a structure whose proportion is not necessarily. In addition, the first SiGe layer system may be a layer containing Ge, capable of accumulating distortion energy, or a distribution of any other Ge composition ratio than these. In addition, in each of the foregoing embodiments, in the second SiGe layer, the inclined composition region that gradually increases the Ge composition ratio toward the surface changes the composition with a certain ratio for the film thickness, but the ratio may not necessarily be Of the structure. In each of the foregoing embodiments, the second SiGe layer is directly disposed on the first SiGe layer. However, the -45- (41) 1222106 __ * S i G e layer may be disposed through the Si layer. In addition, a thin film of a SiGe layer may be formed on the oblique Si layer of the semiconductor wafer in each of the foregoing embodiments. In addition, in each of the foregoing embodiments, as a MOSFET, a semiconductor wafer having a SiGe layer is produced, but it can also be applied to a substrate for other purposes. For example, the method for manufacturing a semiconductor substrate and the semiconductor substrate of the present invention may be applied to a substrate for a solar cell or light. That is, the thin films of the second SiGe layer and the third SiGe layer can be formed in each of the foregoing embodiments, and the top surface can be from 65% to 100% Ge or 100% Ge, and, Forming InGaP (Indium Gallium Phosphate), GaAs (GaAs) or AlGaAs (Gallium Arsenic) thin films, in order to make substrates for solar cells or optical elements in this state, low-dislocation density and high-performance solar cell panels can be obtained. 0 【 EXAMPLES Next, with reference to the eighteenth and nineteenth drawings, the surface or boundary roughness in a state where the heat treatment before honing is performed according to the embodiment will be specifically described. According to the aforementioned seventh embodiment, as an example and a comparative example, a Si substrate 1 having a diameter of 200 mm was used, and a fan-type decompression type epitaxial film device was used to mix SiH4 and GeH4 with a carrier hydrogen under pressure (~ 15000Pa). The film is formed at a temperature ranging from 680 to 850 ° C. Figure 18 shows the production flow chart of these examples and comparative examples. The distorted substrate is used as the body-based element state, and becomes the upper surface (aluminum plate. It is crystallized by using the previous system to form 5000. In the state of 46- (42) (42) 1222106, in this state, annealing treatment and honing treatment Previously, as shown in the nineteenth figure, the first SiGe layer 2, the second SiGe layer 3, the relaxation layer 4 and the skewed Si layer 5 were respectively formed into a film of 30nm, 2.0 // m, 1.0 # m, 20nm. In addition, the Ge composition ratio of the first SiGe layer 2 becomes 0.15, and at the same time, the second SiGe layer 3 is formed of three inclined composition layers 3a, so that the final Ge composition ratio of the inclined composition layer 3a at the outermost surface is Ge. The temperature becomes 0.3. The annealing treatment before honing is performed in a nitrogen flow at 1100 ° C for 30 minutes using a fan-type decompression epitaxial film-forming device. In addition, the honing treatment after annealing ( CMP treatment), so that the honing material becomes 0.5 // m, and after this honing treatment, general SCI washing is performed. Then, after SCI washing, the same film forming conditions as the original and the second The SiGe layer 3 was re-formed at 0.5 // m, and the skew Si layer 4 was formed at 20 nm. Finally, it was used as an element. In order to compare the heat resistance of this example and the comparative example, the simulation test of the heat treatment in the manufacturing operation is performed by using a model heat treatment furnace and performing a heat treatment at 1100 ° C in a nitrogen stream for 30 minutes. In this example and the comparative example, measurement by a surface roughness meter was performed. For comparison, the measurement was performed before honing and before and after the simulation test of the heat treatment of the element. The measurement of the roughness meter was performed by scanning line length of 1 mm, cutting length of 0.1 mm, and measurement step of 0.2 // m. These measurement results are as follows. -47-(43) < Roughness measurement: 1 > (this example and comparative example: wafer before honing) RMS: 1.7 5 nm < roughness measurement: 2-1 > (this example: crystals immediately after honing after re-filming) (Round) RMS: 0.2 4 nm < Roughness measurement: 2-2 > (Comparative example: Wafer immediately after honing and then film formation) RMS: 0.7 5 nm < Roughness measurement: 3-1 > (This example: wafer after heat treatment simulation test) RMS · 0.30nm 1222106 < Roughness measurement: 3 -2 > (Comparative example: Wafer after simulated test of heat treatment) RM S: 0 · 8 5 nm From the foregoing results, it is known that this example is compared with the comparative example, the heat treatment The RMS change after the simulation test is very small, and it becomes a good surface. [Industrial Applicability] According to the present invention, the following effects can be achieved. -48- (44) (44) 1222106 (1) If the semiconductor substrate and the semiconductor substrate manufacturing method of the present invention are used, the film thickness of the first SiGe layer is set to be thinner than that caused by the increase in film thickness to cause dislocation. The critical film thickness of the film thickness causing the lattice relaxation is twice, so that the Ge composition of the second siGe layer is lower than the Ge composition of the first SiGe layer at least at the contact surface with the first SiGe layer or the aforementioned Si. The ratio is the largest, and the second Si Ge layer has an inclined composition region where at least a part of the Ge composition ratio gradually increases toward the surface. Therefore, the interface between the Si substrate and the first SiGe layer and the first SiGe layer can be formed. Near the interface between the SiGe layer and the second SiGe layer, the dislocation is efficiently concentrated, which can reduce the penetration dislocation density and surface roughness of the surface of the second SiGe layer. (2) If the semiconductor substrate and the semiconductor substrate manufacturing method of the present invention are used, During or after the formation of the SiGe layer by epitaxial growth, heat treatment is applied at a temperature exceeding the epitaxial growth temperature, and after the SiGe layer is formed, the heat produced is removed by honing. As a result, the surface or interface can be prevented from being roughened again by applying heat treatment to the substrate by honing the surface unevenness caused by the thermal history in advance. Deterioration (3) If the semiconductor substrate and the method for manufacturing a semiconductor substrate of the present invention are used, the film thickness of the first SiGe layer is set to be thinner than the film thickness caused by the increase in film thickness to cause dislocation and lattice relaxation. The critical film thickness is twice that of the SiGe tilted composition layer alternately and continuously with the Ge composition ratio to make the Ge composition ratio gradually increase toward the surface and -49- (46) 1222106 Figure 5 shows this Sectional view of a semiconductor substrate according to a second embodiment of the invention. Fig. 6 is a graph showing the composition ratio of Ge with respect to the film thickness of the semiconductor substrate according to the second embodiment of the present invention. Fig. 7 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate according to a third embodiment of the present invention.

第8圖係顯示Ge組成比相對於本發明之第一實施形 態之半導體基板膜厚之圖形。 第9圖係顯示Ge組成比相對於本發明之第五實施形 態之半導體基板膜厚之圖形。 第1 0圖係顯示Ge組成比相對於本發明之第六實施形 態之半導體基板膜厚之圖形。 第1 1圖係顯示本發明之第七實施形態之半導體基板 之剖面圖。Fig. 8 is a graph showing the Ge composition ratio with respect to the film thickness of the semiconductor substrate according to the first embodiment of the present invention. Fig. 9 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate according to a fifth embodiment of the present invention. Fig. 10 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate according to a sixth embodiment of the present invention. Fig. 11 is a sectional view showing a semiconductor substrate according to a seventh embodiment of the present invention.

第1 2圖係顯示Ge組成比相對於本發明之第七實施形 態之半導體基板膜厚之圖形。 第13圖係顯示本發明之第七實施形態之第二SiGe層 之剖面圖。 第1 4圖係顯示Ge組成比相對於本發明之第七實施形 態之第二Si Ge層膜厚之圖形。 第15圖係顯示本發明之第八實施形態之第二SiGe層 之剖面圖。 第1 6圖係顯示Ge組成比相對於本發明之第八實施形 態之各個例子中之第一 SiGe層膜厚之圖形。 -51 - (47)1222106 第1 7圖（a )〜（d )係顯示Ge組成比相對於本發明 之第九實施形態之各個例子中之第一 SiGe層膜厚之圖形 〇 第1 8圖係顯示本發明之實施例及比較例之製造流程 圖之圖形。 第1 9圖係顯示本發明之實施例及比較例中之硏磨前 晶圓之層構造及Ge組成比之說明圖。 【圖號說明】 D 汲極區域 S 源極區域 t C 臨界膜厚 W 半導體晶圓（半導體基板） 1 Si基板 2 第一 S i G e層 2 a 界面 3b 界面 3 第二SiGe層 3 a 傾斜組成層 3b 一定組成層 4 SiGe緩和層 5 歪斜S i層 6 Si02閘極氧化膜Fig. 12 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate according to a seventh embodiment of the present invention. Fig. 13 is a sectional view showing a second SiGe layer according to a seventh embodiment of the present invention. Fig. 14 is a graph showing the Ge composition ratio with respect to the film thickness of the second Si Ge layer in the seventh embodiment of the present invention. Fig. 15 is a sectional view showing a second SiGe layer according to an eighth embodiment of the present invention. Fig. 16 is a graph showing the Ge composition ratio with respect to the film thickness of the first SiGe layer in each example of the eighth embodiment of the present invention. -51-(47) 1222106 Figures 17 (a) ~ (d) are graphs showing the composition ratio of Ge to the film thickness of the first SiGe layer in each example of the ninth embodiment of the present invention. Figure 18 It is a figure which shows the manufacturing flowchart of the Example and the comparative example of this invention. Fig. 19 is an explanatory diagram showing the layer structure and Ge composition ratio of the wafer before honing in the examples and comparative examples of the present invention. [Illustration of drawing number] D Drain region S Source region t C Critical film thickness W Semiconductor wafer (semiconductor substrate) 1 Si substrate 2 First SiGe layer 2a Interface 3b Interface 3 Second SiGe layer 3a Tilt Composition layer 3b Certain composition layer 4 SiGe relaxation layer 5 Skew Si layer 6 Si02 gate oxide film

-52- 7 1222106 (48) 12 第一^ S i Ge層 13 第二SiGe層 13a 傾斜組成層 13b 一定組成層 22 第一 SiGe層 32 第一 S i G e層 42 第一 SiGe層-52- 7 1222106 (48) 12 First Si Ge layer 13 Second SiGe layer 13a Tilt composition layer 13b Certain composition layer 22 First SiGe layer 32 First S i Ge layer 42 First SiGe layer

Claims (1)

12221061222106 民國93年6月17日修正 附件 第92102412號專利申請寒 中文申請專利範圍修正： ’ (1) 拾、申請專利範圍 1·一種半導體基板之製造方法，係在Si基板上而對 於SiGe層進行磊晶成長的半導體基板之製造方法，其特 徵爲·’具有： 在前述Si基板上，對於第一 SiGe層進行磊晶成長之 第一層形成作業；Amended Annex No. 92102412 on June 17, 1993. Amendments to the Chinese patent application scope: '(1) Pick up and apply for a patent scope 1. A method for manufacturing a semiconductor substrate, which is based on a Si substrate and SiGe layer The method for manufacturing a crystal-grown semiconductor substrate is characterized by having the following steps: a first layer forming operation for epitaxial growth of a first SiGe layer on the Si substrate; 在前述第一 SiGe層上，直接或透過磊晶成長之Si層 而對於第二SiGe層進行磊晶成長之第二層形成作業； 在藉由磊晶成長而形成前述SiGe層之途中或形成後 ，於超過該磊晶成長溫度之溫度，施加熱處理之熱處理作 業；以及， 在前述SiGe層形成後，藉由硏磨而除去在前述熱處 理所產生之表面凹凸之硏磨作業；此外，On the first SiGe layer, the second layer forming operation for epitaxial growth of the second SiGe layer is performed directly or through the epitaxially grown Si layer; during or after forming the aforementioned SiGe layer by epitaxial growth. A heat treatment operation for applying heat treatment at a temperature exceeding the epitaxial growth temperature; and a honing operation for removing the surface unevenness produced by the heat treatment by honing after the formation of the SiGe layer; 前述第一層形成作業係設定前述第一 SiGe層之膜厚 更加薄於成爲藉由膜厚之增加來產生錯位而產生晶格鬆驰 之膜厚之臨界膜厚之2倍，前述第二層形成作業係形成使 得前述第二SiGe層之Ge組成比至少在和前述第一 siGe 層或則述S i間之接觸面而更加低於第一 S i G e層之G e組 成比之層中最大値並且至少一部分之G e組成比朝向表面 而逐漸地增加的傾斜組成區域。 2 ·如申請專利範圍第1項所記載之半導體基板之製造 方法，其中，前述第一層形成作業係前述第一 SiGe層之 Ge組成比X成爲一定，使得第一 SiGe層，成爲滿足下列 關係式： (2)1222106 tc(nm) = (1.9χ10*3/ε ( x ) 2 ) · In ( tc/ 0.4 ) ε (x) = ( a〇 + 〇·200326χ + 0.026 1 74x2/ a0 ) a0= 〇.5 43 nm ( aG係Si之格子常數） 之臨界fe厚t。之2倍未滿之厚度。The first layer forming operation is to set the film thickness of the first SiGe layer to be thinner than the critical film thickness that is a film thickness that results in dislocation due to an increase in film thickness and a lattice relaxation. The forming operation is performed to form a layer such that the Ge composition ratio of the second SiGe layer is at least lower than the G e composition ratio of the first SiGe layer or the contact surface between the first SiGe layer or the Si. A sloped composition region with a maximum 値 and at least a portion of the G e composition ratio that gradually increases toward the surface. 2 · The method for manufacturing a semiconductor substrate as described in item 1 of the scope of the patent application, wherein the first layer forming operation is a constant Ge composition ratio X of the first SiGe layer, so that the first SiGe layer satisfies the following relationship Formula: (2) 1222106 tc (nm) = (1.9χ10 * 3 / ε (x) 2) · In (tc / 0.4) ε (x) = (a〇 + 〇 · 200326χ + 0.026 1 74x2 / a0) a0 = 0.55 critical thickness t of 43 nm (lattice constant of aG-based Si). 2 times less than full thickness. 3 .如申請專利範圍第〗或2項所記載之半導體基板之 製造方法，其中，前述第一 Si Ge層係Ge組成比X成爲 〇 · 〇 5以上及0.3以下。 4 ·如申請專利範圍第1或2項所記載之半導體基板之 製造方法’其中，前述第二Si Ge層係直接配置在前述第 一* SiGe層上’並且，成爲層整體之Ge組成比朝向表面而 逐漸增加的傾斜組成層。3. The method for manufacturing a semiconductor substrate according to item 1 or 2 of the scope of the patent application, wherein the Ge composition ratio X of the first Si Ge layer system is greater than or equal to 0.5 and less than or equal to 0.3. 4 · The method for manufacturing a semiconductor substrate as described in item 1 or 2 of the scope of the patent application, wherein the aforementioned second Si Ge layer is directly disposed on the aforementioned first * SiGe layer 'and the Ge composition ratio of the entire layer is oriented The surface gradually slopes up to form a layer. 5.—種半導體基板之製造方法，係在Si基板上透過 SiGe層而形成歪斜Si層的半導體基板之製造方法，其特 徵爲： 在藉由如申請專利範圍第1至4項所記載的任一項之 半導體基板之製造方法所製作之半導體基板之前述第二 SiGe層上，直接或透過其他SiGe層，而對於前述歪斜Si 層，進行磊晶成長。 6·—種半導體基板之製造方法，係在Si基板上而對 於SiGe層進行磊晶成長的半導體基板之製造方法，其特 徵爲：具有： 在前述Si基板上，對於第一 SiGe層進行磊晶成長之 -2- (3) (3)1222106 第一層形成作業； 在前述第一 SiGe層上，直接或透過磊晶成長之Si層 而對於第二SiGe層進行磊晶成長之第二層形成作業； 在藉由磊晶成長而形成前述SiGe層之途中或形成後 ，於超過該磊晶成長溫度之溫度，施加熱處理之熱處理作 業；以及， 在前述SiGe層形成後，藉由硏磨而除去在前述熱處 理所產生之表面凹凸之硏磨作業；此外， 前述第一層形成作業係設定前述第一 SiGe層之膜厚 更加薄於成爲藉由膜厚之增加來產生錯位而產生晶格鬆弛 之膜厚之臨界膜厚之2倍，前述第二層形成作業係以連續 之Ge組成比而重複地進行複數次之對於朝向表面而逐漸 地增加Ge組成比之SiGe傾斜組成層來進行磊晶成長之作 業以及藉由前述傾斜組成層之最後Ge組成比而在傾斜組 成層上來對於SiGe —定組成層進行磊晶成長之作業，形 成Ge組成比沿著成膜方向具有傾斜而呈階梯狀地進行變 化之前述第二SiGe層之薄膜，使得該第二SiGe層下面之 G e組成比，更加低於前述第一S i G e層之G e組成比之層 中之最大値。 7·如申請專利範圍第6項所記載之半導體基板之製造 方法，其中，前述第一層形成作業係前述第一 SiGe層之 Ge組成比X成爲一定，使得第一SiGe層，成爲滿足下列 關係式： (4) (4)1222106 t〇 ( nm) = ( 1.9xl〇*3/ ε ( x) 2) · In ( tc/ 〇.4) ε (x) = ^ a〇 + 〇.200326x + 0.026 1 74x2/ a〇 ) a〇= 0.5 43 nm ( aG係Si之格子常數） 之臨界膜厚te之2倍未滿之厚度。 8 ·如申請專利範圍第6或7項所記載之半導體基板之 製造方法’其中’前述第一 Si Ge層係Ge組成比X成爲 〇·〇5以上及0.3以下。 9· 一種半導體基板之製造方法，係在si基板上透過 SiGe層而形成歪斜Si層的半導體基板之製造方法，其特 徵爲： 在藉由如申請專利範圍第6至8項所記載的任一項之 半導體基板之製造方法所製作之半導體基板之前述第二 SiGe層上，直接或透過其他SiGe層，而對於前述歪斜si 層，進行磊晶成長。 10·—種半導體基板，其特徵爲： 具有Si基板、該Si基板上之第一 SiGe層以及直接 或透過Si層而配置在該第一SiGe層上之第二SiGe層， 前述第一 SiGe層係成爲更加薄於藉由膜厚之增加來 產生錯位而產生晶格鬆弛之膜厚之臨界膜厚之2倍之膜厚 前述第二SiGe層係具有使得其Ge組成比至少在和前 述第一 SiGe層或前述Si間之接觸面而更加低於第一 SiGe層之Ge組成比之層中最大値並且至少一部分之Ge -4- (5)1222106 組成比朝向表面而遂漸地增加的傾斜組成區域， _ ή $ if胃利範圍第1項所記載之半導體基板之製 造方法而進行製作。 11 ·如申請專利範圍第1 〇項所記載之半導體基板，其 中’前述第一SiGe層，係Ge組成比χ成爲一定，成爲滿 足下列關係式：5. A method for manufacturing a semiconductor substrate is a method for manufacturing a semiconductor substrate in which a skewed Si layer is formed through a SiGe layer on a Si substrate, and is characterized by: On the aforementioned second SiGe layer of the semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to one item, epitaxial growth is performed on the aforementioned skewed Si layer directly or through other SiGe layers. 6 · A method for manufacturing a semiconductor substrate, which is a method for manufacturing a semiconductor substrate on a Si substrate and epitaxially grows a SiGe layer, which is characterized in that the method includes: epitaxially forming a first SiGe layer on the Si substrate; Growth -2- (3) (3) 1222106 First layer formation operation; on the first SiGe layer, the second layer formation of epitaxial growth of the second SiGe layer is performed directly or through the epitaxially grown Si layer. Operation; during or after the formation of the SiGe layer by epitaxial growth, a heat treatment operation in which heat treatment is applied at a temperature exceeding the epitaxial growth temperature; and after the SiGe layer is formed, it is removed by honing The honing operation of the surface unevenness produced by the heat treatment; in addition, the first layer forming operation is to set the film thickness of the first SiGe layer to be thinner than to increase the film thickness to cause dislocation and lattice relaxation. The film thickness is twice the critical film thickness. The aforementioned second layer forming operation is repeated repeatedly with a continuous Ge composition ratio, and SiGe gradually increases the Ge composition ratio toward the surface. An epitaxial growth operation is performed with an oblique composition layer and an epitaxial growth operation is performed on a tilted composition layer for a SiGe-constant composition layer by using the last Ge composition ratio of the aforementioned inclined composition layer to form a Ge composition ratio along the film formation direction. The thin film having the second SiGe layer inclined and stepwise changed makes the G e composition ratio below the second SiGe layer even lower than the G e composition ratio of the first S i G e layer The biggest 値. 7. The method for manufacturing a semiconductor substrate as described in item 6 of the scope of the patent application, wherein the first layer forming operation is a constant Ge composition ratio X of the first SiGe layer, so that the first SiGe layer satisfies the following relationship Formula: (4) (4) 1222106 t〇 (nm) = (1.9xl〇 * 3 / ε (x) 2) · In (tc / 〇.4) ε (x) = ^ a〇 + 〇.200326x + 0.026 1 74x2 / a〇) a〇 = 0.5 43 nm (thickness constant of aG-based Si) is less than twice the critical film thickness te. 8. The method for manufacturing a semiconductor substrate according to item 6 or 7 of the scope of the patent application, wherein the aforementioned first Si Ge layer system has a Ge composition ratio X of not less than 0.05 and not more than 0.3. 9. A method for manufacturing a semiconductor substrate, which is a method for manufacturing a semiconductor substrate having a skewed Si layer through a SiGe layer on a si substrate, characterized by: In the semiconductor substrate manufacturing method described above, the epitaxial growth is performed on the aforementioned second SiGe layer of the semiconductor substrate, directly or through another SiGe layer, and for the aforementioned skewed si layer. 10 · A semiconductor substrate, comprising: a Si substrate, a first SiGe layer on the Si substrate, and a second SiGe layer disposed on the first SiGe layer directly or through the Si layer, the aforementioned first SiGe layer The thickness of the second SiGe layer is thinner than the critical film thickness which is twice as critical as the film thickness caused by the increase in film thickness to cause dislocation and lattice relaxation. The SiGe layer or the contact surface between Si is lower than the largest Ge in the first SiGe layer, and at least a portion of the Ge -4- (5) 1222106 composition ratio gradually increases toward the surface. Area, which is manufactured by the method for manufacturing a semiconductor substrate as described in item 1 of the stomach range. 11. The semiconductor substrate as described in Item 10 of the scope of patent application, wherein the aforementioned first SiGe layer has a fixed Ge composition ratio χ and satisfies the following relational formula: nm ) = ( 1 .9χΐ 〇*3/ ε ( χ ) 2 ) · In ( tc/ 0.4 ) (x) = (a〇+ 0.200326x+ 0.026174x2/a〇) =〇·543 ηηι ( aG係Si之格子常數） 之臨界膜厚te之2倍未滿之厚度。 1 2 .如申請專利範圍第1 〇或1 1項所記載之半導體基 板’其中’前述第〜SiGe層係Ge組成比x成爲〇.05以 上及0.3以下。nm) = (1.9χΐ 〇 * 3 / ε (χ) 2) In (tc / 0.4) (x) = (a〇 + 0.200326x + 0.026174x2 / a〇) = 〇 · 543 ηηι (aG system of Si Lattice constant) is less than twice the critical film thickness te. 12. The semiconductor substrate according to item 10 or 11 of the scope of the patent application, wherein the aforementioned SiGe layer system Ge composition ratio x is equal to or more than 0.05 and equal to or less than 0.3. 1 3 ·如申請專利範圍第1 〇或1 1項所記載之半導體基 板，其中，目U述第二SiGe層係直接配置在前述第一SiGe 層上，並且’成爲層整體之Ge組成比朝向表面而逐漸增 加的傾斜組成層。 14·一種半導體基板，其特徵爲： 具有直接或透過其他SiGe層而配置在藉由如申請專 利範圍第1 〇至1 3項所記載的任一項之半導體基板之前述 第二SiGe層上之歪斜Si層。 15· —種半導體基板，其特徵爲： -5- (6) (6)1222106 具有Si基板、該Si基板上之第一 SiGe層以及直接 或透過Si層而配置在該第一 SiGe層上之第二Si Ge層， 前述第一 SiGe層係成爲更加薄於藉由膜厚之增加來 產生錯位而產生晶格鬆弛之膜厚之臨界膜厚之2倍之膜厚 前述第二SiGe層係交互地且以連續之Ge組成比，來 構成朝向表面而使得Ge組成比逐漸地增加之SiGe傾斜組 成層和以該傾斜組成層上面之Ge組成比而配置在傾斜組 成層上之SiGe —定組成層，成爲複數層層積狀態，前述 第二SiGe層下面之Ge組成比係構成爲更加低於前述第一 SiGe層之Ge組成比之層中最大値，藉由如申請專利範圍 第6項所記載之半導體基板之製造方法而進行製作。 1 6 ·如申請專利範圍第1 5項所記載之半導體基板，其 中，前述第一 SiGe層，係Ge組成比X成爲一定，成爲滿 足下列關係式：1 3 · The semiconductor substrate according to item 10 or 11 of the scope of patent application, wherein the second SiGe layer described above is directly disposed on the first SiGe layer, and the Ge composition ratio of the entire layer is oriented The surface gradually slopes up to form a layer. 14. A semiconductor substrate, comprising: a semiconductor substrate directly or through another SiGe layer; and disposed on the aforementioned second SiGe layer of the semiconductor substrate according to any one of claims 10 to 13 in the patent application scope. The Si layer is skewed. 15 · A semiconductor substrate, characterized in that: -5- (6) (6) 1222106 has a Si substrate, a first SiGe layer on the Si substrate, and a semiconductor substrate disposed on the first SiGe layer directly or through the Si layer. The second Si Ge layer, the aforementioned first SiGe layer becomes thinner than the film thickness which is twice the critical film thickness of the film thickness that causes the lattice to be dislocated by the increase in film thickness, and the second SiGe layer interacts A continuous Ge composition ratio is used to form a SiGe tilted composition layer facing the surface so that the Ge composition ratio gradually increases, and a SiGe-constant composition layer arranged on the tilted composition layer with the Ge composition ratio above the tilted composition layer. It becomes a state of being laminated in a plurality of layers. The Ge composition ratio under the aforementioned second SiGe layer is configured to be lower than the largest in the Ge composition ratio of the aforementioned first SiGe layer, as described in item 6 of the scope of patent application. It is manufactured by a method for manufacturing a semiconductor substrate. 16 · The semiconductor substrate according to item 15 of the scope of patent application, wherein the first SiGe layer has a constant Ge composition ratio X and satisfies the following relationship: tc ( nm ) = ( 1 .9x10°/ ε ( χ ) 2 ) · In ( tc/ 0.4 ) ε (x) = ( a〇 + 〇·200326χ + 0.026 1 74x2/ a〇 ) a0 =0.543nm(aG係Si之格子常數） 之臨界膜厚te之2倍未滿之厚度。 1 7 ·如申請專利範圍第1 5或1 6項所記載之半導體基 板，其中’前述第一 SiGe層係Ge組成比χ成爲〇.〇5以 上及〇 . 3以下。 -6- (7) (7)1222106 18. —種半導體基板，其特徵爲： 具有直接或透過其他SiGe層而配置在藉由如申請專 利範圍第1 5至1 7項所記載的任一項之半導體基板之前述 第二SiGe層上之歪斜Si層。 1 9.一種場效型電晶體之製造方法，係在SiGe層上之 進行磊晶成長之歪斜S i層而形成通道區域之場效型電晶 體之製造方法，其特徵爲： 在藉由如申請專利範圍第5或9項所記載之半導體基 板之製造方法所製作之半導體基板之前述歪斜Si層上， 形成前述通道區域。 20·—種場效型電晶體，係在siGe層上之進行磊晶成 長之歪斜Si層而形成通道區域之場效型電晶體，其特徵 爲· 藉由如申請專利範圍第1 9項所記載之場效型電晶體 之製造方法而進行製作。tc (nm) = (1.9x10 ° / ε (χ) 2) In (tc / 0.4) ε (x) = (a〇 + 〇200326χ + 0.026 1 74x2 / a〇) a0 = 0.543nm (aG It is a lattice constant of Si) and a thickness less than twice the critical film thickness te. [17] The semiconductor substrate according to item 15 or 16 in the scope of the patent application, wherein the aforementioned Ge composition ratio χ of the first SiGe layer system is equal to or greater than 0.05 and equal to or less than 0.3. -6- (7) (7) 1222106 18. A semiconductor substrate, characterized in that: it has a direct or through other SiGe layer and is arranged in any one of the items described in claims 15 to 17 A skewed Si layer on the aforementioned second SiGe layer of the semiconductor substrate. 1 9. A method for manufacturing a field-effect transistor, which is a method for manufacturing a field-effect transistor in which a channel region is formed by performing an epitaxial growth of a skewed Si layer on a SiGe layer, and is characterized by: The aforementioned channel region is formed on the aforementioned skewed Si layer of the semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate described in item 5 or 9 of the scope of application for a patent. 20 · —A field-effect transistor is a field-effect transistor which is formed on a siGe layer by epitaxial growth of a skewed Si layer to form a channel region. Its characteristics are as follows: It is produced by the manufacturing method of the field effect transistor described.
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