TWI220065B - Method for preventing hole and electron movement on NROM devices - Google Patents

Abstract

Nonvolatile memory devices, such as NROM devices that have an oxide-nitride-oxide (ONO) layer beneath at least one word line structures, and methods for making same, are described. The ONO layer is formed on a substrate, followed by a patterned photoresist layer being formed on the ONO layer. The patterned photoresist layer then serves as an implanting mask to form at least one bit line in the substrate, followed by a material layer being formed on the substrate. The material layer is planarized until the photoresist layer is exposed, and the photoresist layer is then removed. A polymer layer is formed on exposed surfaces of the material layer, with the polymer layer serving as an etching mask to define the top oxide layer and the nitride layer of the ONO layer. The polymer layer and the material layer are then removed.

Description

1220065 五、發明說明（l) 發明所屬之技術領域 本發明是有關於一種非揮 法，且特別是有關於-種且古i 3己憶體几件及其製造方 憶體元件及其製造方法。，、有雙位兀記憶胞之非揮發性記 先前技術 非揮發性半導體印_ — 即使電源供應已消失儲：件t用以儲存程式化資料， 記憶體(_)係為其中1 /揮Λ枓二V消而唯讀 置，例如行動電話。處理數位設備以及手提式電子裝 一般唯讀記憶體元件係佑 每一記憶胞係包括-電晶^佈=複數個記憶胞陣列’而 一金屬氣化丰| 1曰-/、中，典型的電晶體係包括 中之資料位元或編碼係長時：的記憶胞電晶體 或電子特性中…Λ立儲存在每一記憶胞之物理 發性質可以說是儲存在 續忑隱體之非揮 取。 仔在°己隐體疋件中之資料僅可以被讀 已在：：中種？揮發性記憶體元件即氮化矽記憶體(nr〇m) 呓心：：；”矽記憶體較過去3〇年所發展的浮置閘極 抹的優點，其中浮置閉極記憶體例如是可 以及叮ϊϊ式之讀記憶體（epk〇m)、快閃記憶體（以3讣） ，可電除且可程式之唯讀記憶體（eeprom)，其中浮置閘 3己憶體係將電荷儲存在一導電浮置閘極中。 第6頁 8864twf.ptd 1220065 五、發明說明（2) =石夕記憶胞係包括兩位元記憶胞，其係 切—氧化柳0)介電層中。此氮化:記 =括一n型通道M0SFET元件’其中氮化石夕層係用來作 - - ；：b ：：：f ^ ^ 中口任何氧化層之損害而造成電子遂穿。 展的ί ΐ矽記憶體可以加進一標準CM0S製程中，其中0N0 i。而ί步驟係安排在場隔離結構之後但在間氧化步驟之 i5 亂矽記憶體的步驟通常對CMOS製程埶預算的 =很小。另夕卜，氮化石夕記憶胞通常係以通道孰電1异的 ^ - ^ ^ ^ ^ t ；,(ΤΕΗΗ) ^ ^方式抹除《而且，氮化矽記憶 ，存’其可使捕捉的電荷僅保留在注入點=局 進元件速可以提高元件之密度並增 氮η、體較浮置閉極記憶體可以提 叙點。其一，在氮化矽記憶體 |的 都可以較浮置閘極記憶體小3倍或以上。此以及^晶粒尺寸 憶體元件僅需少於6至8道的光罩製程，因此鼠化石夕5己声 較低，且其易與CMOS元件積體化。再去，^/、^耘複雜度 體之抹除啟始電壓低，因此氮化 於虱化矽記憶 產品。^，氮化梦記憶體元件卻存在有—問題，就= 8864twf.ptd 第7頁 U200651220065 V. Description of the invention (l) The technical field to which the invention belongs The present invention relates to a non-volatile method, and in particular, to several kinds of ancient and ancient i 3 memorable bodies and their memorizing body elements and methods . , Non-volatile memory with dual-bit memory cells Previous technology non-volatile semiconductor printing _ — Even if the power supply has disappeared Storage: Piece t is used to store programmatic data, and the memory (_) is 1 / Λ The second V is read-only, such as a mobile phone. Processing digital devices and portable electronic devices generally read-only memory components. Each memory cell line includes -Electron crystal ^ cloth = multiple memory cell arrays. And a metal gasification | 1 Yue-/, medium, typical The data crystal system includes the data bits or codes in the long-term: memory cell electric crystal or electronic characteristics ... The physical hair properties stored in each memory cell can be said to be non-volatile stored in the continuum. The data of the child in the hidden body file can only be read Already in :: Medium? Volatile memory elements are silicon nitride (nr0m) cores ::; "Silicon memory has advantages over the floating gate wiper developed in the past 30 years, where the floating closed-pole memory is, for example, Can read and read memory (epk〇m), flash memory (with 3 讣), programmable read-only memory (eeprom), in which the floating gate 3 Ji memory system will charge Stored in a conductive floating gate. Page 6 8864twf.ptd 1220065 V. Description of the invention (2) = Shi Xi memory cell line consists of two-element memory cells, which are cut-oxide willow 0) dielectric layer. This nitride: note = including an n-type channel M0SFET element 'where the nitride stone layer is used for--;; b ::: f ^ ^ damage caused by any oxide layer in the mouth and cause electrons to pass through. Silicon memory can be added to a standard CM0S process, where 0N0 i. The ί step is arranged after the field isolation structure but in the inter-oxidation step i5. The disordered silicon memory usually has a small budget = CMOS process. In addition, the memory cells of nitrided stones are usually connected in a different way ^-^ ^ ^ ^ t; (ΤΕΗΗ) ^ ^ In addition, the silicon nitride memory can save the trapped charge only at the injection point = localized device speed, which can increase the density of the device and increase the nitrogen η, which can be compared to the floating closed-pole memory. First, the silicon nitride memory can be three times or more smaller than the floating gate memory. This and the ^ memory size memory element only require less than 6 to 8 photomask processes, so the mouse Fossil Xi 5 has a low sound, and it is easy to integrate with CMOS elements. Then, the starting voltage of the ^ /, ^ complexity complexity is low, so it is nitrided to the siliconized silicon memory products. ^, Nitrogen There is a problem with the memory element of the dream memory, just = 8864twf.ptd Page 7 U20065

=”石夕記憶胞之間容易有橫向電洞, 子遷移之問題，特 電子遷移（又稱干 擾Γ之門部分熱製程之後，此種橫向電淚 俊）之問碭更容易發生。 且特：ί:η:種非揮發性記憶體及其製造方法， 法。氮化侧體元件及其改良的製造方 之間的電；二移方戈〜可以減少一氮化秒記憶胞中兩位元 移η、,： 洞遷移，此電子遷移及/或電洞遷 攄太^=干擾，此干擾特別會發生在部分熱製程之後。依 f 之目的，本發明將每一記憶胞中0N0堆疊結構之 :::層切開，以消除上述之一記憶胞中兩位元之間會產 法丨之問題。而1，本發明之方法可克服微影製程之限 ^而將0Ν0堆疊結構圖案化至〇· 15微米之尺寸。利用本發 月之方法可以使用紫外光波長以圖案化光阻層並製造此元 件’而且可以使形成之元件之尺寸小於紫外光波長。 依據本發明之目的，一種形成至少一非揮發性記憶體 疋件之方法包括提供一基底，其中基底上已形成有一捕捉 層以及一圖案化之光阻層；利用此光阻層為一植入罩幕以 形成至少一位元線；在光阻層之間形成一材料層；移除光 阻f ;在材料層之表面上形成一高分子材料層；以及利用 此兩分子材料層作為一姓刻罩幕以定義此捕捉層。 一 依據本發明之另一目的，一種形成一非揮發性記憶體 元件之方法包括在一基底上形成一捕捉層；在捕捉層上形 成一圖案化之光阻層；利用此光阻層為一植入罩幕進行一= "Shi Xi's memory cells are prone to lateral holes and sub-migration problems. The problem of special electron migration (also known as interference with the electrical process of the gate of Γ) is more likely to occur. And special : Ί: η: A kind of non-volatile memory and its manufacturing method, method. Electricity between nitriding side body element and its improved manufacture; two shifting squares ~ can reduce two bits in a nitriding second memory cell Element shift η, :: hole migration, this electron migration and / or hole migration is too ^ = interference, this interference will especially occur after some thermal processes. According to the purpose of f, the present invention stacks 0N0 in each memory cell Structure of the ::: layer is cut to eliminate the problem of the production method between two cells in one of the above memory cells. 1. The method of the present invention can overcome the limitation of the lithography process and pattern the ONO stack structure. Size to 0.15 micron. Using the method of the present month, the wavelength of ultraviolet light can be used to pattern the photoresist layer and the element can be manufactured ', and the size of the formed element can be smaller than the wavelength of ultraviolet light. According to the object of the present invention, a Forms at least one non-volatile memory The method includes providing a substrate, wherein a capture layer and a patterned photoresist layer have been formed on the substrate; using the photoresist layer as an implant mask to form at least one bit line; forming between the photoresist layers A material layer; removing the photoresist f; forming a polymer material layer on the surface of the material layer; and using the two molecular material layers as a mask to define the capture layer. Another object according to the present invention A method for forming a non-volatile memory element includes forming a capture layer on a substrate; forming a patterned photoresist layer on the capture layer; and using the photoresist layer as an implant mask to perform a

8864twf.ptd 第8頁 1^20065 五、發明說明（4) ^ I植入步驟以形成至少一位元線；在光阻層與捕捉層之 銘卜Ϊ形成#料層’平坦化此材料層以暴露出光阻層； ，：；：層；在材料層之表面上形成-高分子材料層：利 成=二子材料層作為一蝕刻罩幕圖案化此捕捉層，以形 ^長條狀捕捉層；移除材料層以及高分子材料層； 在至少一長條狀捕捉層上形成至少一字元線。 此捕捉層包括一 — m au m, ^ ^ % 乳化層、一氮化矽層以及一第二 成〇N〇V疊结構。一上心石夕層以及第二氧化層係構 抗反射層(職）。另外，在材料層表面 上形成回刀子材料層之方法係以一 至少-長條狀捕二卜；i少一位元線包括複數條位元線， 字元線包複數條長條狀捕捉層，且至少- -非一種在一半導體基底上形成 半導體基底上形成：捕捉声法：括J供-半導體基底;在 :上形成複數個長條狀之 及捕捉層之表面上形成一材料層、复平；=之光阻層以 =層；移除光阻層；在材；層：；：==:= 材料層；回钱刻部分捕捉層以形成複數個長條狀捕二； 8864twf.ptd 第9頁 五、發明說明（5) 移除二料層以及高分子材料層；以及形成複數條字元線。 數個ίΐί:植入步驟之後’亦可以將捕捉層圖案化成複 f個雙重長條狀捕捉層。此捕捉層包括-第一氧化層、一 =化石夕層以及「第二氧化層’以構成一 _堆疊結構，其 务述法中在成長第二氧化層時可能會消耗部分氮 # # = /高分子材料層係以一電衆增益型化學氣相 ΐ Λ /巍岁丨置)莫所形成，且所形成之高分子材料層係用來 做為一触刻Μ以在#刻製冑中保護位於其底了之膜層。 本遙：ΐ ί發Γ之目的，一種非揮發性記憶體元件包括-Πΐίί 半導體基底中已植入有複數條位元線。 :揮’“ 5己憶體兀件包括複數個捕捉塊狀結構以及 在對f於複數個捕捉塊狀結構上之複數條字元、線。 位元線之間的捕捉塊狀結構在字元線的方向係彼此分開 的，且每一捕捉塊狀結構在一記憶胞中係對應一單一位 兀。而此複數個捕捉塊狀結構可以包括一氧化層以及一 化砍層。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合 二 細說明如下： ^ U + 實施方式 在本實施例之圖示中 同的或相似之部分。而且 尺寸。在此為了方便以及 ’相同或相似的 ’圖示皆為示意 清楚說明，所揭 參考標號係指相 圖’其並非實際 露的直接項目， 122U065 五、發明說明（6) 下、底下、前面以及德而 而直 接項目並非構成本發明之限：依照圖示之繪示說明。 雖然在本貫施例中你 ^ ， 非用以限定本發明。以下、4:寺疋圖示以詳細說明之，但並 施例，但在不脫離本發明：==然:、為-較佳實 更動_，因此本發0 =:範圍内，當可作些許之 把圍所界疋者為準。例如熟_元件之技術者；：：： 用於取代非揮發性記憶體元件者^以將其 以及EEPROM等浮置閘極技術。 丨、閃圮fe體 在此所描述之製程步驟或結構並 造圓f憶體元件。本發明可以與許多習知已在 在本發中。 般已在貫订之製程步驟亦包括 請參照第1圖’其綠示係為複數條位 ί條，元線21垂直配置之複數條字元線23。而位元線21\ 字^線23可以製作在—半導體基底（摻雜之…上，並良且其 通^沿者CMOS το件製作並與CM〇s元件製作在相同一晶片 i化矽記憶體（nrom)記憶胞的製作可用以應用一標準 CMOS製程，其包括場隔離製程以及離子掺雜步驟。 在A-A’切線25的部分，其延伸之方向係垂直位元線以 ^人切線25所在之位置並未定義有字元線23，而4_厂切 線25的部分係對應於第2圖至第9圖以及第14與第15圖之剖 面圖。同樣的’在B-B’切線27的部分，其延^之方向係垂 直字元線23且B-B，切線27所在之位置並未定義有位元線 8864twf.ptd 第11頁 1220065 五、發明說明（7) =而β-β’切線27的部分係對應於第11與第12圖之剖面 2照第2圖，一捕捉層係沈積及/或成長在一基底％ 上，:中捕捉層較佳的是包括一第一氧化層3〇、一氮化矽 f 32以及—第二氧化層34。雖然基底36較佳的是包括一石夕 基底，但是基底36亦可以使用其他習知任何適 g質取代，例如氮化鍺(GaN)、神化鍺(GaAs)等用其之他丰材導體 以游ί姑f化層30以及第二氧化層34之厚度必須足夠厚， 之門產* ^ =電子在氮化梦層32以及位元線21或字元線23 此情形可能發生在第-氧化層30以及 一氧化# 3曰0之A i ^小於5〇埃的時候。因此較佳的是，第 層32之；产沈積厚度約為5〇埃至100埃，氮化石夕 5〇埃= 度:為35埃至75埃，而第 積的係成長在氮切層32上而並非以沈 分氮化矽層32合被洁缸，n i 4形成乳化層之過程中部 埃的氧彳b #合i & 1 & 肖耗之速率大致是每形成2 #旧虱化矽會湞耗1埃的氮化 γ 入 度較佳的是35埃至75埃，14為第因此，氮化石夕層32之厚 半。例如倘若欲形成第二氧層34厚度的- 氮化矽層32之厚度為50垃4之厚度係為15〇埃，而 度必須是125埃（50埃+ 75埃）Y虱化矽層32 一開始沈積之厚 第一氧化層30、氮化石夕層32以及第二氧化層34係定義 8864twf.ptd 麵 第12頁 12200658864twf.ptd Page 8 1 ^ 20065 V. Description of the invention (4) ^ I implantation step to form at least one bit line; forming a #material layer in the inscription of the photoresist layer and the capture layer to flatten this material layer The photoresist layer is exposed to form a polymer layer on the surface of the material layer-a polymer material layer: Licheng = two sub-material layers as an etching mask to pattern the capture layer to form a long capture layer Removing the material layer and the polymer material layer; forming at least one word line on the at least one elongated capture layer. This capture layer includes a maum, ^^% emulsified layer, a silicon nitride layer, and a second 0N0V stack structure. An upper core stone layer and a second oxide layer structure an anti-reflective layer (position). In addition, the method for forming the material layer of the return knife on the surface of the material layer is to capture at least one-long stripe; i. One bit line at least includes a plurality of bit lines, and the character line includes a plurality of strip-shaped capture layers. And at least-not a semiconductor substrate formed on a semiconductor substrate, formed by: capturing acoustic method: including a semiconductor substrate; forming a material layer on the surface of a plurality of long strips and a capture layer, Fuping; = the photoresist layer to = layer; remove the photoresist layer; in the material; layer:;: ==: = material layer; back to the money engraved part of the capture layer to form a plurality of strip-shaped capture two; 8864twf. ptd page 9 5. Description of the invention (5) Remove the second material layer and the polymer material layer; and form a plurality of character lines. After several implantation steps, the capture layer can also be patterned into f double long strip-shaped capture layers. This capture layer includes-a first oxide layer, a = fossil evening layer, and a "second oxide layer" to form a stacked structure. In the method described, some nitrogen may be consumed when the second oxide layer is grown # # = / The polymer material layer is formed by an electric mass gain type chemical vapor phase (Λ / 岁); and the formed polymer material layer is used as a one-touch engraving M in # 刻制 胄Protect the membrane layer on the bottom of it. Ben Yao: For the purpose of ί ί Γ, a non-volatile memory element includes -Πΐί ί a number of bit lines have been implanted in the semiconductor substrate. The element includes a plurality of capturing block structures and a plurality of characters and lines on the plurality of capturing block structures. The capture block structures between the bit lines are separated from each other in the direction of the word lines, and each capture block structure corresponds to a single bit in a memory cell. The plurality of capturing block structures may include an oxide layer and a chemical cutting layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and a detailed description is given as follows: ^ U + The embodiment is the same in the diagram of this embodiment. Or similar. And size. For the sake of convenience and the “identical or similar” illustrations here are schematic and clear explanations, the reference numerals disclosed refer to the phase diagrams, which are not directly exposed items. 122U065 V. Description of the invention (6) Bottom, bottom, front and Virtue and direct items do not constitute a limitation of the present invention: follow the illustrated description of the diagram. Although in the present embodiment, you are not used to limit the present invention. The following, 4: The temple icon is illustrated in detail, but it is an example, but it does not depart from the present invention: == 然:,-is better to change _, so the present 0 =: range, when it can be done The slightest rule is the one who surrounds the perimeter. For example, those who are familiar with device technology ::: Used to replace non-volatile memory devices ^ to use it and floating gate technology such as EEPROM.丨, flash 体 fe body The process steps or structures described here and round f memory components. The present invention is compatible with many known aspects in the present invention. Generally, the process steps that have been carried out also include referring to FIG. 1 '. The green display is a plurality of bits, and the plurality of character lines 23 are vertically arranged in the yuan line 21. The bit line 21 \ word ^ line 23 can be fabricated on a semiconductor substrate (doped ...), and it is made of CMOS το pieces and is fabricated on the same chip as the CMOS memory. The fabrication of nrom memory cells can be applied to a standard CMOS process, which includes a field isolation process and an ion doping step. In the AA 'tangent line 25, the direction of its extension is the vertical bit line and the tangent line. The character line 23 is not defined at the position of 25, and the part of 4_factory tangent line 25 corresponds to the cross-sectional views of FIGS. 2 to 9 and 14 and 15. The same 'in B-B' The direction of the tangent line 27 is the vertical character line 23 and BB. There is no bit line defined at the position of the tangent line 8864twf.ptd Page 11 1220065 V. Description of the invention (7) = and β-β The part of the tangent line 27 corresponds to the cross section of Figs. 11 and 12. According to Fig. 2, a capture layer is deposited and / or grown on a substrate%. The middle capture layer preferably includes a first oxide. Layer 30, a silicon nitride f 32, and a second oxide layer 34. Although the substrate 36 preferably includes a stone substrate, the substrate The base 36 may also be replaced with any other suitable material, such as germanium nitride (GaN), deuterated germanium (GaAs), etc., using other abundant material conductors to swim the formation layer 30 and the second oxide layer 34. The thickness must be thick enough, the gate production * ^ = electrons in the nitride nitride layer 32 and bit line 21 or word line 23 This situation may occur in the -th oxide layer 30 and the oxide # 3, 0 A i ^ is less than 50 Angstroms. Therefore, it is preferable that the first layer 32 has a thickness of about 50 Angstroms to 100 Angstroms, and nitride nitride 50 Angstroms = degrees: 35 Angstroms to 75 Angstroms. Growing on the nitrogen-cutting layer 32 instead of sinking the silicon nitride layer 32 and cleaning the cylinder, the oxygen atom in the middle of the process of forming the emulsified layer of ni 4b # 合 i & 1 & The rate of consumption is approximately every The formation of # 2 old lice silicon will consume 1 angstrom of nitrided γ. The degree of penetration is preferably 35 angstroms to 75 angstroms, 14 is the third, so the nitrided layer 32 is half thick. 34-thickness-the thickness of silicon nitride layer 32 is 50 Å, and the thickness is 150 Å, and the degree must be 125 Å (50 Å + 75 Å). Layer 30, nitride Xi oxide layer 32 and the second surface layer 34 on page system defined 8864twf.ptd 121220065

五、發明說明（8) 成0N0堆疊38。此0N0堆疊38之作用係將電荷捕捉於氮化矽 層32中，而第二氧化層34以及第一氧化層3〇係作用於電 隔離。 之後，在0Ν0堆疊38上形成一光阻層4〇，其中，光阻 層40可以是一正光阻層或一負光阻層，接著以一般微影製 程而圖案化此光阻層40，以形成圖案化之光阻層，圖案化 之光阻層係往紙面的方向延伸，如第2圖所示。如一般習 知之方法，首先將一光阻層旋轉塗佈在晶圓上，之後"將晶 圓放置在一步進機（圖案化晶圓之微影工具）中，之後將2 圓與一光罩對準，再將其暴露在一紫外光中。此光罩之$ 寸可月b僅月匕覆蓋部分晶圓’因此晶圓在步進機中需歷經多 次步驟，意即逐一將晶圓的每一部分進行曝光，直到整個 晶圓都被紫外光曝光到。之後，將晶圓置放在一化學槽中 以溶解被紫外光曝光之光阻層，之後便可以形成具有特定 圖案之圖案化光阻層4 0。在此係利用習知微影製程，其係 以248nm之曝光波長進行曝光，而所形成之光阻層4〇之間” 隙約為1 3 0 0埃至3 0 0 0埃。 0 請參照第3圖，利用一離子植入製程以將一摻雜物“ 植入於暴露的基底36中’其中摻雜物43例如石申或鱗，而形 成源極以及没極或是複數個位元線2 1。此離子植入步驟會 通過0N0堆疊38，因此0N0堆疊38可提供一表面以使植^二 離子可以不需隨其底層之基底晶格結構而植入，因此可避 免離子產生通道現象（Ion Channeling)。 請參照第4圖，一材料層45係形成在光阻層4〇以及〇N〇V. Description of the invention (8) Stack 38 into 0N0. The ONO stack 38 functions to trap charges in the silicon nitride layer 32, and the second oxide layer 34 and the first oxide layer 30 function to electrically isolate. After that, a photoresist layer 40 is formed on the ON0 stack 38. The photoresist layer 40 may be a positive photoresist layer or a negative photoresist layer, and then the photoresist layer 40 is patterned by a general lithography process. A patterned photoresist layer is formed, and the patterned photoresist layer extends toward the paper surface, as shown in FIG. 2. As is generally known, a photoresist layer is first spin-coated on the wafer, and then the wafer is placed in a stepper (patterning tool for patterning wafers), and then 2 circles and a light are applied. The mask is aligned and exposed to ultraviolet light. The $ inch of this mask can cover only part of the wafer. Therefore, the wafer needs to go through multiple steps in the stepper, which means that each part of the wafer is exposed one by one until the entire wafer is exposed to ultraviolet light. Light is exposed. After that, the wafer is placed in a chemical bath to dissolve the photoresist layer exposed to ultraviolet light, and then a patterned photoresist layer 40 having a specific pattern can be formed. Here, a conventional lithography process is used, which is performed at an exposure wavelength of 248 nm, and the gap between the photoresist layers 40 formed is about 1 300 angstroms to 3 0 0 angstroms. 0 Please refer to In FIG. 3, an ion implantation process is used to implant a dopant into the exposed substrate 36, where the dopant 43 such as Shishen or scales forms a source and an electrode or multiple bits. Line 2 1. This ion implantation step will pass through the 0N0 stack 38, so the 0N0 stack 38 can provide a surface so that the implanted ions can be implanted without following the underlying lattice structure of the substrate, thus avoiding the ion channeling phenomenon (Ion Channeling ). Referring to FIG. 4, a material layer 45 is formed on the photoresist layer 40 and 0N.

!22〇〇65! 22〇〇65

隹疊38之表面上。此材料層45例如是一有機材質之底部抗 反射層（BARC)。通常BARC在圖案化製程中係配置在光阻層 ，底下，用以吸收大部分穿透光阻層的曝光光線，藉以^ 二反射凹痕、駐波效應以及光散射情形。然而，在本發明 ，BARC層並非用來促進圖案化製程之用。此barc層係形 成在光阻層40以及0N0堆疊38上，且其厚度足夠厚以使其v 具有一平坦之表面，例如BARC層係延伸至光阻層上方並 ^具有一平坦之表面，且其對光阻層4〇並不會有不良之影 A *、藍之明參照第5圖，平坦化材料層4 5直到光阻層4 〇 :二出來’其中平坦化材料層45之方法例如是進 剡製程。 μ挪 堉爹照 料層4 5。在 4 0，只要不 光阻層4 0可 (全部）之光 料層4 5移除 光阻層4 0可 請參照 材料層4 7。 利用一電漿 子材料層47 申請之申請 第6圖’選擇性的移除光阻層4〇，而保留下材 此丨不同的製程步驟亦可以進行以移除光阻層 會對材料層4 5之結構或組成有不良之影響。此 以藉由一選擇性濕式蝕刻製程以移除一特定量 阻層40，而且並不會將一特定量之欲保留之# 。在本實施例中，材料層45係為一BARC層，而 ，藉由一曝光製程以及一顯影製程以移除之。 第7圖，在暴露的材料層45表面上形成高分子 在本實施例中，形成高分子材料層47之方法 增益型化學氣相沈積法（pECVD)。而形成高分” 之方法及裝置可以參考於20 0 1年10月18日门提7 案Ν〇· 09/978,546、於2〇〇2年5月13日提出申The stack 38 is on the surface. The material layer 45 is, for example, a bottom anti-reflection layer (BARC) made of organic material. Generally, BARC is arranged in the photoresist layer during the patterning process. Under the barc, it is used to absorb most of the exposure light that penetrates the photoresist layer, so as to reflect the dimples, standing wave effects, and light scattering. However, in the present invention, the BARC layer is not used to facilitate the patterning process. The barc layer is formed on the photoresist layer 40 and the ONO stack 38, and is thick enough so that v has a flat surface. For example, the BARC layer extends above the photoresist layer and has a flat surface, and The photoresist layer 40 does not have a bad shadow A *, and the blue light refers to FIG. 5 to planarize the material layer 45 until the photoresist layer 40: two out. The method of planarizing the material layer 45 is, for example, It's a process. μ shift the care layer 4 5. At 40, as long as the photoresist layer 40 can be removed (all), the photoresist layer 4 5 can be removed. Please refer to the material layer 47. Using a plasma material layer 47, the application of FIG. 6 'selectively removes the photoresist layer 40, while retaining the underlying material. Different process steps can also be performed to remove the photoresist layer on the material layer 4 The structure or composition of 5 has an adverse effect. This is to remove a specific amount of the resist layer 40 through a selective wet etching process, and not to keep a specific amount of #. In this embodiment, the material layer 45 is a BARC layer, and is removed by an exposure process and a development process. In Fig. 7, a polymer is formed on the surface of the exposed material layer 45. In this embodiment, a method of forming a polymer material layer 47 is a gain type chemical vapor deposition (pECVD) method. The method and device for forming high scores can refer to the case No. 07/09 / 978,546 on October 18, 2001, and file on May 13, 2002.

1220065 五、發明說明（10) 請之申請案1 0/1 45, 203以及於2002年6月24日提出 :請案^0^ 78,795。在本實施例中，高分子材料層〇之之 質包括碳氟化合物，而且形成於材料層45頂部之高分子 係為0埃至1〇00埃’形成於材料層45側邊之高 厚度係為5〇0埃至1 0 0 0埃。雖然形成在頂部 與形成在側邊之厚度可以相對改變，但是其亦可： ί ^二之厚f。在1^，高分子材料層厚度的控制係為控制 ^^有一距離^“以及大於距離”…“之一距離^卜制 二V〇〇距垃離二51例如是1 300埃至3〇00埃，而距離”b"49例 材料屏4 R ^ 控制反應之沈積/蝕刻率，以在 ^之側土及頂部形成高分子材料層4 7。 其底=係用來做為一勉刻罩幕，以避免位於 過铲狡曰在後、戈第二氧化層34以氮化矽層32之回蝕刻 比：較;圭的Ϊ大S氧丨化層】“△氮化彻之银刻速率 :㈣速率比例較佳的是：b，二2 J第-氧化層】° 露出的第二备几旺〜 戈弟8圖所不，被暴 ❿ 被移除，而留二：2化矽層32在蝕刻製程中將完全 ^ 留下一暴路的第一氧化層30 〇 除。：將高分子材料層47以及材料層45移 之方式而將=，=以利用一灰化（Ashing)及/或溶劑溶解 知適用的清層47以及材料層45清除。而其他已 料層45。術亦可以用來移除高分子材料層47以及材 母圮憶胞54(虛線）之_〇堆疊38中之氮化矽 8864twf,ptd 第15頁 1220065 五、發明說明（li) ---- 層32係分開而形成兩個分離的位元，如第一位元56以及第 二位元5 8。 严因此’ 0N0堆疊38係圖案化成複數個長條狀之氧化矽-氮化矽（0N)層（例如是長條狀捕捉層），其係位於第一氧化 層3 0上。请參照第1 〇圖之立體圖，每一長條狀之〇N層6 〇係 位於一對應之位元線2 1之上方並與對應之位元線2丨重疊。 因此複數條長條狀0N層6 0係形成並平行延伸在複數條位元 線2 1之上方。 在第11圖NR0M之剖面圖中，其係為第}圖中沿著B_B’ 之剖面，在一已存在之結構上沈積一多晶矽層並且形成複 數條子元線6 2。關於字元線6 2之形成步驟，包括一光阻之 應用、圖案化以及以標準微影技術之顯影，而形成複數個 延伸的光阻結構，之後此延伸的光阻結構係用於蝕刻多晶 矽層以形成複數條延伸閘極或字元線結構6 2。而字元線結 構62係配置在對應的長條狀on層60上，且長條狀0N層60係 以垂直字元線62之方向延伸。 請參照第1 2圖’複數個長條狀〇 N層6 0係钱刻成複數個 ON塊狀結構6 5。關於此蝕刻步驟，字元線62在蝕刻過程中 係做為一蝕刻罩幕以保護位於其底下之膜層。每一字元線 結構62係對應配置在複數個ON塊狀結構65之上方。 第13圖係為第12圖中NR0M元件之立體圖。位元線21所 延伸之方向係垂直於字元線6 2，且每一字元線以及對應的 兩位元線係構成一記憶胞，其中記憶胞係包含第一位元56 以及第二位元58。而在兩位元線21之間之ON塊狀結構係彼1220065 V. Description of the invention (10) The requested application is 1 0/1 45, 203 and was filed on June 24, 2002: Please file ^ 0 ^ 78,795. In this embodiment, the quality of the polymer material layer 0 includes fluorocarbons, and the polymer system formed on the top of the material layer 45 is 0 angstroms to 100 angstroms. It is 50,000 Angstroms to 100 Angstroms. Although the thickness formed at the top and the side can be relatively changed, it can also be: ί 二 之 厚 f. At 1 ^, the control of the thickness of the polymer material layer is to control ^^ a distance ^ "and greater than the distance"… "a distance ^ system two V〇〇 distance two 51 for example is 1 300 Angstroms to 3,000 The distance "b" of 49 cases of material screen 4 R ^ controls the deposition / etching rate of the reaction to form a polymer material layer 4 7 on the side soil and on the top. The bottom = is used as a mask to avoid etch back, the second oxide layer 34 and the silicon nitride layer 32 are etched back. Chemical layer] "△ The rate of silver etched by silver: The ratio of ㈣ rate is better: b, 2 2nd-oxide layer] ° The exposed second Beijiwang ~ Gedi 8 is not shown, was violent Is removed, leaving two: the silicon dioxide layer 32 will be completely removed during the etching process, leaving a blast of the first oxide layer 30 .: the polymer material layer 47 and the material layer 45 are moved = ， = It can be removed by using an ashing and / or solvent to dissolve the applicable clear layer 47 and material layer 45. The other material layers 45 can also be used to remove the polymer material layer 47 and the parent material.圮 Memory cell 54 (dashed line) _〇 Silicon nitride in stack 38 8864twf, ptd Page 15 1220065 V. Description of the invention (li) ---- The layer 32 is separated to form two separate bits, as shown in FIG. One bit 56 and the second bit 5 8. Yan therefore '0N0 stack 38 is patterned into a plurality of long strips of silicon oxide-silicon nitride (0N) layers (for example, long strip capture layers). On the first oxide layer 30. Please refer to the perspective view of FIG. 10, each of the strips of the OO layer 6 is located above a corresponding bit line 21 and corresponds to the corresponding bit line 2 丨Therefore, a plurality of strip-shaped 0N layers 6 0 are formed and extend in parallel above the plurality of bit lines 2 1. In the cross-sectional view of the NR0M in FIG. 11, they are along B_B ′ in FIG. In section, a polycrystalline silicon layer is deposited on an existing structure and a plurality of sub-element lines 62 are formed. With regard to the formation steps of the character line 62, including the application of a photoresist, patterning, and development using standard lithographic techniques, A plurality of extended photoresist structures are formed, and this extended photoresist structure is then used to etch the polycrystalline silicon layer to form a plurality of extended gate or word line structures 62. The word line structure 62 is arranged at the corresponding length. On the strip-shaped layer 60, and the long strip 0N layer 60 extends in the direction of the vertical word line 62. Please refer to FIG. 12 'multiple strips 0N layer 6 0 series is carved into a plurality of ON blocks状 结构 6 5. Regarding this etching step, the word line 62 is used as an etching mask during the etching process to ensure that The film layer underneath is protected. Each word line structure 62 is correspondingly arranged above a plurality of ON block structures 65. Fig. 13 is a perspective view of the NR0M element in Fig. 12. Bit line 21 extends The direction is perpendicular to the character line 62, and each character line and the corresponding two-bit line system constitute a memory cell, where the memory cell line includes a first bit 56 and a second bit 58. ON block structure between element lines 21

8864twf.ptd 第16頁 1 1220065 五、發明說明（12) 此分開來的（切開來）。 (如第H施例中，一_堆疊38係形成在-基底36上 德接著在〇N〇堆疊38上形成一光阻層40，之 條位开入法在暴露的基底36中植入砷或磷以形成複數 I Λ 1 (如第3圖所示）。繼之，請參照第1 4圖，進行 4步驟以移除部分第二氧化層34以及氮化矽層32。在 ，^蝕刻步驟中，可以利用先前所述之pEcvD以在光阻 i中二=ί Γ成一選擇性的高分子材料層，之後的#刻步 此選擇性的高分子材料層可以移除或留下。繼之，在 形成一材料層’例如是一職層。然後平坦化此材 到光阻層4〇暴露出來。並且移除光阻層4〇(以及保 留:來的選擇性高分子材料層）。之後進行一PECVD製程， =材料層45之表面上（以及在任何保留的高分子材料層 形成另一高分子材料層。接著回蝕刻暴露出之第二氧 ::34以及氮化矽層32 ’並且同時移除材料層“以及高分 子材料層，即形成本發明之雙重長條狀之⑽結構，如第15 圖所不。在此，每一單一記憶胞54 (虛線）係包含雙重長條 狀捕捉層，而此雙重長條狀捕捉層係用來形成一第一位元 56以及一第二位元58。 倘若有使用選擇性高分子材料層，所形成之雙重長條 狀0N結構將延伸過（重疊）位元線21，如第15圖所示。 第16圖係為第15圖中NR0M之立體圖。〇N〇堆疊38可分 成複數個雙重長條狀ON結構60。每一長條狀⑽係以平行位 兀線2 1之方向配置。請參照第丨7圖，將一多晶矽層圖案化 Η 8864twf.ptd 第17頁 1220065 五、發明說明（13) 以成複數條字 係垂直於位元 及氮化秒層3 2 0N塊狀結構6 5 塊狀結構係彼 塊狀結構6 5， 位元線以及一 在本發明 來或切開來的 記憶體元件就 施例揭露如上 藝者，在不脫 動與潤飾，因 圍所界定者為 元線結構62，其中字 線21。之後回蝕刻暴 ，以使複數個雙重長 。而在位元線2 1之間 此分開的。每一記憶 每一0N塊狀結構65係 字元線之間。 中，母一記憶胞5 4中 ，因此，本發明以現 可避免干擾之問題。 ’然其並非用以限定 離本發明之精神和範 此本發明之保護範 準。 _ 元線結構62延伸之方向 露出的第二氧化層34以 條狀0N層60形成複數個 並延伸字元線方向之0N 胞54 (虛線）係包括二on 為一位元，其係位於兩 之氮化矽層32係分離開 今NR0M製程製作氮化矽 雖然本發明已以較佳實 本發明，任何熟習此技 圍内，當可作些許之更 當視後附之申請專利範 1220065 圖式簡單說明 圖武簡單說明 第1圖為字元線與位元線形成後之一氮化矽記憶體半 導體元件之示意圖； 第2圖是氮化矽記憶體半導體元件在一中間製程步驟 之剖面示意圖； 第3圖是第2圖中一離子植入步驟之後之剖面示意圖； 第4圖是第3圖中外加一材料層之剖面示意圖； 第5圖是第4圖中一平坦化步驟之後之剖面示意圖； 第6圖是第5圖中移除所有光阻層後之剖面示意圖； 第7圖是第6圖中外加一高分子材料層之剖面示意圖； 第8圖是第7圖中一蝕刻製程步驟之後之剖面示意圖； 第9圖是第8圖中移除高分子材料層以及材料層之後之 剖面示意圖； 第1 0圖是與第9圖相同製程步驟之氮化矽記憶體之立 體圖； 第11圖是氮化矽記憶體元件於一中間製程步驟之剖面 示意圖，其係與第2圖至第9圖之切面垂直； 第1 2圖是第11圖之氮化矽記憶體元件於一蝕刻製程步 驟之後之剖面示意圖； 第1 3圖是與第1 2圖相同製程步驟之氮化矽記憶體之立 體圖； 第1 4圖是第3圖之氮化矽記憶體元件於一蝕刻製程步 驟之後之剖面不意圖， 第1 5圖是另一種氮化矽記憶體元件在一中間製程步驟8864twf.ptd Page 16 1 1220065 V. Description of the invention (12) This is separated (cut out). (As in the H-th embodiment, a stack 38 is formed on the substrate 36, and then a photoresist layer 40 is formed on the ONO stack 38. The strip opening method implants arsenic in the exposed substrate 36. Or phosphorus to form a plurality of I Λ 1 (as shown in FIG. 3). Then, referring to FIG. 14, perform 4 steps to remove a portion of the second oxide layer 34 and the silicon nitride layer 32. At this time, etch In the step, the previously described pEcvD can be used to form a selective polymer material layer in the photoresist i, and the subsequent # 刻 步 this selective polymer material layer can be removed or left. In other words, a material layer is formed, for example, a functional layer. The material is then planarized to the photoresist layer 40 to be exposed. The photoresist layer 40 is removed (and a selective polymer material layer is retained). Afterwards, a PECVD process is performed on the surface of material layer 45 (and another polymer material layer is formed on any remaining polymer material layer. Then the exposed second oxygen :: 34 and silicon nitride layer 32 are etched back. And the material layer and the polymer material layer are removed at the same time, thus forming a double long stripe structure of the present invention. As shown in Figure 15. Here, each single memory cell 54 (dotted line) includes a double strip capture layer, and the double strip capture layer is used to form a first bit 56 and a first bit. Binary bit 58. If a selective polymer material layer is used, the formed double long strip-shaped 0N structure will extend (overlap) the bit line 21, as shown in Fig. 15. Fig. 16 is shown in Fig. 15 A three-dimensional view of the NR0M. The OONO stack 38 can be divided into a plurality of double strip-shaped ON structures 60. Each strip-shaped structure is arranged in the direction of parallel lines 21. Please refer to FIG. 7 for a polycrystalline silicon Layer patterning 8864twf.ptd Page 17 1220065 V. Description of the invention (13) A plurality of characters are perpendicular to the bit and the nitrided layer 3 2 0N block structure 6 5 Block structure is a block structure 6 5. The bit line and a memory element that came or cut in the present invention will be disclosed as an example in the above example. Without moving or retouching, the line defined by the surrounding is the line structure 62, of which the word line 21. Etching back to make a plurality of double long. And this is separated between the bit lines 2 1 each. Recall that each 0N block structure is between 65 series of character lines. In the mother and the memory cell 54, the present invention can avoid the problem of interference. However, it is not intended to limit the spirit and scope of the present invention. This protection standard of the present invention. _ The second oxide layer 34 exposed in the extending direction of the element line structure 62 forms a plurality of stripe 0N layers 60 and extends the 0N cells 54 (dashed lines) in the direction of the word line. One bit, which is located on the two silicon nitride layers. The 32 series is separated from the NR0M manufacturing process. Although the present invention has been implemented in the present invention, anyone familiar with this technology can take a closer look at it. The attached patent application patent 1220065 is a brief description of the figure and a brief description of the figure. Figure 1 is a schematic diagram of a silicon nitride memory semiconductor device after the formation of a word line and a bit line; Figure 2 is a silicon nitride memory semiconductor A schematic cross-sectional view of a component in an intermediate process step; FIG. 3 is a cross-sectional view after an ion implantation step in FIG. 2; FIG. 4 is a cross-sectional view of an additional material layer in FIG. 3; Section after a flattening step in the figure Schematic diagram; Figure 6 is a schematic diagram of the cross-section after removing all photoresist layers in Figure 5; Figure 7 is a schematic diagram of a cross-section of a polymer material layer in Figure 6; Figure 8 is an etching process in Figure 7 Figure 9 is a schematic cross-sectional view after the step; Figure 9 is a schematic cross-sectional view after the polymer material layer and the material layer are removed in Figure 8; Figure 10 is a perspective view of the silicon nitride memory with the same process steps as Figure 9; Figure 11 is a schematic cross-sectional view of a silicon nitride memory device in an intermediate process step, which is perpendicular to the cut planes of Figures 2 to 9; Figure 12 is a silicon nitride memory device of Figure 11 in an etch Sectional schematic diagram after the process steps; Figure 13 is a perspective view of the silicon nitride memory with the same process steps as Figure 12; Figure 14 is a silicon nitride memory device of Figure 3 after an etching process step The cross-section is not intended. Figure 15 is another intermediate process step of another silicon nitride memory device.

8864twf.ptd 第19頁 1220065 圖式簡單說明 之剖面示意圖； 第1 6圖是與第1 5圖相同製程步驟之氮化矽記憶體之立 體圖；以及 第1 7圖是第1 6圖之氮化矽記憶體元件形成字元線之後 之立體圖。 圖式之標示說明 21 :位元線 23 、6 2 :字元線 25 :A - A，之剖面 27 ·· B-B,之剖面 30 :第一氧化層 32 :氮化矽層 34 :第二氧化層 36 :基底 38 :ΟΝΟ堆疊 40 :光阻層 43 :植入離子 45 :材料層 47 :高分子材料層 49 :距離b 51 :距離a 54 :記憶胞 56 、58 :位元 60 :長條狀之ON層8864twf.ptd Page 19 1220065 Schematic cross-section schematic illustration; Figure 16 is a perspective view of silicon nitride memory with the same process steps as Figure 15; and Figure 17 is the nitride of Figure 16 A perspective view of a silicon memory device after forming a character line. Description of the drawings 21: bit line 23, 6 2: word line 25: A-A, section 27 · · BB, section 30: first oxide layer 32: silicon nitride layer 34: second oxide Layer 36: substrate 38: ONO stack 40: photoresist layer 43: implanted ions 45: material layer 47: polymer material layer 49: distance b 51: distance a 54: memory cell 56, 58: bit 60: long bar State layer

8864twf.ptd 第20頁 1220065 圖式簡單說明 65 : ON塊狀結構 1ϋ·ΙΙ 8864twf.ptd 第21頁8864twf.ptd page 20 1220065 Simple illustration 65: ON block structure 1ϋΙΙ 8864twf.ptd page 21

Claims (1)

12200651220065 六、申請專利範圍 1 · 一種非揮發性記憶體的製造方法，包括： 提供一基底，該基底上已形成有一捕捉層以及一圖案 化之光阻層； 以該光阻層為一植入罩幕以形成至少一位元線； 在該光阻層之間形成一材科層； 移除該光阻層； 在該材料層之表面上形成〆阿分子材料層；以及 以該高分子材料層為一#刻罩幕以定義該捕捉層。 2·如申請專利範圍第丨項所述之非揮發性記憶體的製 造方法，其中提供該基底之該夕驟更包括： 在該基底上形成一第一氧化層、一氮化矽層以及_第 二氧化層，以形成該捕捉層；以及 在該捕捉層上形成該光P旦層。 3·如申請專利範圍第1項所述之非揮發性記憶體的製 造方法’其中在該光阻層之間形成该材料層之該步驟更包 括·· ^ 在該光阻層以及該捕捉層之表面上形成一材料層；以 及 爭坦化該材料層以暴露出該光阻層。 4·如申請專利範圍第3項所述之非揮發性記憶體 造方法’其中· 該捕捉層包括一第一氧化層、一氮化矽層以及一 氧化層，而利用該高分子材料層做為一蝕刻罩二 義該第二氧化層以及該氮化矽層；以及 僅疋6. Scope of patent application1. A method for manufacturing non-volatile memory, comprising: providing a substrate on which a capture layer and a patterned photoresist layer have been formed; and using the photoresist layer as an implant cover Forming at least one bit line; forming a material layer between the photoresist layer; removing the photoresist layer; forming a molecular material layer on the surface of the material layer; and using the polymer material layer Carve a curtain for a # to define the capture layer. 2. The method for manufacturing a non-volatile memory according to item 丨 of the patent application scope, wherein the step of providing the substrate further comprises: forming a first oxide layer, a silicon nitride layer on the substrate, and A second oxide layer to form the capture layer; and forming the photo-denier layer on the capture layer. 3. The method for manufacturing a non-volatile memory according to item 1 of the scope of the patent application, wherein the step of forming the material layer between the photoresist layers further includes: ^ between the photoresist layer and the capture layer A material layer is formed on the surface; and the material layer is frankly exposed to expose the photoresist layer. 4. The non-volatile memory manufacturing method according to item 3 of the scope of the patent application, wherein the capture layer includes a first oxide layer, a silicon nitride layer, and an oxide layer, and the polymer material layer is used for the capture layer. Ambiguous the second oxide layer and the silicon nitride layer for an etch mask; and 1220065 六、申請專利蛇圍 該方法更包括移除該材料層以及該高分子材料層，以 及在該捕捉層上形成至少一字元線。 5 ·如申请專利範圍第4項所述之非揮發性記憶體的製 造方法，其中： 該至少一位元線包括複數條位元線； 定義該捕捉層包括將該捕捉層定義成複數個長條 捉層； 、 該至少一字元線包括複數條字元線；以及 形成該些字元線之該步驟包括將該些長條狀捕 成複數個捕捉塊狀結構。 9形 、6·如申請專利範圍第3項所述之非揮發性記憶體的 造方法，其中平坦化該材料層之該步驟包括進行一 製程。 w蚀刻 ^ 7·如申請專利範圍第1項所述之非揮發性記憶體的製 造方法’其中該材料層包括一底部抗反射層。 ^ 8 ·如申請專利範圍第1項所述之非揮發性記憶體的製 造方决’其中該高分子材料層係以一電漿增益型化 沈積法所形成。 乳相 ^ 9 ·如申請專利範圍第1項所述之非揮發性記憶體的製 在一半導體基底上形成一非揮發性記憶體的 種 Γ ^决，其中在形成該至少一位元線之後，接著將該4b姑 足曰^案化成複數個雙重長條狀捕捉層 ~ 方法 8864twf.ptd 體基底 ’包括 a)提供一半導 第23頁 ^200651220065 6. Applying for a patent for snake enclosure The method further includes removing the material layer and the polymer material layer, and forming at least one word line on the capture layer. 5. The method for manufacturing a non-volatile memory according to item 4 of the scope of patent application, wherein: the at least one bit line includes a plurality of bit lines; defining the capture layer includes defining the capture layer as a plurality of lengths Capture layers; the at least one character line includes a plurality of character lines; and the step of forming the character lines includes capturing the strips into a plurality of capture block structures. 9-shape, 6. The method of manufacturing a non-volatile memory as described in item 3 of the scope of patent application, wherein the step of planarizing the material layer includes performing a process. w Etching ^ 7. The method for manufacturing a non-volatile memory as described in item 1 of the scope of the patent application, wherein the material layer includes a bottom anti-reflection layer. ^ 8 The manufacturing method of the non-volatile memory according to item 1 of the scope of the patent application, wherein the polymer material layer is formed by a plasma gain type deposition method. Milk phase ^ 9 · The non-volatile memory as described in item 1 of the scope of the patent application is prepared on a semiconductor substrate to form a non-volatile memory Γ ^, wherein after forming the at least one bit line Then, the 4b case is converted into a plurality of double strip-shaped capture layers ~ Method 8864twf.ptd The body substrate 'includes a) provides half of the guide page 23 ^ 20065 、申請專利範圍 (b)在該半導體基底上形成一捕捉層； 、卜(c )在5亥捕捉層上應用以及圖案化一光阻層，以形成 $复數個長條狀之光阻層； (d )選擇性於该半導體基底中植入離子，以形成複數 條字元線； (e )在該圖案化之光阻層以及該捕捉層之表面上形成 一材料層； (f )平坦化該材料層以使該光阻層暴露出來； (g) 移除該光阻層； (h) 在該材料層之表面上形成一高分子材料層； (i )回钱刻部分該些捕捉層以形成複數個長條狀捕捉 層； (j )移除該材料層以及該高分子材料層；以及 (k)形成複數條字元線。 11 ·如申凊專利範圍第1 〇項所述之方法，其中選擇性 之植入離子之後，接著將該捕捉層圖案化而形成複數個雙 重長條狀捕捉層。 12 ·如申睛專利範圍第1 0項所述之方法，其中該捕捉 層依序包，一第一氧化層、一氮化矽層以及一第二氧化 層，且該第一氧化層、該氮化矽層以及該第二氧化層係構 成一 0N0堆疊層。 卜1 3.如申請專利範圍第1 2項所述之方法’其中該第二 氧化層係成長在該氮切層上，且該第二氧化層 程中會消耗部分氮化矽層。 ^2. The scope of the patent application (b) forming a capture layer on the semiconductor substrate; (b) applying and patterning a photoresist layer on the capture layer to form a plurality of long photoresist layers; (d) selectively implanting ions in the semiconductor substrate to form a plurality of word lines; (e) forming a material layer on the surface of the patterned photoresist layer and the capture layer; (f) planarization The material layer to expose the photoresist layer; (g) removing the photoresist layer; (h) forming a polymer material layer on the surface of the material layer; (i) engraving part of the capture layers To form a plurality of elongated capture layers; (j) remove the material layer and the polymer material layer; and (k) form a plurality of word lines. 11. The method as described in claim 10 of the patent application, wherein after selective ion implantation, the capture layer is then patterned to form a plurality of double-length strip-shaped capture layers. 12. The method as described in item 10 of the Shenjing patent scope, wherein the capture layer sequentially includes a first oxide layer, a silicon nitride layer, and a second oxide layer, and the first oxide layer, the The silicon nitride layer and the second oxide layer constitute a 0N0 stacked layer. [13] The method according to item 12 of the scope of the patent application, wherein the second oxide layer is grown on the nitrogen cut layer, and a part of the silicon nitride layer is consumed during the second oxide layer. ^ 1220065 六、申請專利範圍 1 4·如申請專利範圍第丨2項所述之方法’ 〃其中回蝕刻 部分該捕捉層係僅移除該第二氧化層以及該氮化矽層。 1 5 ·如申請專利範圍第丨〇項所述之方法，其中該高分 子材料層係以一電漿增益型化學氣相沈積法所形成。 驟⑴ 1 6 ·如申請專利範圍第1 〇項所述之方法’其中在該步 )中該高子材料層係作為一蝕刻罩幕。 1 7 · —種於'^半導體基底上之/非揮發性5己丨思體，包 括 (a) —半導體基底； (b )複數條位元線； (c )複數個捕捉塊狀結構；以及 (d )複數條字元線，該些字元線係對應配置在該些捕 捉塊狀結構上，其中位於該些位元線之間並且在該字元線 方向之該些捕捉塊狀結構彼此係分開的。 1 8·如申請專利範圍第丨7項所述之非揮發性記憶體， 其中該些捕捉塊狀結構包括一氧化層以及一氮化矽層。 1 9 ·如申請專利範圍第丨8項所述之非揮發性記憶體， 其中： 該氧化層包括一第二氧化層；以及 一第一氧化層，其係延伸至位於該些位元線之間之誃 些捕捉塊狀結構之間。 〃 20,如申請專利範圍第丨7項所述之非揮發性記憶體， 其中每一該些捕捉塊狀結構係對應於一記憶胞中之一單一 位元。 8864twf.ptd 第25頁1220065 VI. Scope of patent application 1 4. The method described in item 丨 2 of the scope of patent application ′ 〃 The etch-back part of the capture layer only removes the second oxide layer and the silicon nitride layer. 15 · The method as described in item No. 0 of the patent application range, wherein the high molecular material layer is formed by a plasma gain type chemical vapor deposition method. Step 1 6: The method according to item 10 of the scope of the patent application, wherein in this step) the high-level material layer is used as an etching mask. 1 7 · —Non-volatile, non-volatile semiconductors on a semiconductor substrate, including (a) a semiconductor substrate; (b) a plurality of bit lines; (c) a plurality of capture block structures; and (d) a plurality of character lines, the character lines are correspondingly arranged on the capturing block structures, wherein the capturing block structures located between the bit lines and in the direction of the word line are mutually Separate. 18. The non-volatile memory according to item 7 of the scope of the patent application, wherein the capture block structures include an oxide layer and a silicon nitride layer. 19 · The non-volatile memory according to item 8 of the scope of the patent application, wherein: the oxide layer includes a second oxide layer; and a first oxide layer extending to the bit lines Something in between captures massive structures. 〃20. The non-volatile memory according to item 7 of the scope of the patent application, wherein each of these capturing block structures corresponds to a single bit in a memory cell. 8864twf.ptd Page 25