591888 A7 B7 五、發明説明（1 ) 丨 - ^^衣-- (請先閲讀背面之注意事項再填寫本頁) 本發明一般關於具低消耗反相放大器之振盪器電路（ 以下稱爲反相振盪器電路）。更具體的說，本發明關於極 低頻反相振盪器電路，其較佳地包括設計依據扭力震動模 式而震動之石英共振器。 屬 Eta SA Fabriques dΈbauches及EIV[Microelectronic-Marin SA名義的「No. EP 1 111 770 A1」歐洲專利中，已知 一種具改良型熱性能的低頻石英振盪器裝置。該專利案以 提及的方式倂入本文，揭露一種反相型振盪器，包括設計 依據扭力震動模式而震動之特定石英共振器。一九九六年 十月十七至十八日，Bienne「第六屆歐洲測時協會」，由591888 A7 B7 V. Description of the invention (1) 丨-^^ clothing-(Please read the precautions on the back before filling this page) The present invention generally relates to an oscillator circuit with a low-consumption inverting amplifier (hereinafter referred to as inversion Oscillator circuit). More specifically, the present invention relates to an extremely low frequency inverting oscillator circuit, which preferably includes a quartz resonator designed to vibrate in accordance with a torsional vibration mode. It belongs to the European patent of "No. EP 1 111 770 A1" in the name of Eta SA Fabriques dΈbauches and EIV [Microelectronic-Marin SA, and a low-frequency quartz oscillator device with improved thermal performance is known. This patent is incorporated herein by reference and discloses an inverting type oscillator including a specific quartz resonator designed to vibrate in accordance with a torsional vibration mode. From October 17th to 18th, 1996, the Sixth European Timing Association
Messrs. Roger Bourquin及 Philippe Truchot所著，「Barreau de quaitz vibiant en mode detorsion, Application aux captcurs 」文章中透露（以提及的方式倂入上述歐洲專利案中）， 該特定共振器具有由繞石英結晶之結晶X軸旋轉所定義的單 一截角，並包括特別是在第一頻率之不希望的基本彎曲震 動模式，及在高於第一頻率之第二頻率，所希望的扭力震 動模式。 經濟部智慧財產局員工消費合作社印製 維持共振器振盪的電路是反相類型。爲保障共振器的 震動是依據所需基本扭力震動模式，而非依據不希望的基 本彎曲震動模式，該反相電路設計具有轉導値，其加以設 限（或最小及最大轉導値限制），以保障震動滿足於基本 扭力震動模式，而非基本彎曲震動模式。 因而所設計之振盪器裝置的熱性能，相較於傳統振盪 器裝置，已大爲提升，並具有特別是類似於使用AT切割共 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X 297公釐 591888 kl _______B7_ 五、發明説明（2 ) 振器的熱性能，卻適用理想地較低作業頻率（通常扭力共 振器用於393 kHz，而AT切割共振器用於4MHz )，因而消耗 較低。 (請先閱讀背面之注意事項再填寫本頁) 不考慮熱性能的優點，然而，上述歐洲專利案所揭露 之振盪器電路的消耗，仍遠高於傳統低頻振盪器電路。因 而’本發明的主要目標是提供一種具有較低消耗的振盪器 電路，該振盪器電路較佳地但不必須包括上述類型的扭力 震動共振器。 應注意的是，屬富士通（Fujitsu )股份有限公司名義 ，於一九八三年九月廿日申請的「No. JP 60-64506」日本專 利中，已知降低消耗的振盪器電路。圖la及lb顯示該發明 之振盪器電路的功能圖，整體以代號10表示。整體而言， 相對於傳統反相振盪器電路，所描繪的每一振盪器電路， 包括特別是輸入端子A及輸出端子B之間的並聯設計，包含 反相放大器裝置2、3，共振器1，及稱爲反餽電阻器，並具 RF値的電阻元件4。第一及第二負載電容器5、6，一方面分 別連接於輸入端子A及輸出端子B之間’另一方面具有Vss供 應電位。 經濟部智慧財產局員工消費合作社印製 振盪器電路1 〇進一步包括控制裝置8及切換裝置7，以 控制反相放大器裝置2、3，使其於啓動階段具有第一轉導 値，並於啓動階段結束的穩定階段中’具有低於第一轉導 値的第二轉導値。 更明確地，圖la之振盪器電路1〇包括第一反相器2，其 具有代號gm的第一轉導値’及第二反相器3，其具有代號 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） - 5 - 591888 A7 B7 五、發明説明（3 )Messrs. Roger Bourquin and Philippe Truchot, disclosed in the article "Barreau de quaitz vibiant en mode detorsion, Application aux captcurs" (incorporated in the above-mentioned European patent case by reference), this particular resonator has crystal The single truncation angle defined by the crystal X-axis rotation includes an undesired basic bending vibration mode, particularly at a first frequency, and a desired torsional vibration mode at a second frequency higher than the first frequency. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The circuit that maintains the oscillation of the resonator is an inverting type. In order to ensure that the vibration of the resonator is based on the required basic torsional vibration mode rather than the undesired basic bending vibration mode, the inverting circuit design has a transconductance chirp, which is set to a limit (or minimum and maximum transconductance chirp limits) To ensure that the vibration is satisfied with the basic torsional vibration mode instead of the basic bending vibration mode. Therefore, the thermal performance of the designed oscillator device has been greatly improved compared with the traditional oscillator device, and it has a similar size to that of AT-cut common paper. The national standard (CNS) A4 specification (210X 297 mm 591888 kl _______B7_ V. Description of the invention (2) The thermal performance of the vibrator is ideally low operating frequency (usually a torsional resonator is used at 393 kHz and an AT-cut resonator is used at 4 MHz), so the consumption is lower. (Please read the precautions on the back before filling this page) The advantages of thermal performance are not taken into account, however, the consumption of the oscillator circuit disclosed in the above European patent case is still much higher than that of the traditional low-frequency oscillator circuit. The main objective is to provide an oscillator circuit with lower consumption, which preferably does not necessarily include the above-mentioned type of torsional vibration resonator. It should be noted that it is in the name of Fujitsu Co., Ltd. In the Japanese patent of "No. JP 60-64506" filed on September 20, 1983, an oscillator circuit with reduced consumption is known. Figs. The functional diagram of Mingzhi's oscillator circuit is generally represented by the code 10. In general, compared to the traditional inverting oscillator circuit, each oscillator circuit depicted includes, in particular, the parallel connection between input terminal A and output terminal B. The design includes inverting amplifier devices 2, 3, resonator 1, and a resistor element 4 called a feedback resistor and having RF 。. The first and second load capacitors 5, 6 are connected to input terminal A, respectively. And on the other hand, there is a Vss supply potential between the output terminal B. The printed circuit of the oscillator 10 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs further includes a control device 8 and a switching device 7 to control the inverting amplifier devices 2, 3, It has a first transduction 于 during the start-up phase, and 'has a second transduction 低于 lower than the first transduction 稳定 in the stabilization phase at the end of the start-up phase. More specifically, the oscillator circuit 10 of FIG. The first inverter 2 has a first transconductance 値 ′ coded as gm and the second inverter 3 has a code. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm)-5 -59188 8 A7 B7 V. Description of the invention (3)
Gm的第二轉導値，高於第一轉導値gm。切換裝置7用於選 擇性地連接位於輸入及輸出端子A、B之間的第一反相器2或 第二反相器3。啓動階段時，切換裝置7處於位置「1」，所 以連接端子A、B之間的第二反相器。一旦振盪穩定，處於 穩態的切換裝置7，並透由控制裝置8的作業，進入位置「2 j ° 圖lb的振盪器電路10大體上與圖la的電路類似。第二反 相器3此處僅具有代號Agm的其餘或互補値，其於啓動階段 附加至第一反相器2的轉導値gm。因而連接切換裝置7，使 得第二反相器3於啓動階段（切換裝置7處於位置「1」）與 第一反相器2並聯，並於穩態（切換裝置7處於位置「2」） 脫離第一反相器2。 應注意的是，上述日本文件中所提供的設計，可能具 有若干缺點。特別是，在啓動階段結束切換時，轉導値降 低的效果是電流減少（即消耗），其亦導致振盪器輸出信 號的振幅突降。該振盪器電路的切換可導致，特別是明顯 的共振器振盪阻尼，其最終可能導致完全停止，或改變震 動模式。特別的是，吾人已注意到上述日本文件中所提供 的設計，是否直接與上述用於扭力震動的共振器相結合， 其將導致共振器完全停止，或改變震動模式，成爲不希望 的基本彎曲震動模式。 亦應注意的是，振盪器輸出信號的振幅突降，對於與 該振盪器電路相結合的周邊元件，亦爲一缺點。 上述日本專利案所提供的結構組，特別是結合本文開 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I—- -- (請先閱讀背面之注意事項再填寫本頁)The second transduction ridge of Gm is higher than the first transduction ridge gm. The switching device 7 is used to selectively connect the first inverter 2 or the second inverter 3 between the input and output terminals A and B. During the start-up phase, the switching device 7 is in the position "1", so a second inverter between terminals A and B is connected. Once the oscillation is stable, the switching device 7 in the steady state passes through the operation of the control device 8 and enters the position "2 j ° The oscillator circuit 10 of Fig. 1b is substantially similar to the circuit of Fig. 1a. The second inverter 3 Only the remaining or complementary 値, coded Agm, is added to the transconductance 値 gm of the first inverter 2 during the startup phase. Therefore, the switching device 7 is connected so that the second inverter 3 is in the startup phase (the switching device 7 is in the Position "1") is connected in parallel with the first inverter 2 and leaves the first inverter 2 in a steady state (the switching device 7 is in the position "2"). It should be noted that the design provided in the aforementioned Japanese document may have several disadvantages. In particular, at the end of switching during the start-up phase, the effect of reduced transconductance is current reduction (ie, consumption), which also results in a sudden drop in the amplitude of the oscillator output signal. The switching of this oscillator circuit can lead to, in particular, pronounced resonator oscillation damping, which may eventually lead to a complete stop or change in the vibration mode. In particular, I have noticed whether the design provided in the above-mentioned Japanese document is directly combined with the above-mentioned resonator for torsional vibration, which will cause the resonator to stop completely or change the vibration mode to become an undesired basic bending Vibration mode. It should also be noted that the sudden drop in the amplitude of the output signal of the oscillator is also a disadvantage for peripheral components combined with the oscillator circuit. The structure group provided in the above Japanese patent case, especially in combination with this paper, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) I ----(Please read the precautions on the back before filling this page)
1T 經濟部智慧財產局員工消費合作社印製 -6- 591888 ΚΊ B7 五、發明説明（4 ) 頭所提及之「No. EP 1 1 1 1 770 A1」歐洲專利案，假使振盪 器必須滿足特定狀況，使得共振器必須依據所需的震動模 式震動，那麼便需特別地注意。 本發明的另一目標是提供一種具低消耗的振盪器電路 ’其可容易地與整個系統整合，對於系統不會產生干擾， 並保障共振器維持適當的振盪。特別是，在振盪器電路使 用上述類型之扭力震動石英共振器的狀況下，需要一種設 計，除了降低消耗外，可保障維持扭力震動模式。 本發明的又另一目標仍是進一步擴展消耗降低，並提 供消耗較少能源的設計。 本發明的另一目標是提供一種方法，維持上述類型共 振器的振盪，一方面保_減少消耗，另一方面保障共振器 依據所需基本扭力震動之振盪，得以維持。 因而，本發明關於一種反相振盪器電路，其特性列於 申請專利範圍第1項。 本發明亦關於一種方法，維持上述類型共振器的振盪 ，其特性列於申請專利範圍第1 3項。 本發明有利的實施例形成申請專利範圍的主題。 參閱上述「No· EP 1 1 1 1 770 A1」歐洲專利，有關特定 共振器依據扭力震動模式而震動，應注意的是，維持共振 器震動的電路，係設計用以迫使共振器依據所需基本扭力 震動模式而震動，而且爲達此目的，反相器的轉導値應選 擇高於不希望之彎曲震動模式的最大轉導値gm，max。因爲轉 導値通常表示電路所消耗的電流，所以應理解的是，當迫 ---------费本-- (讀先閱讀背面之注意事項再填寫本頁) :、1T' 經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-6- 591888 ΚΊ B7 V. European patent case of "No. EP 1 1 1 1 770 A1" mentioned in the description of the invention (4), if the oscillator must meet specific requirements The condition makes the resonator vibrate according to the required vibration mode, so special attention is needed. Another object of the present invention is to provide an oscillator circuit with low consumption, which can be easily integrated with the entire system, does not cause interference to the system, and ensures that the resonator maintains proper oscillation. In particular, in the case where the oscillator circuit uses the above-mentioned type of torsional vibration quartz resonator, a design is required, which can save the maintenance of the torsional vibration mode in addition to reducing the consumption. Still another object of the present invention is to further expand the consumption reduction and provide a design that consumes less energy. Another object of the present invention is to provide a method for maintaining the oscillation of the above-mentioned type of resonator, on the one hand, to reduce consumption, and on the other hand, to ensure that the oscillation of the resonator according to the required basic torsional vibration is maintained. Therefore, the present invention relates to an inverting oscillator circuit whose characteristics are listed in item 1 of the scope of patent application. The invention also relates to a method for maintaining the oscillation of the above-mentioned type of resonator, and its characteristics are listed in item 13 of the scope of patent application. Advantageous embodiments of the invention form the subject of the patentable scope. Refer to the above-mentioned "No. EP 1 1 1 1 770 A1" European patent. Regarding the vibration of a specific resonator according to the torsional vibration mode, it should be noted that the circuit that maintains the vibration of the resonator is designed to force the resonator according to the required basic Torsional vibration mode vibrates, and for this purpose, the transduction 値 of the inverter should be selected to be higher than the maximum transduction 値 gm, max of the undesired bending vibration mode. Because the transduction 値 usually represents the current consumed by the circuit, it should be understood that when forced --------- fee book-(read the precautions on the back before filling in this page) :, 1T ' Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ZTT 9 A7 _______B7 五、發明説明（5 ) 使共振器依據扭力震動模式而震動時，電路的消耗大於相 同電路依據傳統彎曲震動模式而震動時的消耗。 然而’依據本發明，吾人已注意到一旦振盪器電路啓 動’且輸出信號穩定時，電路的消耗便可降低。特別是， 可啓動該電路，使得共振器依據所需的扭力模式震動，可 滿足上述歐洲專利案中所定義之轉導値限制所決定的標準 ’並於啓動階段結束時，降低消耗，同時保障共振器仍依 據扭力震動模式而震動。此消耗的降低，部分歸功於在啓 動階段之後，於所謂的穩定狀況階段時，將電路切換至另 一狀態’後者的轉導値相對於最初啓動所定義的轉導値， 已予以降低。 有利地，吾人已注意到反相器的轉導値可降低爲低於 轉導値限制的値，在此値之下，不需保證，共振器便可正 常地在扭力震動模式中振盪。吾人已注意到，轉導値限制 於共振器啓動階段中確定。爲安全之故，仍須考量將電路 的轉導値維持在避免共振器依據扭力震動模式而震動之轉 導値的範圍內。 除了在穩態降低消耗外，本發明亦保障振盪器電路透 由初始階段高轉導値的選擇，而快速啓動。 依據本發明，振盪器電路亦配合裝置，使得在啓動階 段進入穩態期間，即當電路的轉導値降低時，交替的信號 輸出振幅得以平順。輸出信號振幅的平順，限制了振盪器 電路轉導値的切換效果，並保障共振器的振盪不致突降， 以確保共振器持續依據所需的震動模式而震動。此外，此 (讀先閱讀背面之注意事項再填寫本頁) -参衣_ :訂 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -8- 經濟部智慧財產局員工消費合作社印製 591888 A7 ________ 五、發明説明（6 ) 平順有利於振盪電路整合進入整個系統，振盪器電路於狀 態間切換所造成的干擾將會最小。 依據本發明的其他實施例，使用互補裝置以降低振盪 器電路在穩態中的消耗。依據第一個該些實施例，電阻元 件串聯於反相器電路的供應路徑中。依據本發明的另一個 該些實施例，該電路進一步包括穩壓器，以降低反相器電 路的供應電壓。 在參閱下列說明及附圖所提供之非侷限性的範例後， 本發明的其他特性及優點，將更顯而易見，其中： 已提及的圖la及lb，顯示上述「No. JP 60-64506」日本 專例中，所揭露之反相振盪器電路的兩功能圖； 圖2顯示依據本發明之反相振盪器電路的總圖； 圖3a描繪圖2之反相振盪器電路的轉導値的全時變化， 特別是自啓動階段，切換至穩態階段； 圖3b描繪圖2之振盪器電路所傳輸振盪信號振幅的全時 變化，特別是自啓動階段，切換至穩態階段； 圖4爲依據本發明之振盪器電路實施例的詳細範例； 圖5a爲產生切換信號STARTUP之電路的實施例，其使 得圖2之振盪器電路自啓動階段，切換至穩態階段；及 圖5b描繪圖5a之產生器電路信號的全時變化。 符號說明 A、 90a 輸入端子 B、 90b、90c 輸出端子 氏張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） --------® 裝----Tl.j 訂*— ·-----^ (請先閲讀背面之注意事項再填寫太頁) 591888 A7 B7 --- -. ________________ ___ 五、發明説明（7 ) 2 ' 3 反相放大器裝置 1 共振器 4、 40、95、96 電阻元件 (請先閲讀背面之注意事項再填寫本頁) 5、 6 負載電容器 1〇 振盪器電路 8 控制裝置 7 切換裝置 9 振幅控制迴路 9〇 振幅控制電路 91、92 電流源 21、 31、901、902、903、904、905 p型金屬氧化物半導 體電晶體 22、 32、910、911、912 η型金屬氧化物半導體電晶體 100 成形階段 7a、7b 開關 921 ' 922、923 電容元件 80 正反器 85 計數器 經濟部智慧財產局員工消費合作社印製 圖2顯示構成本發明較佳實施例之反相器型振盪器電路 的總功能圖。圖2中所描繪之反相振盪器電路1 〇，通常包括 特別是輸入端子A及輸出端子B之間的並聯設計，反相放大 器裝置包含第一及第二反相器2、3，共振器1，及電阻器4 ，第一及第二負載電容器5、6，一方面分別連接於輸入及 -10- 本紙張尺度適用中國國家標準（CNS ) A4規格（2】OX297公釐） 591888 A7 B7 五、發明説明（8 ) 輸出端子A、B之間，另一方面具有V s s供應電位。振S器電 路10進一步包括置於反相器2、3的輸出之間，並具有R〇値 的額外電阻元件4 0，共振器1及負載電容器6。此選擇性電 阻元件40，特別用於提升振盪器電路的穩定性。 二反相器2、3大體上與圖1 b中所描繪的設計類似’即 第一反相器2固定連接於輸入及輸出端子A、B之間，而第二 反相器3則可透由控制裝置8的作業，連接或脫離端子A、B 。在此例中，第二反相器3使用置於反相器供應路徑中的切 換裝置（即受控制裝置8控制的兩開關7a及7b )而起動或停 工，具有Vdd及Vss間的供應電位。 應注意的是，第二反相器3透由與反相器串聯的開關， 可交替地連接或脫離端子A、B，例如圖5中所描繪，本文開 頭提及的「JP 60-64506」日本專利，透由一傳輸閘，其包 括相並聯的一 η型金屬氧化物半導體電晶體及一 P型金屬氧 化物半導體電晶體，彼此經由汲極與源極端子相連。 振盪器電路1 0進一步包括當振盪器電路於啓動階段終 止切換時，使交替的輸出信號Sosc振幅平順的裝置。該些輸 出信號振幅平順裝置的代號9，有利地爲振幅控制迴路的形 式。振幅控制迴路9，一方面連接至振盪器電路10的輸入及 輸出端子A、B之一，另一方面連接至第一反相器2。 振幅控制迴路9一方面包括振幅控制電路90，另一方面 包括連接於反相器2之供應路徑中，至少一個受控制的電流 源91、92 (最好爲兩個）。在本例中，振幅控制電路90的 輸入端子90a，連接至振盪器電路的輸入端子A，而二輸出 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） — ------------- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -11 - 經濟部智慧財產局員工消費合作社印製 591888 A7 ___ B7 _ 五、發明説明（9 ) 端子90b、90c則分別連接至置於反相器2之供應路徑端點的 第一及第二受控制的電流源9 1、92。經由第一改良，每一 受控制的電流源91、92，進一步分別並聯至電阻元件95、96 。以下將回到該些電阻元件的使用。 現在將參閱圖3a及3b，簡述依據本發明之反相振盪器 電路的操作原理。圖3a槪略描繪依據本發明之振盪器電路 的轉導値的全時變化。在圖3a中，藉由前述「No. EP 1 111 770 A1」歐洲專利案中範例，亦就共振器採取基本彎曲（74 kHz )及扭力（393 kHz )震動模式之最小（（gm，min，較低振 盪狀況）及最大（gm，max，較高振盪狀況）轉導値，描繪振盪 狀況。圖3b槪略描繪振盪器的交替輸出信號Sosc的相對應變 在振盪器電路的啓動階段（階段「1」），振盪器電路 的二反相器2、3彼此並聯，如此電路具有所謂啓動轉導値 ’其値高，代號Gm。就此點應注意的是，在最初階段，選 擇高轉導値，將減少振盪器電路的啓動時間。 爲設疋共振器依據所需的基本扭力震動模式而震動， 該電路選擇啓動轉導値Gm，以滿足所需模式（即基本扭力 震動模式）的振盪狀況。在本例中，該些狀況滿足於所包 含的啓動轉導値Gm，處於所不希望之彎曲震動模式（74 kHz )的較高値限制gm，max，與所需扭力震動模式（393 kHz )的較高値限制之間。 藉滿足上述狀況，共振器被設定於依據所需扭力M雲力 模式而震動。如圖3b所描繪，輸出信號Sosc的振幅逐漸增加 本紙張尺度適用中國國家標準（CNS ) A4規格（210X；297公釐） 7^2 -~— -- (讀先閱讀背面之注意事項再填寫本頁)This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) ZTT 9 A7 _______B7 V. Description of the invention (5) When the resonator vibrates according to the torque vibration mode, the circuit consumes more than the same circuit based on traditional bending vibration Consumption when shaking mode. However, according to the present invention, I have noticed that once the oscillator circuit is started and the output signal is stable, the circuit consumption can be reduced. In particular, the circuit can be activated so that the resonator vibrates according to the required torque mode, which can meet the criteria determined by the transmissive 値 limit defined in the aforementioned European patent case ', and reduce the consumption at the end of the startup phase, while ensuring that The resonator still vibrates according to the torsional vibration mode. This reduction in consumption is partly due to the fact that after the start-up phase, the circuit is switched to another state during the so-called steady-state phase, the latter's transduction 値 has been reduced compared to the transduction 定义 defined during initial startup. Advantageously, I have noticed that the transduction 値 of the inverter can be reduced to 低于 below the transduction 値 limit. Below this ，, there is no need to guarantee that the resonator can oscillate normally in the torsional vibration mode. I have noticed that the transduction confinement is limited to the resonator startup phase. For safety reasons, it is still necessary to consider keeping the transconductance of the circuit within the range of the transconductance of the resonator to avoid vibration according to the torsional vibration mode. In addition to reducing the consumption in the steady state, the invention also ensures that the oscillator circuit can be quickly started through the selection of the high transconductance chirp in the initial stage. According to the present invention, the oscillator circuit also cooperates with the device, so that during the start-up phase entering a steady state, that is, when the transconductance of the circuit decreases, the alternating signal output amplitude can be smoothed. The smoothness of the output signal amplitude limits the switching effect of the oscillator circuit's transconductance, and ensures that the oscillation of the resonator does not drop suddenly, so as to ensure that the resonator continues to vibrate according to the required vibration mode. In addition, this (read the precautions on the back before you fill in this page) -Shen Yi_: Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -8- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 591888 A7 ________ V. Description of the invention (6) Smoothness facilitates the integration of the oscillating circuit into the entire system, and the interference caused by the switching of the oscillator circuit between states will be minimal. According to other embodiments of the present invention, complementary devices are used to reduce the consumption of the oscillator circuit in the steady state. According to the first embodiments, the resistor element is connected in series in the supply path of the inverter circuit. According to another embodiment of the present invention, the circuit further includes a voltage regulator to reduce the supply voltage of the inverter circuit. Other features and advantages of the present invention will be more apparent after referring to the non-limiting examples provided in the following description and accompanying drawings, among which: The already mentioned figures la and lb show the above-mentioned "No. JP 60-64506" Two functional diagrams of the inverting oscillator circuit disclosed in the Japanese example; FIG. 2 shows a general diagram of the inverting oscillator circuit according to the present invention; FIG. 3a depicts the transconductance of the inverting oscillator circuit of FIG. 2 Full-time change, especially the self-starting phase, switching to the steady-state phase; Figure 3b depicts the full-time change of the amplitude of the oscillating signal transmitted by the oscillator circuit of Figure 2, especially the self-starting phase, switching to the steady-state phase; Figure 4 is A detailed example of an embodiment of an oscillator circuit according to the present invention; FIG. 5a is an embodiment of a circuit that generates a switching signal STARTUP, which enables the oscillator circuit of FIG. 2 to switch from a startup phase to a steady state phase; and FIG. 5b depicts FIG. 5a The generator circuit signal changes all the time. Explanation of symbols A, 90a Input terminal B, 90b, 90c Output terminal scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) -------- ® Installation ---- Tl.j order * — · ----- ^ (Please read the notes on the back before filling out the page) 591888 A7 B7 ----. ________________ ___ V. Description of the invention (7) 2 '3 Inverting amplifier device 1 Resonator 4, 40, 95, 96 resistance elements (please read the precautions on the back before filling this page) 5, 6 load capacitor 10 oscillator circuit 8 control device 7 switching device 9 amplitude control circuit 90 amplitude control circuit 91, 92 current source 21, 31, 901, 902, 903, 904, 905 p-type metal oxide semiconductor transistor 22, 32, 910, 911, 912 n-type metal oxide semiconductor transistor 100 Forming stage 7a, 7b Switch 921 '922, 923 Capacitor element 80 Flip-flop 85 Counter Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs FIG. 2 shows a general functional diagram of an inverter-type oscillator circuit constituting a preferred embodiment of the present invention. The inverting oscillator circuit 10 depicted in FIG. 2 usually includes a parallel design especially between the input terminal A and the output terminal B. The inverting amplifier device includes first and second inverters 2 and 3 and a resonator. 1, and resistor 4, the first and second load capacitors 5, 6 are connected to the input and -10- respectively. This paper size applies Chinese National Standard (CNS) A4 specifications (2) OX297 mm 591888 A7 B7 5. Description of the invention (8) Between the output terminals A and B, on the other hand, it has a V ss supply potential. The oscillator circuit 10 further includes an additional resistance element 40, a resonator 1 and a load capacitor 6, which are placed between the outputs of the inverters 2 and 3, and have an additional resistance. This selective resistive element 40 is particularly used to improve the stability of the oscillator circuit. The two inverters 2 and 3 are generally similar to the design depicted in FIG. 1 b. That is, the first inverter 2 is fixedly connected between the input and output terminals A and B, and the second inverter 3 is transparent. The terminals A and B are connected or disconnected by the operation of the control device 8. In this example, the second inverter 3 is started or stopped using a switching device (ie, two switches 7a and 7b controlled by the control device 8) placed in the inverter supply path, and has a supply potential between Vdd and Vss . It should be noted that the second inverter 3 can be alternately connected or disconnected from the terminals A and B through a switch connected in series with the inverter, for example, as depicted in FIG. 5 and referred to as "JP 60-64506" at the beginning of this article. The Japanese patent discloses a transmission gate, which includes an n-type metal oxide semiconductor transistor and a P-type metal oxide semiconductor transistor connected in parallel and connected to each other via a drain electrode and a source terminal. The oscillator circuit 10 further includes means for smoothing the amplitude of the alternate output signal Sosc when the oscillator circuit terminates switching during the startup phase. The code 9 of these output signal amplitude smoothing devices is advantageously in the form of an amplitude control loop. The amplitude control loop 9 is connected to one of the input and output terminals A, B of the oscillator circuit 10 on the one hand, and to the first inverter 2 on the other hand. The amplitude control loop 9 includes, on the one hand, an amplitude control circuit 90 and, on the other hand, at least one controlled current source 91, 92 (preferably two) in the supply path connected to the inverter 2. In this example, the input terminal 90a of the amplitude control circuit 90 is connected to the input terminal A of the oscillator circuit, and the second output size of this paper applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) — ---- --------- (Please read the notes on the back before filling this page) Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -11-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 591888 A7 ___ B7 _ V. Description of the invention (9) Terminals 90b and 90c are respectively connected to the first and second controlled current sources 9 1 and 92 placed at the ends of the supply path of the inverter 2 respectively. With the first improvement, each controlled current source 91, 92 is further connected in parallel to the resistance elements 95, 96, respectively. The following will return to the use of these resistance elements. Referring now to Figs. 3a and 3b, the operation principle of the inverting oscillator circuit according to the present invention will be briefly described. Figure 3a schematically illustrates the full-time variation of the transconductance of an oscillator circuit according to the present invention. In Figure 3a, following the example in the aforementioned European Patent No. EP 1 111 770 A1, the resonator also adopts the minimum bending (74 kHz) and torque (393 kHz) vibration modes ((gm, min, Lower oscillation conditions) and maximum (gm, max, higher oscillation conditions) transduction 値, depicting the oscillation conditions. Figure 3b (a) briefly depicts the relative strain of the oscillator's alternate output signal Sosc during the startup phase of the oscillator circuit (phase " 1 ″), the two inverters 2 and 3 of the oscillator circuit are connected in parallel with each other, so that the circuit has a so-called start transconductance 値 ′, whose code is Gm. At this point, it should be noted that in the initial stage, a high transconductance Will reduce the startup time of the oscillator circuit. In order to set the resonator to vibrate according to the required basic torsional vibration mode, the circuit chooses to start the transduction 値 Gm to meet the oscillation condition of the required mode (ie, the basic torsional vibration mode) In this example, these conditions are satisfied with the included inductive transduction 値 Gm, which is at a higher 値 of the undesired flexural vibration mode (74 kHz), the limit gm, max, and the required torque vibration mode (393 kHz) of Between the high and low limits. By meeting the above conditions, the resonator is set to vibrate according to the required torque M cloud force mode. As depicted in Figure 3b, the amplitude of the output signal Sosc gradually increases. This paper applies the Chinese National Standard (CNS) A4. Specifications (210X; 297mm) 7 ^ 2-~--(Read the precautions on the back before filling in this page)
591888 A7 B7 五、發明説明（10 ) ，而振盪頻率則趨向於穩態。通常稱振盪在預定時段Tstab 終止時已穩定。 在啓動階段終止時，一旦振盪電路的振盪穩定（處於 穩態，爲各圖中的階段「2」），第二反相器3便停工，以 減少電路的轉導値，至所謂降低値gm，並因而降低了電路 的消耗。爲安全之故，降低的轉導値gm，應較佳地決定， 使其仍滿足所需扭力震動模式的振盪狀況限制。吾人仍可 注意到，轉導値可降低至不在滿足上述振盪狀況。在圖3a 的範例中，可將電路的轉導値降低至處於所不希望之彎曲 震動模式的較高値限制gm，max，與所需扭力震動模式的較低 値限制之間，此可能性在圖3a中以虛線描繪。因而應 理解的是，本發明使得反相器電路的消耗降低至較低振盪 狀況所定義的消耗位準之下，即所不希望的彎曲震動模式 的$乂 Γ^Ι轉導値g m，m a X ( g亥値通吊局於所需扭力震動彳旲式的較 低轉導値gm，min )。 依據本發明，由於連接至振盪器電路之第一反相器的 振幅控制迴路的加入，自啓動轉導値Gm，轉變成降低的轉 導値，並非突然而是逐漸地發生。如圖3b中所描繪的，此 導致輸出信號Sosc之振幅的全面且逐漸地減少。 再次參閱圖2，應注意的是振盪器電路的消耗，可藉由 在第一反相器2的供應路徑中，加入電阻元件9 5、9 6，並與 每一受控制的電流源9 1、9 2並聯，而進一步地降低。加入 該些電阻元件的效果，將限制反相器2的供應路徑中的最大 電流，因而進一步降低穩態反相振盪器電路的消耗。 本紙張尺度適用中周國家標準（CNS ) A4規格（21〇X 297公釐） I .-------- (請先閱讀背面之注意事項再填寫本頁) :訂 經濟部智慧財產局員工消費合作社印製 -13- 591888 A7 B7 五、發明説明（11 ) 亦經由改進，可降低反相振盪器電路端子的供應電壓 ，即產生處於供應電位Vdd及Vss之間的中間供應電位VR。 —---------41^衣— (請先閱讀背面之注意事項再填寫本頁) 圖4顯示圖2之反相振盪器電路的詳細實施例。爲求淸 晰，共振器1 (連接於端子A、B之間）及負載電容器5、6 ( 分別連接端子A、B )，並不顯示於圖4之中。 第一及第二反相器2、3爲互補金屬氧化物導體（CMOS )反相器，各包括一 P型金屬氧化物半導體電晶體21、31， 後者的汲極則分別連接η型金屬氧化物半導體電晶體22、32 的汲極。電晶體21、22、31及32的閘極連接相同的節點，並 形成振盪器電路的輸入端子Α。電晶體21、22、31及32的汲 極，共同透由額外電阻π件40，連接至輸出端子B。反餽電 阻元件4連接於電晶體21、22、31及32的閘極連接節點與汲 極連接節點之間。振盪器電路輸出信號（本例中於端子Α處 產生），以典型的方式施予成形階段100的輸入，以傳輸方 形輸出信號。 經濟部智慧財產局員工消費合作社印製 第二反相器3之p型金屬氧化物半導體電晶體3 1的源極 ，透由形成開關7a的另一 p型金屬氧化物半導體電晶體，連 接至高供應電位VDD。同樣地，第二反相器3之η型金屬氧化 物半導體電晶體32的源極，透由形成開關7b的另一 η型金屬 氧化物半導體電晶體，連接至低供應電位（此處爲中間供 應電位V〇 。一控制信號STARTUP (透由反相器）施予η型 金屬氧化物半導體電晶體7b的閘極，及ρ型金屬氧化物半導 體電晶體7a的閘極，以控制其傳導狀態，並選擇地啓動或 使第二反相器3停工。 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 7u - 591888 A7 B7 五、發明説明（12 ) (請先閱讀背面之注意事項再填寫本頁) 第一反相器2之p型金屬氧化物半導體電晶體21的源極 ’透由連接於電阻器組態（閘極電位接地）中的另一 p型金 屬氧化物半導體電晶體，連接至高供應電位VDD，該p型金 屬氧化物半導體電晶體形成圖2之電阻元件95。一形成第一 受控制電流源9 1的p型金屬氧化物半導體電晶體，亦***於 P型金屬氧化物半導體電晶體21的源極，與高電位V。。之間， 並與電晶體9 5並聯，形成一電阻。同樣地，η型金屬氧化物 半導體電晶體22的源極，透由連接於電阻器組態（閘極電 位接至高電位）中的另一 η型金屬氧化物半導體電晶體，連 接至低供應電位VR，並形成圖2之電阻元件96。一形成第二 受控制電流源92的η型金屬氧化物半導體電晶體，亦***於 η型金屬氧化物半導體電晶體2 2的源極，與低電位V R之間， 並與電晶體96並聯，形成一電阻。 形成受控制電流源的P型金屬氧化物半導體電晶體9 1， 及η型金屬氧化物半導體電晶體92，受振幅控制電路90控制 ，現在將簡單說明後者的結構。應注意的是，熟悉本技藝 支人士，可設想其它的組態，以形成本振幅控制電路，因 此所描繪的組態不應視爲本發明的侷限。 經濟部智慧財產局員工消費合作社印製 振盪器電路的輸入端子Α施予第一電容元件921，電容 元件921的其他端子，一方面連接至第一p型金屬氧化物半 導體電晶體901的汲極，另一方面連接至第二p型金屬氧化 物半導體電晶體902的閘極。後者的源極連接至高電位Vdd， 其汲極則連接至第一 p型金屬氧化物半導體電晶體901的源 極，及第三p型金屬氧化物半導體電晶體903的源極。第三p -15- 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 591888 A7 ________B7 五、發明説明（13 ) 型金屬氧化物半導體電晶體903的閘極及汲極，連接至第一 電晶體901的閘極。p型金屬氧化物半導體電晶體902的汲極 ’與P型金屬氧化物半導體電晶體901、903的源極之間的連 接節點，連接至第四p型金屬氧化物半導體電晶體904的閘 極，後者的源極連接至高供應電位VDD。第二及第三電容元 件922、9 23，亦透由其端子之一，分別連接至p型金屬氧化 物半導體電晶體902的汲極，及p型金屬氧化物半導體電晶 體903的汲極，電容元件922、923的其他端子連接至高供應 電位V D D。 形成第一受控制電流源91之p型金屬氧化物半導體電晶 體的閘極，連接至第四p型金屬氧化物半導體電晶體904的 閘極，連接於電容器組態（汲極及源極端子連接至高供應 電位VDD )的第五p型金屬氧化物半導體電晶體905，透由其 閘極，連接至p型金屬氧化物半導體電晶體9 1及904之間的 相同連接。形成第二受控制電流源92之η型金屬氧化物半導 體電晶體的閘極，連接至第四Ρ型金屬氧化物半導體電晶體 904的汲極。 振幅控制電路90之電晶體的偏壓’由偏壓電流IBPOSC 確保，其藉由包括三個η型金屬氧化物半導體電晶體910、 911及91 2的電流對映，映入包括Ρ型金屬氧化物半導體電晶 體9 04的旁路，電流對映之第一及第二輸出旁路的電晶體 911及912，分別與ρ型金屬氧化物半導體電晶體903、904串 圖5a顯示爲開關7a及7b產生控制信號STARTUP之控制電 II-------- (請先閱讀背面之注意事項再填寫本頁) •訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（2]0'乂 297公釐） -16 - 591888 A7 B7 五、發明说明（14) 路8的實施例。控制電路8係數位型式，主要包括正反器s-R 80及計數器85。計數器85由時序信號CLK (藉由描繪及非侷 限之範例，源自振盪器電路輸出信號的時序信號，1 28 Hz ) 計時。零重置信號RESET透由反相器，施予計數器85的零重 置端子，及正反器80的激發端子S。計數器用於計數既定的 脈衝數，本例爲十六個脈衝，因而定義1 6 X 1 /1 2 8 = 1 2 5毫 秒的時段。 如圖5b中所描繪的，切換信號STARTUP於既定時段 Tstab中成爲高邏輯位準。在此時段中，圖2的振盪器電路因 而切換至「局超導」丨旲式’以利快速啓動振邊。一旦此時 段一過，信號STARTUP便成爲低邏輯位準，因而將圖2的振 盪器電路切換至「低超導」模式，以降低電路消耗。 應理解的是，熟悉本技藝人士在不偏離本發明之申請 專利範圍下，顯然可對本文中說明的實施例，進行各種修 改及/或改進。例如，以圖1 a原理爲主的設計，亦適用於 振幅控制迴路，可避免開關切換時振盪器減緩。 I _, — (請先閲讀背面之注意事項再填寫本頁) %訂_ Φ 經濟部智慧財產局員工消費合作社印製591888 A7 B7 5. Description of the invention (10), but the oscillation frequency tends to a steady state. Oscillation is usually said to have stabilized at the end of a predetermined period of Tstab. At the termination of the start-up phase, once the oscillation of the oscillating circuit is stable (at a steady state, it is the stage "2" in each figure), the second inverter 3 is stopped to reduce the transduction 値 of the circuit to the so-called 値 gm , And thus reduce the consumption of the circuit. For safety reasons, the reduced transduction 値 gm should be better determined so that it still meets the limit of the oscillation conditions of the required torsional vibration mode. I can still notice that the transduction maggots can be reduced to no longer satisfy the above-mentioned oscillation conditions. In the example of Figure 3a, the transconductance of the circuit can be reduced to a higher 値 limit gm, max, which is in an undesired bending vibration mode, and a lower 値 limit of the required torsional vibration mode. This possibility is between It is depicted in dashed lines in Figure 3a. It should be understood that the present invention reduces the consumption of the inverter circuit below the consumption level defined by the lower oscillation conditions, that is, the $ 乂 Γ ^ Ι transduction 値 gm, ma of the undesired bending vibration mode X (g 値 値 値 于 于 转 m gm, min at the lower transmissive vibration mode of the required torque vibration). According to the present invention, since the amplitude control loop of the first inverter connected to the oscillator circuit is added, the self-starting transconductance 値 Gm is transformed into a reduced transconductance 値, which does not occur suddenly but gradually. As depicted in Figure 3b, this results in a comprehensive and gradually decreasing amplitude of the output signal Sosc. Referring again to FIG. 2, it should be noted that the consumption of the oscillator circuit can be achieved by adding resistance elements 9 5 and 9 6 to the supply path of the first inverter 2 and connecting with each controlled current source 9 1 , 9 2 are connected in parallel, and further reduced. The effect of adding these resistance elements will limit the maximum current in the supply path of the inverter 2 and thus further reduce the consumption of the steady-state inverting oscillator circuit. This paper size is applicable to the China National Standard (CNS) A4 specification (21〇X 297 mm) I .-------- (Please read the precautions on the back before filling this page): Order the intellectual property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives-13- 591888 A7 B7 5. The invention description (11) has also been improved to reduce the supply voltage at the terminals of the inverting oscillator circuit, which produces an intermediate supply potential VR between the supply potential Vdd and Vss . —--------- 41 ^ 衣 — (Please read the precautions on the back before filling out this page) Figure 4 shows a detailed embodiment of the inverting oscillator circuit of Figure 2. For clarity, resonator 1 (connected between terminals A and B) and load capacitors 5 and 6 (connected to terminals A and B respectively) are not shown in Figure 4. The first and second inverters 2 and 3 are complementary metal-oxide-conductor (CMOS) inverters, each of which includes a P-type metal-oxide semiconductor transistor 21 and 31, and the drains of the latter are respectively connected to n-type metal oxides. Of the semiconductor transistors 22, 32. The gates of the transistors 21, 22, 31, and 32 are connected to the same node and form the input terminal A of the oscillator circuit. The drains of the transistors 21, 22, 31, and 32 are connected to the output terminal B through an additional resistance π member 40 in common. The feedback resistance element 4 is connected between the gate connection node and the drain connection node of the transistors 21, 22, 31, and 32. The oscillator circuit output signal (generated at terminal A in this example) is applied to the input of the forming stage 100 in a typical manner to transmit a square-shaped output signal. The source of the p-type metal oxide semiconductor transistor 31 of the second inverter 3 is printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The source of the p-type metal oxide semiconductor transistor 31 is connected to Supply potential VDD. Similarly, the source of the n-type metal-oxide-semiconductor transistor 32 of the second inverter 3 is connected to a low-supply potential (here, the middle) through another n-type metal-oxide-semiconductor transistor forming the switch 7b. Supply potential V. A control signal STARTUP (through an inverter) is applied to the gate of the n-type metal oxide semiconductor transistor 7b and the gate of the p-type metal oxide semiconductor transistor 7a to control its conduction state. , And selectively start or stop the second inverter 3. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 7u-591888 A7 B7 V. Description of the invention (12) (Please read first Note on the back, please fill in this page again.) The source of the p-type metal oxide semiconductor transistor 21 of the first inverter 2 is connected to another p-type metal in the resistor configuration (gate potential ground). An oxide semiconductor transistor is connected to a high supply potential VDD, and the p-type metal oxide semiconductor transistor forms the resistance element 95 of Fig. 2. A p-type metal oxide semiconductor transistor that forms the first controlled current source 91 is also Insert at P The source of the metal oxide semiconductor transistor 21 is connected to the high potential V, and is connected in parallel with the transistor 95 to form a resistor. Similarly, the source of the n-type metal oxide semiconductor transistor 22 is transparent. A second n-type metal oxide semiconductor transistor connected to a resistor configuration (gate potential to high potential) is connected to a low supply potential VR and forms a resistance element 96 of Fig. 2. One forms a second controlled The n-type metal oxide semiconductor transistor of the current source 92 is also inserted between the source of the n-type metal oxide semiconductor transistor 22 and the low potential VR, and is connected in parallel with the transistor 96 to form a resistor. The P-type metal oxide semiconductor transistor 91, which controls the current source, and the n-type metal oxide semiconductor transistor 92 are controlled by an amplitude control circuit 90. The latter structure will now be briefly explained. It should be noted that you are familiar with this technology. People, can imagine other configurations to form this amplitude control circuit, so the configuration depicted should not be considered as a limitation of the present invention. The Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperative Printed Oscillation The input terminal A of the circuit is applied to the first capacitive element 921, and the other terminals of the capacitive element 921 are connected to the drain of the first p-type metal oxide semiconductor transistor 901 on the one hand and to the second p-type metal oxide on the other hand. Gate of the physical semiconductor transistor 902. The source of the latter is connected to the high potential Vdd, and its drain is connected to the source of the first p-type metal oxide semiconductor transistor 901 and the third p-type metal oxide semiconductor transistor. Source of 903. The third p -15- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 591888 A7 ________B7 V. Description of the invention (13) Gate of metal oxide semiconductor transistor 903 And the drain, which are connected to the gate of the first transistor 901. The connection node between the drain 'of the p-type metal oxide semiconductor transistor 902 and the sources of the p-type metal oxide semiconductor transistors 901 and 903 is connected to the gate of the fourth p-type metal oxide semiconductor transistor 904 The latter source is connected to a high supply potential VDD. The second and third capacitor elements 922, 9 and 23 are also connected to the drain of the p-type metal oxide semiconductor transistor 902 and the drain of the p-type metal oxide semiconductor transistor 903 through one of its terminals. The other terminals of the capacitive elements 922 and 923 are connected to a high supply potential VDD. Forms the gate of the p-type metal oxide semiconductor transistor of the first controlled current source 91, is connected to the gate of the fourth p-type metal oxide semiconductor transistor 904, and is connected to the capacitor configuration (drain and source terminals) The fifth p-type metal-oxide-semiconductor transistor 905, which is connected to a high supply potential (VDD), is connected to the same connection between the p-type metal-oxide-semiconductor transistors 9 1 and 904 through its gate. The gate of the n-type metal oxide semiconductor transistor forming the second controlled current source 92 is connected to the drain of the fourth P-type metal oxide semiconductor transistor 904. The bias voltage of the transistor of the amplitude control circuit 90 is ensured by the bias current IBPSC, which is reflected in the current including three n-type metal oxide semiconductor transistors 910, 911, and 91 2 to include the P-type metal oxide. The bypass of the semiconductor transistor 904, and the first and second output bypasses of the current mirror 911 and 912, respectively, are in series with the p-type metal oxide semiconductor transistor 903 and 904. Figure 5a shows the switch 7a and 7b Control signal II that generates control signal STARTUP (Please read the precautions on the back before filling out this page) • Order the paper size printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs to apply Chinese national standards ( CNS) A4 specification (2] 0 '乂 297 mm) -16-591888 A7 B7 V. Description of the invention (14) Example of Road 8. The 8-bit type of the control circuit mainly includes a flip-flop s-R 80 and a counter 85. The counter 85 is timed by a timing signal CLK (by drawing and non-limiting example, a timing signal derived from the output signal of the oscillator circuit, 1 28 Hz). The zero reset signal RESET is passed through the inverter to the zero reset terminal of the counter 85 and the excitation terminal S of the flip-flop 80. The counter is used to count a given number of pulses. In this example, there are sixteen pulses, so a period of 1 6 X 1/1 2 8 = 1 2 5 milliseconds is defined. As depicted in FIG. 5b, the switching signal STARTUP becomes a high logic level in the established period Tstab. During this period, the oscillator circuit in Fig. 2 is switched to the "local superconductor" 丨 mode to facilitate the rapid start of the vibration edge. Once this period has elapsed, the signal STARTUP becomes a low logic level, so the oscillator circuit of Fig. 2 is switched to the "low superconducting" mode to reduce the circuit consumption. It should be understood that those skilled in the art can obviously make various modifications and / or improvements to the embodiments described herein without departing from the scope of the patent application of the present invention. For example, the design based on the principle of Figure 1a is also applicable to the amplitude control loop, which can avoid the oscillator from slowing down when the switch is switched. I _, — (Please read the notes on the back before filling out this page)% Order_ Φ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
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