五、發明說明（2) 艘更換為可降低晶片或系統 取記憶體。為了便；^ ϋ成本的動態隨機存 : %用勳恶隨機存 丨丁 機存取記憶體，在性能不影變记體來取代靜態隨 憶體必需克服二個問題·· θ 、則下’動態隨機存取記 (1)内部更新作業必需透 ⑺耗電量必需降低。月化…亥置之外部作業； 如第1圖所示，其传氧 m /r JLU 取記憶體裝置1〇之示意：為：假：靜態隨機存 靜態隨機存取記憶體相容之存^ γ之、置中，一與 :ΐ η! ΐ 4和一陣列式動態記憶體晶格28來存 取育枓，藉由整合陣列式靜態記憶體晶格2 4和陣列式動離 記憶體晶格28 ’可以得到動態晶格較低整合成本之部分‘ 點以及靜態晶格較低待命電流之部分優點。一般典型的設 置上陣列式動態圮憶體晶格2 8通常製作地約略大些，以 便於執行龐大的主動模式之記憶轉換，而陣列式靜態記憶 體晶格24通常製作地小些，以便於保存在低電源模式狀離 下仍需維持之資料。 〜 在該結構中，一更新控制器32係用來週期性地更新所 有於陣列式動態記憶體内之晶格以避免記憶狀態消失。該 類型之假性靜態隨機存取記憶體裝置亦得設有一省電模式 ’此時的更新控制器3 2是關閉的，在這狀態時，所有在陣 列式動態記憶體晶格2 8内的資料都會消失，而只有在陣列 式靜態記憶體晶格2 4内的資料才會保留下來。習知技術中 的假性靜態隨機存取記憶體最大的缺點在於它需要陣列式 584859 五、發明說明（3) " ' 靜態€憶體晶格24來進行省電模式，該陣列式靜態記憶體 晶格24對於積體電路佈局而言，由於它較大的晶格大小所 以無法達到成本效益功能，而無法將資料保留於動態陣列 中亦造成了嚴重的應用問題和程式設計上的限制。 習知的許多專利案係有關於動態隨機存取記憶體裝置 的更新控制。Song的美國專利案第6, 094, 7〇5號案，描述了 一於動態隨機存取記憶體内使用選擇性更新功能之降低電 源消耗的方法和系統，該方法使用了有效的、與一列記憶 體裝置相連接之位元來指出是否該列需要進行更新，此 法無法與一標準靜態隨機存取記憶體或假性靜態隨機存取 記憶體、電路相容。Beiley et al的美國專利案第5, 724, 2 9 5號案，亦揭示了一動態隨機存取記憶體電路，當配置 (all〇cate)過多的（redundant)電路時，可啟動或關閉陣 列式的動態隨機存取記憶體的隔板。Vishin的美國 案第6, 3丨丨，280號案則揭示了 一攜帶式的數位收音機之低 耗電記憶體系統，其中，動態隨機存取記憶體資料 以 選擇性地更新或不更新以便於儲存電源。 【發明之内容】 本發明的主要目的，在於創作出一種有效且可製 假性靜態隨機存取記憶體電路。 本發明的次要目的，在於創作出一種具有離隨 機存取記憶體相容之存取控制器、和一陣列式動態記；體 ，假性靜態隨機存取記憶體電路，以便於降低待命電：的 消耗。 ” 584859 五、發明說明（4) 本發明的 消耗之假性靜 格内提供局部 本發明的 活性（fiexibi 再一目的，在於創 態隨機存取記憶體 資料的保存能力。 又一目的，在於創 lity)之省電模式 為資料不予保存。 另一目的，在於創 相容之電路。 式】 明目的係藉由一依 本發明的 或混合記憶體 【解決方 上述本發 述之假性靜態 申請專利範圍 的額外結構。 【功效】 依據本發 憶體積體電路 之陣列式記憶 提供從一外部 ，該存取控制 之性能相容； 模式，藉由該 為選擇性的更 作出一種可降低待命電流 電路，並於陣列式動態晶 作出種可提供兩種高靈 -為局部:身料保存、另 作出一種與—動態、靜態 隨機存取記憶體電 的附屬項係陳述本 明之目的，係藉由 裝置，主要包括一 體，以及一存取控 裝置至該陣列式記 器的性能與 此外，該存 模式可達到 一標準 取控制 至少 新，以及至少其它 為不予以更新之目的。 為求進一步瞭解本發明之構 據申請專利範圍第1項所 路的特徵來達成。於其它 發明之具有優點及目的性 一種假性靜態隨機存取記 具有複數個動態儲存晶格 制器，其中該存取控制器 憶體的讀/寫存取. ，態隨機存取記憶體裝置 器係啟動一局部資料保存 部分的該陣列式記憶體可 部分的該陣列式記憶體可 造特徵、技術内容與功能 五、發明說明（5) 月〆閱以下有關本發明之詳細 示乃供參考與說明用，並】ς附圖，然而所附圖 【實施方式】 卩用以對本發明施予限制者。 本發明之實施例揭示了—種^ ^ ^ ^ 。惟以ΐ %：： 局部資料保存（PDR)和省電模a 惟以下所述者，僅為本發明之較 電杈式 來限定本發明之範圍，即凡依 ；::二已’並非用 均等變化與修飾，皆為本發卜專利砣圍所作之 如第2圖所示，係本發二 路之較佳實施例，尤指一且 =酼機存取記憶體電 多重要特= = = :積：電路5〇。本發明的許 之陣列式紀愔T 具有稷數個動態儲存晶格 和其它習知之支持性電路；該陣 態，並以包括許多單一電晶體晶格為=的曰曰格^十和型 所有二存取控制器60廣泛定義為 部動態記憶體68之電處^ ¢7 4^ ^ M Mr ·« + . P 在實際應用上，存取控制得 ^ . r ^ mu ipllClty)的資料區塊（block)和資料子 了一 21〇ck)，其得以進行多樣性的分割（partition) ,jf :二’ f取控制器6〇提供了從一外部裝置，例如微 处口，到該陣列式内部動態記憶體68的讀寫存取，但在 五、發明說明（6) 作為一重要特徵時，該存取控 準靜態隨機存取記憶體褒置 $為60的表現就必需與一標 體結構、控制線路定義和 ，相符。換言之，I /0實 標準靜態隨機存取記愔髀馬存取程序都必需與習知的 此外，作為本發相符且相容。 得啟動一局部資料保存（PD 要特徵，該存取控制器60 係定義為至少陣列式内％ ^ μ。部身料保存（PDR)模式 新、以及至少陣歹,;=:=，憶_-部分的w ’於陣列式内部動態記憶體6;内己ϊ Γ更8 J : : t =更新 維持有效的資料狀態…旦是 ：：f新之部分或區塊可 無效（invalid)。 每』並未更新的區塊將變成 更新控制器72啟動陳别彳& ^ 乂 能。該更新控制器72係為一 態：憶體68的更新功 部動態記憶體68内晶格之資料狀；：可二中廡該陣列式内 後該狀態再予以更新或重新讀^曰J感應或項取，然 以維持資料的有效狀能期性地不斷重覆該程序 ，該更新控 ==能另-重要特徵上 而月b列主少兩種運作辟能，铱 ^ =該更新控制器72必需無選擇性地、週期：地更；J 於陣列式内部動態記憶體68内之區塊； 有 :::控制器72僅針對陣列式内部動態記憶刪二定 [塊進行選擇性地更新，該第二狀態即為所謂 保存（PDR)模式，也是本發明的最重要特徵之一。。貝；斗 在本發明的假性靜態隨機存取記憶體裝置50的較佳實 第10頁 584859V. Description of the invention (2) Replacement of the vessel can reduce the chip or system access memory. For convenience; ^ ϋDynamic random storage of cost:% use random memory to store memory, and use memory to access memory. When performance does not change memory, replace static memory. Two problems must be overcome ... θ, then ' Dynamic random access (1) The internal update operation must be transparent and the power consumption must be reduced. Moonlight ... Haizhi's external operations; as shown in Figure 1, the schematic diagram of its oxygen transfer m / r JLU and memory device 10 is: false: static random memory static random access memory compatible memory ^ The center of γ, an AND: ΐ η! ΐ 4 and an array-type dynamic memory lattice 28 to access the education system, by integrating the array-type static memory lattice 2 4 and the array-type movable memory crystal Lattice 28 'can get part of the lower integration cost of the dynamic lattice' point and some advantages of lower standby current of the static lattice. On a typical setting, the array type dynamic memory cell lattice 2 8 is usually made slightly larger in order to perform a large active mode memory conversion, and the array type static memory lattice 24 is generally made smaller in order to facilitate Stores data that needs to be maintained in low power mode. ~ In this structure, an update controller 32 is used to periodically update all the lattices in the array type dynamic memory to prevent the memory state from disappearing. This type of pseudo static random access memory device must also be provided with a power saving mode. At this time, the update controller 32 is turned off. In this state, all the devices in the array dynamic memory lattice 28 The data will disappear, and only the data in the array static memory lattice 24 will be retained. The biggest shortcoming of the pseudo static random access memory in the conventional technology is that it requires an array type 584859. V. Description of the invention (3) " 'Static memory cell 24 for power saving mode, the array type static memory For the integrated circuit layout, the bulk lattice 24 cannot achieve cost-effective functions due to its large lattice size, and the inability to retain data in the dynamic array also causes serious application problems and programming limitations. Many known patents relate to update control of dynamic random access memory devices. Song's U.S. Patent No. 6,094,705, describes a method and system for reducing power consumption by using a selective update function in a dynamic random access memory. The method uses an effective Bits connected to the memory device to indicate whether the row needs to be updated. This method is not compatible with a standard static random access memory or a pseudo static random access memory, or circuit. Beiley et al. US Patent No. 5,724, 295 also discloses a dynamic random access memory circuit. When all excess circuits are configured, the array can be turned on or off. A partition of dynamic random access memory. Vishin's U.S. Case No. 6, 3 丨 丨, 280 discloses a low power consumption memory system of a portable digital radio, in which dynamic random access memory data is selectively updated or not updated to facilitate Store power. [Summary of the Invention] The main object of the present invention is to create an effective and pseudo static random access memory circuit. A secondary object of the present invention is to create an access controller with compatibility with random access memory and an array type dynamic memory; a pseudo static random access memory circuit to reduce standby power. : Consumption. 584859 V. Description of the invention (4) The consumption of the present invention provides local activity of the present invention within a false static grid (fiexibi's other purpose is to maintain the ability to create random access memory data. Another object is to create The power saving mode of lity) is that the data is not saved. Another purpose is to create compatible circuits. Formula] The purpose is to use a solution according to the present invention or mixed memory Additional structure in the scope of patent application. [Effectiveness] According to the array memory of the volume memory circuit provided by the Memories, the performance of the access control is compatible from the outside; The mode, by making it optional, can reduce the standby time. The current circuit and seeding on the array type dynamic crystal can provide two kinds of high spirits-for local: body preservation, and another kind of-dynamic, static random access memory. The subsidiary items of electricity are stated for the purpose of this article. The performance of the device, including an integrated body, and an access control device to the array register, and in addition, the storage mode can achieve a standard access control at least New and at least other purposes are not updated. In order to further understand the features of the present invention, it is achieved according to the characteristics of the first patent application scope. A pseudo static random access that has advantages and purpose in other inventions The recorder has a plurality of dynamic storage lattice controllers, in which the access controller reads / writes the memory. The state random access memory device device activates a local data storage portion of the array-type memory. Features, technical content and functions of the array memory can be made. 5. Description of the invention (5) The following detailed description of the present invention is for reference and explanation, and the drawings, but the attached drawings [implementation] [Method] 卩 is used to impose restrictions on the present invention. The embodiments of the present invention disclose a kind of ^ ^ ^ ^. However, ΐ% :: Partial Data Preservation (PDR) and power saving mode a The scope of the present invention is defined by the more electronic version of the present invention, that is, Fanyi ;: Erji 'is not used for equal changes and modifications. It is all made by the present patent as shown in Figure 2. The better way The embodiment, especially one, and how important it is to access the memory of the computer ===: product: circuit 50. The array array method of the present invention has several dynamic storage lattices and other known Supporting circuit; this array is widely defined as the electrical place of the dynamic memory 68 with a number of single-transistor crystal lattices = ^ ^ and all two access controllers 60 ^ ¢ 7 4 ^ ^ M Mr · «+. P In practical applications, the access control is ^. R ^ mu ipllClty) block (block and data block 21 ck), which can be divided in a variety of ways (partition ), jf: The f f controller 60 provides read and write access from an external device, such as a micro processor, to the array-type internal dynamic memory 68, but in V. Invention Description (6) as a The important feature is that the performance of the access control quasi-static random access memory setting $ 60 must be consistent with a standard structure and control circuit definition. In other words, the I / 0 real standard static random access memory access program must be consistent with and compatible with the conventional ones. You must start a local data save (PD is a feature, the access controller 60 is defined as at least% ^ μ in the array type. The new body shape save (PDR) mode is new, and at least arrays,; =: =, recall_ -Part of w 'in the array-type internal dynamic memory 6; internal self ϊ 更 more 8 J:: t = update maintains a valid data state ... once: f new parts or blocks can be invalid. Each "The blocks that have not been updated will become the update controller 72 to start Chen Bie 彳 & ^ No. The update controller 72 is in a state: the state of the data in the lattice of the dynamic memory 68 of the memory 68's update function ;: The state can be updated or re-read after the array is stored in the array. J induction or term fetching can be repeated to maintain the effective state of the data and the process can be repeated periodically. The update control == able Another important feature is that there are two main operations in the month b column. Iridium ^ = The update controller 72 must be non-selectively and periodically: the ground is changed; J is the block in the array-type internal dynamic memory 68; There are ::: controllers 72 that are only updated for array-type internal dynamic memory. The state is the so-called preservation (PDR) mode, and it is also one of the most important features of the present invention. The best practice of the pseudo static random access memory device 50 of the present invention is page 10 584859
施例中， 行三種模 一。在第 體電路50 新於陣列 係為局部 器7 2僅針 新；第三 存取控制 式内部動 假性靜 式中之 一種模 之兩運 式内部 資料保 對陣列 種模式 器60處 態記憶 態隨機存取記憶體積體電路5 〇是有能力執 任一模式，這些運作模式請參閱下列之表 式中，相對於假性靜態隨機存取記憶體^ 作的主動和待命狀態，該更新控制器72更 動態記憶體6 8内之所有區塊；第二種模式 存（PDR)的運作模式，其中，該更新控^ 式内部動態記憶體68内的特定區塊予以更 為一深度電源關閉（DPD)模式，其中，节 於關閉狀態，因此，無法更新任何於陣 體68内的區塊。 假性靜態隨機存取記憶體的更新運作模式 更新運作結果 更新所有區塊 更新特定區塊 不更新任何區塊 k i靜態隨機存取記憶體的 運作模式 主動和待命 =部資料保存（PDR) 深度電源關閉（DPD) 用可二記憶體積體電路50之運作模式㈣ 號來進行控制=存取記憶體標準運作相容之控制; 更新狀態之間進;制訊號是需要於全更新狀態和局: 體積體電路50以運你。然而，忒假性靜態隨機存取記 電路5〇μ運作於四種模式：±動、待命、局部:】:In the embodiment, three modes are performed. The first body circuit 50 is new to the array system, and the local device 7 2 is only new; the third access control type is one of the two modes of internal dynamic and static type. The internal data is guaranteed to the state memory of the array type modeler 60. The state random access memory volume circuit 5 is capable of performing any mode. For these operating modes, please refer to the following table. Compared to the active and standby states of the pseudo static random access memory ^, the update control The device 72 further updates all blocks in the dynamic memory 6.8; the second mode of storage (PDR) operation mode, in which specific blocks in the update control internal dynamic memory 68 are further powered down (DPD) mode, in which the node is in a closed state, and therefore, any blocks in the array 68 cannot be updated. Update operation mode of pseudo static random access memory Update operation results Update all blocks Update specific blocks Do not update any blocks Ki Operation mode of static random access memory Active and standby = Department of data preservation (PDR) Deep power Close (DPD) Control with the operation mode 可 of the two-volume memory circuit 50 = access to the memory's standard operation compatible control; progress between update states; the signal needs to be in the full update state and round: volume The body circuit 50 carries you. However, the pseudo static random access memory circuit 50μ operates in four modes: ± active, standby, local:]:
584859 五、發明說明（8) ' ' "一" 保存（PDR)和深度電源關閉（DPD)模式，其中之一為最佳，_ ，了能夠在這些模式中進行選擇，則需要兩種控制訊號。. 在較佳實施例中係使用CSB和ZZB兩種控制訊號。在定義一 四種模式、且與習知靜態隨機存取記憶體的運作相符之功 能性的狀態表格上有兩種較佳的方式，同時也增加局部資 · 料保存（PDR)功能，運作模式的第—種狀 格係 下面的表二中。 表二：運作模式的第一種狀態表 CSB 0 1 0 1 ZZB 1 1 0 運作模式 主動 待命 局部資料保存（PDR) 深度電源關閉（DPD)模式 替代型（alternative)狀態表係表示於表三。 表三：運作模式的替代型（alternative)狀態表 運作模式 主動 待命 局部資料保存（PDR) CSB011 ZZB110584859 V. Description of the invention (8) '' A 'Save (PDR) and Deep Power Off (DPD) mode, one of which is the best, _, to be able to choose among these modes, you need two Control signal. In the preferred embodiment, CSB and ZZB control signals are used. There are two better ways to define one or four modes and a functional state table that is consistent with the operation of the conventional static random access memory. At the same time, it also adds the function of local data storage (PDR) and the operation mode. The first-specific lattice is in Table 2 below. Table 2: The first status table of the operating mode CSB 0 1 0 1 ZZB 1 1 0 Operating mode Active Standby Partial Data Saving (PDR) Deep Power Off (DPD) Mode The alternative status table is shown in Table 3. Table 3: Alternative status table of operation mode Operation mode Active Standby Local data storage (PDR) CSB011 ZZB110
第12頁 584859 五、發明說明（9) 深度電源關閉（DPD)模式 〇 〇 再請參閱第2圖，在主動模式中，該假 取記憶體積體電路50係啟動來進行讀人寫動作^更^ 制器72更新於陣列式内部動態記憶體68内的所有區塊 itJi:寫=靜態隨機存取記憶體積體電路50裝置 無法進灯Μ寫，但陣列式内部動態記憶體μ的全 續進行的。另，選擇局部資料保存（pDR)模 、 里 仏模式疋在仍需維持動態記憶體的工作區時使用的 體ΪΪ，ΐΐί源關閉(DPD)模式是當不需保存任 仃忑it體狀悲、且當最低的電流消耗（current打心 d使曰用益的’在深度電源關閉（_)模式下，資料存取 Λ性靜疋離产機進/丁的。將局部資料保存（PDR)模式添加到 ，j貯L酼機存取記憶體是本發明的最重要特徵之一， 疋一項創新的能力，該創新式的特徵可讓低成太僅瓦 機存取記憶體具有-低耗=資= 關閉（DPD)模4 /局部資料保存（PDR)模式與深度電源 早留^ J王保召功此；有低電力下，眘斗a Α ;在極低電力下，資料無=。貝科僅可作部分的保留 擇以;=圖，如表二和表三所示之運作模式的選 才、式選擇區塊64來進行控制者為佳；該模式選 584859 五、發明說明（10) 擇區塊6 4係使用C S B和Z Z B的輸入來啟動上述之审 ,, <〜尺新運作握 式。本發明之較佳實施例另包括一局部資料保存（p⑽ 、 式結構暫存器（register)，藉由該局部資料保存 1 暫存器（PM C〇NFIG REG)64得以選擇陣列式内部動f 體68的特定區塊，以便於局部資料保存（pDR)模時—心 =更新。另外，局部資料保存（PDR)更新區塊亦硬 (hard-coded)至該設計中。 更、、扁碼 /接著，請參閱第3圖，本發明之另一實 ，靜態隨機存取記憶體積體電路5 〇中，係添 ^ ^ 態記憶體8 0以形成一組人々沾介 、’、、 車列式靜 體電路50，該實施例俜；f :,性靜態隨機存取記憶體積 保存= 式中。將局部資料 中係添加了使用上之、一、工的假丨生靜恶隨機存取記憶體 本發明之優點得：重要的、額外的靈活性。 一種有效且可製造之以:^結論：藉由本發明可創作出 性靜態隨機存取記憔^陸靜態隨機存取記憶體電路；該假 體相容之存取控制^電路’具有一與靜態隨機存取記憶 低待命電流的消耗士和一陣列式動態記憶體，以便於降 命電流消耗可予降低^饭性靜態隨機存取記憶體電路之待 資料的保存能力；另j ^時於陣列式動態晶袼内提供局部 之省電模式，一為兩種咼靈活性（flexibility) 最後，該電路係與二=^料保存，另一為資料不予保存； 如上述實施例所悲、靜態或混合記憶體相容。 ’具有局部資料保存（PDR)能力的 584859 五、發明說明（11) 創新式假性靜態隨機存取記憶體，係提供了 一相對於習知 技術之替代性的有效、且可製造的方法和系統。 惟以上所述者，僅為本發明之較佳實施例而已，並非 用來限定本發明之範圍。即凡依本發明申請專利範圍所作 之均等變化與修飾，皆為本發明專利範圍所涵蓋。Page 12 584859 V. Description of the invention (9) Deep power off (DPD) mode 〇 Refer to Figure 2 again. In the active mode, the fake memory volume circuit 50 is activated to read and write. ^ More ^ Controller 72 updates all blocks in array internal dynamic memory 68 itJi: write = static random access memory volume circuit 50 device cannot write to lamp M, but full internal array dynamic memory μ continues of. In addition, the local data saving (pDR) mode and the internal mode are selected for use in the work area where dynamic memory is still needed. The source-disabled (DPD) mode is used when the body is not required to be saved. , And when the lowest current consumption (current mind d makes good use of 'in the deep power off (_) mode, the data access is statically away from the production machine / D. Local data preservation (PDR) mode Adding to that, memory storage is one of the most important features of the present invention. 疋 An innovative ability, this innovative feature allows low-wattage memory access to memory with low power consumption. = 资 = Closed (DPD) mode 4 / Partial Data Preservation (PDR) mode and early retention of deep power ^ J Wang Baozhao credits this; under low power, be careful a Α; under extremely low power, data is not =. Beco Only part of the reservation can be selected; = diagram, as shown in Tables 2 and 3, the operation mode is selected, and it is better to select the block 64 to control; the mode is selected 584859 V. Description of the invention (10) Select block 6 4 uses CSB and ZZB input to start the above review, < ~ new operation grip type The preferred embodiment of the present invention further includes a local data storage (p⑽, type structure register), by which the local data storage 1 register (PM CONF REG) 64 can select an array-type internal motion f The specific block of the body 68, so that the local data storage (pDR) model time-heart = update. In addition, the local data storage (PDR) update block is also hard-coded into the design. More, flat code / Next, please refer to FIG. 3. In another embodiment of the present invention, a static random access memory volume circuit 50 is added with a state memory 8 0 to form a group of people. F :, static static random access memory volume storage = in the formula. In the local data is added the use of the first, the first, the work of false static and evil random access memory The advantages of the present invention are: important, additional flexibility. An effective and manufacturable: ^ Conclusion: With the present invention, a static static random access memory can be created. ^ A static random access memory circuit; the Prosthesis-compatible access control circuit has a random and static Low memory standby current consumption and an array type dynamic memory, in order to reduce the current consumption can reduce the storage capacity of the data of the static static random access memory circuit; the other is the array type The dynamic crystal chip provides local power-saving modes. One is two kinds of flexibility. Finally, the circuit is saved with two materials, and the other is not saved. As described in the above embodiments, static or static Mixed memory is compatible. '584859 with local data preservation (PDR) capabilities V. Description of the invention (11) Innovative pseudo-static random access memory, which provides an alternative effective, And manufacturable methods and systems. However, the above are only preferred embodiments of the present invention and are not intended to limit the scope of the present invention. That is to say, all equivalent changes and modifications made in accordance with the scope of patent application of the present invention are covered by the scope of patent of the present invention.
第15頁 584859 圖式簡單說明 【圖示之簡單說明】 第1圖係為—習知技術之假性靜態隨機存 裝置，其具有一與靜態隨機存取 之存取控制器、一陣列式靜態記 楚。•列式動態記憶體晶格之示意圖卜體晶格以及- 圖係為一本發明較佳實施例假 憶體積體電路裝置，1且有隨機存取記 憶體相容之存【；制=-：靜態隨機存取記 晶格，其中句e = j為以及一陣列式動態記憶體 第3圖係為本發明較佳1部資料保存（PDR)模式。 之陣列式靜態記d=:-附加至該裝置 態隨機存取記憶體鞋a日彳0以形成一組合式假性靜 【圖式元件號數參照】x置。 1〇、50...假性靜離' 2。…靜態隨機存取'己憮體存取記憶體 24…陣列式靜態記憶；容之存取控制器 28…陣列式動態記憶體曰曰:‘ CSB，ETC ···控制線路 …資料/位址 32…更新控制器 塔 60 64 68 72Page 15 584859 Simple description of the diagram [Simplified description of the diagram] Figure 1 is a pseudo static random storage device of the conventional technology, which has an access controller with static random access, an array static Remember Chu. • Schematic diagram of the in-line dynamic memory lattice, and the lattice is a pseudo-memory volume circuit device according to a preferred embodiment of the present invention. 1 and a random access memory compatible memory [; system =-: static random The access record lattice, in which the sentence e = j, and an array type dynamic memory, FIG. 3 is a preferred data saving (PDR) mode of the present invention. Array static record d =:-Attached to the device state random access memory shoes a day 0 0 to form a combined pseudo-static [refer to the number of the figure element number] x set. 10, 50 ... pseudo-static separation '2. … Static random access 'own memory access memory 24… array type static memory; Rongzhi access controller 28… array type dynamic memory said:' CSB, ETC ··· Control circuit ... data / address 32 ... Update Controller Tower 60 64 68 72
靜態隨機存取記悴 模式選擇 g體相容之存取控制器 陣列式動態記憶體晶袼 更新控制器Static random access memory mode selection g-body compatible access controller array type dynamic memory crystal update controller
第16頁 584859 圖式簡單說明 76…局部資料保存模式配置暫存器 CSB，ZZB…控制線路 Do-Dn, ETC...資料/位址線路 80…陣列式靜態記憶體晶格Page 16 584859 Brief description of the diagram 76… Registration register for local data saving mode CSB, ZZB… Control line Do-Dn, ETC ... Data / address line 80… Array type static memory lattice
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