TW577144B

TW577144B - Damascene process capable of preventing punch through of etching stop layer

Info

Publication number: TW577144B
Application number: TW92100128A
Authority: TW
Inventors: Chao-Cheng Chen; Kang-Cheng Lin
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2003-01-03
Filing date: 2003-01-03
Publication date: 2004-02-21
Also published as: TW200412648A

Abstract

A damascene process capable of preventing punch through of etching stop layer comprises: sequentially forming an etching stop layer and a dielectric layer on a substrate, and covering the metal layer in the substrate; performing a first patterning process to form a via going through the dielectric layer on the active region; forming a first photoresist layer on the dielectric layer in the active region and filling up the via layer; performing a second patterning process to form a first trench going through the dielectric layer in the seal ring region; removing a portion of the first photoresist layer allowing the dielectric layer to be left with the first photoresist layer; forming a second photoresist layer on the dielectric layer and filling up the trench; and partially etching back the second photoresist layer allowing the trench to be left with the second photoresist layer. According to the present invention, there is no need in considering the difference in etching rate between the via layer and the first trench, thereby avoiding the etching stop layer from being punched through.

Description

577144577144

[發明所屬之技術領域] 本發明是有關於半導體積體電路（semicQnduetQi_ ICs)之製程技術，特別是有關於避免蝕刻停止層 Stop layer)被钱穿（punch through)的鑲嵌製程 (damascene process ) 〇 [先前技術] 近年來’為了配合積體電路元件尺寸縮小化的發展以及提高元件操作速度的需求，具有低電阻常數和高電子遷移阻抗的銅金屬，已逐漸被應用來作為金屬内連線的材質，取代以往的鋁金屬製程技術。銅金屬的鑲礙式 (damascene)内連線技術，不僅可達到内連線的縮小化並且可減少RC時間延遲，同時也解決了金屬銅蝕刻不易的問題’因此已成為現今多重内連線主要的發展趨勢。在習知的銅内連線之錶肷製程中，由於介層窗（或稱接觸孔’ via)與密封環（seal ring)或墊（pad)的溝槽係在同一蝕刻製程中形成，然而習知製程會有許多缺點，以下利用第1 A〜第1 D圖所示的銅鑲嵌製程示意圖，來說明習知技術之缺點。首先，請參照第1 A圖，第1 A圖係剖面示意圖，提供具有一銅金屬層11〇(例如第一層金屬層）的一基底1〇〇，該基底100具有既定之一主動區（active area)120與一密封環 (seal ring)區1 25。然後，形成一蝕刻停止層1 30於該基底1 0 0上，並覆蓋該銅金屬層1 1 0。然後，形成一金屬間介[Technical Field to which the Invention belongs] The present invention relates to a process technology of semiconductor integrated circuits (semicQnduetQi_ICs), and in particular to a damascene process in which the stop layer of the etching stop layer is punched through. [Previous technology] In recent years, in order to meet the development of the reduction in the size of integrated circuit components and the need to increase the speed of component operation, copper metals with low resistance constants and high electron migration resistance have gradually been used as metal interconnects. Material, replacing the traditional aluminum metal process technology. The damascene interconnect technology of copper metal can not only reduce the interconnect size and reduce the RC time delay, but also solve the problem of difficult copper metal etching. Therefore, it has become the main issue of multiple interconnects today. Development trend. In the conventional surface forming process of copper interconnects, since the vias (or contact holes' via) and the grooves of the seal ring or pad are formed in the same etching process, however, There are many shortcomings in the conventional manufacturing process. The following uses the schematic diagram of the copper inlaying process shown in Figures 1A to 1D to illustrate the shortcomings of the conventional technology. First, please refer to FIG. 1A. FIG. 1A is a schematic cross-sectional view. A substrate 100 having a copper metal layer 110 (for example, a first metal layer) is provided. The substrate 100 has a predetermined active area ( active area) 120 and a seal ring area 1 25. Then, an etch stop layer 130 is formed on the substrate 100 and covers the copper metal layer 110. Then, an intermetallic is formed

0503-8879TW(Nl) ； TSMC2002-0557 ； Jacky.ptd 第5頁 577144 五、發明說明（2) 電層（intermetal layer， IMD) 140於該蝕刻停止層130 上。接著，請參照第1 B圖，第1 B圖係一立體示意圖，進行一圖案化製程，利用電漿餘刻（p 1 a s m a e t c h i n g )去除部分該金屬間介電層1 4 0而形成介層窗（v i a ) 2 2以及溝槽 (trench) 33。由於介層窗22的開孔尺寸遠小於溝槽33的開口尺寸’所以溝槽3 3的#刻速率（e t c h i n g r a ΐ e )遠大於介層窗2 2的餘刻速率，因此常常造成有蝕刻停止層丨3 〇被蝕穿（punch through)的問題，蝕穿之處44會露出銅金屬層 110。此日^會使得銅金屬層110容易產生缺陷（defect)及造成銅污染’影響產品良率’更者，電漿餘刻的電子可能會集中至姓穿之處44，而造成晶圓尖端放電（wafer arcing) 而損害元件。接著’明參知弟1 C圖’弟1 c圖係剖面示意圖，為了要得到較為平坦之一表面，以利後續製程之進行，則必須要將第一能量感應層1 5 0 (例如光阻層）塗佈於該金屬間介電贗1 4 0上並填滿介層窗2 2與溝槽3 3。然後，再經部分回蝕 (etching back)而露出金屬間介電層14〇表面。然而，由於介層窗22的開孔尺寸遠小於溝槽33的開口尺寸，所以溝槽33的蝕刻速率（etching rate)遠大於介層窗“的蝕刻速率，因此，得殘留在介層窗22與溝槽33的剩餘第一能量感應層1 5 0 ’高度差別仍大，如第丨D圖所示。所以必須進行第二回光阻沉積/回蝕之製程，甚至第三回’因而增加製造成本。0503-8879TW (Nl); TSMC2002-0557; Jacky.ptd Page 5 577144 V. Description of the invention (2) An intermetal layer (IMD) 140 is on the etch stop layer 130. Next, please refer to FIG. 1B. FIG. 1B is a three-dimensional schematic diagram. A patterning process is performed, and a part of the intermetal dielectric layer 1 4 0 is removed by using plasma etch (p 1 asmaetching) to form a dielectric window. (Via) 2 2 and trench 33. Because the opening size of the via 22 is much smaller than the opening size of the trench 33, the #etching rate (etchingra ΐ e) of the trench 3 3 is much higher than the remaining etch rate of the via 22, so it often causes an etch stop. The problem that the layer 3 is punched through, the copper metal layer 110 is exposed at the etched place 44. On this day ^, the copper metal layer 110 will be prone to defects and copper contamination 'affecting product yield'. Furthermore, the electrons in the plasma may be concentrated at the place where the surname is penetrated44, causing the wafer tip to discharge. (Wafer arcing) and damage the component. Next, 'Mingshen Zhidi 1 C' is a cross-sectional schematic diagram. In order to obtain a relatively flat surface for the subsequent process, the first energy sensing layer 15 0 (such as photoresist Layer) is coated on the intermetal dielectric 1400 and fills the interlayer windows 22 and the trenches 33. Then, the surface of the intermetal dielectric layer 14 is exposed through a partial etch back. However, since the opening size of the via window 22 is much smaller than the opening size of the trench 33, the etching rate of the trench 33 is much higher than the etching rate of the via window, and therefore, it remains in the via window 22 The height difference between the remaining first energy-sensing layer 150 ′ of the trench 33 is still large, as shown in FIG. 丨 D. Therefore, a second photoresist deposition / etchback process must be performed, and even the third process is increased. manufacturing cost.

0503>8879TW(N1) ； TSMC2002-0557 ； Jacky.ptd 第6頁 577144 五、發明說明（3) 么=如’請參照第1 D圖，第1D圖係剖面示意圖，塗佈第二能量感應層（例如是光阻層，未圖示）於該金屬間介電層上3並填滿介層窗22與溝槽33 °然後’再經部分回1虫第二能置感應層而露出金屬間介電層丨4 〇表面。如此使得殘留在介層窗2 2與溝槽3 3的剩餘能量感應層高度差別減小。符號160係剩餘第二能量感應層。目W有許多專利係揭示關於密封環（sea 1 r i ng )的結構設計’例如美國專利第57 2338 5號、第59295 〇9號與第 6 3 6 2 5 2 4號。然而該等資料皆沒有揭示或教導在進行鑲嵌與密封環溝槽的姓刻製程時，如何解決蝕刻停止層被蝕穿 (punch through)的方法。 [發明内容] 有鑑於上述習知技術的問題，本發明的目的在於提供一種鑲嵌製程，以確實防止蝕刻停止層被蝕穿，進而提高產品良率。 ° 根據上述目的，本發明提供一種避免蝕刻停止層被蝕穿的鑲嵌製程，包括下列步驟： 9 提供具有一金屬層的一基底，該基底具有既定之一主動區與一密封環（seal ring)區；形成一钱刻停止層於該基底上，並覆蓋該金屬層；形成一金屬間介電層於該姓刻停止層上；進行一第一圖案化製程，去除部分該金屬間介電層而形成至少一介層窗（via)穿越位在該主動區的該金屬間^介 577144 五、發明說明（4) 電層；形成一第一能量感應層於位在該主動區的該金屬間介電層上’並填滿該介層窗；以該第一能量感應層為罩幕，進行一第二圖案化製程，去除部分該金屬間介電層而形成至少一第一溝槽 (trench)穿越位在该密封壞區白勺該金屬間介電層，去除部分該第一能量感應層而露出該金屬間介電層表面，並使該介層窗中有殘留的該第一能量感應層；形成一第二能量感應層於該金屬間介電層上，並填滿該溝槽；以及 _ 部分回I虫該第二能量感應層而露出該金屬間介電層表面，其中該第一溝槽中有殘留的該第二能量感應層，該介層窗中有殘留的該第一能量感應層，如此即得到較為平坦之一表面，以利後續製程之進行。如此，由於介層窗（via)與溝槽（trench)係由不同之圖案化製程所形成，所以可以使蝕刻製程條件單純化，並且不用考慮介層窗與第一溝槽的蝕刻速率之差別，而避免蝕刻停止層被蝕穿，進而提高產品良率。此外，本發明僅需一回的光阻沉積/回蝕製程，就能填滿第一溝槽，而不必像習知般地要進行兩回以上的光阻0 沉積/回蝕製程，故能減少整體製造成本。為了讓本發明之上述目的·、特徵、和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：0503 > 8879TW (N1); TSMC2002-0557; Jacky.ptd Page 6 577144 V. Description of the invention (3) Mod = If 'please refer to Figure 1D, Figure 1D is a schematic cross-section diagram, coating the second energy sensing layer (For example, a photoresist layer, not shown) on the intermetal dielectric layer 3 and fills the dielectric window 22 and the trench 33 °, and then returns to the second energy sensing layer to partially expose the metal interlayer. The surface of the dielectric layer. This reduces the difference in height of the remaining energy-sensing layers remaining in the via window 22 and the trench 33. Symbol 160 is the remaining second energy sensing layer. There are many patents that disclose the structural design of a seal ring (sea 1 r ng), such as U.S. Patent Nos. 57 2338 5, 59295 009 and 6 3 6 2 5 2 4. However, none of these materials reveals or teaches how to solve the problem of punch through of the etch stop layer when performing the inscription and seal ring trench engraving process. [Summary of the Invention] In view of the problems of the above-mentioned conventional technology, an object of the present invention is to provide a damascene process to surely prevent the etching stop layer from being eroded, thereby improving the product yield. According to the above object, the present invention provides a damascene process to prevent the etching stop layer from being eroded, including the following steps: 9 Provide a substrate having a metal layer, the substrate having a predetermined active area and a seal ring Area; forming a coin stop layer on the substrate and covering the metal layer; forming an intermetal dielectric layer on the last stop layer; performing a first patterning process to remove part of the intermetal dielectric layer And forming at least one interlayer window (via) passing through the metal interposition in the active region ^ 577144 V. Description of the invention (4) electrical layer; forming a first energy sensing layer in the metal interposition interposing in the active region On the electrical layer and fill the dielectric window; using the first energy-sensing layer as a cover, a second patterning process is performed to remove at least one intermetal dielectric layer to form at least a first trench Pass through the intermetal dielectric layer located in the sealed bad area, remove part of the first energy sensing layer to expose the surface of the intermetal dielectric layer, and leave the first energy sensing layer in the dielectric window Form a second A volume sensing layer is on the intermetal dielectric layer and fills the trench; and _ part of the second energy sensing layer exposes the surface of the intermetal dielectric layer, and there is a residue in the first trench The second energy-sensing layer is left, and the first energy-sensing layer is left in the interlayer window. In this way, a relatively flat surface is obtained to facilitate subsequent processes. In this way, since the vias and trenches are formed by different patterning processes, the etching process conditions can be simplified, and the difference between the etching rates of the vias and the first trenches need not be considered. , And avoid the etching stop layer from being etched through, thereby improving product yield. In addition, the present invention only needs one photoresist deposition / etchback process to fill the first trench, and does not need to perform more than two photoresist 0 deposition / etchback processes as is conventional, so it can Reduce overall manufacturing costs. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows:

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第8頁 5771440503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd page 8 577144

實施方式：以下利用第2〜9圖所示之鑲嵌製程示意圖，以詳細地說明本發明。首先，請參照第2圖，提供具有一金屬層2丨〇 (例如第一層銅金屬層）的一基底2〇〇，該基底2〇〇具有既定之一主動區 Uctive area) 2 2 0 與一密封環（seal ring)區 2 25。然後’形成一姓刻停止層2 3 0於該基底2 0 0上，並覆蓋該金屬層210。然後，形成一金屬間介電層（intermetal ^ayer，Embodiments: The present invention will be described in detail by using the mosaic process schematic diagrams shown in Figs. 2 to 9 below. First, referring to FIG. 2, a substrate 200 having a metal layer 2 (such as a first copper metal layer) is provided, and the substrate 200 has a predetermined active area Uctive area 2 2 0 and A seal ring area 2 25. Then, a nick stop layer 230 is formed on the substrate 200 and covers the metal layer 210. Then, an intermetal dielectric layer (intermetal ^ ayer,

IMD) 2 4 0於該蝕刻停止層2 3 〇上。其中，該蝕刻停止層2 3 〇例如疋經由 >儿積法所形成之氮化石夕層或氮氧化石夕層，而該金屬間介電層2 4 0例如是經由沉積法所形成之二氧化石夕層或氟摻雜二氧化矽層（F S G)。接著，仍請參照第2圖，進行一第一圖案化製程，利用電漿蝕刻（plasma etching)去除部分該金屬間介電層 240而形成至少一介層窗（via)250穿越位在該主動區220的該金屬間介電層2 4 0。其中，該電漿蝕刻例如是採用c4 F8、 CH2F2或C5F8之蝕刻氣體，其製程條件例如是2〇m Torr、 200〜1200W 。IMD) 2 40 is on the etch stop layer 23. The etch stop layer 2 3 0 is, for example, a nitrided nitride layer or oxynitride layer formed by the > pediatric method, and the intermetallic dielectric layer 2 4 0 is formed by a deposition method, for example. Stone oxide layer or fluorine-doped silicon dioxide layer (FSG). Then, still referring to FIG. 2, a first patterning process is performed, and a part of the intermetal dielectric layer 240 is removed by plasma etching to form at least one via 250 passing through the active area. The intermetal dielectric layer of 220 is 2 40. The plasma etching is, for example, an etching gas using c4 F8, CH2F2, or C5F8. The process conditions are, for example, 20m Torr, 200 ~ 1200W.

接著，請參照第3圖，塗佈當作是圖案化罩幕層的一第一能量感應層310(energy sensitive layer，例如是光阻層photoresist layer)於至少位在該主動區220的該金屬間介電層2 4 0上，並填滿該介層窗2 5 0。接著，仍請參照第3圖，以該第一能量感應層3 1 0為罩Next, referring to FIG. 3, a first energy sensitive layer 310 (such as a photoresist layer) coated as a patterned mask layer is coated on the metal at least in the active region 220. An interlayer dielectric layer 2 40 is formed and fills the interlayer dielectric layer 2 50. Then, referring to FIG. 3 again, the first energy sensing layer 3 1 0 is used as a cover.

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第9頁 577144 五、發明說明（6) 幕’進仃一第二圖案化製程，利用電漿蝕刻（plasma etching)去除部分該金屬間介電層24〇而形成至少一第一溝槽（trench) 3 2 0穿越位在該密封環區225的該金屬間介電層2 4 0，這裡要特別說明的是，此步驟亦可同時定義晶圓上的其他溝槽（未圖示）。其中，該電漿蝕刻例如是採用 QF8、CHJ2或CJ8之蝕刻氣體，其製程條件例如是2〇m Torr、2 0 0〜1 2 0 0 W。這裡要特別提醒的是，由於該介層窗 2 5 0與該第一溝槽3 2 0係由不同之圖案化製程所形成，所以不用考慮該介層窗2 5 0的蝕刻速率與該第一溝槽3 2 〇的蝕刻0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd Page 9 577144 V. Description of the invention (6) The screen is advanced to a second patterning process, and plasma etching is used to remove part of the metal intermediary The electrical layer 24 is formed to form at least a first trench 3 2 0 through the intermetal dielectric layer 2 40 located in the sealing ring region 225. It should be particularly noted here that this step can also be defined at the same time. Other trenches (not shown) on the wafer. The plasma etching is, for example, an etching gas using QF8, CHJ2, or CJ8, and the process conditions are, for example, 20 m Torr, and 2000 to 1,200 W. It should be particularly reminded that, because the interlayer window 250 and the first trench 3200 are formed by different patterning processes, it is not necessary to consider the etching rate of the interlayer window 250 and the first trench 3020. Etching of a trench 3 2 0

速率之差別，而避免該蝕刻停止層2 3 0被蝕穿（pilnch through) 〇接著，請參照第4圖，第4圖係一立體示意圖，例如以氧電漿灰化（ashing)去除部分該第一能量感應層31 0而露出该金屬間介電層240表面，並使該介層窗250中有殘留的該第一能量感應層3 1 0，。接著，請參照第5圖，塗佈一第二能量感應層5 1 〇 (例如是光阻層）於該金屬間介電層2 4 0上，並填滿該第一溝槽 32 0。其中該第二能量感應層51〇當作是一犧牲材料。Speed difference to prevent the etching stop layer 2 3 0 from being etched through. Then, please refer to FIG. 4, which is a three-dimensional schematic diagram. For example, oxygen plasma ashing is used to remove part of the The first energy-sensing layer 31 0 exposes the surface of the intermetal dielectric layer 240 and leaves the first energy-sensing layer 3 1 0 ′ in the dielectric window 250. Next, referring to FIG. 5, a second energy sensing layer 5 1 0 (for example, a photoresist layer) is coated on the intermetal dielectric layer 2 40 and fills the first trench 32 0. The second energy sensing layer 51 is regarded as a sacrificial material.

接著，請參照第6圖，例如利用氧電漿灰化而部分回 I虫該第二能量感應層510而露出該金屬間介電層240表面，其中該第一溝槽3 2 0中有殘留的該第二能量感應層5 1 0，，該介層窗2 50中有殘留的該第一能量感應層310，，如此即得到較為平坦之一表面，以利後續製程之進行。這裡要特別提醒的是，本步驟僅需一回的光阻沉積/回蝕製程，就Next, referring to FIG. 6, for example, the second energy-sensing layer 510 is partially exposed by oxygen plasma ashing to expose the surface of the intermetal dielectric layer 240, and there is a residue in the first trench 3 2 0. The second energy-sensing layer 5 1 0, and the first energy-sensing layer 310 remaining in the interlayer window 2 50, so as to obtain a relatively flat surface to facilitate subsequent processes. It should be especially reminded that this step only requires one photoresist deposition / etchback process.

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第10頁 577144 五、發明說明（7) 能填滿該第一溝槽3 2 〇。此外’這裡要特別說明的是，雖然上述實施例之步驟係先形成介層窗2 5 0，然後再形成第一溝槽3 2 〇。然而事實上可以先形成第一溝槽3 2 〇，然後再形成介層窗2 5 〇，由於此製程與上述步驟類似，在此不再贅述。總之，本發明重點是介層窗2 5 0與第一溝槽3 2 〇係由不同之圖案化製程所形成’所以不用考慮介層窗2 5 〇的蝕刻速率與第一溝槽3 2 〇的餘刻速率之差別’而避免該蝕刻停止層2 3 〇被蝕穿。接著’說明後績鑲嵌製程，請參照第7〜9圖。請蒼照第7圖’先形成一第三能量感應層7 1 0 (例如是光阻層）於部分該金屬間介電層24〇上。然後，以該第三能量感應層710為罩幕（mask)，進行一第三圖案化製程，電装蝕刻去除部分該金屬間介電層24〇而形成一第二溝槽72〇與-第二溝槽73G於該金屬間介電層24Q中槽72 0與該介層窗2 5 0有重晶，# ^ ^ ^ 播μη亡舌晶 ^董宜，该第三溝槽730與該第一溝曰，麟/、 /亥電漿蝕刻例如是採用CJ8、CHJ2或 C5F8之蝕』齓脰，，、衣程條件例如 200〜1200W 。接著，請參照第8圖，彳丨 -能量感應層310,、該第二旦利用氧電漿灰化去除該第感應層710。然後，以短時月匕=感應層51〇’與該第三能量在該介層窗2 5 0與該第~溝^ 、、、π 〇秒内）電漿蝕刻去除位 23 0。其中，該電漿蝕刻例/ θ底部之該姓刻停止層並加入Ν2/02，其製程條件二'採用CF4或⑽3之蝕刻氣體」如疋5〇m Torr 、 500W 。0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd page 10 577144 V. Description of the invention (7) The first trench 3 2 can be filled. In addition, it is to be particularly noted here that although the steps of the above embodiment are to form the interlayer window 2 50 first, and then to form the first trench 3 2 0. However, in fact, the first trench 3 2 0 can be formed first, and then the interlayer window 2 5 0 can be formed. Since this process is similar to the above steps, it will not be repeated here. In short, the focus of the present invention is that the interlayer window 250 and the first trench 3 2 0 are formed by different patterning processes, so it is not necessary to consider the etching rate of the interlayer window 2 5 0 and the first trench 3 2 0. The difference in the remaining etching rate 'prevents the etch stop layer 23 from being etched through. Next ’explains the post-insertion process, please refer to Figures 7-9. According to FIG. 7 ', a third energy sensing layer 7 1 0 (for example, a photoresist layer) is formed on a part of the intermetal dielectric layer 240. Then, using the third energy sensing layer 710 as a mask, a third patterning process is performed, and a part of the intermetal dielectric layer 24 is removed by electrical etching to form a second trench 72o and a second trench. The trench 73G is recrystallized in the trench 72 0 and the dielectric window 2 50 in the intermetal dielectric layer 24Q. # ^ ^ ^ Broadcast μη dead tongue crystal ^ Dong Yi, the third trench 730 and the first The ditch said that Lin /, / Hai plasma etching is, for example, using CJ8, CHJ2 or C5F8, and the process conditions are 200 ~ 1200W. Next, referring to FIG. 8, the energy-sensing layer 310 and the second layer are removed by oxygen plasma ashing to remove the first sensing layer 710. Then, the plasma etching is used to remove the bit 23 by plasma etching with a short period of time = inductive layer 51〇 ′ and the third energy within the interlayer window 2 50 and the first trench ^,, and π seconds). Among them, the plasma etching example / the bottom engraved stop layer at θ is added with N2 / 02, and the process condition 2 is that the etching gas of CF4 or ⑽3 is used, such as 疋 50m Torr, 500W.

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第11頁 577144 五、發明說明（8) 接著，請參照第9圖，填入金屬材料（例如是鋼）於該介層窗2 5 0、該第二溝槽72 0、該第一溝槽3 2 0與該第三溝槽73〇，而形成一插塞（plug)910(例如是銅插塞）、一金屬連線9 2 0 (例如是銅連線）與一密封環9 3 〇 (例如是銅密封環）。之後，再進行一平坦化製程去除多餘之金屬。 [發明特徵與效果] 一根據本發明，由於介層窗（via)與溝槽（trench)係 :同之圖案化製程所形《，所以可以使蝕刻製程條件單 3?n的亚爲且^\考慮^亥介層窗250的餘刻速率與該$ 一溝才接 3 2 0的蝕刻速率之差別，再不曰進而提高產品良率。而避免该蝕刻停止層2 3 0被蝕穿，另外，本發明僅需— 填滿該第一溝槽25 0，而不Ί光^沉積/回㈣程，就能的光阻沉積/回#製程，般地要進行兩回以上雖然本發明已以較佳徐月"7 ^正體製造成本。限定本發明，任何孰習并汽她例揭露如上，然其並非用以神和範圍内，當可作更動T技藝者，在不脫離本發明之精當視後附之申請專利範圍^潤飾因此本發明之保護範圍礼阁所界定者為準。0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd Page 11 577144 V. Description of Invention (8) Next, please refer to Figure 9 and fill in the metal material (such as steel) in the interlayer window 2 5 0 , The second groove 72 0, the first groove 3 2 0 and the third groove 73 ° to form a plug 910 (for example, a copper plug) and a metal connection 9 2 0 (For example, a copper wire) and a seal ring 9 3 0 (for example, a copper seal ring). After that, a planarization process is performed to remove excess metal. [Features and Effects of the Invention] According to the present invention, since the vias and trenches are formed by the same patterning process, the conditions of the etching process conditions can be made 3 to n and ^ \ Consider the difference between the etch rate of the ^ Hai interlayer window 250 and the etching rate of the $ 1 groove before the 3 2 0, and further improve the product yield. In order to prevent the etching stop layer 230 from being etched through, in addition, the present invention only needs to-fill the first trench 250 without photo-resistance deposition / return process, and photoresist deposition / return # The manufacturing process generally takes two or more rounds, although the present invention has a better manufacturing cost. Limiting the present invention, any study and disclosure of her example are as above, but it is not used within the scope of the gods. When you can make changes to T skills, you can attach the scope of patents attached without departing from the essence of the present invention. The scope of protection of the present invention shall be as defined by the court.

577144 圖式簡單說明第1 A〜1 D圖為習知鑲嵌製程的示意圖。第2〜9圖為根據本發明實施例之鑲嵌製程的示意圖。 [符號說明] 習知部分（第1A〜1D圖） 100〜基底； 1 10〜銅金屬層； 120〜主動區； 125〜密封環區； 1 3 0〜蝕刻停止層； 1 4 0〜金屬間介電層； 22〜介層窗（vis) ; 33〜溝槽（trench); 44〜蝕穿之處； 1 5 0〜第一能量感應層（例如是光阻層）； 1 5 0 ’〜剩餘之第一能量感應層； 1 6 0〜剩餘之第二能量感應層。本案部分(第2〜9圖） 2 0 0〜基底； 210〜金屬層； 2 2 0〜主動區； 2 2 5〜密封環區； 2 3 0〜餘刻停止層； 2 4 0〜金屬間介電層； 250〜介層窗（via); 3 1 0〜第一能量感應層（例如是光阻層）； f 31 0 ’〜剩餘之第一能量感應層； 320〜溝槽（trench); 5 1 0〜第二能量感應層（例如是光阻層）； 51 0 ’〜剩餘之第二能量感應層；577144 Brief description of the drawings Figures 1 A to 1 D are schematic diagrams of the conventional mosaic process. Figures 2-9 are schematic diagrams of a mosaic process according to an embodiment of the present invention. [Symbol description] Conventional part (Figures 1A ~ 1D) 100 ~ substrate; 1 10 ~ copper metal layer; 120 ~ active area; 125 ~ seal ring area; 1 3 0 ~ etch stop layer; 1 4 0 ~ metal Dielectric layer; 22 ~ visor window; 33 ~ trench; 44 ~ etched place; 150 ~ first energy sensing layer (for example, photoresist layer); 150 '~ The remaining first energy-sensing layer; 160 to the remaining second energy-sensing layer. Part of the case (Figures 2 to 9) 2 0 0 ~ substrate; 210 2 ~ metal layer; 2 2 0 ~ active area; 2 2 5 ~ sealing ring area; 2 3 0 ~ remaining stop layer; 2 4 0 ~ metal Dielectric layer; 250 ~ via window; 3 1 0 ~ first energy sensing layer (for example, photoresist layer); f 31 0 '~ remaining first energy sensing layer; 320 ~ trench 5 1 0 ~ second energy sensing layer (for example, photoresist layer); 51 0 '~ remaining second energy sensing layer;

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第13頁 5771440503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd page 13 577144

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第14頁0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd page 14

Claims

577144 六、申請專利範圍 1. 一種避免姓刻停止層被钱穿的鑲欲製程，包括下列步驟：提供具有一金屬層的一基底，該基底具有既定之一主動區與一密封環（seal ring)區；形成一餘刻停止層於該基底上，並覆蓋該金屬層；形成一金屬間介電層於該钱刻停止層上；去除部分該金屬間介電層而形成至少一介層窗（via) 穿越位在該主動區的該金屬間介電層；形成一圖案化罩幕層於位在該主動區的該金屬間介電層上，並填滿該介層窗；去除部分該金屬間介電層而形成至少一第一溝槽 (trench)穿越位在該密封環區的該金屬間介電層；填入一犧牲材料於該溝槽中；以及對該基底進行一平坦化程序而得到之一平坦表面，以利後續製程之進行。 2. 如申請專利範圍第1項所述之避免钱刻停止層被# 穿的鑲嵌製程，在形成該圖案化罩幕層於位在該主動區的該金屬間介電層上並填滿該介層窗之後，更包括下列步驟：去除部分該圖案化罩幕層而露出該金屬間介電層表面，並使該介層窗中有殘留的該圖案化罩幕層。 3. 如申請專利範圍第1項所述之避免蝕刻停止層被蝕穿的鑲嵌製程，更包括下列步驟：形成一能量感應層於部分該金屬間介電層上；577144 VI. Application for Patent Scope 1. An inlaying process to prevent the last name engraving stop layer from being worn by money, including the following steps: Provide a substrate with a metal layer, the substrate having a predetermined active area and a seal ring ) Area; forming a stop layer on the substrate and covering the metal layer; forming an intermetal dielectric layer on the stop layer; removing a part of the intermetal dielectric layer to form at least one dielectric window ( via) through the intermetal dielectric layer located in the active area; forming a patterned mask layer on the intermetal dielectric layer located in the active area and filling the dielectric window; removing part of the metal Inter-dielectric layer to form at least a first trench passing through the inter-metal dielectric layer located in the seal ring region; filling a sacrificial material in the trench; and performing a planarization process on the substrate A flat surface is obtained to facilitate subsequent processes. 2. As described in item 1 of the scope of the patent application, the inlay process to prevent the money-cut stop layer from being penetrated by # is used to form the patterned mask layer on the intermetal dielectric layer in the active area and fill the After the interlayer window, the method further includes the following steps: removing part of the patterned mask layer to expose the surface of the intermetal dielectric layer, and leaving the patterned mask layer in the interlayer window. 3. The damascene process for preventing the etching stop layer from being penetrated as described in item 1 of the scope of the patent application, further comprising the following steps: forming an energy sensing layer on part of the intermetal dielectric layer;

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第15頁 577144 六、申請專利範圍以該能槽於該金屬疊，該第三去除該去除位層；以及填入金與該第三溝 4 ·如申穿的鑲嵌製 5 ·如申穿的鑲嵌製層。 6.如申穿的鑲嵌製雜二氧化矽 7 ·如申穿的鑲嵌製層窗的方法 8 ·如申穿的鑲嵌製一溝槽的方 9 ·如申穿的鑲嵌製請專利範程，其中層（FSG)' 請專利範程，其中係採用電請專利範程，其中法係採用請專利範程，其中量感應層為罩幕，定義一第二溝槽與一第三溝間介電層中，其中該第二溝槽與該介層窗有重溝槽與該第一溝槽有重疊；圖案化罩幕層、該犧牲材料與該能量感應層；在該介層窗與該第一溝槽底部之該蝕刻停止屬材料於該介層窗、該第二溝槽、該第一溝槽槽，而形成一插塞、一金屬連線與一密封環。請專利範圍第1項所述之避免蝕刻停止層被蝕程，其中該金屬層係銅金屬層。請專利範圍第1項所述之避免蝕刻停止層被蝕程，其中該蝕刻停止層係氮化矽層或氮氧化矽圍第1項所述之避免蝕刻停止層被蝕該金屬間介電層係二氧化矽層或氟摻 ) 圍第1項所述之避免蝕刻停止層被蝕去除部分該金屬間介電層而形成該介漿蝕刻製程。圍第1項所述之避免I虫刻停止層被I虫去除部分該金屬間介電層而形成該第電漿#刻製程。圍第3項所述之避免蝕刻停止層被蝕該圖案化罩幕層、該犧牲材料與該能0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd Page 15 577144 Sixth, the scope of the patent application is to use the energy slot in the metal stack, the third remove the removal bit layer; and fill the gold with the third trench 4 · Mosaic system as applied by Rushen 5 · Mosaic system as applied by Rushen. 6. Rushen wear-inlaid heterogeneous silicon dioxide 7 · Rushen wear-inlaid laminated window method 8 · Rushen wear-inlaid one trench 9 · Russon wear-inlaid please apply for patent procedures, The middle layer (FSG) 'patent-seeking process, which uses the patent-seeking process, where the law system uses the patent-seeking process, where the volume-sensing layer is a mask that defines a second trench and a third trench. In the electrical layer, wherein the second trench and the interlayer window have heavy trenches overlapping the first trench; the patterned mask layer, the sacrificial material and the energy sensing layer; between the interlayer window and the The etching stop material at the bottom of the first trench is formed on the via window, the second trench, and the first trench groove to form a plug, a metal connection, and a sealing ring. The process of avoiding the etch stop layer described in item 1 of the patent scope is required, wherein the metal layer is a copper metal layer. The etch stop layer described in item 1 of the patent scope is etched, wherein the etch stop layer is a silicon nitride layer or a silicon oxynitride layer. It is a silicon dioxide layer or fluorine doped) as described in item 1 to prevent the etching stop layer from being etched away to remove a part of the intermetal dielectric layer to form the slurry etching process. The first plasmon etch stop process described in item 1 removes part of the intermetallic dielectric layer to form the first plasma #etching process. The etch stop layer described in item 3 is not to be etched. The patterned mask layer, the sacrificial material and the energy

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第16頁 577144 六、申請專利範圍量感應層係由光阻所組成。 1 0.如申請專利範圍第3項所述之避免蝕刻停止層被蝕穿的鑲嵌製程，其中去除該圖案化罩幕層係採用氧電漿灰化製程。 11.如申請專利範圍第3項所述之避免蝕刻停止層被蝕穿的鑲嵌製程，其中去除該犧牲材料係採用氧電漿灰化製程。 1 2.如申請專利範圍第3項所述之避免蝕刻停止層被蝕穿的鑲嵌製程，其中去除該能量感應層係採用氧電漿灰化製程。 1 3.如申請專利範圍第2項所述之避免蝕刻停止層被蝕穿的鑲嵌製程，其中去除位在該介層窗與該第一溝槽底部之該蝕刻停止層係採用電漿蝕刻製程。 1 4. 一種避免蝕刻停止層被蝕穿的鑲嵌製程，包括下列步驟：提供具有一銅金屬層的一基底，該基底具有既定之一主動區與一密封環（seal ring)區；形成一蝕刻停止層於該基底上，並覆蓋該銅金屬層；形成一金屬間介電層於該#刻停止層上；電漿#刻去除部分該金屬間介電層而形成至少一介層窗（via)穿越位在該主動區的該金屬間介電層，形成一圖案化罩幕層於位在該主動區的該金屬間介電層上，並填滿該介層窗；電衆#刻去除部分該金屬間介電層而形成至少一第一0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd Page 16 577144 Sixth, the scope of patent application The amount sensing layer is composed of photoresist. 10. The damascene process for preventing the etching stop layer from being penetrated as described in item 3 of the scope of the patent application, wherein the patterned mask layer is removed by an oxygen plasma ashing process. 11. The damascene process for preventing the etching stop layer from being penetrated as described in item 3 of the scope of the patent application, wherein the sacrificial material is removed by an oxygen plasma ashing process. 1 2. The damascene process for preventing the etching stop layer from being penetrated as described in item 3 of the scope of patent application, wherein the removal of the energy sensing layer is performed by an oxygen plasma ashing process. 1 3. The damascene process for preventing the etching stop layer from being eroded as described in item 2 of the scope of the patent application, wherein the etching stop layer at the bottom of the via and the first trench is removed by a plasma etching process. . 1 4. A damascene process to prevent the etch stop layer from being eroded, including the following steps: providing a substrate having a copper metal layer, the substrate having a predetermined active region and a seal ring region; forming an etch A stop layer on the substrate and covering the copper metal layer; forming an intermetal dielectric layer on the #etch stop layer; plasma #etch removing part of the intermetal dielectric layer to form at least one via window Pass through the intermetal dielectric layer in the active area to form a patterned mask layer on the intermetal dielectric layer in the active area, and fill the dielectric window; 电众 # 刻 Removed The intermetal dielectric layer forms at least a first

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0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第17頁 577144 六、申請專利範圍溝槽（t r e n c h )穿越位在該密封環區的該金屬間介電層；填入一犧牲材料於該溝槽中；以及對該基底進行一平坦化程序而得到之一平坦表面，以利後續製程之進行。 1 5.如申請專利範圍第1 4項所述之避免蝕刻停止層被蝕穿的鑲嵌製程，在形成該圖案化罩幕層於位在該主動區的該金屬間介電層上並填滿該介層窗之後，更包括下列步驟：氧電漿灰化去除部分該圖案化罩幕層而露出該金屬間介電層表面，並使該介層窗中有殘留的該圖案化罩幕層。 _ 1 6 .如申請專利範圍第1 4項所述之避免蝕刻停止層被 _ 蝕穿的鑲嵌製程，更包括下列步驟：形成一能量感應層於部分該金屬間介電層上；以該能量感應層為罩幕，電漿:#刻去除部分該金屬間介電層而形成一第二溝槽與一第三溝槽於該金屬間介電層中，其中該第二溝槽與該介層窗有重疊，該第三溝槽與該第一溝槽有重疊；氧電漿灰化去除該圖案化罩幕層、該犧牲材料與該能量感應層；電漿蝕刻去除位在該介層窗與該第一溝槽底部之該蝕刻停止層；以及填入銅金屬於該介層窗、該第二溝槽、該第一溝槽與該第三溝槽，而形成一銅插塞、一銅連線與一銅密封環。 1 7 .如申請專利範圍第1 4項所述之避免蝕刻停止層被0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd page 17 577144 VI. Patent application trench (trench) passes through the intermetal dielectric layer located in the seal ring area; a sacrificial material is filled in the In the trench; and performing a planarization process on the substrate to obtain a flat surface to facilitate subsequent processes. 1 5. According to the damascene process for preventing the etching stop layer from being penetrated as described in item 14 of the scope of the patent application, the patterned mask layer is formed on the intermetal dielectric layer in the active area and filled. After the interlayer window, the method further includes the following steps: oxygen plasma ashing removes part of the patterned mask layer to expose the surface of the intermetal dielectric layer, and leaves the patterned mask layer in the interlayer window. . _ 16. The damascene process to prevent the etch stop layer from being etched as described in item 14 of the scope of the patent application, further including the following steps: forming an energy sensing layer on part of the intermetal dielectric layer; using the energy The sensing layer is a mask. Plasma: # etch removes part of the intermetal dielectric layer to form a second trench and a third trench in the intermetal dielectric layer, wherein the second trench and the dielectric The layer window has overlap, and the third groove and the first groove overlap; oxygen plasma ashing removes the patterned mask layer, the sacrificial material and the energy sensing layer; plasma etching removes the dielectric layer. The etch stop layer at the bottom of the window and the first trench; and filling copper metal in the interlayer window, the second trench, the first trench, and the third trench to form a copper plug, A copper connection and a copper seal ring. 17. Avoid the etch stop layer as described in item 14 of the scope of patent application.

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第18頁：)/ / 丄 44 六、申請專利範圍嚓虫穿的鎮、缶矽層。敗焱程，其中該蝕刻停止層係氮化矽層或氣氧化蝕穿=鑲如Λ請專利範圍第14項所述之避免触刻停止層妯摻雜二氡^衣程，其中該金屬間介電層係二氧化矽屏$皮乳化矽層（FSG)。曰或氣蝕穿=·鑲如專利範圍第16項所遂之避免#刻停止舞站处旦代由〜氣_壬’其中該圖案化罩幕層、該犧牡从曰破 -'感〇應—層係由光阻所組成：錢牲材料與該列步驟：種避免蝕刻停止層被蝕穿的鑲嵌製程，包括下主供具有一金屬層的一基底，該基底具有既定> 動區與一宓4 υ火之一 ;、在封％(seal ring)區； ^ j 一蝕刻停止層於該基底上，並覆蓋該金 ^ 、a金屬間介電層於該蝕刻停止層上；曰’ 除部分該金屬間介電層而形成至少一第一、、# μ trench)牙越位在該密封環區的該金屬間介電層；曰填入一犧牲材料於該溝槽中；去除部分該金屬間介電層而形成至少一介屑办牙越位在該主動區的該金屬間介電層；曰肉（vla 幵y成圖案化罩幕層於位在該主動區的該全層上，並填滿該介層窗；以及金屬間介對该基底進行一平坦化程序而得到之一平扭利後續製程之進行。一表面， 2 1 ·如申請專利範圍第2 〇項所述之避免蝕 ιτ止層；j0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd Page 18 :) // / 44 6. Scope of applying for patents The towns and maggots that maggots wear. Silicon layer. In the failure process, the etch stop layer is a silicon nitride layer or a gas-oxidized erosion layer. The contact stop layer is doped as described in item 14 of the patent application, and the doping process is performed. The dielectric layer is a silicon dioxide screen skin-emulsified silicon layer (FSG). Said or cavitation erosion = · Established as described in item 16 of the scope of the patent. # 刻 STOP 舞站处代代由 ~ 气 _ 任 'Wherein the patterned cover curtain layer and the sacrificed sacrifice-'sense. The stress-layer system is composed of photoresist material and the series of steps: a mosaic process to prevent the etching stop layer from being eroded, including a substrate provided with a metal layer, the substrate having a predetermined > active area. And one of 4 υ fire; in the seal ring area; ^ j an etch stop layer on the substrate, and covers the gold ^, a intermetal dielectric layer on the etch stop layer; 'Remove at least a portion of the intermetal dielectric layer to form at least a first, # μ trench) the intermetal dielectric layer located in the seal ring region; fill a sacrificial material in the trench; remove a portion The intermetallic dielectric layer forms at least one intermetallic dielectric layer that is off-site in the active area; said meat (vla 幵 y is a patterned mask layer on the full layer in the active area, And filling the interstitial window; and performing a planarization process on the substrate by the intermetallic to obtain a flat twist Facilitate the subsequent process. One surface, 2 1 · Avoid the corrosion stop layer as described in item 20 of the scope of patent application; j

0503-8879TW(Nl) · TSMC2002-0557 ； Jacky.ptd 第19頁 577144 六、申請專利範圍蝕穿的鑲嵌製程，更包括下列步驟：形成一能量感應層於部分該金屬間介電層上；以該能量感應層為罩幕，定義一第二溝槽與一第三溝槽於該金屬間介電層中，其中該第二溝槽與該介層窗有重疊，該第三溝槽與該第一溝槽有_重疊；去除該圖案化罩幕層、該犧牲材料與該能量感應層；去除位在該介層窗與該第一溝槽底部之該蝕刻停止層；以及填入金屬材料於該介層窗、該第二溝槽、該第一溝槽與該第三溝槽，而形成一插塞、一金屬連線與一密封環。 2 2 .如申請專利範圍第2 0項所述之避免蝕刻停止層被蝕穿的鑲嵌製程，其中該金屬層係銅金屬層。 2 3 .如申請專利範圍第2 0項所述之避免蝕刻停止層被餘穿的镶喪製程，其中該钱刻停止層係氮化石夕層或氮氧化矽層。 24.如申請專利範圍第2 0項所述之避免蝕刻停止層被 I虫穿的鑲嵌製程，其中該金屬間介電層係二氧化石夕層或氣摻雜二氧化矽層（F S G)。 » 2 5 .如申請專利範圍第2 0項所述之避免蝕刻停止層被蝕穿的鑲嵌製程，其中去除部分該金屬間介電層而形成該介層窗的方法係採用電漿蝕刻製程。 2 6 .如申請專利範圍第2 0項所述之避免蝕刻停止層被蝕穿的鑲嵌製程，其中去除部分該金屬間介電層而形成該第一溝槽的方法係採用電漿蝕刻製程。0503-8879TW (Nl) · TSMC2002-0557; Jacky.ptd Page 19 577144 VI. The patented mosaic process of etching through further includes the following steps: forming an energy sensing layer on part of the intermetal dielectric layer; The energy-sensing layer is a mask, defining a second trench and a third trench in the intermetal dielectric layer, wherein the second trench and the dielectric window overlap, and the third trench and the The first trench has overlap; removing the patterned mask layer, the sacrificial material and the energy sensing layer; removing the etch stop layer located at the bottom of the via window and the first trench; and filling in a metal material A plug, a metal connection and a sealing ring are formed on the via window, the second trench, the first trench and the third trench. 2 2. The damascene process as described in item 20 of the scope of patent application to prevent the etching stop layer from being etched through, wherein the metal layer is a copper metal layer. 2 3. The inlaying process for avoiding over-etching of the etching stop layer as described in item 20 of the scope of patent application, wherein the money stop layer is a nitride nitride layer or a silicon oxynitride layer. 24. The damascene process for preventing the etching stop layer from being penetrated by insects as described in item 20 of the scope of the patent application, wherein the intermetallic dielectric layer is a silica dioxide layer or a gas-doped silicon dioxide layer (FSG). »25. The damascene process for preventing the etching stop layer from being etched as described in item 20 of the scope of patent application, wherein a method of removing a part of the intermetal dielectric layer to form the dielectric window is a plasma etching process. 26. The damascene process for preventing the etching stop layer from being etched according to item 20 of the scope of the patent application, wherein a method of removing a part of the intermetal dielectric layer to form the first trench is a plasma etching process.

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd 第20頁 577144 ----- 六、申請專利範圍蝕穿U鐘如Λ請專利範圚第2]項所述之避免蝕刻停止層被 Ab旦肷衣程，其t該圖案化覃幕層、該犧牲材料與該 1應層係由光阻所組成。 ‘ ·如申凊專利範圍第2 7項所述之避免蝕刻停止層被灰Γ匕集^嵌製程，其中去除該圖案化罩幕層係採用氧電漿 3· &如申請專利範圍第2 7項所述之避免蝕刻停止層被 ^ 6、鑲肷製程，其中去除該犧牲材料係採用氧電漿灰化製程。办3 〇 ·如申睛專利範圍第2 7項所述之避免蝕刻停止層被蝕鑲嵌製程，其中去除該能量感應層係採用氧電漿灰化製程。 * 3 1 ·如申請專利範圍第2 1項所述之避免蝕刻停止層被 ^穿的鑲嵌製程，其中去除位在該介層窗與該第一溝槽底部之該蝕刻停止層係採用電漿蝕刻製程。曰一0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd Page 20 577144 ----- VI. Patent application scope Erosion of U clock as described in item Λ, please refer to patent model 圚 2] to prevent the etching stop layer from being In the process of dressing, the patterned Qin curtain layer, the sacrificial material and the single layer are composed of photoresist. '· As described in item 27 of the patent application scope, the etch stop layer is prevented from being ashed ^ embedding process, in which the patterned mask layer is removed using an oxygen plasma 3. & The etch stop layer described in item 7, and the inlay process, wherein the sacrificial material is removed by an oxygen plasma ashing process. Office 30 • The etching stop layer is etched as described in item 27 of Shen Jing's patent scope, wherein the energy sensing layer is removed by an oxygen plasma ashing process. * 3 1 · The inlaying process for preventing the etch stop layer from being penetrated as described in item 21 of the scope of patent application, wherein the etch stop layer located at the bottom of the interlayer window and the first trench is made of plasma. Etching process. Yueyi

0503-8879TWF(Nl) ； TSMC2002-0557 ； Jacky.ptd0503-8879TWF (Nl); TSMC2002-0557; Jacky.ptd