564444 件’再與電容電極同-層之電容元件以接地面隔絕，接地面可能 為一走線方式。*僅可簡小電容與餘間_距，減少元件間 的耦合效應’更可以提高電容值。 另外，此引線或盲孔可利用半導體積體電路、印刷電路板、 陶竟基板燒結賴程技術來實現，所以可衫層的結構中直接做 零件間的串並聯，而達到更高㈣連接（_ Density Interconnection，HDI)之立體構裝技術。 因此’為達上述目的，本發明所揭露之埋藏式電容屏蔽結構， 包括有複數個電極板、-走線層、以及—接地面，其特徵在於接 地面係配置於該f極板與該走線層之間，肋減少電極板與走線 層之寄生效應。另外，電極板周圍更包括有一邊緣接地面，以減 少電極板間的耦合效應。 有關本發明的特徵與實作，魏合圖示作最佳實施例詳細說 明如下。 【實施方式】 要將埋藏式電容應用於各種電路中並保持訊號的完整性，元 件_合效應的絲便成為最重要的目標。—般的埋藏式電容佈 局方式是利用固定間距的設計，也就是利用最大的間距效果來減 '、政應可Τξ：相對增加電路佈局面積。本發明提丨電容佈局 法由於，接地的屏蔽效應（shielding)，不僅可以縮小電容與 電容間的間距，減少S件間_合效應，還可以控·距進而控 寄生電谷與邊緣電容（parasitic』fri卿㈣cit_ )，利用此 谷饭增大整體電容。另外電極的引線由另—電極板穿出，減少傳 輪線與電雜合的效應，此方㈣容結触佈局最佳化。 如第3圖』所示，為本發明之電容屏蔽結構之結構示意圖， 取上層為走線層1〇，第二層為接地面3G，第三層為電極板， 走線層10、接地面30以及電極板20間為介電層4〇。此方法係將 埋藏於電路或耕基材中的電極板肅、電極板施以及電極板 襄’以引線50A、引線避以及引線5QC分別由其電極板2〇a、 電極板20B以及電極板2〇c面向走線層1〇，穿過介電層牝與接 s 0而接出’構成立體的埋藏式電容結構。亦即將接地層％ 配置於走線層10與電極板2G之間。各層間縣介電㈣作為絕 緣以防止不同電極板間的電氣干擾。本發明所揭露之埋藏式電 容結構，可適祕多層電路製程，或是積體電路餘，且亦試用 各種介電材料作為填充介質。 如圖所示，其電場線分佈在板與接地面(Ground Plane) 中而由於有接地面的屏蔽致應陶ding)，使得在走線層1〇的 敦路不a又到埋藏電容元件的干擾，因為此埋藏電容树已被配 置於接地面30之下，g甘& 且其寄生元件也僅集中於接地面與導孔之 間，可說是大幅減少元件的雜散寄生效應。 、 •第3圖』中所揭露之埋藏式電容結構，因為接地面3〇的對 _板20的屏蔽姊可以有效解決電容與走_姆散寄生效 應。然而，電極板20A，板施、以及電極板咖、之間同 樣存在雜合電容_，因此本剌在『第3圖』所示之埋藏式 電谷屏蔽結構之架構下，於電極板遞周圍配置—接地面，其侧 視圖如第4圖』所示，電極板施與接地面30A之上視圖如『第 圖』所不’電極板2〇B外框為接地面3〇A，空白部分為介電層， 兩者之間有等效之邊、賴合電容，因此整體電容值*只有上下電 極板間之齡效應，還會因此接地面猶所造成的邊緣電容而加 大整體的電容值。·，躲板之_齡效應會被接地面隔開， 、保持元件特性與訊號傳輸的完整性。由於是埋藏式電容，為 了線路佈局可以有好種形狀可以實現，不—定為本發明所揭露 貫施例中之频，任何電減形綱可躺於本剌所要求之效 ^04444 之概念之第三較佳 配置一層接地面30， 第6圖』所示為赫本發明所揭露 例，如圖所*，儀在電極板τ方再多 〜m圭實施 效增加整體電容值。 a ，可以有 『第^圖』所示為應用本發明所揭露之概念之第四較佳實‘ 、歹在屏敝結構上電容側邊有電極板，雖然有接地面屏蔽，/ 為了接地面的電壓要完整，會在接地面㈣至少―個以上^ (VIA)方式維持上下接地面電愿等電位。 60 為了有更精麵比較’_高介電係數材質，相對介電 為30，DF=〇.〇4，基板厚度為加 麩 _ 电各尺寸為30*30milQ，& 構示意圖如『第8圖』所示： 〜 電容間距S Cll ; C12 — 9 mil 1571 - 20 mil Ϊ58Γ 40 mil l6li 9 mil (中間有 3mil接地面隔 開） 表一、 兩金 C2TTC22 3^563 cnTc2T~ΪΟΪΓ, 0.04013 ί〇2Γ83" ί〇0587ίοοπΤ O0290J- 0^01264ο^οοοϊ^ 各金屬板間相1電容轉合效應 由表中觀察出，上下電極板（⑶與C12、C21與⑶）間 的電容值隨著電容間距s的增加而增加，然若在電容間距9 mil 時’中間以3mil接地面隔開，則上下電極板之電容量要比間距為 40mil為㈤’因此’電容間的接地面可以有效增加整體電容值。 而在電極板⑽與C21、⑶與⑶）間之輕合電容部分，中 間有接地面隔開的電容麵合電容值小了好，當兩個電容相距 4〇mil以上，才會有近似相同的效果。可見這種接地面的設計確 貫可以將麵合訊號區隔。 附件』’單一電容尺寸為5*5麵八2,所採用的材料為FR4 基板’相對介電常數為4.2，如_4，基板厚度為a8mm，較 下方之曲線表示電容周圍無接麵，低親容值為2.76PF，上方 線表示電有接地面，間距為Μ·，低頻電容值為 3.25pF纟圖中可知有接地面保護的電容值比較大。 縮!内藏電4元相距，縮小整體電路佈局面積，接地面與 元件的間距可以是製程上的最小值。 除了可以減》埋藏電容元件間麵合效應。更可以應用提高整 體電容值’阻絕傳輸植方式影響電容健罐完整性。 另外’埋藏式電容結構可以為各種縱向結構、電極板形狀與 564444 » » 尺寸之内喊容元件。_舰容結顯局可翻於半導體積體 電路、印刷電路板、陶咨 、te ，是基板、奈米、微機電等各種製程技術鱼 材料來實現。 ^ 、么月以别述之較佳實施例揭露如上，然其並非用 定本跡觸⑽嫩，在娜綱之精神和範圍 内田可作些許之更動與潤飾，因此本發明之專利保護 本說明書所附之申請專利範圍所界定者為準。 &須視 【圖式簡單說明】 第1圖，係為習知埋藏式電容屏蔽結構示意圖； 第2圖，係為另—習知+并、 — ·知埋臧式電容屏蔽結構示意圖； 電容屏蔽結構之苐 .較 第3圖’係為本發騎揭露之埋藏式 佳實施例； 第4圖，係為本發明所揭露之埋藏式電容屏蔽結構 佳實施例； 之第二較 第5圖，係為本發騎揭露之埋駐電容屏蔽結 佳實施例之上視圖； 構之第二較 第6圖’係為應財發明所揭露之概红第三較佳 第7圖，係為應用本發明所揭露 施例； 之概念之第四較佳實施例； 564444 弟8圖，為說明電容值比早父之結構不意圖，以及 附件一，為應用本發明之電容屏蔽結構與習知電容屏蔽結構 之電容值比較圖。 【主要元件符號說明】564444 pieces of capacitor elements that are on the same layer as the capacitor electrode are isolated from the ground plane. The ground plane may be a wiring method. * Only the capacitor and the margin can be reduced, and the coupling effect between components can be reduced. The capacitance value can be increased. In addition, this lead or blind hole can be realized by semiconductor integrated circuit, printed circuit board, ceramic substrate sintering process technology, so in the structure of the shirt layer, the series and parallel connections between the parts are directly achieved to achieve a higher ㈣ connection ( _ Density Interconnection (HDI). Therefore, in order to achieve the above-mentioned object, the buried capacitor shielding structure disclosed in the present invention includes a plurality of electrode plates, a trace layer, and a ground plane, which is characterized in that the ground plane is disposed between the f-plate and the trace. Between the wire layers, the ribs reduce the parasitic effect of the electrode plate and the wiring layer. In addition, an edge ground plane is included around the electrode plates to reduce the coupling effect between the electrode plates. Regarding the features and implementation of the present invention, Wei He illustrated the preferred embodiment in detail as follows. [Embodiment] To apply buried capacitors to various circuits and maintain signal integrity, the element-combination effect wire becomes the most important target. -The general buried capacitor layout method is to use a fixed pitch design, that is, to use the maximum spacing effect to reduce ', the response should be τξ: relatively increase the circuit layout area. The capacitor layout method provided by the present invention is due to the shielding effect of the ground, which can not only reduce the distance between capacitors and capacitors, reduce the S-piece effect, but also control the distance and thus the parasitic valley and edge capacitance. 』Fri 卿 ㈣cit_), use this rice to increase the overall capacitance. In addition, the lead wire of the electrode is led out by another electrode plate, which reduces the effect of the hybrid of the transmission line and the electric wire, and the layout of the contact structure is optimized. As shown in Figure 3 ", this is a schematic structural diagram of the capacitor shielding structure of the present invention. The upper layer is the wiring layer 10, the second layer is the ground plane 3G, the third layer is the electrode plate, the wiring layer 10, and the ground plane. A dielectric layer 40 is provided between 30 and the electrode plate 20. This method involves burying an electrode plate, an electrode plate, and an electrode plate buried in a circuit or a substrate with a lead 50A, a lead avoider, and a lead 5QC from the electrode plate 20a, the electrode plate 20B, and the electrode plate 2 respectively. 〇c faces the wiring layer 10, passes through the dielectric layer 牝 and connects to s 0 to form a three-dimensional buried capacitor structure. That is, the ground layer% is disposed between the wiring layer 10 and the electrode plate 2G. The dielectric barriers between the layers are used as insulation to prevent electrical interference between different electrode plates. The buried capacitor structure disclosed in the present invention can be suitable for multi-layer circuit manufacturing processes or integrated circuit circuits, and various dielectric materials are also used as filling media. As shown in the figure, the electric field lines are distributed between the board and the ground plane (ground plane due to the shielding of the ground plane), so that the road at the wiring layer 10 does not reach the buried capacitor element. Interference, because this buried capacitor tree has been arranged below the ground plane 30, and its parasitic elements are only concentrated between the ground plane and the via, which can be said to greatly reduce the stray parasitic effect of the element. • The buried capacitor structure disclosed in Figure 3, because the shield of the ground plane 30 on the board 20 can effectively solve the parasitic effects of capacitors and capacitors. However, there is also a hybrid capacitor _ between the electrode plate 20A, the plate electrode, and the electrode plate, so this document is built around the electrode plate under the structure of the buried electric valley shield structure shown in "Figure 3". Configuration—The ground plane, whose side view is shown in Figure 4 ", the top view of the electrode plate applied to the ground plane 30A is not shown in the" Figure ", the outer surface of the electrode plate 20B is the ground plane 30A, and the blank part As a dielectric layer, there is an equivalent edge and capacitance between the two, so the overall capacitance value * is only the effect of the age between the upper and lower electrode plates, and the overall capacitance will be increased due to the edge capacitance caused by the ground plane. value. · The aging effect of the hidden board will be separated by the ground plane to maintain the characteristics of the components and the integrity of the signal transmission. Because it is a buried capacitor, in order to have a good shape of the circuit layout can be achieved, not necessarily the frequency of the embodiment disclosed in the present invention, any electrical reduction form can lie in the effect required by this concept ^ 04444 concept The third preferred configuration is a layer of ground plane 30. Fig. 6 "shows an example disclosed by the present invention. As shown in the figure, the instrument can be implemented on the electrode plate τ as much as possible to increase the overall capacitance value. a, there can be "fourth figure" shows the fourth best practice of applying the concept disclosed in the present invention. "On the screen structure, there are electrode plates on the capacitor side, although there is a ground plane shield, / for the ground plane. The voltage must be intact, and at least ― (VIA) or more on the ground plane will be used to maintain the electrical potential of the upper and lower ground planes. 60 In order to have a more refined comparison, _ high-dielectric constant material, relative dielectric is 30, DF = 0.04, substrate thickness is bran _ each size of electricity is 30 * 30milQ, and the schematic diagram of the structure is as shown in "第 8 As shown in the figure: ~ Capacitance distance S Cll; C12 — 9 mil 1571-20 mil Ϊ58Γ 40 mil l6li 9 mil (3mil ground plane separated in the middle) Table 1. Two gold C2TTC22 3 ^ 563 cnTc2T ~ ΪΟΪΓ, 0.04013 ί〇 2Γ83 " ί〇0587ίοοπΤ O0290J- 0 ^ 01264ο ^ οοοϊϊ ^ The capacitance switching effect of phase 1 between each metal plate is observed in the table. The capacitance value between the upper and lower electrode plates (⑶ and C12, C21 and ⑶) varies with the capacitance distance s. When the capacitor spacing is 9 mil, if the distance between the capacitors is separated by a 3 mil ground plane, the capacitance of the upper and lower electrode plates is larger than the spacing of 40 mil. Therefore, the ground plane between the capacitors can effectively increase the overall capacitance value. . In the light-capacitance section between the electrode plate ⑽ and C21, ⑶ and ⑶), the capacitance value of the capacitor surface separated by the ground plane in the middle is small. When the two capacitors are more than 40mil away, they will be approximately the same. Effect. It can be seen that the design of this ground plane can surely separate the area signal. Attachment '' Single capacitor size is 5 * 5 face 8 2 and the material used is FR4 substrate 'Relative dielectric constant is 4.2, such as _4, substrate thickness is a8mm, the lower curve indicates that there is no interface around the capacitor, low The affinity value is 2.76PF, the upper line indicates that there is a ground plane, the spacing is M ·, and the low-frequency capacitance value is 3.25pF. The figure shows that the capacitance value with ground plane protection is relatively large. Shrink! The distance between the built-in electricity is 4 yuan, which reduces the overall circuit layout area. The distance between the ground plane and the component can be the minimum value in the manufacturing process. In addition, the face-to-face effect between buried capacitor elements can be reduced. It can also be applied to increase the overall capacitance value to prevent the transmission planting method from affecting the integrity of the capacitor tank. In addition, the buried capacitor structure can be a variety of vertical structures, electrode plate shapes and 564444 »» components within the size. _The display of the ship's capacity can be realized in semiconductor integrated circuits, printed circuit boards, ceramics, te, and various process technologies such as substrates, nanometers, and micro-electromechanical technology. ^, Mo Yue revealed the above with a preferred embodiment, but it is not a touch of the original, but in the spirit and scope of Na Gang, Tian can make some changes and retouches. Therefore, the patent of the present invention protects the specification. The attached application patent shall prevail. & Must see [Schematic description] Figure 1 is a schematic diagram of the conventional buried capacitor shield structure; Figure 2 is another—the conventional + parallel, — · · Known buried capacitor shield structure schematic diagram; Shielding structure: Compared with Figure 3, it is the best embodiment of the buried type disclosed by the present invention; Figure 4, which is the best embodiment of the buried capacitor shielding structure disclosed by the present invention; This is a top view of the embodiment of the buried capacitor shielding structure disclosed by the present invention; the second and sixth figure of the structure is the third best and the seventh best picture of the red color disclosed by the financial invention, and is the application The fourth preferred embodiment of the concept disclosed by the present invention; the fourth preferred embodiment of the concept; Capacitance comparison chart of shield structure. [Description of main component symbols]
10 走線層 20 電極板 20A 電極板 20B 電極板 20C 電極板 30 接地面 30A 邊緣接地面 40 介電層 50A 引線 50B 引線 50C 引線 60 貫孔 70 導通孔 12 4 410 Routing layer 20 Electrode plate 20A Electrode plate 20B Electrode plate 20C Electrode plate 30 Ground plane 30A Edge ground plane 40 Dielectric layer 50A lead 50B lead 50C lead 60 through hole 70 through hole 12 4 4
專利說吸皇 (本說明t 式 '順序，請勿任意更動，※記號部分請勿填寫） ※申請案號：叫丨/^”泛 ※申請日：qi … 一 X ※㈣分類： 私月石％ .(中文/英文） 電容屏蔽結構 二、中文發明摘要： 種電各屏蔽結構，包栝有複數個電極板、一走線層、以及 接地面，其特徵在於接地面係配置於該電極板與該走線層之 ^用以減少電極板與走線層之寄生效應。另外，電極板周圍更 匕括有邊緣接地面，以減少電極板間的轉合效應。本發明所揭 路的引線方式可簡祕半導體積體電路、多層印刷電路板電 路陶究基板燒結等多層電路結構。 三、英文發明摘要： 564444 七、申請專利範圍： h種電容屏蔽結構，應用於多層電路結構中， 包括有 複數個電極板； 一走線層；以及 走線層之間。 其中更包括一層 電極板間為不 一接地面，係配置於該電極板與該 2·如申請專利翻第丨項所述之電容屏蔽結構， 以上之介電層，係配置於該電極板之間，使得各 導通狀態。 如申請專利範圍第！項所述之電容屏蔽結構，其中更包括複數 個引線，鍵電極板面向該走線層，穿過接地面接出。 《如申請專利範圍第！項所述之電容碰結構，其中該電極板周 圍更包括有-邊緣接地面’㈣減少電極板間之齡效應。 5·如申請專纖圍第1項所述之電容屏蔽結構，其中該引線係為 金屬引線。 6·如申μ翻範圍第1項所述之電容屏蔽結構，其中該引線係為 一導孔。 7·如申請專利範圍第1項所述之電容屏蔽結構，其中該引線係為 一盲孔。 13 564444 8.如申請專利範圍第1項所述之電容屏蔽結構，其中該引線係為 一埋孔。Patent said to attract the emperor (the t-style 'order in this description, please do not change arbitrarily, ※ please do not fill in the mark part) ※ application number: called 丨 / ^ "pan ※ application date: qi… one X ※ ㈣ classification: private moon stone (Chinese / English) Capacitive shielding structure II. Abstract of Chinese invention: Each kind of shielding structure includes a plurality of electrode plates, a wiring layer, and a ground plane, which is characterized in that the ground plane is arranged on the electrode plate This wiring layer is used to reduce the parasitic effect of the electrode plate and the wiring layer. In addition, an edge ground plane is provided around the electrode plate to reduce the turning effect between the electrode plates. The leads disclosed in the present invention The method can simplify the multilayer circuit structure of semiconductor integrated circuits, multilayer printed circuit boards, ceramic substrate sintering, etc. 3. Abstract of English invention: 564444 7. Application scope: h kinds of capacitor shielding structures, which are used in multilayer circuit structures, including There are a plurality of electrode plates; a wiring layer; and between the wiring layers. Among them, there is a ground plane between the electrode plates, which are arranged between the electrode plate and the 2nd. The above-mentioned capacitor shielding structure, the above dielectric layer, is arranged between the electrode plates so as to make each state of conduction. The capacitor shielding structure as described in the scope of the patent application item No.!, Which further includes a plurality of leads, key electrodes The board faces the wiring layer and is connected through the ground plane. The capacitive touch structure described in item No.! Of the patent application scope, wherein the electrode plate includes a -edge ground plane around the electrode plate to reduce the age effect between the electrode plates. 5. The capacitor shielding structure according to item 1 of the application for fiber optic enclosure, wherein the lead is a metal lead. 6. The capacitor shielding structure according to item 1 of the application, wherein the lead is a guide hole. 7. The capacitive shielding structure according to item 1 in the scope of patent application, wherein the lead wire is a blind hole. 13 564444 8. The capacitive shielding structure according to item 1 in the scope of patent application, wherein the lead wire is a Buried hole.
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