TW554172B

TW554172B - Semiconductor device test apparatus

Info

Publication number: TW554172B
Application number: TW089112503A
Authority: TW
Inventors: Yasuyuki Okamoto
Original assignee: Mitsubishi Electric Corp
Priority date: 1999-07-07
Filing date: 2000-06-26
Publication date: 2003-09-21
Also published as: JP2001021622A; KR20010029856A; KR100383006B1

Abstract

Semiconductor device test apparatus tests a semiconductor device at a frequency exceeding the maximum frequency of the hardware of the semiconductor device test apparatus. Two timing pulses are produced so as to correspond to the respective operation cycle of the semiconductor device test apparatus, at a predetermined period n2, which is shorter than one-half of the minimum cycle ""n"" corresponding to the lower limit of the operation cycle. The timing -at which the first timing pulse corresponding to each of the operation cycles is produced- is qradually shifted from the end point to the start point of the operation cycle, such that the interval between the second timing pulse corresponding to the respective operation cycle and the first timing pulse corresponding to the next operation cycles becomes equal to the predetermined interval n2. Signals c1 to c5 formed as a result of the shift are combined into a signal C1 output from the semiconductor device test apparatus.

Description

554172 五、發明說明（1) 【發明所屬之技術領域j 憶====;袭置、半導體測試方法以及記於到為了以讀取的記錄媒體，尤其關半導體測試方法以及ΐΐΠΓ則試的半導體測試裝置、取的記錄媒體 fe+導體測試處理程式的電腦可讀【習知之技術】二；的生產步驟中用半侧時流程圖。Γ且二V說明從前的半導體測試方法的定動作周期相一致U:(a)表示與半導體測試襄置的的外部時鐘作號们^ ^ =卜。卩時鐘信號R1的波形。以標準檢查物件ic。號；半導體測試裝置提供給控制信號τι(控制信號攸半導體^置^供給ic的外部半導體測試裝置/^ σ犰、貧料信號等）的波形。 ▲(以下稱"最高頻置;確圖%^^^ 採用從么半外導部:空制信號T1的定時。的 :』與最小周期：準的外部時鐘信於標準外部時鐘仁^ (芩看圖7(Α))的同時，使ΪΓ ν:: 方法，能以车道唬的定時獲取外部控制信號同步的動作41 體測試裝置的最高頻率以W按照上述 τ的頻率檢查ic ""月所欲解決之問題】554172 V. Description of the invention (1) [Technical field to which the invention belongs] 忆 ====; attack, semiconductor test methods, and recording media for reading, especially about semiconductor test methods and semiconductors tested by ΐΐΠΓ The test device and the computer-readable recording medium fe + conductor test processing program are computer-readable. [Knowledgeable Technology] II. The half-time flow chart is used in the production steps. Γ and two V indicate that the fixed operation period of the previous semiconductor test method is consistent with U: (a) indicates that the external clocks provided with the semiconductor test are numbered ^ ^ = Bu.卩 The waveform of the clock signal R1. Check object ic by standard. The waveform provided by the semiconductor test device to the control signal τι (the control signal is provided by the external semiconductor test device / sigma arm, lean signal, etc.). ▲ (Hereinafter referred to as " highest frequency setting; exact map% ^^^ uses the timing of the external pilot: the timing signal T1. '' And the minimum period: the quasi external clock is trusted by the standard external clock ^ (芩 Look at Figure 7 (Α)) while using the ΪΓ ν :: method to obtain the synchronized action of the external control signal at the timing of the lane block 41 The highest frequency of the body test device is checked at the frequency of W according to the above τ " & quot The problem that the moon wants to solve]

Ptd 89π 2503. 第6頁五、發明說明（2) 為了驗證半導體裝置的能保證半導體裝置動作的田=正確與否，對半導體裝置以的。因此，隨著半導體=间，率進行測試是完全必要逐漸要求高的動作速度:的岗速化對半導體測試裝置也超過能保證動作頻率的相:了坪價半導體裝置的能力，以故，此時對半導體裝置^ ^剛試半導體裝置也是必要的。但是，採用從前的4=的速度。在預先設定好的超過最高玄· °式方法，無法對半導體裝置用從前的方法以比目前^下進行測試。因此採導體裴置不能進行測試。““式装置更快速度動作的半本發明為了解決上述誣θ§ ^ 4 過最高頻率的頻率進行導，弟：二2是提供以石更體上超 ” ::2個目的是提 IT頻率的頻率下能夠進行半導體測試的半導^ 本發明的第3個目的是以半導Ptd 89π 2503. Page 6 V. Description of the invention (2) In order to verify that the semiconductor device can guarantee the operation of the semiconductor device = correct or not, the semiconductor device is used. Therefore, it is absolutely necessary to gradually test the semiconductor device with high operation speed. As a result, the speed of the semiconductor test device also exceeds the phase that can guarantee the operation frequency: the capability of the semiconductor device is low. It is also necessary for the semiconductor device to test the semiconductor device. However, the previous speed of 4 = is used. In the pre-set method exceeding the highest threshold, it is impossible to test the semiconductor device with the previous method at a lower level than the current method. Therefore, the conductor cannot be tested. "" The semi-invention device of the type device operates at a faster speed in order to solve the above-mentioned 诬 θ§ ^ 4 to conduct at frequencies exceeding the highest frequency. Brother: The second 2 is to provide more physical and ultra-high performance. ":: 2 The purpose is to increase the IT frequency Semiconductors capable of conducting semiconductor tests at high frequencies ^ The third object of the present invention is to use semiconductors

高頻率的頻率下能夠進行半導體V試V 理程式的電腦可讀取的記錄媒體。 D丨思丰―體測試處【解決問題之手段】 ' :請專利範圍第i項所述之發明，，其係對半導體裝置提供信號以進 +導:測試裝置為··包含有，作測试，其特徵定時產生器，與半導體測試裝置的依次產生複數個定時； 7周期分別對應並A computer-readable recording medium capable of performing semiconductor V test and V program at high frequencies. D 丨 Sifeng—Physical Testing Division [Methods of Solving Problems] ': Please refer to the invention described in item i of the patent scope, which provides a signal to the semiconductor device for further guidance: The test device includes ... Test, its characteristic timing generator generates a plurality of timings in sequence with the semiconductor test device;

II 89112503.ptd 五、發明說明（3) 圖案產生器，與上述定時產而可改變輸出信號的值；以&所產生的定時分別同步 Ί工制機構，上述定日鼻嘉& ^ ^ ^ Τ „ Μ ^ „ 6,1/2 ^ ^ ^ 日可，同時使對應每個動作周期、—生至少2個定每個動作周期中以賴—真存取初疋時的產生時期，在到起點側。、疋、又逐漸攸動作周期的終點側移動 :請專利範圍第2項之發明，係如半導體測試裝置。月專利靶圍第1項之其中上述定時產生器每個動該等2個定時，係在小 °短的定時數是2個，間隔内產生，上述控制機構^最移^^、+的j/2的第1規定 :』俾使對應母個動作周期度生作周期的最初定時之間的間p，與對應下一個動申喑鼻利r二變成上述第1規定間隔。甲明專利乾圍第3項之發明係如申請半導體測試裝置。專利乾圍弟2員之其中亡述定時產生器，係可在下一個動生對應每個動作周期的第2個定時， ° / ，、產上述控制機才冓，係用以將產生上點申Ϊί=2:4定時拖延2個動作周期心半導體測試】置。$之發明’係如申請專利範圍第3項之 "、:上述疋日守產生器在每個動作周期產生定時數為3 該專3個定時’係在小於上述最短周期的1/3的第2為個3規 554172 五、發明說明（8) 器18及圖案產生器2〇盥、、丨 9 定時產生器是使驅動=出2:襄設的驅動器24連接。生電路。1案產生器2。：二=信號產生變化的定時產路。因此，驅動哭24且：動器24輸出信號波形的電出4^^具有圖案產生器2〇決定的波形，並輸出由疋日守產生為18決定的定時改變1值的㈣。 η = =重ΐ據硬體的制約等因素在測試器10和測 ”#•古ife " ^ ^乍的頻率的上限值。以下稱該上限值為二哭1 Π且：才應於最高頻率的周期為Π最短周期n"。II 89112503.ptd V. Description of the invention (3) The pattern generator can change the value of the output signal with the above-mentioned timing; synchronize the masonry mechanism with the timing generated by & the above-mentioned Tingri Bijia & ^ ^ ^ Τ Μ ^ ^ 6, 1/2 ^ ^ ^ day is possible, at the same time, corresponding to each action cycle,-at least 2 times in each action cycle depends on-the generation time of the initial access to true access, in To the starting point. , 疋, and then gradually move to the end of the action cycle: Please invent the second scope of the invention, such as a semiconductor test device. One of the monthly target ranges of the patent mentioned above is that each of the above timing generators moves 2 timings, and the number of timings at a small angle is 2. The interval is generated. The above control mechanism ^ 最 shift ^^, + j The first rule of / 2: "The interval p between the initial timing of the corresponding cycle of the mother's action cycle and the corresponding one of the next motion cycle is changed to the first prescribed interval described above. The invention of item 3 of the Jiaming patent is the application of a semiconductor test device. The patented timing generator of the two members of the gang siblings can be used to generate the above control machine at the next timing corresponding to the second timing of each action cycle. Ϊί = 2: 4 Delayed 2 operation cycles at regular intervals. The invention of "$" is as described in the item 3 of the scope of the patent application: The above-mentioned day-to-day generator generates a timing number of 3 in each operating cycle. The three special timings are less than 1/3 of the shortest period. The second is a 3 gauge 554172. 5. Description of the invention (8) The generator 18 and the pattern generator 20, 9 and 9 The timing generator is connected to the driver 24 which is driven = out 2: set up.生电路。 Circuits. 1 Case generator 2. : Two = Timing circuit where the signal changes. Therefore, the driver 24 cries: the output of the signal waveform of the actuator 24 has a waveform determined by the pattern generator 20, and outputs ㈣, which changes by 1 at a timing determined by 18 of the next day. η = = The maximum value of the frequency in the tester 10 and the measurement "# • 古 ife " ^ ^ the upper limit of the frequency according to hardware constraints and other factors. The upper limit is hereinafter referred to as the second cry 1 Π and: The period at the highest frequency is Π shortest period n ".

:Γ丨文;、*的結構，對應於最短周期可以形成-個RZ (返回到零）波形。呈雕 H m地溝，疋時產生器1 8對應最短周期11的各個周期，可以生成2個界限，即2個定時。而圖安. 產生=0,收對應各個周期的2個界限，使信號值可按二二H變化。因此本實施形態的半導體測試裝置 :=周二的各個周期，從驅動器“可 —H—L或H—L—H變化的輸出信號。十家知道，作為能實現測試器1〇的公認的裝置，生裔1 8使其對應各個周期產生的定時數可以改變。且麟定時產生H18可以實現使其對應各個周期產生二疋b的方式以及使其產生3減時的方式。對置’圖案產生器20能以規定的周期數作二衷出信號的波形。早位决疋輸採用這種裝f (測試器）能夠產生以下的輸出信號對應各個周期使其值最多變化2次、並且以規定的周^數作為-個單位實現規定波形的輸出们虎，以及對應各個周: Γ 丨文;, * structure, corresponding to the shortest period can form a RZ (return to zero) waveform. In the Hm trench, the generator 18 at the time corresponds to each cycle of the shortest cycle 11 and can generate 2 boundaries, that is, 2 timings. And Tuan. Generates = 0, and accepts 2 limits corresponding to each cycle, so that the signal value can be changed according to H. Therefore, the semiconductor test device of this embodiment: = Output signals that can be changed from the driver to -H-L or H-L-H for each cycle on Tuesday. Ten companies know that as a recognized device that can realize the tester 10, The born 18 can change the number of timings corresponding to each cycle. And the timing generation H18 can realize the way to generate two 疋 b corresponding to each cycle and the way to generate 3 time reduction. Opposition 'pattern generator 20 can use the specified number of cycles to make a signal waveform in the middle. Using this device f (tester) can generate the following output signals for each cycle to change its value up to 2 times, and with a specified The number of weeks is used as a unit to achieve the output of the specified waveform, and corresponding to each week

89112503.ptd 第13頁 554172 五、發明說明（9) ' "—''— ------- = 變化3次、並且以規定的周期數作為-個單這i裝置ί現形的輸出信號。本實施形態的測試器10可由 ☆家知冑’作為能實現測試器1〇的公認 ==定時的-部分有的禁止在其他周期中產J有的形S能：Γ”產生。本實施形態的測試器10對該兩種 T r q n】忒頭2 2哀有性能板2 6，性能板2 6通過插座2 8安裝在 ^。驅動器24輸出的信號通過性能板26和插座Μ輸出、、、6 iLd0的各個管腳。护ΐΐ表示/用本實施形態的半導體測試裝置進行1C的測試 :I仃一系列處理的流程圖。在1 C的測試步驟，首先將檢 —物件IC30 (si〇〇 )安裝在插座28上。接著，從外存丨6將半導體測試處理程式裝 14 (S102)。、忒八。己U版凌置的裎式由測試器1〇運行，再由定時產生器18和圖生裔2 0形成輸出信號的波形（S1 〇 4 )。、 ^疋日守產生器1 8和圖案產生器2 0形成輸出信號從驅動哭輸出（Sl〇6)。。〇橹驅動器2 4的輸出施加於IC 3 0。（ S 1 0 8 ) ，後，對於IC30 ,由半導體測試裝置以規輪=信號’實行規定的測試（SUO)。連串的剩試完成後’ I C 3 0的測試結束（s 1 1 2 )。本實施形態的半導體測試裝置經過上述步驟§1 〇4的處89112503.ptd Page 13 554172 V. Description of the invention (9) '" —''-- ------- = change 3 times, and use the specified number of cycles as a single output of this device signal. The tester 10 of this embodiment can be recognized by ☆ Jiazhi 胄 as the tester 10 can be realized == timing-some of them are forbidden to produce J-shaped form S energy: Γ "in other cycles. The tester 10 has two types of T rqn] hoe 2 2 and a performance board 2 6, and the performance board 26 is installed at ^ through the socket 2 8. The signal output by the driver 24 is output through the performance board 26 and the socket Μ, 6 Each pin of iLd0. The protection indicator indicates that the 1C test is performed using the semiconductor test apparatus of this embodiment: I: a series of processing flowcharts. In the 1C test procedure, the inspection object IC30 (si〇〇) is first Installed on the socket 28. Next, install the semiconductor test processing program 14 from external storage 6 (S102). 忒。. The U version of the set mode is run by the tester 10, and then by the timing generator 18 and The figure 20 generates a waveform of the output signal (S1 04). The 守守 generator 18 and the pattern generator 20 form an output signal from the drive output (S106). The driver 2 4 The output is applied to IC 3 0. (S 1 0 8), and then for IC30, tested by semiconductor Set the gauge wheel = signal to perform the prescribed test (SUO). After a series of remaining tests is completed, the test of IC 30 is completed (s 1 1 2). The semiconductor test device of this embodiment goes through the above steps §1 〇4 The place

554172 五、發明說明（ίο) 理，能夠形成在超過上述最高頻率的頻率下波動的輸出信號。以下，麥考圖3，就本實施形態的半導體測試裝置生成上述高頻信號的方法進行說明。圖3表示為了說明本實施形態的半導體測試裝置動作的定時流程。更具體地講，圖3 (A)表示與半導體測試裝置的動作周期相-致的標準外部時鐘信號Ri的波形。如圖3 A所不，在達到標準外部時鐘信號R丨的周期與最小周 -致的速度之前’半導體測試裝置的動作周期可以實測試裝置輸出信號clic5的小：期的各個周期半導體致的輸出信號C1。對於本實施形態，將圖3 二)。所不的輸出信鎖作為時鐘信號提供給檢查物件本實施形態的半導體測試骏置，成信號cl。信號cl，在椤準冰、上述S104 1里百先形 ή mn ,, ? 在枯丰外邛時鐘信號R1的周期即最小周期η的後半、小於苴噩小Η 間η2內十AH k工//、周』n的一半（n/2 )的很小期 ΪΓ信號。測試器10，使定時產生器18於期η的最後產生第2個定時生同時’於最小周 ^ a, -^h ^ % VV/^/Λ2! Γ " ^ 本實施形態的半導體測試f 生^號cl。 c2，於信號cl下降後在 ^ f，接者形成信號c2。信號定的期辑持二以^ ㈣應第2個最小周期n，從/ 6式了，使定時產生器 < 唬cl開始下降“時間使其產 554172 五、發明說明（11) 生最初的定時，π 士時，並使圖荦產Τ 再經過η2時間使其產生第2個定 ^ ^ 7座生器20以同步於定時的；L —H —L·順序變化輪出值，產生信號c2。而後，本半逡雕、ηϊ 、各個周期依次產：試裝置以產生c 2同樣的方法使其對應的信號C1，如圖3 ; 。此時’從半導體裝置供給1C30 期m内變化。圖3 所不’在比最小周期n還要小的周測試裝置供給的夕卜部:，是1，獲取的從半導體料信號等）。卫制化唬（控制#號、位址信號、資物：ί 3戶:述丰Ϊ據本實施形態的半導體測試方*，對檢查 ^ ^ ^ hu ^ ^ ^ 使1 C 3 0以超過半導體測試裝置的最 =:去:、了 2 :力作。因此，採用本實施形態的半導體測試 Π首I 目前的半導體測試裳置的處理速度，用目前554172 V. Description of the invention (ίο) The principle can form an output signal that fluctuates at a frequency exceeding the above-mentioned highest frequency. Hereinafter, a method of generating the above-mentioned high-frequency signal by the semiconductor test apparatus of this embodiment will be described with McCaw Fig. 3. Fig. 3 shows a timing flow for explaining the operation of the semiconductor test apparatus according to this embodiment. More specifically, FIG. 3 (A) shows a waveform of a standard external clock signal Ri in accordance with the operation cycle of the semiconductor test device. As shown in Figure 3A, before the period of the standard external clock signal R 丨 and the minimum cycle-consistent speed are reached, the operating period of the semiconductor test device can be as small as the output signal clic5 of the test device: the semiconductor-induced output of each cycle Signal C1. For this embodiment, refer to Fig. 3 (b). The output lock is provided as a clock signal to the inspection object, and the semiconductor test device of this embodiment forms a signal cl. The signal cl, at 椤 quasi-ice, the above-mentioned S104 1 hundred cents price mn ,,? In the cycle of the clock signal R1, that is, the second half of the minimum period η, which is less than ten AH k within the time period η2 /, Zhou ”n half (n / 2) a very small period of ΪΓ signal. The tester 10 causes the timing generator 18 to generate a second timing generator at the end of the period η at the same time 'at the minimum cycle ^ a,-^ h ^% VV / ^ / Λ2! Γ " ^ Semiconductor test of this embodiment Health ^ cl. c2, after the signal cl falls, the signal c2 is formed at ^ f. The fixed period of the signal is set to ^ ㈣ should correspond to the second minimum period n, which is from the / 6 formula, so that the timing generator < bl cl begins to fall "time to make it 554172 V. Description of the invention (11) Timing, π ± hours, and make the graph production time η2 time to generate a second fixed ^ ^ 7 block generator 20 to synchronize with the timing; L-H-L · sequentially change the rotation value to generate a signal c2. Then, this semi-sculpture, ηϊ, and each cycle are sequentially produced: the test device uses the same method to generate c 2 to make its corresponding signal C1, as shown in Figure 3; At this time, 'from the semiconductor device supply 1C30 period m changes. Fig. 3 is provided in the test device supplied by the test device in a cycle smaller than the minimum period n: 1, is the signal obtained from the semiconductor material, etc. (defense system control (#, address signal, materials) : Ί 3 households: Shu Fengzheng, according to this embodiment of the semiconductor test party *, check ^ ^ ^ hu ^ ^ ^ Make 1 C 3 0 to exceed the maximum of the semiconductor test device =: go :, and 2: masterpiece. Therefore Using the semiconductor test of this embodiment, the current processing speed of the semiconductor test device is

料導體測試裝置可以進行高速的IC檢查。 J 期二丰在:】:斤示的動作例中，信號_^ 沪c5l"生的V Λ’广在周編内產生並持續，因此在信 ί水平曰:周期。的後半部需… ί Λ 試器10對應各個周期能約產生3個定日Γ的；：個周期產生2個定時的方式與每個周期產生3個定切.奐。因此，根據本實施形態的“ :収…輸出m周期内的信號期間受到有限期間的限 CPU1 2根據從外存裝置1 6 於上述實施形態讀入的程The conductor tester can perform high-speed IC inspection. In the action example of J Feng Erfeng:]: In the action example of Jin Jin, the signal _ ^ hu c5l " Health V Λ 'is generated and continued in the weekly series, so at the level of the letter: cycle. The second half of… needs to be used. Ί Λ Tester 10 can generate about 3 fixed dates Γ for each cycle;: The method of generating 2 timings for each cycle and 3 fixed cuts for each cycle. Therefore, according to the present embodiment, ": the signal period within the output m cycle is limited by a limited period of time. CPU1 2 According to the process read from the external storage device 16 in the above embodiment,

554172 五、發明說明（13) 本實施形態的半導體測試裝置，接著形成信號c2。信t ’於信號c 1下降後在規定的期間n2以後為Η水平，在規的翻Ρ。, η 9祕II丄 CTV从政 ~ S3· 1 Π ，乂由企Β主立丄口口著形成信號c2。信號 r傻你规疋日μ期间η △以後為Η水平’在規定的期間η2維持Η水平後下降。測試器1 0，使定時產生器 1 8對應第2個最小周期η，從信號c 1開始下降η2時間使其產 ^最初的定時，同時，再經過η2時間使其產生第2個定時，並使圖案產生器20以同步於定時的L ->H —L順序變化輸出值，產生信號c 2。而後’半導體測試裝置以產生c2同樣的方法使其對應各 :周期依次產生c3〜c8。此時，從半導體裝置供給IC3〇的 i 圖4如彳4、（C)所示’在比最小周期n更小的周期m内裝置供^的^所不^Α"，是1C3〇獲取的從半導體測試號等f 了、。卩控制信號（控制信號、位址信號、資料信如上所述，根據本實施物件IC30，半導體測二=的+導體測试方法，對檢查動的信號C1。即Γ可二J :供以超過最高頻率的頻率波高頻率的速度動作。因:1^0以超過半導體測試裝置的最方法，可提高目前的4體半導體測試的半導體測試裝置可以I版I1忒裝置的處理速度，用目前本實施形態的半⑽檢查。與實施形態1 一樣，Α "表置施輸出周期m的信號期間形態’容許對應各個又周：=限制。但是’於本實施因此，根據本實施形能的個疋時拖長2個周期後產生。場合相比’可在比較ί的坤：f測試裝置與實施形態1的 __, 4内將周期m的信號持續供給 89112503.ptd 第18胃 554172 五、發明說明（15) ^見疋的期間n3是小於最小周期n的1/3的時間。信號cl的生使定時產生器1 8在從最初的最小周期n的結束時期追 =2 X n3時刻時產生第}定時、而後經過n3時刻使其產生定時，而後在經過n3時刻產生第3定日寺，與此同時使圖二產生器20按照L-H—L—Η的順序與上述3個定時同步地，交化輸出信號的值。本貫施形態的半導體測試裝置，接著生成信號“。信號 d丄於信號cl下降後在規定的期間η3後為L水平，然後在 =疋的期間n3後上升到Η水平，η水平只維持在規定的⑻期 =，然後下降。定時產生器18對應第2個最小周期n，從信唬cl上升開始每經過n3時間就能依次產生3個定時俨號，° 並且圖案產生器20與這些定時同步並依次按照η―匕的順序改變輸出值，依此生成信號c2。本實1形態的半導體測試裝置，接著生成信號“。信號 c ，於彳§號。2下降後在規定的期間n3後成為η水平，然後在規定的期間η3後下降到L水平，L水平只維持在規定的η3 =間，然後上升。定時產生器丨8對應第3個最小周期η，從信號c2下降開始每經過“時間就能依次產生3個定時信號並且圖案產生為2 0與這些定時同步並依次按照[η — L —Η的順序改變輸出值，依此生成信號c3。 … 以後，半導體測試裝置以產生c2信號同樣的方法應第4和第6個最小周期產生“和。6，同時以產生信號同樣的方法對應第5個最小周期產生c 5。此時，從半置供給IC30的信號C1 ’如圖5 (c)所示，是在比最小a周期554172 V. Description of the invention (13) The semiconductor test device of this embodiment forms a signal c2 next. The letter t 'is at a level of Η after a predetermined period of time n2 after the signal c1 falls, and is turned over at a regular level. , η 9 secret II 丄 CTV politics ~ S3 · 1 Π, the signal c2 is formed by the main stand of enterprise B. The signal r is stupid. You define the period μ during the period η Δ and thereafter become the level ′. After the period η2 maintains the level Η, it decreases. The tester 10 causes the timing generator 18 to correspond to the second minimum period η, and decreases from the signal c 1 by η 2 time to produce the initial timing, and at the same time, η 2 time is passed to generate the second timing, and The pattern generator 20 is caused to sequentially change the output value in the order of L-> H-L synchronized with the timing to generate a signal c 2. Then the 'semiconductor test device' corresponds to each method in the same way as c2: cycles c3 to c8 are generated sequentially. At this time, as shown in FIG. 4 and (C), the IC i supplied from the semiconductor device is shown in FIG. 4. 'In the period m smaller than the minimum period n, the device supply ^^^ A " is obtained by 1C30. From the semiconductor test number, etc.卩 Control signals (control signals, address signals, and data signals are as described above. According to this implementation object IC30, the semiconductor test two = + conductor test method, the signal C1 of the inspection movement. That is, Γ can be two J: for more than The highest frequency frequency wave operates at high frequency speed. Because: 1 ^ 0 is the best method to exceed the semiconductor test device, which can improve the current 4-body semiconductor test. The semiconductor test device can process the I version I1 忒 device with the current implementation. A half-inspection of the form. As in the first embodiment, A " forms the signal period of the output period m and the form of the signal is allowed to correspond to each cycle: = restricted. However, in this embodiment, therefore, according to this embodiment, It takes two cycles to generate. It can be compared to the occasion. It can be compared to the ί: f test device and the first embodiment of the __, 4 to continuously supply the signal of the cycle m to 89112503.ptd 18th stomach 554172 V. Invention Explanation (15) ^ See the period n3 is less than 1/3 of the minimum period n. The generation of the signal cl causes the timing generator 18 to generate when the time from the end of the initial minimum period n is equal to 2 X n3. } Timing, After that, the timing is generated at time n3, and then the third Tingrim Temple is generated at time n3. At the same time, the generator 20 in FIG. 2 synchronizes the output signals with the above three timings in the order of LH-L-Η The value of the semiconductor test device according to this embodiment is then to generate a signal ". The signal d 丄 is at the L level after a predetermined period η3 after the signal cl falls, and then rises to the Η level and the η level after the period n3 = 疋. Only keep it at the specified time period =, and then decrease. The timing generator 18 corresponds to the second minimum period n, and every time n3 time elapses from the rise of the signal cl, 3 timing signs can be sequentially generated, and the pattern generator 20 Synchronize with these timings and sequentially change the output value in the order of η-dagger to generate the signal c2. The semiconductor test device of the first form then generates a signal ". The signal c is at 彳 §. 2 falls after the specified The period n3 becomes the η level, and then falls to the L level after the specified period η3, and the L level is maintained only within the specified η3 = and then rises. The timing generator 丨 8 corresponds to the third minimum period η and falls from the signal c2 At the beginning of each "time, 3 timing signals can be generated in sequence, and the pattern is generated as 2 0. Synchronize with these timings and change the output value in the order of [η — L — 依次], and then generate the signal c3.… Later, the semiconductor test device The same method for generating the c2 signal should generate the sum of the 4th and 6th minimum periods. At the same time, the same method for generating the signal should generate the c5 for the 5th minimum period. At this time, the signal C1 supplied to the IC30 from the half is set. 'As shown in Figure 5 (c),

第20頁、發明說明（17) 圖6表示為了言兑日月士的定時流程圖。更的半導體測試裝置的動作裳置的動作周期：二;二!準：6二A…與半編圖6 ( A )所-如、的^卓外部時鐘信號R1的波形。如 n相-致的速度以前達ί]^卜時鐘信舰的周期與最小周期速化。圖6 (B )夺-射+泠脰測試裝置的動作周期可以高試裝置輸出信號c; :c8 :=周期的各個周期的半導體測〜⑸一致的輸出作波：丄：6 (C)表示與上述信號示的輸出作辦r f 本實施形態，請（C)所太本:二乍為日可鐘信號提供給檢查物件IC30。声i¥ : I 2卜的半導體測試裝置，於上述圖2所示的S1 0 4 ^ — σ ^Cl。仏號cl在最小周期η當中上升到Η水平，牲1 ρ見疋的期間η3保持Η水平，然後於所規定的期間η3保水平。在下一個最小周期π當中上升到Η水平。規定的 ^η3是1、於最小周期nm/3的時間。信號cl的生成，使，％產生1 8在最初的最小周期n的結束為止的時間小於2 ※η 3規疋日才期内產生第1定時、而後每經過一次w時刻就使其產生第2和第3定時，與此同時使圖案產生器2〇與上述 3個疋日守同步，按照L — Η — L — η的順序改變輸出信號的值0 本實施形態的半導體測試裝置，接著生成信號以。信號 c2 ’於信號cl上升後在規定的期間η3後成為[水平，然後在經過規定的期間η3後上升到Η水平，Η水平只保持在規定的η3期間’然後下降。定時產生器1 8對應第2個最小周期 η，從信號c 1上升開始每經過η3時間就能依次產生3個定時Page 20, Description of the invention (17) Figure 6 shows the timing flow chart for talking to the sun and moon. Further operation of the semiconductor test device The operation cycle of the device is as follows: two; two! Quasi: six two A ... and a half series Figure 6 (A)-the waveform of the external clock signal R1. For example, the phase-to-phase speed was previously reached. The speed and minimum cycle of the clock and ship were accelerated. Fig. 6 (B) The operation period of the capture-emission + ling test device can output the signal c of the high-test device;: c8: == semiconductor measurement of each period of the cycle ~ ⑸ consistent output wave: 丄: 6 (C) With the output of the above-mentioned signal operation rf In this embodiment mode, please (C) Taiben: Erzha provides the signal to the inspection object IC30. Sound i ¥: I 2 b semiconductor test device, S1 0 4 ^ — σ ^ Cl shown in FIG. 2 above. No. cl rises to the level of Η in the minimum period η, and η3 is maintained at the level of 13 during the period of time 1 ρ, and then maintained at the level of η3 for the prescribed period. It rises to π in the next minimum period π. The prescribed ^ η3 is a time in the minimum cycle nm / 3. The signal cl is generated so that the% generation time is less than 2 before the end of the initial minimum period n. ※ η 3 generates the first timing within the day period, and then generates the second time every time w passes. At the same time as the third timing, at the same time, the pattern generator 20 is synchronized with the above-mentioned three day guards, and the value of the output signal is changed in the order of L — Η — L — η. The semiconductor test device of this embodiment then generates a signal. To. The signal c2 'becomes the [level] after a predetermined period? 3 after the signal cl rises, and then rises to the Η level after the lapse of the predetermined period η3, and the Η level remains only within the predetermined η3 period' and then falls. The timing generator 18 corresponds to the second minimum period η, and 3 timings can be sequentially generated every time η3 elapses from the rise of the signal c 1

89112503.ptd 第22頁 554172 五、發明說明（18) 信號，並且圖案產生器20與這些定時同步並依次按照H — Η — L的順序改變輸出值，依此生成信號“。本實施形態的半導體測試裝置，接著生成信號以。信於 c 3 ’於彳§號c 2下降後在規定的期間η 3後成為Η水平，然後在規定的期間η3後下降到L水平，L水平保持在規定的=髮間，然後上升。定時產生器18對應第3個最小周期n，彳^ j 號c 2下降開始母經過η 3時間就能依次產生3個定時作號並且圖案產生器2 0與這些定時同步並依次按照L — η 〜的順序改變輸出值，依此生成信號(：3。以後，半導體測試裝置以產生C2信號同樣的方法應偶數編號（第4、第6及第8 )的最小周期產生信號c4和對 c6及C8，同時以產生信號㈡同樣的方法對應奇數/第已ϋ 第7 )的最小周期產生信號c5及以。此時，從半供給腳的信號π，如圖6 (c)所示，在小於最小且周;月置n 2周期m内變化。圖6 (C)所示的"A„ ，是1(：3〇獲取的從半導肽測試裝置供給的外部控制信號（控制信號、位址號、資料信號等）。 ^ 按照本實施形態的半導體測q古、土卜夺月丑，則式方法，母經過最小周期η 可產生3次定時，因此與實施彤能坦似壬> β、古，, /、貝她形悲1或2相比，能夠為IC30 么、更南頻率的輸出信號。戶斥、,. w Μ、目i 4七4 1 * 所以’根據本實施形態的半導體測试方法，可以繼维传用盾士 ^ ^ TP使用原有的半導體測試裝置，與實 ί Ϊ 4 Ϊ /、C測試的動作速度可進-步提高。本貫施形悲的半導體測續駐片味如„ 扣— > …、八放置，在能夠輸出周期為m的 5虎期間’與貫施形態3的場人说6 士 7 %合一樣受有限的時間限制。89112503.ptd Page 22 554172 V. Description of the invention (18) Signals, and the pattern generator 20 synchronizes with these timings and sequentially changes the output value in the order of H-Η-L, and generates signals accordingly. "Semiconductor of this embodiment The test device then generates a signal. Believe that c 3 ′ drops at 彳 § number c 2 and becomes a Η level after a predetermined period η 3, and then falls to an L level after a predetermined period η 3, and the L level is maintained at a predetermined level. = Interval, then rise. The timing generator 18 corresponds to the third minimum period n, 彳 ^ j number c 2 starts to fall. After the time η 3, the mother can generate 3 timing numbers in sequence and the pattern generator 20 and these timings. Synchronize and sequentially change the output value in the order of L — η ~, and generate a signal accordingly: (3. In the future, the semiconductor test device should use the same method for generating the C2 signal as the minimum period of the even number (4th, 6th, and 8th). Generate signal c4 and pair c6 and C8, and use the same method to generate signals ㈡ to generate signals c5 and above corresponding to the minimum period of odd / numbered 第 7). At this time, the signal π is supplied from half of the foot, as shown in Figure 6 ( c) as shown in It is less than the minimum and week; the month is set to change within a period of m. The "A" shown in Fig. 6 (C) is an external control signal (control signal, control signal, Address number, data signal, etc.) ^ According to this embodiment, the semiconductor method is used to measure the ancient and the earth to capture the moon, and the formula method, the mother can generate 3 timings after the minimum period η, so it is similar to the implementation of Tongneng & gt β, ancient, /, compared with Beta 1 or 2, can be the output signal of IC30, more south frequency. Hu Hu, .. w Μ, head i 4 7 4 1 * So 'according to this implementation The semiconductor test method of the form can continue to use the shield tester ^ ^ TP uses the original semiconductor test device, and the actual test speed can be further improved. The taste of semiconductor continuity films is like „buckle —…, eight places, during the period of 5 tigers capable of outputting period m ', and the same time as the field person of Form 3 said that 6 ± 7% is subject to a limited time limit.

89112503.ptd 第23頁 554172 圖式簡單說明圖1為本發明實施形態1〜4的半導體測試裝置的方塊圖。圖2為使用圖1所示的半導體測試裝置進行半導體測試時說明處理流程的流程圖。圖3為說明本發明實施形態1的半導體測試裝置動作用的定時圖。圖4為說明本發明實施形態2的半導體測試裝置動作用的定時圖。圖5為說明本發明實施形態3的半導體測試裝置動作用的定時圖。圖6為說明本發明實施形態4的半導體測試裝置動作用的定時圖。圖7為說明習知半導體測試裝置動作用的定時圖。傖89112503.ptd Page 23 554172 Brief description of the drawings Fig. 1 is a block diagram of a semiconductor test device according to the first to fourth embodiments of the present invention. Fig. 2 is a flowchart illustrating a processing flow when a semiconductor test is performed using the semiconductor test device shown in Fig. 1. Fig. 3 is a timing chart for explaining the operation of the semiconductor test apparatus according to the first embodiment of the present invention. Fig. 4 is a timing chart for explaining the operation of the semiconductor test apparatus according to the second embodiment of the present invention. Fig. 5 is a timing chart for explaining the operation of the semiconductor test apparatus according to the third embodiment of the present invention. Fig. 6 is a timing chart for explaining the operation of the semiconductor test apparatus according to the fourth embodiment of the present invention. FIG. 7 is a timing chart for explaining the operation of a conventional semiconductor test device. rude

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Claims

554172 22 m ^ ± a 鍾89”潮六、申請專利範圍 ].一種半導體測試裝置’其係對半 @ νργ 進行動作測試者，其特徵為包含有··且、mk hn，疋％·產生器’與半導體測試裝置的勒你闽如八依次產生複數個定時； /置的動作周期分別對應並圖案產生器，與上述定時產生哭而可改變輸出信號的值；以及°。生的定時分別同步控制機構，上述定時產生器在每㈣下限的最短周期的】/2的短間母:内動二時使對應每個動作周期之最初定時的產生時:疋/ 母個動作周期中以規定長度逐漸從動/ :到起點側，藉此得以在上述圖案產二;2側移動最小周期還要短的周期來士成/、〇〇成以較上述 ::2.如申續專利i = ϋ成1周期之變化的輸出信號。 I本a神玄丄靶圍弟1項之半導體測試裝置，：&中^、才、 l':f9每個動作周期產生的定時數是2個/、 L f間=產生定時’係在小於上述最短周期的1/2的第1規定 Θ上述控制機構，係移動上述最 I應每個動作周期的第2個定時斑對 __個 ^月俾使對舍初定時之間的間隔，變成 ς 冑作周期的最質0 ，士夂成上述弟1規定間隔。 i 内二：：請專利範圍第2項之半導體測試裝置疋4產生器，係可在下一個動作周期生、中上迷動作周期的第2個定時， /、產生對應每個上，制機構’係用以將產生上述最初定點’ δ又疋成上述2個宁η主4·Λ» η /月的起個疋時拖延2個動作周期所產生的萨 t期。 89112503.ptc 第28頁 554172 修正案號 89112503 六、申請專利範圍 —4士如申請專利範圍第1項之半導體測試裝置，其中上述定牯產生器在每個動作周期產生定時數為3，以。玄寻3個疋日守’係在小於上述最短周期的1 / 3的第2個指定間隔内產生，兄上述控制機構，係移動上述最初的定時產生時期，俾使上述控制機構在對應每個動作周期的第3個定時與對應下一個動作周期的最初定時之間的間隔，變成上述第2規定間隔。 …%如申請專利範圍第4項之半導體測試裝置，其中上述定時產生器，係可在下一個動作周期中產生對應每個作周期的3個定時的一部分，戸上述控制機構，係用以將產生上述最初定時時期的起點設定成上述3個定時拖延2個動作周期所產生的時期。554172 22 m ^ ± a bell 89 ”Tide VI. Patent Application Scope]. A semiconductor test device 'It is a tester for the action of half @ νργ, which is characterized by including ... and, mk hn, 疋% · generator 'Several timings are generated in sequence with the test device of the semiconductor test device; the set operation cycles correspond to the pattern generators, which can change the value of the output signal with the above-mentioned timings; and °. The timings are generated separately. Control mechanism, the shortest period of the shortest period of each timing generator] / 2 short time mother: internal movement of two o'clock makes the initial timing corresponding to each operation cycle: 疋 / mother action cycle with a predetermined length Gradually move from /: to the starting point side, thereby making it possible to produce the second pattern in the above pattern; the minimum period of movement on the 2 side is shorter than the above period. The output signal is changed in one cycle. I This is a semiconductor test device for the God Xuanyuan target sibling 1 item: & 中 ^ 、才, l ': f9 The number of timings generated per operation cycle is 2 /, L f interval = generation timing 'is less than The first stipulation of 1/2 of the shortest period described above is that the above-mentioned control mechanism moves the second timing spot pair __ ^^ of each operation cycle of the above-mentioned minimum cycle so that the interval between the initial timing of the pair becomes The maximum quality of the operating cycle is 0, and the interval between the above-mentioned brothers is 1. i Inner 2: The semiconductor test device 请 4 generator, which is subject to the scope of the patent, can be generated in the next action cycle. At the second timing of the cycle, /, corresponding to each generation, the control mechanism 'is used to generate the above-mentioned initial fixed point' δ into the above two Ning η main 4 · Λ »η / month delay time Sat period generated by 2 action cycles. 89112503.ptc Page 28 554172 Amendment No. 89112503 6. Patent application scope—4 semiconductor test devices such as the first scope of patent application, where the above-mentioned fixed generator is in each The number of timings for each operation cycle is 3, so Xuan Xun's 3 day guards are generated within the second specified interval that is less than 1/3 of the shortest period. The above control mechanism is moved by the above initial timing. Period The interval between the control mechanism's third timing corresponding to each operation cycle and the initial timing corresponding to the next operation cycle becomes the above-mentioned second specified interval.…% As for the semiconductor test device in the fourth scope of the patent application, where The timing generator can generate a part of the 3 timings corresponding to each working cycle in the next operation cycle. 周期 The control mechanism is used to set the starting point for generating the initial timing period to the above-mentioned 3 timing delays and 2 The period of the action cycle.

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