550769 —一___^_修正 五、發明說明（1) 〜^ 本發明專利隸屬一種晶圓級構裝體之技術領域，藉由 晶片於連結塾塊（Pad)頂面形成導電或非導電體的彈曰性 體’並於彈性體上植設導電體的特殊設計，有效解決晶片 構裳體（D i e)貼設於基板時，常因熱膨脹係數所生之剝 離及變形問題，有效的提升晶片（丨c)整體的傳輪品質及 生產良率。 、 按’為因應科技產品的功能日趨精緻，晶片（丨c)封 裝的接腳數越來越多，晶片（1C)尺寸縮小也就更為迫 切’利用傳統表面黏著技術之晶片（丨c)封裝漸漸無法滿 足這些需要，而現有的晶片（IC)封裝方法有薄小型之引 腳式封裝體（TS0P)、球陣式之封裝體（BGA)、尺寸型 之封裝體（CSP)及晶圓級之封裝體（WLCSP)等，但以薄 小型之引腳式封裝體（TS0P):為例其導線架太大、且引線 太長延遲（Delay)太久，無法提供高傳輸之需求，且無 法縮小其面積，而球陣式之封裝體（BGA)因其基板面積 太大’而造成延遲（Delay)，雖已比薄小型之引腳式封 裝體（TS0P)之功能增強了許多，然仍無法達成高傳輸、 低成本之需求，而尺寸型之封裝體（CSP)雖已倶備此能 力，但仍擺脫不了基板，打線連接（Wire Bond)、封膠 (Encapsulant)之封裝製程，晶圓級之封裝體（WLCSP) 雖然已經不需封裝，但因錫球（Solder ball)直接上在 構裝體（Die)上，而構裝體（Die)之熱膨脹係數 (CTE)約為百萬分之3〜4，當此構裝體（Die)焊接於基 板上時，會因與基板之熱膨脹係數（CTE)(約為百萬分 之16〜18)差異太大，而影響可靠性（Rel iabi 1 i ty)(會 550769 MM 90131783 年 月 曰 五、發明說明（2) 斷裂）’或者需在主板與晶片（IC)間灌入填充劑以黏著 雙方’但灌入填充劑之製程並不容易處理（良率不高）、 且又太貴’再者晶圓級之封裝體（WLCSp)此種方式之長 金屬層的成本太高、且又需封膠，無疑又多了成本； 由於上述不論係在封裝方法有薄小型之引腳式封裝體 (TS0P) '球陣式之封裝體（BGA)、尺寸型之封裝體 (csp)或是晶圓級之封裝體（WLCSP)等各種不同的封裝 體上，均各自存在有不少的問題，因此在美國專利第 5,67255 0號、第6,32949 7號、歐盟專利£?1137067、日本 專利JP6 1 2 6 0 64 9，以及台灣專利公告第46 5 〇58號「無接腳 式=方扁平封裝結構及其製造方法」、公告第464 9 6 1號 「咼性能積體電路晶片封裝」、公告第4 6 4丨5 4號「改善撓 曲之基板構造」、公告第464〇54號「積體電路之封裝二 構」、公告第46 3342號「覆晶式四方肩平無接腳構裝、°、 么告第463274號「晶圓級晶片尺寸構裝之 告第45768 1號「晶片封裝方法等 ^ +套」及么 則述各種封裝體或方法所面臨的問題。 别解決 基於上述的推論，現有的封裝 未臻完善，而仍然分別存在有不裝：法的設計尚 一種具有高傳輸、且高密度，並担 文如何開發出 裝體及方法，係被期待的Γ 、…升整體良率的封裳構 有签於此’本發明人乃藉由 與開發經驗，#對上述晶片以領域的研究 入採討，並積極尋求解決的方案，^ —面臨的問題深 作，終於成功的發明出_種晶構開發與試 —_s __ 攝裝體及其製作方法， 550769 修正 五、發明說明（3) 藉以有效克服熱膨脹係數的 .,^ 為達到上述各項目的：題，亚大幅提升產品良率。 手段來進一步呈體實本發明主要係透過下列的技術 ^ « ( Waf eVt ^ ^ ^ ： ,ρ ^ 的連結墊塊（Pad)内加入雪：：在金屬層 體，再完成晶圓（Wafer) #導電或Γ導電性質的彈性 導電體連接； 後續該完成之製程即可，再與 藉此，可使切割下來的 e u , 接焊接於基板上，而完全不=顆曰曰片（IC)構裝體即可直 係數（CTE)，而達到防止餘需填充劑’同時吸收掉熱膨脹 整體的良率。 欠形或剝離的現象，有效提升 接下來舉一較佳實施例， 做進一步之說明，其能使責㈠時配合下列的圖式及圖號 的瞭解，惟以下所述者僅為用$查委員對本發明有更詳細 例，並非企圖據以對本發明做2解釋本發明之較佳實施 以本發明之創作精神為基礎，而=形式上之限制，故凡是 或變更，皆仍應屬於本發明意圖發，任何形式的修飾 本發明係一種可吸收單顆曰曰曰片、4 。 係數（CTE)的晶圓級構裝體及/ ( IC)與基板間熱膨脹 圖所顯示者，本發明係於單顆晶片法，請參閱第一 俗稱構褒體（Die)】上形成金屬\^)構裝體I5【亦即 【此為晶片製程】，然Pad) ^ 20 上佈設有一層彈性體1 0，該彈性體、了塊（Pad)層 非導電材質所製成，本發明的彈^貝/n係由導電性材質或 且在於彈性體10頂面設置導電^體°;石夕膠為實施例’ 艰3〇，隶後於該導電體3 0頂 ^ ~-—-——— 550769 案號 90131783 年 月— 修正 五、發明説明（4) 面設置導電體4 0，該導電體4 0係用來直接焊設於基板（圖 中未視）上’藉以利用彈性體1 0的應變量與導電體3 0之延 展性來吸收晶片（I C)構裝體1 5與基板間的熱膨脹係數 (CTE)變形量； 至於本發明上述構裝體的製造方法，則係如第二圖所 示，其包含有： A、 在晶圓5 0 ( Wafer)製程中的最後一層護層55表面 上最後一金屬層60，並於塗佈一層光阻65 ( PR)後，經曝 光顯影後留下覆蓋於連結墊塊20 ( Pad)上的光阻65 (PR)，然後以勒刻的方式將光阻65 ( PR)以外的金屬層 60除去，接著去除光阻65 ( PR)，於晶圓50 ( Wafer)表 面形成所需之連結墊塊2 0 ( Pad); B、 在第一次去除光阻65 ( PR)後，再一次於晶圓50 (Wafer)表面塗佈光阻70 ( PR)，並以曝光顯影方式去 除連結墊塊20 ( Pad)上方的光阻70 ( PR)，使光阻70 (PR)形成開孔狀； C、接著將彈性體1 0材質印在開孔處（開孔 <=連結墊 塊20 ( PAD)大小，並#應連結墊塊20 ( Pad)處），然後 再將其他光阻70( PR)去除，使晶圓50( Wafer)表面的 連結墊塊2 0 ( Pa d)頂面形成彈性體1 〇 ; D、最後再鍍上一層金屬層80(可為濺鍍、無電電鍍、有 電電鍍或化學電鍍等製程），並於金屬層8〇頂面上一層光 阻9 0 ( PR) ’且在經過曝光顯影後，留下開孔對應彈性體 1 0的光阻9 0 ( PR)，而在經過蝕刻的製程後，於彈性體i 〇 頂面形成導電體3 0，最後在於導電體3 〇周圍塗佈護層3 5即 550769 案號 90131783 曰 五、發明說明（5) 可，最後並於導電體30形成一供與基板接觸的導 。 藉此，本發明在經過前述鍍金屬層6〇形成連社 (Pad)，再於連結塾塊20( Pad)上形成=心 於彈性體i〇上形成導電體40的製程，使晶圓^後 在切割成早顆晶片15( IC)構裝體後，再盥 可利用，•體10與導電胃40之延展 連，時’ f ΓΤΡ、的傲祀旦 + , 收熱膨脹係數 (CTE)的k形里，有效提升其良率， 高傳輸、…度及降低成本的晶圓構裝且體構成-種具有 又鈾述印上彈性體的流程，亦可以鋼版_ 性體印於連結墊塊（Pad)頂面· 、、同版的方式將彈 =刚印於定位點上或直接以光阻材料（pR):為方彈 構，=ί:ΪΓ透過本發明特殊的製作方法與結 J如本發明的構裝體至少存在有下列的優點及實用價值； 1 、提高產品良率： 由於晶片（I C)構裝體的連結墊塊 間形点右一强料辦 α 、racu興导電體 單顆曰片（1C)槿駐辨用彈性體具有相當應變性的特性， 脹，（CTE)所產生的變形有收兩者 或剝離的現有，大幅的提升 避尤知玍蔓形 率。 圾开早I顆日日片（1C)連接基板之良 2、減少不必要之設備與製程： 承前所述，由於單羱s μ , Τ Γ、W & 的效果佳極，因此相f+ ρ ^曰（）構裝體在連貼基板時 —_ 此相對上亦不需要如佈置構裝禮(Die) 550769 ___案號90131783_年月曰 修正__________ 五、發明說明（6) 之機器（BONDER)、打線機（ Wire BONDER)、封膠 (Encapsulant)等機台設備的投資，也可以減少不必的 製程。 3、降低成本： 由前述兩點說明，進一步可以理解到，在產品良率提 升、設備與製程減少後，確實可降低產品的製程成本，有 效提升其經濟效益。550769 — a ___ ^ _ Amendment V. Description of the invention (1) ~ ^ The invention patent belongs to the technical field of a wafer-level structure, and a conductive or non-conductive body is formed on the top surface of a pad by a wafer. The special design of the “elastic body” and the conductive body planted on the elastic body can effectively solve the problem of peeling and deformation often caused by the thermal expansion coefficient when the wafer structure (Die) is attached to the substrate, effectively improving Chip (丨 c) overall transfer quality and production yield. According to 'for the increasingly sophisticated functions of technology products, the number of pins of the chip (丨 c) package is increasing, and the reduction in the size of the chip (1C) is even more urgent.' Chips using traditional surface adhesion technology (丨 c) Packaging is gradually unable to meet these needs, and the existing chip (IC) packaging methods include thin and small pin package (TS0P), ball array package (BGA), size package (CSP) and wafer Level package (WLCSP), etc., but taking a thin and small lead package (TS0P): as an example, the lead frame is too large, and the lead is too long delay (Delay) is too long, and can not provide high transmission requirements, and Can not reduce its area, and the ball array package (BGA) because of its substrate area is too large 'Delay' (Delay), although the function has been much enhanced than the thin and small lead package (TS0P), but Still unable to meet the requirements of high transmission and low cost, although the size package (CSP) has been equipped with this capability, but still cannot get rid of the substrate, wire bonding (Wire Bond), encapsulant (Encapsulant) packaging process, crystal WLCSP package Package, but because the solder ball (Solder ball) is directly on the structure (Die), and the thermal expansion coefficient (CTE) of the structure (Die) is about 3 to 4 parts per million, when this structure ( Die) When soldering to a substrate, the coefficient of thermal expansion (CTE) (approximately 16 to 18 parts per million) is too different from the substrate, which affects reliability (Rel iabi 1 i ty) (meeting 550769 MM 90131783) May 5th, invention description (2) Fracture) 'or filler needs to be filled between the main board and the chip (IC) to adhere to both sides', but the process of filling the filler is not easy to handle (the yield is not high), and Too expensive, and the wafer-level package (WLCSp) has a long metal layer that costs too much, and requires sealing, which is undoubtedly more expensive; because the above-mentioned packaging method has a thin and small lead, Pin packages (TS0P) 'ball array packages (BGA), size packages (csp) or wafer-level packages (WLCSP) There are few problems, so in US patent No. 5,67255 0, 6,32949 7, European Union patent £ 1137067, Japanese patent JP6 1 2 6 0 64 9 and Taiwan Patent Bulletin No. 46 5 0058 "Pinless Type = Square Flat Package Structure and Manufacturing Method", Bulletin No. 464 9 6 1 "Performance Integrated Circuit Chip Package", Bulletin No. 4 6 4 丨 5 No. 4 "Improved deflection of the substrate structure", Announcement No. 4640404 "Second package of integrated circuit", Announcement No. 46 3342 "Flip-chip quadrilateral flat shoulderless structure No. 463274 "Wafer-level Wafer Dimension Construction Report No. 45768 No. 1" Wafer Packaging Methods and Other Sets "and Mod. No. 4 describes the problems faced by various packages or methods. Do n’t solve the problem. Based on the above inferences, the existing package is not perfect, but there are still disguises: the design of the method is still a high-transmission, high-density, and how to develop a package and method is expected Γ, ... Feng Sang, who has improved the overall yield, has signed here. The inventor has used the development experience to #review the above-mentioned wafers in the field of research and actively seek solutions. ^ —Problems facing After further research, we finally succeeded in inventing the _ seed crystal structure development and test — _s __ camera body and its manufacturing method, 550769 Amendment V. Description of the invention (3) In order to effectively overcome the thermal expansion coefficient., ^ In order to achieve the above items: Problem, Asia substantially improved product yield. Means to further actualize the present invention is mainly through the following technology ^ «(Waf eVt ^ ^ ^:, ρ ^ to join the pad (Pad) snow: :: metal layer body, and then complete the wafer (Wafer) # Conductive or Γ conductive elastic conductor connection; the subsequent process can be completed, and then with this, the cut eu can be connected to the substrate without soldering = IC The body can have a coefficient of straightness (CTE) to prevent the remaining fillers from absorbing the overall yield of thermal expansion at the same time. The phenomenon of under-formation or peeling effectively improves the next example, for further explanation, It can be used in conjunction with the understanding of the following drawings and numbers, but the following is only a detailed example of the present invention with $ check members, and is not an attempt to explain the preferred implementation of the present invention based on 2 Based on the creative spirit of the present invention, and = restrictions on the form, any changes or changes should still belong to the intention of the present invention, any form of modification The present invention is an absorbable single piece of film, 4. Coefficient (CTE) wafer level fabrication As shown in the thermal expansion diagram between the body and the (IC) and the substrate, the present invention is based on a single wafer method. Please refer to the first commonly known as the structure (Die) to form a metal \ ^) the structure I5 [that is, [ This is the wafer manufacturing process], but Pad) ^ 20 is provided with a layer of elastomer 10, which is made of a non-conductive material of Pad layer. The elastic shell of the present invention is made of conductive material. Or, a conductive body is provided on the top surface of the elastic body 10; Shi Xijiao is an example of the 'hard 30', followed by the conductive body 30 top ^ ~-----550769 case number 90131783 month-amendment V. Description of the invention (4) A conductive body 40 is provided on the surface, and the conductive body 40 is used to be directly soldered on a substrate (not shown in the figure) so as to use the strain of the elastic body 10 and the conductive body 30. The ductility is used to absorb the thermal expansion coefficient (CTE) deformation between the IC (IC) structure 15 and the substrate; as for the manufacturing method of the above structure of the present invention, as shown in the second figure, it includes: A The last metal layer 60 is on the surface of the last protective layer 55 in the wafer 50 (wafer) process, and after a photoresist 65 (PR) is applied, After exposure and development, the photoresist 65 (PR) covering the connecting block 20 (Pad) is left, and then the metal layer 60 other than the photoresist 65 (PR) is removed by engraving, and then the photoresist 65 (PR) is removed. ), Forming the required bonding pads 20 (Pad) on the surface of the wafer 50 (Wafer); B. After removing the photoresist 65 (PR) for the first time, coating the wafer 50 (Wafer) surface again Photoresist 70 (PR), and remove the photoresist 70 (PR) above the connecting block 20 (Pad) by exposure and development to make the photoresist 70 (PR) form an opening; C, then the elastomer 10 material Printed on the opening (the size of the opening < = link pad 20 (PAD), and # should be connected to the pad 20 (Pad)), and then remove the other photoresist 70 (PR), so that the wafer 50 ( Wafer) The surface of the connecting pad 20 (Pa d) on the top surface forms an elastic body 10; D. Finally, a metal layer 80 is plated (can be a process such as sputtering, electroless plating, electroplating or chemical plating), A photoresist 9 0 (PR) 'is formed on the top surface of the metal layer 80. After exposure and development, an opening corresponding to the photoresist 9 0 (PR) of the elastomer 10 is left, and after the etching process, , In the elastomer i 〇 A conductive body 30 is formed on the top surface, and a protective layer 3 is coated around the conductive body 30. That is, 550769, case number 90131783, fifth, description of the invention (5) Yes, and finally, a conductive body 30 is formed on the conductive body 30 for contact with the substrate. . With this, the present invention is a process of forming a pad (Pad) through the aforementioned metal plating layer 60, and then forming a bonding pad 20 (Pad) = forming a conductor 40 on the elastic body i0, so that the wafer ^ After cutting into an early chip 15 (IC) structure, it can be used again. • The extension of the body 10 and the conductive stomach 40, when 'f ΓΤΡ, proud of the +, thermal expansion coefficient (CTE) In the k-shape, it can effectively improve its yield, high transmission, ... degree and reduce cost. Wafer structure and body structure-a process with elastomer printed on uranium, can also be printed on steel pads. The top surface of the Pad (Pad), the same version, will be used = just printed on the positioning point or directly using the photoresistive material (pR): as a square elastic structure, = ΪΓ through the special manufacturing method and results J. The structure of the present invention has at least the following advantages and practical values; 1. Improve product yield: Because of the shape point between the connecting pads of the IC (IC) structure, a strong material α, racu guide Electric body single piece (1C) hibiscus elastomer has considerable strain characteristics. Swelling, (CTE) deformation can be both or peeled. The existing situation has greatly improved the rate of avoiding the spread of unknown knowledge. Good morning and day I (1C) connection substrate good 2. Reduce unnecessary equipment and processes: As mentioned before, because the effect of single 羱 μ, Τ Γ, W & is excellent, so phase f + ρ ^ (When the structure is attached to the substrate — relatively, it is not necessary to arrange the installation ceremony (Die) 550769 ___ Case No. 90131783 _ year month month amendment __________ V. Machine description (6) (BONDER), wire bonder (Wire BONDER), encapsulant (Encapsulant) and other equipment investment, can also reduce unnecessary manufacturing processes. 3. Reducing costs: From the foregoing two points, it can be further understood that after the product yield is improved and the equipment and processes are reduced, the process costs of the products can be reduced and the economic benefits can be effectively improved.
綜上所述，藉由本發明利用自然法則的高度創作，有效解 決構裝體易變形及剝離的問題，並提升其產品良率，同時 大幅提升其傳輸速度，完全符合專利法第十九條及第二十 條之規定，為一利用自然法則之高度技術的創作，故爰依 法提出發明專利申請，懇請貴審查委員賜予核准發明專 利0In summary, the invention uses the high degree of creation of natural laws to effectively solve the problem of easy deformation and peeling of the structure, and improve its product yield, while greatly increasing its transmission speed, which fully complies with Article 19 of the Patent Law and The provisions of Article 20 are highly technical creations that make use of the laws of nature. Therefore, they have filed an application for an invention patent in accordance with the law.
第9頁 550769 _____案號90131783_年月曰 一^L·____________________ 圖式簡單說明 (一） 圖式說明 第一圖：係本發明構裝體的局部剖面示意圖，用以說明各 層之相對關係。 第二圖：係本發明之製程步驟示意圖。 (二） 圖號說明 (10)彈性體 （15)晶片（1C) (20)連結墊塊（Pad) ( 30)導電體 (40)導電體 (5 5 )護層 (65)光阻 (80)金屬層 (50)晶圓 (60)金屬層 (70)光阻 (90)光阻Page 9 550769 _____ Case No. 90131783_Year Month ^ L · ____________________ Brief Description of the Schematic Diagram (1) Schematic Diagram The First Diagram: It is a partial cross-sectional schematic diagram of the structure of the present invention, which is used to explain the relative relationship of each layer . The second figure is a schematic diagram of the process steps of the present invention. (2) Explanation of drawing number (10) Elastomer (15) Chip (1C) (20) Connecting pad (Pad) (30) Conductor (40) Conductor (5 5) Protective layer (65) Photoresist (80 ) Metal layer (50) Wafer (60) Metal layer (70) Photoresist (90) Photoresist
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