TW545099B

TW545099B - Bump forming technology with high resolution

Info

Publication number: TW545099B
Application number: TW91113157A
Authority: TW
Inventors: Kun-Yao Ho; Moriss Kung
Original assignee: Via Tech Inc
Priority date: 2002-06-17
Filing date: 2002-06-17
Publication date: 2003-08-01

Abstract

A bump forming technology with high resolution is disclosed. The invention utilizes a dielectric layer which is preferably a release film and laser or plasma etching, to precisely define the pattern of solder bumps both on a substrate or a wafer so as to form openings with high resolution in the dielectric layer. Solder bumps thereby can be precisely formed on bump pads of the substrate and under bump metal layers of the wafer with high aspect ratio, fine pitch and high density. The invention overcomes alignment problems and high cost of the conventional method which uses a stencil mask or plating method to form solder bumps. The invention also solves the resolution problem of the conventional printing by using photo film defined mask instead of stencil mask method. Furthermore, the invention also solves the problems of high cost and long process time of conventional plating processes by utilizing a squeegee printing method to fill the openings having laser opened high aspect ratio, fine pitch and high resolution with a micro-solder ball powder/paste to form solder bumps.

Description

4 545099 五、發明說明（1) 5 - 1發明領域：本發明係關於一種高解析度銲接凸塊形成方法，特別是一種可形成高縱橫比（H i g h A s p e c t R a t i 〇 )細間距高密集度之銲接凸塊的銲接凸塊形成方法。 5-2發明背景：含有積體電路之半導體晶片為電子裝置中極重要的元件。這些半導體晶片通常固定在一具有端子的底材上以連接其他外部電路。此底材可為單層金屬導線架或是多層印刷線路板。除了提供半導體晶片其他外部電路的連接之外，底材也提供機械性的支撐。半導體晶片的外部包覆能保護半導體晶片不受外在環境以及外力衝擊的影響。4 545099 5. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming a high-resolution welding bump, particularly a method capable of forming a high aspect ratio (H igh A spect R ati) fine pitch high density Welding bump forming method of high-degree welding bump. 5-2 Background of the Invention: Semiconductor wafers containing integrated circuits are extremely important components in electronic devices. These semiconductor wafers are usually fixed on a substrate with terminals to connect other external circuits. This substrate can be a single-layer metal lead frame or a multilayer printed circuit board. In addition to providing connections to other external circuits of the semiconductor wafer, the substrate also provides mechanical support. The outer coating of the semiconductor wafer can protect the semiconductor wafer from the external environment and the impact of external forces.

第一 A圖至第一 G圖顯示一種傳統封裝製程之凸塊形成方法。參考第一 A圖所示，顯示一銲接凸塊形成前的元件封裝結構，此元件封裝結構包含一元件1 0 0、一銲墊1 0 2 ( Pad)、一保護層 104(Passivation Layer)與一銲接凸塊下金屬層106( Under Bump Metal)。如第一 B圖所示，為了形成銲接凸塊於銲接凸塊下金屬層1 0 6上，必須形成一光阻層1 0 8於第一 A圖所示的結構上。接著如第一 C圖所示，以微影製程將光阻層1 0 8曝光顯影以暴露出銲接凸塊下金屬層1 0 6，使銲接凸塊能形成於銲接凸塊下金屬層1 0 6。Figures A through G show a bump formation method for a conventional packaging process. Referring to FIG. 1A, a component packaging structure before a solder bump is formed is shown. The component packaging structure includes a component 100, a pad 102, a protection layer 104, and a passivation layer. An under bump metal layer 106 (Unbump Metal). As shown in FIG. 1B, in order to form a solder bump on the metal layer 106 under the solder bump, a photoresist layer 108 must be formed on the structure shown in FIG. Then, as shown in FIG. 1C, the photoresist layer 108 is exposed and developed by a photolithography process to expose the metal layer 106 under the solder bump, so that the solder bump can be formed on the metal layer 10 under the solder bump. 6.

第6頁 545099 五、發明說明（2) ~ - 接著如弟一 D圖所示，以雷供沾制 R 、 11Γ乂笔鍵的製程將一銲接凸塊（SolderPage 6 545099 V. Description of the invention (2) ~-Next, as shown in Figure D of D, a welding bump (Solder) is produced by the process of dipping the R and 11Γ 乂 pen keys with lightning.

Bump) 1 1 0形成於銲接凸媸析過程繁複且耗時較長久製鬼太^層1〇6上，而一般電鍍的塊於銲接凸換下入，久Ik成本較高。另一種形成銲接凸 Mask)將鲜锡膏上的方法是利用鋼版（Stencil 版上的圖案必須真::；版上的開口’前提是鋼 -種形成銲接凸塊於鋒接106精確對準。還有用一種光阻膜定義的印刷屬層106上的方法是利 Panting)方式，但 θ 為 h t〇 Fllm Defined 度而不適於米点一疋又又於光阻犋（Photo Film)的解、t成向縱橫比f w ; uBump) 1 1 0 is formed on the welding bump. The process is complicated and takes a long time to prepare the ghost layer 206. The general plating block is replaced by the welding bump, which has a high Ik cost. Another way to form solder bumps is to use fresh steel paste (the pattern on the Stencil plate must be true ::; the opening on the plate 'provided that the steel-a kind of solder bumps are formed on the butt joint 106 for precise alignment. There is also a method on the printed metal layer 106 which is defined by a photoresist film using the Panting method, but θ is ht ° Fllm Defined degree, which is not suitable for the solution of the photometer and t Directional aspect ratio fw; u

Fine Pitch、沾》日 1 ^ ttlgh Aspect Ratio)細間距 u的鲜接凸堍。果 q 4不形成銲接个▽而第一 F圖顯示蝕:鬼1 1 0後移除光阻層1 0 8的結護層1 0 4的結果。在正^杯接凸塊下金屬層1 〇 6以曝露出保程加熱後，銲接工進订銲接前，經回銲（Ref l〇w)製塊110形成如第—G圖所示的型態。上述傳統封裝制 A衣之Λ诒W !_、。弟一 A圖至第_ 6圖尾形成方法具有以下多項缺點成本的電鍍製程，而不的凸塊形成方法使用了耗時且高版成本高。另外光阻膜Z鋼版形成銲接凸塊對準不易且鋼 Printing)的方式受限疋義的印刷（Photo Film Defined 而不適於形成高縱$ 光阻膜（Photo Film)的解析度接凸塊。、 Hlgh AsPect Rat i〇)細間距的銲 545099 五、發明說明（3) 有鑑於上述傳統封裝結構與製程的缺點，因此有必要發展出一種新穎進步的結構與製程以克服傳統結構與製程的缺點。本發明正能符合這樣的需求。 5 - 3發明目的及概述：本發明之一目的為提供一種低成本與製程精簡且製程所需時間較短的銲接凸塊形成方法。本發明之另一目的為提供一種可形成較小的銲接凸塊與銲接凸塊間距的高縱橫比銲接凸塊形成方法。本發明之另一目的為提供一種對準精確度高的高解析度銲接凸塊形成方法。接步銲下度以析含解包高法種方一成供形提塊明凸發接本銲，度的析目解之高述該上，成法達方了成為形塊凸個、數塾複銲有二具第上個板數基複該有中具其上，圓圓日BB 晶該一而與，板膜基銲一防供一提與先塾首銲 ο 〆驟第個一數第複一及成層形護著保接之。墊層銲體二導第下該塊出凸露接暴銲以之口上開墊個銲數二複第有該具於一位入塾進銲案一圖第的該塊出凸露接暴銲並一 Π 第開個一數第複個移數轉複並成板形基以該層蓋電覆介層一電第介該"Fine Pitch, Dipping" Day 1 ^ ttlgh Aspect Ratio) Fresh ridges with fine pitch u. If q 4 does not form a solder joint, the first F picture shows the results of the etch: ghost 1 110 removal of the photoresist layer 108 protective layer 1 104. After the metal layer 1 06 under the positive cup connection bump is exposed to heat and exposed to heat, before the welder advances the welding, the block 110 is formed by reflow (Ref l0w) as shown in Figure -G. . Λ 诒 W! _, Of the above-mentioned traditional packaged A-coat. Yiyi Figure A to Figure _6 The tail formation method has many disadvantages such as the cost of the electroplating process, and the non-bump formation method uses time consuming and high cost. In addition, the photoresist film Z steel plate forms solder bumps that are difficult to align and the steel Printing method is limited. The meaning of the printing (Photo Film Defined is not suitable for the formation of high-resolution photo film). Hlgh AsPect Rat i〇) Fine-pitch soldering 545099 V. Description of the invention (3) In view of the shortcomings of the traditional packaging structure and process described above, it is necessary to develop a novel and progressive structure and process to overcome the traditional structure and process. Disadvantages. The present invention is able to meet such needs. 5-3 Objects and Summary of the Invention: An object of the present invention is to provide a method for forming a solder bump with low cost and streamlined manufacturing process, and a shorter processing time. Another object of the present invention is to provide a method for forming a high aspect ratio welding bump capable of forming a smaller welding bump-to-solder bump pitch. Another object of the present invention is to provide a method for forming a high-resolution solder bump with high alignment accuracy. In the next step of welding, the analysis of the unpacked high-level method is used to form the block and the convex block is sent out. The high-level analysis of the degree is described above.塾 Re-welding has two sets of the first plate number, and there should be the middle one. The circle BB crystals should be combined with each other, and the plate-film-based welding is to prevent the supply and mention the first welding first. 〆The first one Count the first one and protect it in layers. The second layer of the cushion welding body is exposed to the bottom of the block, and the number of the welding is opened on the mouth. The number of the welding is two, and the one of the block is exposed to the welding. First, the first, the first, the first, the second, the number of shifts are turned into a plate-shaped base, and the layer is covered with an electrical layer.

第8頁 545099 五、發明說明（4) 。然後將銲料如銲膏或微小銲球填入該第一開口並執行回銲製程。接著移除該第一介電層並形成一第二介電層覆蓋該晶圓。然後轉移複數個第二銲接凸塊的圖案進入該第二介電層以形成複數個第二開口並暴露出該銲接凸塊下導體層。最後將銲料如銲膏或微小銲球填入該第二開口及執行回銲製程。上述有關發明的簡單說明及以下的詳細說明僅為範例並非限制。其他不脫離本發明之精神的等效改變或修飾均應包含在的本發明的專利範圍之内。 5 - 4發明的詳細說明：在此必須說明的是以下描述之製程步驟及結構並不包含完整之製程。本發明可以藉各種製程方法來實施，在此僅提及瞭解本發明所需之製程方法。以下將根據本發明所附圖示做詳細的說明，請注意圖示均為簡單的形式且未依照比例描繪，而尺寸均被誇大以利於瞭解本發明。在本發明之較佳實施例中，凸塊形成方法係應用於覆晶封裝（Flip Chip Package)製程上。第二A圖至第二Η圖以及第三Α圖至第三Η圖分別顯示本發明較佳實施例中之有Page 8 545099 5. Description of the invention (4). Then, a solder such as a solder paste or a small solder ball is filled into the first opening and a reflow process is performed. The first dielectric layer is then removed and a second dielectric layer is formed to cover the wafer. The pattern of the plurality of second solder bumps is then transferred into the second dielectric layer to form a plurality of second openings and expose the conductor layer under the solder bumps. Finally, solder such as solder paste or micro solder balls is filled into the second opening and a reflow process is performed. The foregoing brief description of the invention and the following detailed description are examples only and are not limiting. Other equivalent changes or modifications that do not depart from the spirit of the invention should be included in the patent scope of the invention. 5-4 Detailed Description of the Invention: What must be explained here is that the process steps and structures described below do not include a complete process. The present invention can be implemented by various manufacturing methods, and only the manufacturing methods required for understanding the present invention are mentioned here. The following detailed description will be made according to the accompanying drawings of the present invention. Please note that the drawings are in simple form and not drawn to scale, and the dimensions are exaggerated to facilitate understanding of the present invention. In a preferred embodiment of the present invention, the bump forming method is applied to a flip chip package process. The second diagram A to the second diagram and the third diagram A to the third diagram respectively show some of the preferred embodiments of the present invention.

第9頁 545099 五、發明說明（5) 關於基板（Subs t rat e)部份之製程，而第四A圖至第四G 圖以及第五A圖至第五F圖則顯示有關於包含積體電路晶片之晶圓部份的製程。參考第二A圖所示，一基板2 0 0上具有複數個覆晶接合凸塊銲墊（Flip Chip Bump Pad) 20 2與一防銲膜（Solder Mask) 2 0 4。防銲膜係用於覆蓋並保護基板上銲接點以外的部份，並避免銲接凸塊形成於基板上銲墊以外的部份，同時避免基板上的電路導線受到外來環境的侵害。第二A 圖所示之基板20 0為非防銲膜定義（Non-Solder-Mask-Defined)的基板，但本發明所用之基板亦可為（Solder-^I a s k - D e f i n e d) 之基板，亦即防銲膜覆蓋整個基板包括凸塊銲墊的周邊，而僅暴露出凸塊銲墊的平面部份。防銲膜 2 0 4可由傳統的材料與方法形成，例如感光材料與曝光及顯影製程。接著參考第二B圖所示，在第二A圖所示之結構上覆蓋一介電層206，此介電層20 6以一離形膜（^丨6356 F i 1 m)較佳。而離形膜為一般封裝製程所用之介電膜，用於防止基板在運送至後續製程之過程中遭受外部環境所污染。本發明使用之離形膜則係用於定義銲接凸塊的形成位置並於製程完成後可剝離除去。參考第二C圖所示，介電層2 0 6為離形膜，钱刻介電芦 2 0 6的方式為垂直方向開孔加工的方法，例如非等向性|全刻法。特別是以雷射開孔（L a s e r )的方式或是電漿；|虫刻（Page 9 545099 V. Description of the invention (5) The process of the substrate (Subs t rat e) part, and the fourth A to fourth G and the fifth A to fifth F graphs show the inclusion product. The manufacturing process of the wafer portion of the bulk circuit wafer. Referring to FIG. 2A, a substrate 200 has a plurality of flip chip bonding pads Flip Chip Bump Pad 20 2 and a solder mask 2 0 4. The solder mask is used to cover and protect the parts other than the solder joints on the substrate, and to prevent solder bumps from being formed on the substrate other than the pads, and at the same time to prevent the circuit wires on the substrate from being attacked by the external environment. The substrate 200 shown in the second A is a non-Solder-Mask-Defined substrate, but the substrate used in the present invention may also be a (Solder- ^ I ask-De efined) substrate. That is, the solder mask covers the entire substrate including the periphery of the bump pads, and only the flat portion of the bump pads are exposed. The solder mask 2 0 4 can be formed by conventional materials and methods, such as photosensitive materials and exposure and development processes. Referring next to FIG. 2B, a dielectric layer 206 is covered on the structure shown in FIG. 2A. The dielectric layer 206 is preferably a release film (^ 6356 F i 1 m). The release film is a dielectric film used in general packaging processes, and is used to prevent the substrate from being contaminated by the external environment during the transportation to the subsequent processes. The release film used in the present invention is used to define the formation position of the solder bump and can be peeled off after the process is completed. Referring to FIG. 2C, the dielectric layer 206 is a release film, and the method of engraving the dielectric 206 is a method of vertical hole processing, such as an anisotropic | full engraving method. Especially in the form of laser perforation (Laser) or plasma; |

第10頁 545099 五、發明說明（6)Page 10 545099 V. Description of the invention (6)

Plasma Etching)的製程移除離形膜位於凸塊銲墊2〇 2上的部分’以形成開口（Opening)。利用雷射開孔或是電漿蝕刻可以達成向解析度精確對準的開口，使銲接凸塊能準確形成於凸塊銲塾上，同時可進一步縮小銲接凸塊的間距（ Pitch) ’並成功地形成咼縱橫比（high Aspect Ratio)細距高密集度之銲接凸塊。接著參考第二D圖所示，將銲馬或微小銲球（Solder Paste/Solder Powder) 208以刮刀 P刷（Squeegee Printing)的方式填入暴露出凸塊銲墊2〇2 /的開口内，並將溢出的銲膏或微小銲球移除。銲膏由許多认小銲球（Solder Sphere}、溶劑與助銲（炼）劑（Flux 構成’而銲球通常為共晶成分之錫鉛合金。參考第二E圖所示，第二_中所示之銲膏2〇8經回銲、清洗製程形成圖=的銲接凸塊21〇。而當使用微小銲球 p於印刷後回銲前再加入助銲劑，％此可將銲球氣泡縮 ^最少圖中，將介電層2〇6移除，並可使用 =式蝕刻或電： >月洗表®。然後如第二G圖中所示，可再，一次回銲製程。最後如第二H圖中所$，進行一次壓 :(C〇ining)製程使銲接凸塊21〇頂部平坦共平面性以利與晶圓上之銲接凸塊接人。有1 第三A圖至第三Η圖所示者為兀g 士之制1 一 A曰士具有防銲膜之基板部份 I 4程，一基板3 0 0上具有複數個考電肷从磁qnzi而筮- η固個设晶接合凸塊銲墊3 0 2與电路結構304。而第二Β圖所示兔太结叮不為在弟三Α圖所示之結構上Plasma Etching) removes the part of the release film on the bump pad 202 to form an opening. Using laser openings or plasma etching can achieve openings precisely aligned to the resolution, so that the solder bumps can be accurately formed on the bump pads, and at the same time, the pitch of the solder bumps can be further reduced (successfully). Ground to form high aspect ratio (high aspect ratio) fine-pitch high-density solder bumps. Next, referring to the second figure D, a soldering horse or a small solder ball (Solder Paste / Solder Powder) 208 is filled into the opening exposing the bump pad 20 / with a Squeegee Printing method. Remove spilled solder paste or tiny solder balls. The solder paste is composed of many small solder balls (Solder Sphere), solvents and fluxes (Flux), and the solder balls are usually tin-lead alloys with eutectic composition. Refer to Figure 2E, Second_Medium The solder paste 208 shown is formed into the solder bump 21 by the re-soldering and cleaning process. However, when using a small solder ball p to add a flux before re-printing after printing, the solder ball bubbles can be reduced. ^ At least in the figure, the dielectric layer 206 is removed, and can be used for etching or electricity: > Moon Wash®. Then, as shown in the second figure G, a re-soldering process can be performed again. Finally As shown in the second H figure, a single pressing: (Coining) process is used to make the top of the solder bump 21 ° flat and coplanar to facilitate access to the solder bump on the wafer. There are 1 third A to The third figure shows the structure of a Ugishi 1-A, a substrate with solder mask I 4 pass, a substrate 300 has a plurality of test electricity from magnetic qnzi and 筮-ηsolid A crystal bonding bump pad 3 0 2 and a circuit structure 304 are provided. The rabbit rabbit knot shown in the second picture B is not on the structure shown in the third picture A.

545099 五、發明說明（7) · 覆蓋介電層3 0 6與3 0 7的結果，介電層3 0 6與3 0 7用於定義銲接凸塊的形成位置，此而介電層3 0 6與3 0 7包含非感光性介電層，而介電層3 0 7以離形膜較佳。此外，介電層3 0 6與 3 0 7之間可選擇性地加上一黏性膠膜。接著參考第三C圖所示，介電層3 0 6與3 0 7被蝕刻以暴露出凸塊銲墊3 0 2，蝕刻介電層3 0 6與3 0 7的方式可為傳統垂直方向開孔加工的方法，例如非等向性蝕刻法。介電層 3 0 7為離形膜，則可以雷射開孔的方式或是電漿蝕刻的製程移除介電層3 0 6與離形膜位於凸塊銲墊3 0 2上的部分，以形成開口。利用電漿蝕刻的製程來形成開口必須於離形膜上應用蝕刻遮罩。利用雷射開孔或是電漿蝕刻可以達成高解析度精確對準的開口，使銲接凸塊能準確形成於凸塊銲墊上，同時可進一步縮小銲接凸塊的間距，並成功地形成高縱橫比細間距高密集度之銲接凸塊。接著參考第三D圖所示，將銲膏或微小銲球3 0 8以刮刀印刷的方式填入暴露出凸塊銲墊3 0 2的開口内，並將溢出的銲膏或微小銲球移除。銲膏由許多微小銲球、溶劑與助銲（熔）劑構成，而銲球通常為共晶成分之錫鉛合金。參考第三E圖所示，第三D圖中所示之銲膏3 0 8經回銲、清洗製程形成圖中的銲接凸塊3 1 0。而當使用微小銲球則須於印刷後回銲前再加入助銲劑，如此可將銲球氣泡縮減至最少。而於第三F圖中，將介電層3 0 7移除，並可使用545099 V. Description of the invention (7) · The results of covering the dielectric layers 3 0 6 and 3 0 7; the dielectric layers 3 0 6 and 3 0 7 are used to define the formation positions of the solder bumps, and the dielectric layer 3 0 6 and 3 0 7 include a non-photosensitive dielectric layer, and the dielectric layer 3 7 is preferably a release film. In addition, an adhesive film can be selectively added between the dielectric layers 306 and 307. Referring to FIG. 3C, the dielectric layers 3 06 and 3 7 are etched to expose the bump pads 3 2. The method of etching the dielectric layers 3 6 and 3 7 can be the traditional vertical direction. The method of the hole processing is, for example, anisotropic etching. The dielectric layer 3 07 is a release film, and the portion of the dielectric layer 3 6 and the release film located on the bump pad 3 2 can be removed by laser opening or plasma etching process. To form an opening. Plasma etching is used to form openings and an etching mask must be applied to the release film. The use of laser drilling or plasma etching can achieve high-resolution and precisely aligned openings, so that solder bumps can be accurately formed on the bump pads, and at the same time, the pitch of the solder bumps can be further reduced, and a high aspect ratio can be successfully formed. Higher density solder bumps than fine pitch. Next, referring to the third figure D, fill the solder paste or micro solder ball 3 0 8 with a doctor blade into the opening where the bump pad 3 2 is exposed, and move the overflowing solder paste or micro solder ball. except. Solder paste consists of many tiny solder balls, solvents and fluxes, and solder balls are usually tin-lead alloys with eutectic composition. Referring to FIG. 3E, solder paste 3 0 8 shown in FIG. 3 D is re-soldered and cleaned to form a solder bump 3 1 0 in the figure. When using micro solder balls, flux must be added before reflow after printing, so that the solder ball bubbles can be minimized. In the third F diagram, the dielectric layer 3 7 is removed and can be used.

第12頁 545099 五、發明說明（8) 乾式蝕刻或電漿清洗表面。然後如第三G圖中所示，可再進行一次回銲製程。最後如第三Η圖中所示，進行一次壓平製程使銲接凸塊31 0頂部平坦化並有較佳之共平面性以利與晶圓上之銲接凸塊接合。第四Α圖至第四G圖顯示本發明較佳實施例中之包含積體電路晶片之晶圓部份的製程。參考第四A圖所示，顯示本發明於銲接凸塊形成前包含積體電路晶片之晶圓部份元件封裝結構，此晶圓部份元件封裝結構包含晶片4 0 0、銲墊 4 0 2 ( Metal Pad)、保護層 4 0 4 ( Passivation Layer) 與銲接凸塊下金屬層406( Under Bump Metal)。銲墊402 包含鋁銲墊，但其他材料銲墊亦不應被排除。銲墊4 0 2可以傳統的沈積、微影與蝕刻製程形成。保護層4 0 4可由傳統方法形成。保護層4 0 4係被傳統的微影與蝕刻製程蝕刻以形成開口並曝露出銲墊4 0 2。銲接凸塊下金屬層4 0 6以傳統的沈積、微影與蝕刻製程形成於開口内及銲墊4 0 2上。接著參考第四B圖所示，在第四A圖所示之結構上覆蓋一介電層408，此介電層40 8以一離形膜（Release Film)較佳。而離形膜為一般封裝製程所用之介電膜，可輕易地被剝離。在經過一道簡易的清洗步驟後可被完全地移除。離形膜則係用於定義銲接凸塊的形成位置。接著參考第四C圖所示，介電層4 0 8被開孔以暴露出銲接凸塊下金屬層4 0 6，介電層4 0 8為離形膜，則可以雷射開Page 12 545099 V. Description of the invention (8) Dry etching or plasma cleaning the surface. Then, as shown in the third G diagram, a reflow process can be performed again. Finally, as shown in the third figure, a flattening process is performed to flatten the tops of the solder bumps 310 and have better coplanarity to facilitate bonding with the solder bumps on the wafer. Figures 4A to 4G show the manufacturing process of a wafer portion including an integrated circuit wafer in a preferred embodiment of the present invention. Referring to FIG. 4A, the present invention shows a component part packaging structure of a wafer including an integrated circuit wafer before the formation of a solder bump. The component part packaging structure of the wafer includes a wafer 4 0, a pad 4 2 (Metal Pad), protection layer 404 (Passivation Layer) and solder bump metal layer 406 (Under Bump Metal). Pad 402 includes aluminum pads, but other material pads should not be excluded. The pads 4 2 can be formed by conventional deposition, lithography and etching processes. The protective layer 4 0 4 can be formed by a conventional method. The protective layer 4 0 4 is etched by a conventional lithography and etching process to form an opening and expose the solder pad 4 2. The metal layer 406 under the solder bump is formed in the opening and on the solder pad 402 by a conventional deposition, lithography and etching process. Referring next to FIG. 4B, a dielectric layer 408 is covered on the structure shown in FIG. 4A. The dielectric layer 408 is preferably a release film. The release film is a dielectric film used in general packaging processes and can be easily peeled off. It can be completely removed after a simple cleaning step. The release film is used to define the formation position of the solder bump. Referring to FIG. 4C, the dielectric layer 408 is opened to expose the metal layer 406 under the solder bump. The dielectric layer 408 is a release film, which can be opened by laser.

第13頁 545099 五、發明說明（9) 孔（Laser)的方式或是電漿触刻（Plasma Etching)的製程移除離形膜位於銲接凸塊下金屬層4 0 6上的部分，以形成開口。利用雷射開孔或是電漿蝕刻可以達成高解析度精確對準的開口，使銲接凸塊能準確形成於銲接凸塊下金屬層上，同時可進一步縮小銲接凸塊的間距，並成功地形成高縱橫比（H i g h A s p e c t R a t i 〇 )細間距高密集度之銲接凸塊。接者蒼考弟四D圖所不’以到刀印刷的方式將鲜貧或微小鮮球（Solder Paste/Solder Powder) 410填入暴露出銲接凸塊下金屬層4 0 6的開口内，並將溢出的銲膏或微小銲球移除。銲膏由許多微小鍀球或銲粉（S ο 1 d e r P 〇 w d e r)、溶劑與助銲（熔）劑（F1 ux)構成，而銲球通常為共晶成刀之錫热合金0 清洗須於至最介電為其可使 1可步進裝結，結Page 13 545099 V. Description of the invention (9) The method of laser or Plasma Etching removes the part of the release film located on the metal layer 4 06 under the solder bump to form Opening. Using laser openings or plasma etching can achieve high-resolution precisely aligned openings, so that the solder bumps can be accurately formed on the metal layer under the solder bumps, and at the same time, the pitch of the solder bumps can be further reduced, and successfully Formation of high aspect ratio (H igh A spect R ati) fine-pitch high-density solder bumps. The Cang Kaodi ’s four-D picture does not use the method of knife printing to fill in the poor or tiny fresh balls (Solder Paste / Solder Powder) 410 into the openings that expose the metal layer 4 0 6 under the solder bumps, and Remove spilled solder paste or tiny solder balls. The solder paste is composed of many tiny balls or solder powder (S ο 1 der P 〇wder), solvent and flux (flux) (F1 ux), and the solder ball is usually eutectic into the knife of the tin thermal alloy 0 cleaning must For the most dielectric, it can make 1 stepping knotting, knotting

參考第四E圖所示，第四D圖中所示之銲膏4 1 〇經回銲， ‘私形成圖中的銲接凸塊4 1 2。而當使用微小銲球則印刷後回銲前再加入助銲劑，如此可將銲球氣泡縮減少。於第四F圖中，若介電層4 0 8為一離形膜，則可將層^0 8輕易移除（也可視需要不移除），但若介電層4 〇 8 他介電材料，則以電漿蝕刻移除或以化學液剝除，並用乾式餘刻或電漿清洗表面。然後如第四G圖中所示再進行一次回銲製程以形成圖中所示之型態。在進一行封裝製程時，將第四G圖中所示之晶圓部份元件封構兵第—Η圖或第二Η圖中所示基板部份封裝結構結合合時第四G圖中之銲接凸塊4丨2與第二Η圖或第三Η圖中Referring to FIG. 4E, the solder paste 4 1 0 shown in FIG. 4 D is re-soldered to form a solder bump 4 1 2 in the figure. When using tiny solder balls, add flux before printing and reflow, which can reduce the solder ball bubbles. In the fourth F diagram, if the dielectric layer 408 is a release film, the layer ^ 0 8 can be easily removed (and may not be removed if necessary), but if the dielectric layer 408 is dielectric, The material is removed by plasma etching or stripped by chemical liquid, and the surface is cleaned by dry etching or plasma. Then, as shown in the fourth figure G, a reflow process is performed again to form the pattern shown in the figure. When proceeding with the packaging process, the wafer part components shown in the fourth G diagram are shown in the first G diagram or the second part in the second G diagram. Welding bump 4 丨 2 and the second or third picture

第14頁 545099 五、發明說明（ίο) 之銲接凸塊2 1 0或3 1 0對準銲接（S ο 1 d e r i n g)結合以便進行下一步覆晶封裝的製程。第五A圖至第五F圖顯示本發明較佳實施例中之包含^ 體電路晶片之晶圓部份的製程。參考第五A圖所示，顯示貝本發明於銲接凸塊形成前包含積體電路晶片之晶圓部份*** 件封裝結構，此晶圓部份元件封裝結構包含晶片5 〇 70 墊5 0 2、保護層5 0 4、銲接凸塊下金屬層5〇 6、 '干，介電層⑽5。9用於定義銲接凸塊的形成，Page 14 545099 V. Description of the invention The solder bumps 2 1 0 or 3 1 0 are aligned and soldered (S 1 d e r i n g) for the next process of flip chip packaging. 5A to 5F show the manufacturing process of a wafer portion including a bulk circuit wafer in a preferred embodiment of the present invention. Referring to FIG. 5A, it is shown that the present invention includes a wafer portion and a component packaging structure of an integrated circuit wafer before a solder bump is formed. The wafer portion of the component packaging structure includes a wafer 5 070 pad 5 0 2 Protective layer 5 0 4, Metal layer 5006 under the solder bump, 'Dry, dielectric layer ⑽5.9 is used to define the formation of solder bump,

5 0 8與5 0 9包含非感光性介電[而介電層5〇二 H Ϊ佳。此外，介電層5 0 8與5〇9之間可選擇性地加t 站，，膜。銲墊5 0 2包含鋁鮮塾，作豆 :被銲墊赌以傳統的沈積仁微成。保護層504可由傳統方法形占仅喝c 形微影與蝕^程㈣^彡^成/保^層5 04係被傳統的凸塊下金屬展德把成開亚曝鉻出銲墊5 0 2。銲接5 0 8 and 5 0 9 include non-photosensitive dielectrics [and the dielectric layer 502 H is excellent. In addition, the dielectric layer can be optionally added between the 508 and 509, t film. The pad 502 contains fresh aluminum, which is made of beans: the pad is staked with traditional deposition kernels. The protective layer 504 can be formed by conventional methods, and only consumes c-shaped lithography and etching. 2. welding

s出ί:::第五Γ所示，介電層5 0 8與509被#刻以下金屬層5〇6,餘刻介電層508與5 0 9的方法:人雷；方向開孔加工的方法’例如非等向性蝕安 ur為離形膜，則可以雷射開孔的方式或是屬/二二Γ除介電層5 08與離形膜位於銲接凸塊下屬層06上的部分，以形成開口。利用編刻的製程s 出 ί ::: Fifth, as shown in the fifth Γ, the dielectric layers 508 and 509 are engraved with the following metal layer 506, and the dielectric layers 508 and 509 are etched: human thunder; direction hole processing The method 'for example, anisotropic etching An ur is a release film, you can laser open the hole or the metal / 22 Γ to remove the dielectric layer 5 08 and the release film located on the solder bump lower layer 06 Part to form an opening. Use the process of engraving

第15頁 545099 五、發明說明（11) 形成開口必須於離形膜上應用蝕刻遮罩。利用雷射開孔或是電漿蝕刻可以達成高解析度精確對準的開口，使銲接凸塊能準確形成於凸塊銲墊上，同時可進一步縮小銲接凸塊的間距，並成功地形成高縱橫比細間距高密集度之銲接凸塊。接著參考第五c圖所示，以刮刀印刷的方式將銲膏或微小銲球5 1 0填入暴露出銲接凸塊下金屬層5 0 6的開口内，並將溢出的銲膏或微小銲球移除。銲膏由許多微小銲球或銲粉（So 1 der Powder)、溶劑與助銲（、J：容）劑（F 1 ux)構成5而鲜球通常為共晶成分之錫热合金。 Φ 接著參考第五D圖所示，第五C圖中所示之銲膏5 1 0經回銲、清洗製程形成圖中的銲接凸塊5 1 2。而當使用微小銲球則須於印刷後回銲前再加入助銲劑，如此可將銲球氣泡縮減至最少。然後參考第五E圖所示，將介電層5 0 9移除，並可使用乾式蝕刻或電漿清洗表面。然後如第五F圖中所示，可再進行一次回銲製程以形成圖中所示之型態。在進一步進行封裝製程時，將第五F圖中所示之晶圓部份元件封裝結構與第二Η圖或第三Η圖中所示基板部份封裝結構結合，結合時第五F圖中之銲接凸塊5 1 2與第二Η圖或第三Η圖中之銲接凸塊210或3 10對準銲接（Soldering)結合以便進行下一步覆晶封裝的製程。Page 15 545099 5. Description of the invention (11) An etching mask must be applied to the release film to form the opening. The use of laser drilling or plasma etching can achieve high-resolution and precisely aligned openings, so that solder bumps can be accurately formed on the bump pads, and at the same time, the pitch of the solder bumps can be further reduced, and a high aspect ratio can be successfully formed. Higher density solder bumps than fine pitch. Then, referring to the fifth figure c, fill the solder paste or micro solder balls 5 1 0 into the openings that expose the metal layer 5 06 under the solder bumps by scraper printing, and fill the solder paste or micro solder with overflow. The ball is removed. The solder paste is composed of many tiny solder balls or solder powders (So 1 der Powder), solvent and flux (, J: flux) (F 1 ux), and the fresh balls are usually eutectic tin thermal alloys. Φ Then refer to the fifth D chart, the solder paste 5 1 0 shown in the fifth C chart is re-soldered and cleaned to form the solder bump 5 1 2 in the figure. When using tiny solder balls, flux must be added before reflow after printing, so that the solder ball bubbles can be minimized. Then referring to the fifth figure E, the dielectric layer 509 is removed, and the surface can be cleaned by dry etching or plasma. Then, as shown in Figure 5F, a reflow process can be performed to form the pattern shown in the figure. In the further packaging process, the component packaging structure of the wafer part shown in the fifth figure F is combined with the packaging structure of the substrate part shown in the second figure or the third figure. The solder bumps 5 1 2 and the solder bumps 210 or 3 10 in the second or third drawing are aligned for soldering in order to perform the next flip-chip packaging process.

第16頁 545099 五、發明說明（12) 在本發明的一較佳實施例中利用介電層特別是離以及雷射開孔的方式或是電漿韻刻的製輕來精確定彳立&模上之銲接凸塊與晶圓上之銲接凸塊的形成位置，可以基板電層内形成高解析度精確對準的開口，使銲接凸塊於介形成於基板上之凸塊銲墊與晶圓上之銲接凸塊下金$準確，同時可進一步縮小銲接凸塊的間距，並成功地形成=上橫比（H i g h A s p e c t R a t i 〇 )細間距高密集度之鲜接凸塊$纖同時可克服使用鋼版（Stencil Mask)形成|爭接^&土鬼" 成之對準不易及鋼版（Stencil Mask)高成本的問題戶斤造及解決傳統光阻膜定義的印刷（Photo Fiim Defined M Printing)方式受限於光阻膜（Photo Film)的解析度而難以形成高縱橫比（h i g h A s p e c t R a t i ο )細間距的鮮接凸塊或銲墊的問題。此外’利用銲膏或微小銲球填入高縱橫比（high Aspect Rat io)細間距高密集度以及高解析度精 1對準的開口内以形成銲接凸塊可解決傳統以電鍍法形成辉接凸塊耗時且高成本的問題。上述有關發明的詳細說明僅為範例並非限制。其他不 :f本發明之精神的等效改變或修飾均應的專利範圍之内。Page 16 545099 V. Description of the invention (12) In a preferred embodiment of the present invention, the dielectric layer, especially the way of opening and laser openings, or the lightness of the plasma rhyme is used to precisely determine the standing & The formation position of the solder bumps on the mold and the solder bumps on the wafer can form high-resolution and precisely aligned openings in the electrical layer of the substrate, so that the solder bumps are formed between the bump pads and the pads formed on the substrate. The solder bumps on the wafer are accurately deposited, and at the same time, the pitch of the solder bumps can be further reduced, and successfully formed = high aspect ratio (H igh A spect R ati) fine pitch high density fresh bumps $ Fiber can also overcome the use of steel (Stencil Mask) formation | continued ^ & dirt ghost " success of alignment and high cost of steel (Stencil Mask) problems can be created and solved by traditional photoresist film definition printing The (Photo Fiim Defined M Printing) method is limited by the resolution of the Photo Film and it is difficult to form high-aspect ratio fine-pitch fresh bumps or pads. In addition, 'Using solder paste or tiny solder balls to fill high aspect ratio (high aspect rat io) fine pitch high density and high resolution fine-aligned openings to form solder bumps can solve the traditional formation of glow joints by electroplating The problem of bumps being time consuming and costly. The above detailed description of the invention is merely an example and not a limitation. Other equivalent changes or modifications not falling within the spirit of the present invention are within the scope of the patent.

第17頁 545099 圖式簡單說明為了能讓本發明上述之其他目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：第一 A圖顯示一銲接凸塊形成前的元件封裝結構；第一 B圖顯示形成一光阻層於第一 A圖所示的元件封裝結構上的結果；第一 C圖顯示曝光顯光阻層以暴露出銲接凸塊下金屬層的結果；第一 D圖顯示形成一銲接凸塊於銲接凸塊下金屬層上的結果；第一 E圖顯示移除光阻層的結果；第一 F圖顯示蝕刻銲接凸塊下金屬層以曝露出保護層的結果；第一 G圖顯示銲接凸塊經回銲的結果；第二A圖顯示一基板上具有複數個覆晶接合凸塊銲墊與一防銲膜； 1 第18頁 545099 圖式簡單說明第二B圖顯示在第二A圖所示之結構上覆蓋一介電層的結果；第二C圖顯示介電層被蝕刻以暴露出凸塊銲墊的結果第二D圖顯示將銲膏或微小銲球填入暴露出凸塊鮮墊的開口内，並將溢出的銲膏或微小銲球移除的結果；第二E圖顯示第二D圖中所示之銲膏或微小銲球經回銲製程形成銲接凸塊的結果；第二F圖顯示將介電層移除的結果；第二G圖顯示再進行一次回銲製程的結果；第二Η圖顯示進行一次壓平製程使銲接凸塊頂部平坦化的結果；第三Α圖顯示一基板上具有複數個覆晶接合凸塊銲墊與電路結構；第三B圖顯示在第三A圖所示之結構上覆蓋二非感光性 11 第19頁 545099 圖式簡單說明介電層的結果，第三c圖顯示二非感光性介電層被蝕刻以暴露出凸塊銲墊的結果；第三D圖顯示將銲膏或微小銲球填入暴露出凸塊銲墊的開口内，並將溢出的銲膏或微小銲球移除的結果；第三E圖顯示第三D圖中所示之銲膏或微小銲球經回銲製程形成銲接凸塊的結果；第三F圖顯示將離形膜介電層移除的結果；第三G圖顯示再進行一次回銲製程的結果；第三Η圖顯示進行一次壓平製程使銲接凸塊頂部平坦化的結果；第四Α圖顯示包含積體電路晶片之晶圓部份元件封裝結構；第四B圖顯示在第四A圖所示之結構上覆蓋一介電層的結果；第20頁 545099 圖式簡單說明第四c圖顯示介電層被蝕刻以暴露出銲接凸塊下金屬層的結果；第四D圖顯示將銲膏或微小銲球填入暴露出銲接凸塊下金屬層的開口内並將溢出的銲膏或微小銲球移除的結果第四E圖顯示第四D圖中所示之銲膏或微小銲球經回銲製程形成銲接凸塊的結果；Page 545099 Brief description of the drawings In order to make the other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Figure A shows the device package structure before a solder bump is formed; Figure B shows the result of forming a photoresist layer on the device package structure shown in Figure A; Figure C shows the exposed photoresist layer The result of exposing the metal layer under the solder bump is shown in FIG. 1. The first D image shows the result of forming a solder bump on the metal layer under the solder bump. The first E image shows the result of removing the photoresist layer. The first F image The result of etching the metal layer under the solder bump to expose the protective layer is shown. The first graph G shows the result of reflow soldering of the solder bump. The second graph A shows a substrate with a plurality of flip-chip bonding bump pads and one Solder mask; 1 Page 18 545099 Brief description of the diagram Second diagram B shows the result of covering a dielectric layer on the structure shown in second A; second diagram C shows the dielectric layer is etched to expose the protrusions The result of the block pad is shown in the second D graph. The result of filling the paste or micro solder balls into the openings that expose the bump pads and removing the overflowing solder paste or micro solder balls; Figure 2E shows the solder paste or tiny solder shown in Figure 2D The result of the ball forming a solder bump after the reflow process; the second graph F shows the result of removing the dielectric layer; the second graph G shows the result of another reflow process; the second graph shows a flattening process The result of flattening the top of the solder bump; the third diagram A shows a substrate with a plurality of flip-chip bonding bump pads and a circuit structure; the third diagram B shows the structure shown in FIG. Photosensitive 11 Page 19 545099 The diagram briefly illustrates the results of the dielectric layer. Figure 3c shows the results of the two non-photosensitive dielectric layers being etched to expose the bump pads. Figure 3D shows the solder paste or The result of filling the solder balls into the openings that expose the bump pads and removing the overflowing solder paste or solder balls; Figure 3E shows the solder paste or solder balls shown in Figure 3D. Results of solder bump formation during reflow process; Figure 3 F shows shift of the release film dielectric layer The third graph G shows the results of another reflow process; the third graph shows the results of a flattening process to flatten the top of the solder bumps; the fourth graph A shows a wafer containing integrated circuit wafers Partial component package structure; Figure 4B shows the result of covering a dielectric layer on the structure shown in Figure 4A; page 545099 diagrams briefly explain Figure 4c shows the dielectric layer is etched to expose The result of soldering the metal layer under the bump; the fourth D image shows the result of filling the solder paste or micro solder ball into the opening exposing the metal layer under the solder bump and removing the overflowing solder paste or micro solder ball. Figure E shows the results of solder bumps or tiny solder balls shown in Figure 4D forming solder bumps after the reflow process;

第四F圖顯示移除介電層的結果；第四G圖再進行一次回銲製程以形成圖中所示之型態的結果；第五A圖顯示包含積體電路晶片之晶圓部份元件封裝結構；第五B圖顯示在第五A圖所示之二非感光性介電層被蝕刻以暴露出銲接凸塊下金屬層的結果；第五C圖顯示將銲膏或微小銲球填入暴露出銲接凸塊下金屬層的開口内，並將溢出的銲膏或微小銲球移除的結果；Figure 4F shows the results of removing the dielectric layer. Figure 4G shows the results of another reflow process to form the type shown in the figure. Figure 5A shows the part of the wafer containing the integrated circuit wafer Device package structure; Figure 5B shows the result of etching the non-photosensitive dielectric layer shown in Figure 5A to expose the metal layer under the solder bump; Figure 5C shows the solder paste or micro solder balls The result of filling into the opening that exposes the metal layer under the solder bump and removing the overflowing solder paste or tiny solder balls;

第21頁 545099 圖式簡單說明第五D圖顯示第五C圖中所示之銲膏或微小銲球經回銲製程形成銲接凸塊的結果；第五E圖顯示將離形膜介電層移除的結果；及第五F圖顯示再進行一次回銲製程的結果。主要部分之代表符號： 1 0 0元件 1 0 2銲墊 1 0 4保護層 1 0 6銲接凸塊下金屬層 1 0 8光阻層銲接 1 1 0凸塊 2 0 0基板 2 0 2覆晶接合凸塊銲墊 2 0 4防銲膜 2 0 6介電層 _ 2 0 8銲膏或微小銲球 2 1 0銲接凸塊 3 0 0基板 3 0 2覆晶接合凸塊銲墊 3 0 4電路結構Page 545099 Brief description of the diagram The fifth diagram D shows the results of solder bumps formed by the re-soldering process of the solder paste or micro solder balls shown in the fifth diagram C; the fifth E diagram shows the release film dielectric layer The results of the removal; and the fifth F chart shows the results of another reflow process. Representative symbols of the main parts: 1 0 0 component 1 0 2 solder pad 1 0 4 protective layer 1 0 6 solder metal layer under the bump 1 0 8 photoresist layer welding 1 1 0 bump 2 0 0 substrate 2 0 2 flip chip Bonding pads 2 0 4 Solder mask 2 0 6 Dielectric layer _ 2 0 8 Solder paste or micro solder balls 2 1 0 Soldering bumps 3 0 0 Substrate 3 0 2 Chip bonding pads 3 0 4 Circuit configuration

第22頁 545099 圖式簡單說明 3 0 6介電層 3 0 7介電層 3 0 8銲膏或微小銲球 3 1 0銲接凸塊 4 0 0晶片 4 0 2銲墊 4 0 4保護層 4 0 6銲接凸塊下金屬層 4 0 8介電層 4 1 0銲膏或微小銲球 4 1 2銲接凸塊 5 0 0晶片 5 0 2銲墊 5 0 4保護層 5 0 6銲接凸塊下金屬層 5 0 8介電層 5 0 9介電層 5 1 0銲膏或微小銲球 5 1 2銲接凸塊Page 22 545099 Brief description of the drawing 3 0 6 Dielectric layer 3 0 7 Dielectric layer 3 0 8 Solder paste or micro solder ball 3 1 0 Solder bump 4 0 0 Wafer 4 0 2 Pad 4 4 Protective layer 4 0 6 Solder bump metal layer 4 0 8 Dielectric layer 4 1 0 Solder paste or micro solder ball 4 1 2 Solder bump 5 0 0 Wafer 5 0 2 Solder pad 5 0 4 Protective layer 5 0 6 Solder bump Metal layer 5 0 8 Dielectric layer 5 0 9 Dielectric layer 5 1 0 Solder paste or micro solder ball 5 1 2 Solder bump

第23頁Page 23

Claims

545099 六、申請專利範圍 1. 一種高解析度銲接凸塊形成方法，該高解析度銲接凸塊形成方法包含：提供一基板，其中該基板上具有複數個銲墊與一防銲膜；形成一離形膜覆蓋該基板；以一垂直方向開孔加工的方法轉移複數個銲接凸塊的圖案進入該離形膜以形成複數個開口並暴露出該銲墊；將銲料填入該開口；對該基板執行回銲製程以形成複數個銲接凸塊；移除該離形膜；及對該銲接凸塊執行一壓平製程。 2. 如申請專利範圍第1項所述之高解析度銲接凸塊形成方法，其中上述之該基板包含一防銲膜定義基板。 3. 如申請專利範圍第1項所述之高解析度銲接凸塊形成方法，其中上述之該基板包含一非防銲膜定義基板。 4. 如申請專利範圍第1項所述之高解析度銲接凸塊形成方法，其中上述之該垂直方向開孔加工的方法包含雷射開孔法。 5. 如申請專利範圍第1項所述之高解析度銲接凸塊形成方法，其中上述之該垂直方向開孔加工的方法包含電漿蝕刻545099 6. Application Patent Scope 1. A method for forming a high-resolution solder bump, the method for forming a high-resolution solder bump includes: providing a substrate, wherein the substrate has a plurality of solder pads and a solder mask; forming a A release film covers the substrate; a pattern of a plurality of solder bumps is transferred into the release film to form a plurality of openings and expose the solder pads by a vertical hole-opening method; solder is filled into the openings; A reflow process is performed on the substrate to form a plurality of solder bumps; the release film is removed; and a flattening process is performed on the solder bumps. 2. The method for forming a high-resolution solder bump as described in item 1 of the scope of the patent application, wherein the substrate includes a solder mask to define the substrate. 3. The method for forming a high-resolution solder bump as described in item 1 of the scope of the patent application, wherein the substrate includes a non-solder mask-defined substrate. 4. The method for forming a high-resolution solder bump as described in item 1 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a laser hole method. 5. The method for forming a high-resolution solder bump as described in item 1 of the scope of the patent application, wherein the above-mentioned method for processing the vertical hole includes plasma etching

第24頁 545099 六、申請專利範圍法0 方填成式形方塊的凸刷接印銲刀度刮析以解係高球之銲匕、 iid 所微項或 1—I 古T 第銲圍該範之利述專上請中申其如，。 6法入方式成乾形一塊行凸執接板銲基度該析對解，高後之除述移所膜。項形面 1離表第該板圍之基範述該利上洗專 <口田立硐請中程申其製 D rnuj.士，亥 7法蝕 8 方回成次形一塊行凸執接板銲基度該析對解，高後之除述移所膜項形 ^•離第該圍之範述利上專當請中。申其程如，製，法銲方成形塊凸接銲度析。解球高銲之小述微所或項膏 1 鲜第為圍可範料利銲專該請中申其如， 9法凸接銲度析解高該法方成形塊凸接銲度：析含解包高法種方一成 •形 ο 1塊 Φ ^___I 覆膜形 ;0 塾一銲與個板數基複該有蓋具覆上層板電基介該性中光；其感層，非電板一介基成性一形光供序感提依非該蓋的並塊口凸開接個銲數個複數成複形移以轉層法電方介的性工光加感」 br孑与開與向膜方形直離垂該一入以進案圖Page 24 545099 VI. Method of Patent Application Scope 0 The convex-blade welded welding knife of a square-shaped block is scraped to analyze the high-blade welding dagger, the iid derivative, or the 1-I ancient Tth welding enclosure. For the post-secondary, please ask Zhongshen Qiru. The 6 way method is a dry-shaped one-row convex splice plate. The welding base should be analyzed and resolved, and the higher one should be removed. Item form 1 off the table of the base of the board around the general description of the washing up school <Kuta Tachibana asks Cheng Chengshen to make D rnuj. Shi, Hai 7 method etch 8 square back to form a row of convex welding plate welding Fundamentals should be resolved, and the high-level descriptive shifts the membrane form ^ • Fan Shuli from Di Gaowei should be invited. Analysis of the welding degree of Shen Qicheng's convex welded joints. The solution to the problem of high welding is to explain the details or items of the paste. 1 Fresh is the range of materials that can be used for welding. Please apply for it. The 9 method of convex welding analysis analyzes the high degree of convex welding of this method. With unpacked high-precision method Fang Yicheng • Shape ο 1 piece Φ ^ ___ I film shape; 0 塾 a welding and number of plates based on the cover with the upper layer of the dielectric base of the medium light; its sense layer, non The electric plate, a substrate, a form of light, and a sense of sequential light are lifted. The joint opening of the cover is not convex, and a plurality of plural pieces are welded to form a complex shape. Enter the case directly from the square of the membrane

第25頁 545099 六、申請專利範圍暴露出該銲墊；將銲料填入該開口；對該基板執行回銲製程以形成複數個銲接凸塊；移除該離形膜；及對該銲接凸塊執行一壓平製程。 1 1 .如申請專利範圍第1 0項所述之高解析度銲接凸塊形成方法，其中上述之該垂直方向開孔加工的方法包含雷射開孔法。 1 2.如申請專利範圍第1 0項所述之高解析度銲接凸塊形成方法，其中上述之該垂直方向開孔加工的方法包含電漿蝕刻法。 1 3.如申請專利範圍第1 0項所述之高解析度銲接凸塊形成方法，其中上述之該銲膏或微小銲球係以刮刀印刷的方式填入。 1 4.如申請專利範圍第1 0項所述之高解析度銲接凸塊形成方法，其中當上述之該離形膜移除後，對該基板執行一乾式#刻製程清洗該基板表面。 1 5.如申請專利範圍第1 0項所述之高解析度銲接凸塊形成方法，其中當上述之該離形膜移除後，對該基板執行一次Page 25 545099 6. The scope of the patent application exposes the solder pad; fills the solder into the opening; performs a re-soldering process on the substrate to form a plurality of solder bumps; removes the release film; and the solder bumps Perform a flattening process. 11. The method for forming a high-resolution solder bump as described in item 10 of the scope of the patent application, wherein the above-mentioned method for processing the vertical hole includes a laser hole method. 1 2. The method for forming a high-resolution solder bump as described in item 10 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a plasma etching method. 1 3. The method for forming a high-resolution solder bump as described in item 10 of the scope of the patent application, wherein the solder paste or micro solder balls mentioned above are filled by doctor blade printing. 1 4. The method for forming a high-resolution solder bump as described in item 10 of the scope of patent application, wherein after the release film is removed, a dry # etch process is performed on the substrate to clean the surface of the substrate. 1 5. The method for forming a high-resolution solder bump as described in item 10 of the scope of patent application, wherein when the release film is removed, the substrate is performed once.

第26頁 545099 六、申請專利範圍回銲製程。 1 6.如申請專利範圍第1 0項所述之高解析度銲接凸塊形成方法，其中該銲料可為銲膏或微小銲球。 1 7. —種高解析度銲接凸塊形成方法，該高解析度銲接凸塊形成方法包含：Page 26 545099 6. Scope of patent application Reflow soldering process. 16. The method for forming a high-resolution solder bump according to item 10 of the scope of the patent application, wherein the solder may be a solder paste or a micro solder ball. 1 7. —A method for forming a high-resolution welding bump, the method for forming a high-resolution welding bump includes:

提供一晶圓，其中該晶圓上具有複數個銲墊、一具有複數個開口以暴露出該銲墊之保護層及複數個位於該銲墊上之銲接凸塊下導體層（UBM); 形成一非感光性介電層覆蓋該晶圓；藉由一垂直方向開孔加工的方法轉移複數個銲接凸塊的圖案進入該介電層以形成複數個開口並暴露出該銲接凸塊下導體層；將銲料填入該開口；對該晶圓執行一次回銲製程以形成複數個銲接凸塊；及移除該介電層。Provide a wafer, wherein the wafer has a plurality of bonding pads, a protective layer having a plurality of openings to expose the bonding pads, and a plurality of solder bump under conductor layers (UBM) on the bonding pads; forming a A non-photosensitive dielectric layer covers the wafer; a pattern of a plurality of solder bumps is transferred into the dielectric layer by a method of vertical opening processing to form a plurality of openings and expose the conductor layer under the solder bumps; Filling the opening with solder; performing a reflow process on the wafer to form a plurality of solder bumps; and removing the dielectric layer.

1 8.如申請專利範圍第1 7項所述之高解析度銲接凸塊形成方法，其中上述之該非感光性介電層包含一離形膜。 1 9.如申請專利範圍第1 7項所述之高解析度銲接凸塊形成方法，其中上述之該垂直方向開孔加工的方法包含雷射開18. The method for forming a high-resolution solder bump according to item 17 in the scope of the patent application, wherein the non-photosensitive dielectric layer described above includes a release film. 19. The method for forming a high-resolution solder bump according to item 17 in the scope of the patent application, wherein the above-mentioned method for processing the hole in the vertical direction includes laser opening.

第27頁 545099 六、申請專利範圍孔法。 2 0 .如申請專利範圍第1 7項所述之高解析度銲接凸塊形成方法，其中上述之該垂直方向開孔加工的方法包含電漿蝕刻法。 2 1.如申請專利範圍第1 7項所述之高解析度銲接凸塊形成方法，其中上述之該銲膏或微小銲球係以刮刀印刷的方式填入。Page 27 545099 6. Scope of patent application Hole method. 20. The method for forming a high-resolution solder bump as described in item 17 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a plasma etching method. 2 1. The method for forming a high-resolution solder bump as described in item 17 of the scope of the patent application, wherein the solder paste or micro solder balls mentioned above are filled by doctor blade printing.

2 2.如申請專利範圍第1 7項所述之高解析度銲接凸塊形成方法，其中當上述之該介電層移除後，對該晶圓執行一乾式#刻製程清洗該晶圓表面。 2 3 .如申請專利範圍第1 7項所述之高解析度銲接凸塊形成方法，其中當上述之該介電層移除後，對該晶圓執行一次回銲製程。2 2. The method for forming a high-resolution solder bump as described in item 17 of the scope of the patent application, wherein after the dielectric layer is removed, a dry #etch process is performed on the wafer to clean the surface of the wafer . 2 3. The method for forming a high-resolution solder bump as described in item 17 of the scope of patent application, wherein after the dielectric layer is removed, a reflow process is performed on the wafer.

2 4 .如申請專利範圍第1 7項所述之高解析度銲接凸塊形成方法，其中該銲料可為銲膏或微小銲球。 2 5. —種高解析度銲接凸塊形成方法，該高解析度銲接凸塊形成方法包含：提供一晶圓，其中該晶圓上具有複數個銲墊、一具有24. The method for forming a high-resolution solder bump according to item 17 in the scope of the patent application, wherein the solder may be a solder paste or a micro solder ball. 2 5. —A method for forming a high-resolution solder bump, the method for forming a high-resolution solder bump includes: providing a wafer, wherein the wafer has a plurality of solder pads,

第28頁 545099 六、申請專利範圍複數個開口以暴露出該銲墊之保護層及複數個位於該銲墊上之銲接凸塊下導體層；依序形成一非感光性介電層覆蓋該晶圓與一離形膜覆蓋該非感光性介電層；以一垂直方向開孔加工的方法轉移複數個銲接凸塊的圖案進入該離形膜與非感光性介電層以形成複數個開口並暴露出該銲接凸塊下導體層；將銲料填入該開口；對該晶圓執行回銲製程以形成複數個銲接凸塊；及移除該離形膜。 2 6 .如申請專利範圍第2 5項所述之高解析度銲接凸塊形成方法，其中上述之該垂直方向開孔加工的方法包含雷射開孔法。 2 7 .如申請專利範圍第2 5項所述之高解析度銲接凸塊形成方法，其中上述之該垂直方向開孔加工的方法包含電漿蝕刻法。 2 8 .如申請專利範圍第2 5項所述之高解析度銲接凸塊形成方法，其中上述之該銲膏或微小銲球係以刮刀印刷的方式填入。 2 9 .如申請專利範圍第2 5項所述之高解析度銲接凸塊形成Page 28 545099 VI. Patent application: Multiple openings to expose the protective layer of the pad and the conductor layer under the solder bump on the pad; sequentially forming a non-photosensitive dielectric layer to cover the wafer And a release film covering the non-photosensitive dielectric layer; transferring a pattern of a plurality of solder bumps into the release film and the non-photosensitive dielectric layer to form a plurality of openings by exposing a vertical hole; A conductor layer under the solder bump; filling solder into the opening; performing a reflow process on the wafer to form a plurality of solder bumps; and removing the release film. 26. The method for forming a high-resolution solder bump according to item 25 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a laser hole method. 27. The method for forming a high-resolution solder bump as described in item 25 of the scope of the patent application, wherein the above-mentioned vertical hole processing method includes a plasma etching method. 2 8. The method for forming a high-resolution solder bump as described in item 25 of the scope of the patent application, wherein the solder paste or micro solder balls mentioned above are filled by doctor blade printing. 2 9 .High-resolution solder bump formation as described in item 25 of the scope of patent application

545099 六、申請專利範圍方法，其中當上述之該離形膜移除後，對該晶圓執行一乾式I虫刻製程清洗該晶圓表面。 3 0 .如申請專利範圍第2 5項所述之高解析度銲接凸塊形成方法，其中當上述之該離形膜移除後，對該晶圓執行一次回銲製程。 3 1 .如申請專利範圍第2 5項所述之高解析度銲接凸塊形成方法，其中該銲料可為銲膏或微小銲球。545099 6. Method for applying for a patent, wherein after the release film is removed, a dry I-worm process is performed on the wafer to clean the surface of the wafer. 30. The method for forming a high-resolution solder bump as described in item 25 of the scope of the patent application, wherein after the release film is removed, a reflow process is performed on the wafer. 31. The method for forming a high-resolution solder bump according to item 25 of the patent application scope, wherein the solder may be a solder paste or a micro solder ball.

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