JP2000040713A - Manufacture of semiconductor package - Google Patents
Manufacture of semiconductor packageInfo
- Publication number
- JP2000040713A JP2000040713A JP20767798A JP20767798A JP2000040713A JP 2000040713 A JP2000040713 A JP 2000040713A JP 20767798 A JP20767798 A JP 20767798A JP 20767798 A JP20767798 A JP 20767798A JP 2000040713 A JP2000040713 A JP 2000040713A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor package
- chip
- manufacturing
- same
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体パッケージの
製造方法に係わり、更に詳しくは、基板両面に同じバン
プを形成した後、フリップチップボンディングした半導
体パッケージの製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a semiconductor package in which the same bumps are formed on both surfaces of a substrate and then flip-chip bonded.
【０００２】[0002]
【従来の技術】近年、半導体パッケージの小型化、高密
度化に伴いベア・チップを直接フェイスダウンで、基板
上に実装するフリップチップボンディングが開発されて
いる。カメラ一体型ＶＴＲや携帯電話機等の登場によ
り、ベア・チップと略同じ寸法の小型パッケージ、所謂
ＣＳＰ（チップサイズ／スケール・パッケージ）を載せ
た携帯機器が相次いで登場してきている。最近ＣＳＰの
開発は急速に進み、その市場要求が本格化している。2. Description of the Related Art In recent years, with the miniaturization and high density of semiconductor packages, flip chip bonding has been developed in which bare chips are directly mounted face down on a substrate. With the advent of camera-integrated VTRs and mobile phones, portable devices equipped with a small package having substantially the same dimensions as a bare chip, that is, a so-called CSP (chip size / scale package) are appearing one after another. Recently, CSP development has progressed rapidly, and the market demand has been in full swing.
【０００３】図４は、従来の半導体パッケージの製造方
法を説明する工程図である。先ず、図４（ａ）におい
て、両面銅張りされた印刷配線板である回路基板１にＮ
Ｃ穴明け加工によりスルーホール２を形成した後、無電
解銅メッキ及び電解銅メッキにより銅メッキ層を形成
し、更にメッキレジストをラミネートし、露光現像して
パターンマスクを形成した後、エッチング液を用いてパ
ターンエッチングを行うことにより、前記回路基板１の
上面側にＩＣ接続用のボンディングパッド３、下面側に
パッド電極である外部端子４を形成する。次にソルダー
レジスト処理を行い、所定の部分にレジスト膜５を形成
することにより、前記回路基板１の下面側には外部端子
４を露呈するように、マトリックス状に多数の同一形状
の半田付け可能な表面であるレジスト膜５の開口部が形
成される。FIG. 4 is a process chart for explaining a conventional method of manufacturing a semiconductor package. First, in FIG. 4A, a circuit board 1 which is a printed wiring board copper-clad on both sides is provided with N
After forming a through hole 2 by C drilling, a copper plating layer is formed by electroless copper plating and electrolytic copper plating, a plating resist is laminated, and a pattern mask is formed by exposure and development. By performing pattern etching using the same, bonding pads 3 for IC connection are formed on the upper surface side of the circuit board 1, and external terminals 4 as pad electrodes are formed on the lower surface side. Next, by performing a solder resist process and forming a resist film 5 on a predetermined portion, a large number of solders having the same shape can be soldered in a matrix so that the external terminals 4 are exposed on the lower surface side of the circuit board 1. The opening of the resist film 5, which is a proper surface, is formed.
【０００４】図４（ｂ）に示すＩＣチップ実装は、先
ず、ＩＣチップ６をバンプ工程に流して前記ＩＣチップ
６のパッド電極面に半田バンプ７を形成する。前記半田
バンプ７の形成方法には、一般に、スタッドバンプ方
式、ボールバンプ方式、及びメッキバンプ方式等がある
が、その中で、パッド電極位置にレジストにて窓を形成
し半田浴槽中に浸漬してメッキにて半田バンプを形成す
るメッキバンプ方式は、パッド電極間の狭い配列でバン
プを形成することが可能で、ＩＣチップの小型化には有
効な半田バンプの形成手段である。In the IC chip mounting shown in FIG. 4B, first, the solder bump 7 is formed on the pad electrode surface of the IC chip 6 by flowing the IC chip 6 to a bump process. The method of forming the solder bump 7 generally includes a stud bump method, a ball bump method, a plating bump method and the like. Among them, a window is formed with a resist at a pad electrode position, and immersed in a solder bath. The plating bump method of forming solder bumps by plating can form bumps in a narrow arrangement between pad electrodes, and is an effective means for forming solder bumps for miniaturizing IC chips.
【０００５】図４（ｃ）において、前記半田バンプ付き
ＩＣチップ６、又は前述した回路基板１のボンディング
パッド３にフラックスを塗布して、ＩＣチップ６を回路
基板１上の所定位置に搭載した後、半田リフロー工程を
経て、フリップチップ実装を行う。In FIG. 4C, a flux is applied to the IC chip 6 with solder bumps or the bonding pad 3 of the circuit board 1 described above, and the IC chip 6 is mounted at a predetermined position on the circuit board 1. After the solder reflow process, flip-chip mounting is performed.
【０００６】図４（ｄ）に示す封止工程は、熱硬化性の
封止樹脂８でサイドポッティングにより一体的に樹脂封
止することにより、ＩＣチップ６はフェイスダウンで回
路基板１上に固定される。In the sealing step shown in FIG. 4D, the IC chip 6 is fixed face down on the circuit board 1 by integrally sealing the resin with a thermosetting sealing resin 8 by side potting. Is done.
【０００７】図４（ｅ）は、前記回路基板１の下面側に
形成された外部端子４の位置に、半田ボール９を配置し
てリフローすることによりボール電極が形成される。In FIG. 4E, a ball electrode is formed by disposing a solder ball 9 at the position of the external terminal 4 formed on the lower surface side of the circuit board 1 and performing reflow.
【０００８】前記半田ボール９の半田組成は、フリップ
チップの半田より融点の低い半田ボールが使用される。
例えば、フリップチップの半田バンプ７の組成は、Ｐ
ｂ：９０％、Ｓｎ１０％、融点２５０°Ｃで、半田ボー
ル９の組成は、Ｐｂ：４０％、Ｓｎ６０％、融点１８０
°Ｃで、それぞれ半田の融点が異なる。以上により半導
体パッケージ１０が完成される。As the solder composition of the solder ball 9, a solder ball having a lower melting point than the flip chip solder is used.
For example, the composition of the solder bump 7 of the flip chip is P
b: 90%, Sn 10%, melting point 250 ° C. The composition of the solder ball 9 is Pb: 40%, Sn 60%, melting point 180.
At ° C, the melting points of the solders are different. Thus, the semiconductor package 10 is completed.
【０００９】図５は、従来の他の半導体パッケージの製
造方法を説明する工程図である。図５（ａ）は上述した
図４（ａ）と同様である。図５（ｂ）、（ｃ）におい
て、回路基板１の下面側の外部端子４に、例えば、６／
４半田の半田ボール９をフラックスを塗布して仮固定す
る。FIG. 5 is a process chart for explaining another conventional method for manufacturing a semiconductor package. FIG. 5A is the same as FIG. 4A described above. In FIGS. 5B and 5C, for example, 6 /
A solder ball 9 made of 4 solder is temporarily fixed by applying a flux.
【００１０】図５（ｄ）において、ＩＣチップ６側に予
め、前記半田ボール９と半田の組成が同質の６／４半田
の半田バンプ７を形成する。半田バンプ７にフラックス
を塗布した後、図５（ｅ）で回路基板１の上面側に形成
したＩＣ接続用のボンディングパッド３に仮固定する。In FIG. 5D, solder bumps 7 of 6/4 solder having the same solder composition as the solder balls 9 are formed in advance on the IC chip 6 side. After the flux is applied to the solder bumps 7, the solder bumps 7 are temporarily fixed to the bonding pads 3 for IC connection formed on the upper surface side of the circuit board 1 in FIG.
【００１１】図５（ｆ）において、上記した半田バンプ
７と半田ボール９の半田組成が同質の６／４半田のた
め、加熱炉中で２１０〜２３０°Ｃ程度で加熱すること
により、フラックスが半田と溶融して、一回のリフロー
工程で、回路基板１のボンディングパッド３にＩＣチッ
プ６を接続すると同時に、外部端子４にマザーボード基
板接続用の半田ボール電極を形成する。In FIG. 5 (f), since the solder composition of the solder bumps 7 and the solder balls 9 is 6/4 solder having the same quality, the flux is heated at about 210 to 230 ° C. in a heating furnace. After melting with the solder, the IC chip 6 is connected to the bonding pads 3 of the circuit board 1 in one reflow step, and at the same time, the solder ball electrodes for connecting the mother board to the external terminals 4 are formed.
【００１２】図５（ｆ）において、ＩＣチップ６の側面
を覆うように、熱硬化性の封止樹脂８でサイドポッティ
ングすることにより半導体パッケージ１０が完成する。In FIG. 5F, the semiconductor package 10 is completed by side potting with a thermosetting sealing resin 8 so as to cover the side surface of the IC chip 6.
【００１３】[0013]
【発明が解決しようとする課題】しかしながら、前述し
た２つの半導体パッケージの製造方法には次のような問
題点がある。即ち、いずれの方法においても、回路基板
の下面側の半田ボールとは別に、ＩＣチップ側に半田バ
ンプをバンピングし回路基板上面側にフリップチップボ
ンディング接続する。そのため、生産性が低く、コスト
アップ等の問題があった。However, the above-described two semiconductor package manufacturing methods have the following problems. That is, in each of the methods, a solder bump is bumped on the IC chip side and flip-chip bonded to the upper side of the circuit board, separately from the solder balls on the lower side of the circuit board. Therefore, there are problems such as low productivity and increased cost.
【００１４】本発明は、上記従来の課題に鑑みなされた
ものであり、その目的は、小型携帯機器等に搭載する生
産性に優れた、安価な半導体パッケージの製造方法を提
供するものである。The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a method of manufacturing an inexpensive semiconductor package excellent in productivity and mounted on a small portable device or the like.
【００１５】[0015]
【課題を解決するための手段】上記目的を達成するため
に、本発明における半導体パッケージの製造方法は、一
方の面にボンディングパッド、他方の面に外部端子を有
する印刷配線板に半導体チップをボンディングし、ボー
ルグリッドアレイ（ＢＧＡ）を製造する半導体パッケー
ジの製造方法において、予め印刷配線板の両面に突起電
極を形成した後、半導体チップをボンディングパッド側
の突起電極にフリップチップ接続し、半導体パッケージ
を形成したことを特徴とするものである。In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention comprises bonding a semiconductor chip to a printed wiring board having bonding pads on one surface and external terminals on the other surface. Then, in a method of manufacturing a semiconductor package for manufacturing a ball grid array (BGA), after projecting electrodes are formed on both sides of the printed wiring board in advance, the semiconductor chip is flip-chip connected to the projecting electrodes on the bonding pad side, and the semiconductor package is connected. It is characterized by having been formed.
【００１６】また、前記印刷配線板の両面に形成された
ボンディングパッドと外部端子の突起電極位置が、平面
的に略同一の位置に有ることを特徴とするものである。Further, the present invention is characterized in that the bonding pads formed on both sides of the printed wiring board and the protruding electrode positions of the external terminals are substantially at the same position in plan view.
【００１７】また、前記印刷配線板の両面に形成された
２つの突起電極の大きさが略同一であることを特徴とす
るものである。Further, the present invention is characterized in that two projecting electrodes formed on both sides of the printed wiring board have substantially the same size.
【００１８】また、前記印刷配線板の両面に形成された
２つの突起電極の材質が同一であることを特徴とするも
のである。The material of the two projecting electrodes formed on both sides of the printed wiring board is the same.
【００１９】また、前記突起電極の材質は、半田である
ことを特徴とするものである。The material of the protruding electrode is solder.
【００２０】[0020]
【発明の実施の形態】以下図面に基づいて本発明におけ
る半導体パッケージの製造方法について説明する。図１
は、本発明の実施の形態に係わり、図１（ａ）は、半導
体パッケージの上面側の平面図、図１（ｂ）は、下面側
の平面図、図２は、図１（ａ）の部分断面図。図３
（ａ）は、図１のＡ−Ａ線断面図、図３（ｂ）〜（ｅ）
は、本発明の半導体パッケージの製造方法を説明する工
程図である。図において、従来技術と同一部材は同一符
号で示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor package according to the present invention will be described below with reference to the drawings. FIG.
1A is a plan view of an upper surface side of a semiconductor package, FIG. 1B is a plan view of a lower surface side, and FIG. 2 is a plan view of FIG. Partial sectional view. FIG.
FIG. 3A is a cross-sectional view taken along the line AA in FIG. 1, and FIGS.
FIG. 4 is a process diagram illustrating a method for manufacturing a semiconductor package according to the present invention. In the drawings, the same members as those of the prior art are denoted by the same reference numerals.
【００２１】先ず、図１、図２及び図３（ａ）におい
て、両面銅張りされた回路基板１に、ＮＣ穴明け加工に
より複数個のスルーホール２をマトリックス状に形成し
た後、無電解銅メッキ及び電解銅メッキによりスルーホ
ール２の内壁に銅メッキ層２ａを形成することは、従来
技術と同様である。半導体パッケージの小型化により、
狭い回路基板１の表面に配線パターン形成に有効な面積
を確保するため、及びスルーホール２内に半田の流れを
防ぎ、半田パンプの高さ精度を維持するために、樹脂２
ｂでスルーホール２を穴埋めする。First, referring to FIGS. 1, 2 and 3A, a plurality of through holes 2 are formed in a matrix by NC drilling on a circuit board 1 having copper clad on both sides. Forming the copper plating layer 2a on the inner wall of the through hole 2 by plating and electrolytic copper plating is the same as in the related art. With the miniaturization of semiconductor packages,
In order to secure an effective area for forming a wiring pattern on the surface of the narrow circuit board 1 and to prevent the flow of solder in the through hole 2 and maintain the height accuracy of the solder pump, the resin 2
Fill the through hole 2 with b.
【００２２】前記穴埋めした樹脂２ｂの上下端部を無電
解銅メッキ及び電解銅メッキによりＣｕメッキ層２ｃを
形成する。The Cu plating layer 2c is formed on the upper and lower ends of the filled resin 2b by electroless copper plating and electrolytic copper plating.
【００２３】更に、従来と同様に、ＤＦレジストをラミ
ネートし、露光現像してパターンマスクを形成した後、
エッチング液を用いてパターンエッチングを行うことに
より、回路基板１の上面側にボンディングパッド３、下
面側にパット電極である外部端子４をパターニングす
る。次に、ソルダーレジスト処理を行い、所定の部分に
レジスト膜５を形成することにより、マトリックス状に
複数の同一形状の半田付け可能な表面であるレジスト膜
５の開口部が形成される。Further, as in the prior art, after laminating a DF resist, exposing and developing to form a pattern mask,
By performing pattern etching using an etchant, the bonding pads 3 are patterned on the upper surface side of the circuit board 1, and the external terminals 4 as pad electrodes are patterned on the lower surface side. Next, a solder resist process is performed to form a resist film 5 on a predetermined portion, thereby forming a plurality of openings of the resist film 5 that are solderable surfaces of the same shape in a matrix.
【００２４】更に、前記レジスト膜５の開口部に無電解
ニッケル及び金メッキにより、Ｎｉ＋Ａｕメッキ層２ｄ
が形成される。Further, an Ni + Au plating layer 2d is formed in the opening of the resist film 5 by electroless nickel and gold plating.
Is formed.
【００２５】半田コートすべき物品を半田コート形成液
で処理することにより、金属の露出部のみに粘着性を付
与し、これに半田粉末をその部分に選択的に付着させ、
加熱溶融することによって半田コートする技術が、特開
平７−７４４５９号公報に開示されている。An article to be solder-coated is treated with a solder-coating liquid so as to impart tackiness only to the exposed portion of the metal, to which a solder powder is selectively adhered.
A technique of performing solder coating by heating and melting is disclosed in Japanese Patent Application Laid-Open No. 7-74459.
【００２６】図３（ｂ）において、前記マトリックス状
に複数の同一形状の半田付け可能な表面であるレジスト
膜５の開口部が形成された回路基板１を、半田コート形
成液に数分間出浸漬することにより、ボンディングパッ
ド３及び外部端子４の表面に粘着性物質が生成される。
これに半田粉末をふりかけ、軽くブラッシングして粘着
性物質部分に選択的に付与させた後、所定の温度で半田
粉末を溶融し、回路基板１の上面に半田バンプ７と、下
面に半田ボール９が同時に、精度良く形成される。In FIG. 3 (b), the circuit board 1 in which a plurality of openings of the resist film 5, which are a plurality of solderable surfaces of the same shape, are formed in a matrix, is immersed in a solder coat forming solution for several minutes. By doing so, an adhesive substance is generated on the surfaces of the bonding pads 3 and the external terminals 4.
A solder powder is sprinkled on this, lightly brushed and selectively applied to the adhesive material portion, and then melted at a predetermined temperature to form a solder bump 7 on the upper surface of the circuit board 1 and a solder ball 9 on the lower surface. Are formed with high accuracy at the same time.
【００２７】前記回路基板１の両面に形成された半田バ
ンプ７と半田ボール９の位置が、スルーホール２の上下
で平面的に略同一位置に形成される。また、その大きさ
が略同一で、その材質が共に半田で形成される。The positions of the solder bumps 7 and the solder balls 9 formed on both sides of the circuit board 1 are formed at approximately the same position in the plane above and below the through hole 2. Further, their sizes are substantially the same, and their materials are both formed of solder.
【００２８】図３（ｃ）、（ｄ）において、ＩＣチップ
６の実装は、ＩＣチップ６を前記回路基板１の上面に形
成された半田バンプ７の所定位置に搭載した後、半田リ
フロー工程を経ることにより、ＩＣチップ６をフリップ
チップ接続することができる。3C and 3D, the IC chip 6 is mounted by mounting the IC chip 6 at a predetermined position on a solder bump 7 formed on the upper surface of the circuit board 1 and then performing a solder reflow process. Through this, the IC chip 6 can be flip-chip connected.
【００２９】図３（ｅ）において、熱硬化性樹脂８でサ
イドポッティングにより封止することにより半導体パッ
ケージ１０が完成される。In FIG. 3E, the semiconductor package 10 is completed by sealing with a thermosetting resin 8 by side potting.
【００３０】以上説明したように、本発明のＢＧＡパッ
ケージは、予め回路基板の両面に突起電極を形成した
後、半導体チップをフリップチップ接続するものであ
る。As described above, in the BGA package of the present invention, the bumps are formed on both sides of the circuit board in advance, and the semiconductor chip is flip-chip connected.
【００３１】[0031]
【発明の効果】本発明の半導体パッケージの製造方法に
よれば、半田コート形成液で処理することにより、回路
基板の両面の金属の露出部のみに粘着性を付与し、これ
に半田粉末をその部分に選択的に付着させ、加熱溶融す
ることによって、２つの突起電極の位置が、スルーホー
ルの上下の位置に、略同じ大きさで、同質の半田で、且
つ、一回のリフロー工程で形成することができる。生産
性が優れた安価な半導体パッケージの製造方法を提供す
ることが可能である。According to the method of manufacturing a semiconductor package of the present invention, by applying a treatment with a solder coat forming solution, only the exposed portions of the metal on both sides of the circuit board are provided with adhesiveness, and the solder powder is applied to the exposed portions. By selectively adhering to the portion and melting by heating, the positions of the two protruding electrodes are formed at the upper and lower positions of the through hole with approximately the same size, of the same quality solder, and in one reflow process can do. It is possible to provide a method for manufacturing an inexpensive semiconductor package having excellent productivity.
【図１】本発明の実施の形態に係わる半導体パッケージ
の製造方法に係わり図１（ａ）は回路基板の上面側の平
面図、図１（ｂ）は下面側の平面図、図１（ｃ）は部分
拡大断面図である。1 (a) is a plan view of an upper surface side of a circuit board, FIG. 1 (b) is a plan view of a lower surface side, and FIG. 1 (c) relates to a method of manufacturing a semiconductor package according to an embodiment of the present invention; () Is a partially enlarged sectional view.
【図２】図１（ａ）のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】本発明の半導体パッケージの製造工程を示す説
明図である。FIG. 3 is an explanatory view showing a manufacturing process of the semiconductor package of the present invention.
【図４】従来の半導体パッケージの製造工程を示す説明
図である。FIG. 4 is an explanatory view showing a manufacturing process of a conventional semiconductor package.
【図５】従来の他の半導体パッケージの製造工程を示す
説明図である。FIG. 5 is an explanatory view showing another conventional semiconductor package manufacturing process.
１ 回路基板 ２ スルーホール ３ ボンディングパッド ４ 外部端子 ５ レジスト膜 ６ ＩＣチップ ７ 半田バンプ ８ 封止樹脂 ９ 半田ボール １０ 半導体パッケージ DESCRIPTION OF SYMBOLS 1 Circuit board 2 Through hole 3 Bonding pad 4 External terminal 5 Resist film 6 IC chip 7 Solder bump 8 Sealing resin 9 Solder ball 10 Semiconductor package
Claims (5)
面に外部端子を有する印刷配線板に半導体チップをボン
ディングし、ボールグリッドアレイ（ＢＧＡ）を製造す
る半導体パッケージの製造方法において、予め印刷配線
板の両面に突起電極を形成した後、半導体チップをボン
ディングパッド側の突起電極にフリップチップ接続し、
半導体パッケージを形成したことを特徴とする半導体パ
ッケージの製造方法。1. A method of manufacturing a ball grid array (BGA) by bonding a semiconductor chip to a printed wiring board having bonding pads on one surface and external terminals on the other surface, the method comprising the steps of: After forming the protruding electrodes on both sides of the semiconductor chip, the semiconductor chip is flip-chip connected to the protruding electrodes on the bonding pad side,
A method for manufacturing a semiconductor package, comprising forming a semiconductor package.
ディングパッドと外部端子の突起電極の位置が、平面的
に略同一位置に有ることを特徴とする請求項１記載の半
導体パッケージの製造方法。2. The method of manufacturing a semiconductor package according to claim 1, wherein the positions of the bonding pads formed on both sides of the printed wiring board and the protruding electrodes of the external terminals are substantially the same in plan view. .
の突起電極の大きさが略同一であることを特徴とする請
求項１又は２記載の半導体パッケージの製造方法。3. The method according to claim 1, wherein two projecting electrodes formed on both sides of the printed wiring board have substantially the same size.
の突起電極の材質が同一であることを特徴とする請求項
１〜３記載の半導体パッケージの製造方法。4. The method for manufacturing a semiconductor package according to claim 1, wherein the material of the two projecting electrodes formed on both surfaces of the printed wiring board is the same.
を特徴とする請求項４記載の半導体パッケージの製造方
法。5. The method according to claim 4, wherein the material of the protruding electrode is solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20767798A JP2000040713A (en) | 1998-07-23 | 1998-07-23 | Manufacture of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20767798A JP2000040713A (en) | 1998-07-23 | 1998-07-23 | Manufacture of semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000040713A true JP2000040713A (en) | 2000-02-08 |
Family
ID=16543751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20767798A Pending JP2000040713A (en) | 1998-07-23 | 1998-07-23 | Manufacture of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000040713A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6569708B2 (en) | 2000-05-17 | 2003-05-27 | Nec Electronics Corporation | Repairable flip chip semiconductor device with excellent packaging reliability and method of manufacturing same |
| KR20030072855A (en) * | 2002-03-07 | 2003-09-19 | 주식회사 심텍 | The method for plating bump pads of printed circuit board for flip chip BGA semiconductor package |
| WO2006064534A1 (en) * | 2004-12-13 | 2006-06-22 | Renesas Technology Corp. | Semiconductor device |
| US7091619B2 (en) | 2003-03-24 | 2006-08-15 | Seiko Epson Corporation | Semiconductor device, semiconductor package, electronic device, electronic apparatus, and manufacturing methods of semiconductor device and electronic device |
| US7230329B2 (en) | 2003-02-07 | 2007-06-12 | Seiko Epson Corporation | Semiconductor device, electronic device, electronic equipment, method of manufacturing semiconductor device, and method of manufacturing electronic device |
| US7256072B2 (en) | 2003-03-25 | 2007-08-14 | Seiko Epson Corporation | Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device |
| CN100367452C (en) * | 2003-06-19 | 2008-02-06 | 精工爱普生株式会社 | Semiconductor device and its manufacturing method |
| JP2008071869A (en) * | 2006-09-13 | 2008-03-27 | Kyocera Corp | Wiring substrate |
| KR101243603B1 (en) | 2011-09-30 | 2013-03-15 | 에스티에스반도체통신 주식회사 | Method for fabricating of semiconductor package |
-
1998
- 1998-07-23 JP JP20767798A patent/JP2000040713A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6569708B2 (en) | 2000-05-17 | 2003-05-27 | Nec Electronics Corporation | Repairable flip chip semiconductor device with excellent packaging reliability and method of manufacturing same |
| KR20030072855A (en) * | 2002-03-07 | 2003-09-19 | 주식회사 심텍 | The method for plating bump pads of printed circuit board for flip chip BGA semiconductor package |
| US7230329B2 (en) | 2003-02-07 | 2007-06-12 | Seiko Epson Corporation | Semiconductor device, electronic device, electronic equipment, method of manufacturing semiconductor device, and method of manufacturing electronic device |
| US7091619B2 (en) | 2003-03-24 | 2006-08-15 | Seiko Epson Corporation | Semiconductor device, semiconductor package, electronic device, electronic apparatus, and manufacturing methods of semiconductor device and electronic device |
| US7256072B2 (en) | 2003-03-25 | 2007-08-14 | Seiko Epson Corporation | Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device |
| CN100367452C (en) * | 2003-06-19 | 2008-02-06 | 精工爱普生株式会社 | Semiconductor device and its manufacturing method |
| WO2006064534A1 (en) * | 2004-12-13 | 2006-06-22 | Renesas Technology Corp. | Semiconductor device |
| JPWO2006064534A1 (en) * | 2004-12-13 | 2008-08-07 | 株式会社ルネサステクノロジ | Semiconductor device |
| US7759793B2 (en) | 2004-12-13 | 2010-07-20 | Renesas Technology Corp. | Semiconductor device having elastic solder bump to prevent disconnection |
| US7951701B2 (en) | 2004-12-13 | 2011-05-31 | Renesas Electronics Corporation | Semiconductor device having elastic solder bump to prevent disconnection |
| JP4731495B2 (en) * | 2004-12-13 | 2011-07-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US8101514B2 (en) | 2004-12-13 | 2012-01-24 | Renesas Electronics Corporation | Semiconductor device having elastic solder bump to prevent disconnection |
| JP2008071869A (en) * | 2006-09-13 | 2008-03-27 | Kyocera Corp | Wiring substrate |
| KR101243603B1 (en) | 2011-09-30 | 2013-03-15 | 에스티에스반도체통신 주식회사 | Method for fabricating of semiconductor package |
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