TW544895B

TW544895B - Copper fuse structure and method for manufacturing the same

Info

Publication number: TW544895B
Application number: TW91109289A
Authority: TW
Inventors: Der-Yuan Wu; Chiu-Te Lee
Original assignee: United Microelectronics Corp
Priority date: 2002-05-03
Filing date: 2002-05-03
Publication date: 2003-08-01

Abstract

A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furthermore, the openings on a bonding pad and the fuse of the semiconductor structure can be identified with the method according to this invention. Moreover, in contrast of the fuse formed with an upper aluminum layer in prior art, the cost of the fuse manufacture is lower in the method according to this invention by fabricating the fuse with an inner copper layer.

Description

544895 五、發明說明（1) 5 - 1發明領域：本發明係有關於一種積體電路的形成，特別是有關於一種形成於半導體結構中的銅熔絲之方法及其結構。 5-2發明背景：在高解像微影（high -resolution photolithography) 與非專向性電漿麵刻（anisotropic plasma etching)之類的半導體製程技術中，其發展方向主要是盡量縮小半導體元件的大小，並提升半導體元件的封裝密度（packing density )。然而，許多積體電路元件的最後產出率（晶片產出率）將會隨著在晶片（chip)上的半導體元件密度之增加而下降。例如，位於一晶片上具有64 mega-bits的動態隨機存取記憶體（dynamic random access memory; DRAM) 之電路元件將會隨著電路元件數量的升高而增加產出率的才貝耗。一種用來克服上述θ己丨思體產出率下降的方法是另外提供數排的記憶體電路胞（memory cells)並以熔絲的方式來連接每一排的電路胞。通常是使用雷射光來打開在諸如 DRAM或SRAM之類的記憶體中的連結（熔絲），以抑制記憶體電路胞中出現缺陷的部分’並修正位址解碼機（a d d r e s s544895 V. Description of the invention (1) 5-1 Field of invention: The present invention relates to the formation of an integrated circuit, and more particularly to a method and structure of a copper fuse formed in a semiconductor structure. 5-2 Background of the Invention: In semiconductor process technologies such as high-resolution photolithography and anisotropic plasma etching, the development direction is mainly to minimize the size of semiconductor components. Size, and increase the packing density of semiconductor components. However, the final yield (wafer yield) of many integrated circuit components will decrease as the density of semiconductor components on the chip increases. For example, a circuit element with 64 mega-bits of dynamic random access memory (DRAM) on a chip will increase its output rate as the number of circuit elements increases. One method to overcome the above-mentioned decline in the output rate of the mind is to provide additional rows of memory circuit cells and connect the circuit cells of each row with a fuse. Laser light is usually used to open the connection (fuse) in the memory such as DRAM or SRAM to suppress defective parts in the memory cell ’and correct the address decoder (a d d r e s s

544895 五、發明說明（2) decoder)使備用的記憶排可以用來取代上述的缺陷排。第一圖是習知技藝中半導體元件的熔絲之示意圖。在一底材ίο上沉積一第一内金屬介電層（inter—metai dielectric layer; IMD layer)20。接著在第一内金屬介電層20中形成數個開口，並填入第一金屬插塞（meta；l plug)22與22a。沉積一第二内金屬介電層24於第一内金屬介電層20與第一金屬插塞22與22a之上。在第二内金屬介電層24中开》成接觸窗於第一金屬插塞上，並填入第一金屬層2 6與2 6 a。經過類似的模式及重複的步驟之後將可形成第三内金屬介電層28，第二金屬插塞30與3〇a，第四内金屬介電層32，及第二金屬層34與34a。最後在第四内金屬 "電層32與第二金屬層34與34a上沉積一保護層（ passivation)36，並對保護層36進行蝕刻。由於第二金屬層34將會連接至外界的導線，所以在蝕刻過程後必須露出用來與外界連接的第二金屬層34。另— 方面、，第二金屬層34a是用來作為上述半導體元件之炫絲 #所以在上述蝕刻過程之後必須保持一層薄的保護層於第一金屬層34a上。為了達到上述目的，一種習知技藝中、常見的方法是先使用—错___止变第一光罩來|虫刻保護層3 6以露出第一金屬層34且T會蝕刻第二金屬層34a上的保護層36。接〇下來，再、以一第二光罩來蝕刻保護層36使得在第二金屬層 34a上可以保有一層薄的保護層3β。曰 544895 五、發明說明（3) 在習知技藝中，上述的第一金屬插塞與第一金屬層通常是銅（copper)金屬層，而上述的第二金屬插塞與第二金屬層通常是鋁（aluminum)金屬層◦一般而言，在製程中較不傾向於使用銅來作為熔絲。這是因為銅是良好的熱傳導物質，而且，形成於頂層的銅金屬層的厚度通常會很厚。所以，在以雷射光修補工具（1 a s e r r e p a i r t ο ο 1 )來切割熔絲的時候，需要使用較高的能量才能切斷銅熔絲。解決熔絲不易切割的方法之一是將銅熔絲改為鋁熔絲。因為鋁的熔點比銅低，所以在切割時不需使用高能量的雷射光即可切割铭溶絲。但是，铭溶絲的成本卻比銅溶絲高。因xtb，為了能提高製程的效率以及節省半導體元件的製作成本，本發明提供了一種形成銅金屬層上的銅熔絲之結構與形成方法。 5 - 3發明目的及概述：鑒於上述之發明背景中，習知技藝在半導體結構的熔絲方面所出現的諸多缺點，本發明的主要目的在於藉由以半導體結構的内層中之薄的銅金屬層來作為半導體結構的熔絲，使得所形成的銅熔絲可以使用雷射光修補工具來切割。544895 V. Description of the invention (2) Decoder) The spare memory bank can be used to replace the above defect bank. The first figure is a schematic view of a fuse of a semiconductor device in the conventional art. A first inter-metal dielectric layer (IMD layer) 20 is deposited on a substrate. Next, a plurality of openings are formed in the first inner metal dielectric layer 20, and first metal plugs (meta; l plugs) 22 and 22a are filled. A second inner metal dielectric layer 24 is deposited on the first inner metal dielectric layer 20 and the first metal plugs 22 and 22a. A contact window is opened in the second inner metal dielectric layer 24 on the first metal plug, and the first metal layers 26 and 26 are filled. After similar patterns and repeated steps, a third inner metal dielectric layer 28, a second metal plug 30 and 30a, a fourth inner metal dielectric layer 32, and second metal layers 34 and 34a can be formed. Finally, a passivation layer 36 is deposited on the fourth inner metal " electric layer 32 and the second metal layers 34 and 34a, and the passivation layer 36 is etched. Since the second metal layer 34 will be connected to the external wires, the second metal layer 34 for connection with the outside must be exposed after the etching process. On the other hand, the second metal layer 34a is used as the dazzling wire of the semiconductor element. Therefore, a thin protective layer must be maintained on the first metal layer 34a after the above-mentioned etching process. In order to achieve the above purpose, a common method in the conventional art is to first use the wrong photomask to prevent the first metal layer 34 and etch the second metal layer 34 and T will etch the second metal. Protective layer 36 on layer 34a. Next, the protective layer 36 is etched with a second photomask so that a thin protective layer 3β can be retained on the second metal layer 34a. 544895 5. Description of the invention (3) In the conventional art, the above-mentioned first metal plug and the first metal layer are usually copper metal layers, and the above-mentioned second metal plug and the second metal layer are usually It is an aluminum metal layer. Generally speaking, copper is less likely to be used as a fuse in the manufacturing process. This is because copper is a good thermal conductive material, and the thickness of the copper metal layer formed on the top layer is usually very thick. Therefore, when cutting a fuse with a laser repair tool (1 a s r r e p a i r t ο ο 1), a higher energy is required to cut the copper fuse. One of the methods to solve the problem that the fuse is not easy to cut is to change the copper fuse to the aluminum fuse. Because aluminum has a lower melting point than copper, it does not require the use of high-energy laser light when cutting. However, the cost of Mingrong silk is higher than that of copper. Because of xtb, in order to improve the process efficiency and save the manufacturing cost of semiconductor devices, the present invention provides a structure and a method for forming a copper fuse on a copper metal layer. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, the conventional technique has many shortcomings in the fuse structure of the semiconductor structure. The main object of the present invention is to use a thin copper metal in the inner layer of the semiconductor structure. This layer serves as a fuse for the semiconductor structure, so that the formed copper fuse can be cut using a laser repair tool.

544895 五、發明說明（4) 本發明的另一目的在於本發明以半導體結構之一薄的銅金屬層來取代習知技藝中的鋁金屬層成為半導體元件的熔絲，以節省半導體製程的成本。本發明的再一目的在於本發明的方法可以結合形成保護層的開口於接合墊上的製程與形成保護層的開口於熔絲上的製程。換言之，本發明的方法可以一道餘刻製程來分別定義出在接合墊與熔絲上方的開口。也就是，本發明的方法可以精簡半導體生產的製程。根據以上所述之目的，本發明提供了一種半導體結構的銅熔絲及其形成方法。本發明係使用位於半導體結構中的内層銅金屬層來作為半導體元件之銅熔絲。再者，在上述銅熔絲上方的開口與上述半導體結構與外界連接的接合墊之上方開口可以於同一蝕刻製程中完成。如此一來，便可有效且經濟地形成一組銅熔絲於半導體結構之中。 5 - 4發明詳細說明：本發明的一些實施例會詳細描述如下。然而，除了詳細描述外，本發明還可以廣泛地在其他的實施例施行，且本發明的範圍不受限定，其以之後的專利範圍為準。544895 V. Description of the invention (4) Another object of the present invention is that the present invention replaces the aluminum metal layer in the conventional technology with a thin copper metal layer of a semiconductor structure to become a fuse of a semiconductor element, so as to save the cost of the semiconductor process. . Another object of the present invention is that the method of the present invention can combine the process of forming a protective layer opening on a bonding pad and the process of forming a protective layer opening on a fuse. In other words, the method of the present invention can define an opening above the bonding pad and the fuse respectively by a post-etching process. That is, the method of the present invention can simplify the process of semiconductor production. According to the above-mentioned object, the present invention provides a copper fuse for a semiconductor structure and a method for forming the same. The present invention uses an inner copper metal layer in a semiconductor structure as a copper fuse for a semiconductor element. Furthermore, the opening above the copper fuse and the opening above the bonding pad connected to the semiconductor structure and the outside can be completed in the same etching process. In this way, a set of copper fuses can be efficiently and economically formed in a semiconductor structure. 5-4 Detailed Description of the Invention: Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents.

第8頁 544895 五、發明說明⑸ 再者，半導體元件的不同部分並沒有依照尺寸繪圖。某些尺度與其他相關尺度相比已經被誇張，以提供更清楚的描述和本發明的理解。本發明之一較佳實施例為一種具有銅熔絲的半導體結構。在根據本發明的半導體結構中具有一半導體底材’在上述底材上具有一第一金屬層與一銅熔絲。上述的第一金屬層與銅熔絲位於同一層中且彼此分離。在上述的銅熔絲上具有一餘刻終止層，其中，上述的钱刻終止層包含一第一氮化石夕層/或是包含一氧化石夕層與一第一氮化石夕層。在上述的第一金屬層上具有一介電層。上述的介電層可以是一低介電常數的内金屬介電層（low K inter-metal dielectric layer)。在上述的介電層中具有一金屬連接層，上述的金屬連接層與上述的第一金屬層之間具有電性耦合。在上述的介電層上具有一第二金屬層，且上述的第二金屬層可以經由上述的金屬連接層而與上述的第一金屬層產生電性耦合◦在上述的第二金屬層與第一氮化矽層上具有一保護層，上述的保護層可以包含一氧化碎保護層與一氮化石夕保護層。在上述的保護層中具有一第^ 一開口與一第二開口，其中，上述的第一開口可以曝露出上述的第二金屬層以作為上述半導體結構之接合墊，且上述的第二開口可以曝露出上述的氧化矽層/第一氮化矽層。在上述的Page 8 544895 V. Description of the Invention ⑸ Furthermore, the different parts of the semiconductor components are not drawn according to size. Certain dimensions have been exaggerated compared to other related dimensions to provide a clearer description and understanding of the invention. A preferred embodiment of the present invention is a semiconductor structure having a copper fuse. A semiconductor substrate in a semiconductor structure according to the present invention 'has a first metal layer and a copper fuse on the substrate. The first metal layer and the copper fuse are located in the same layer and separated from each other. The copper fuse has a termination layer for a short period of time, wherein the termination layer for money includes a first nitride layer and / or a oxide layer and a first nitride layer. A dielectric layer is provided on the first metal layer. The above-mentioned dielectric layer may be a low K inter-metal dielectric layer. A metal connection layer is provided in the dielectric layer, and the metal connection layer and the first metal layer are electrically coupled with each other. There is a second metal layer on the dielectric layer, and the second metal layer can be electrically coupled with the first metal layer through the metal connection layer. The second metal layer and the first metal layer are electrically coupled. A silicon nitride layer has a protective layer. The above protective layer may include an oxide crush protective layer and a stone nitride protective layer. The protective layer has a first opening and a second opening, wherein the first opening may expose the second metal layer as a bonding pad for the semiconductor structure, and the second opening may be The above-mentioned silicon oxide layer / first silicon nitride layer is exposed. In the above

544895 五、發明說明（6) 第一開口與第二開口之侧邊上形一一一的第二氮化矽層可以避免水氣之類：?矽層’上述介電層進而影響本發明的半導體結構透至上述的本發明之另一較佳實施例為一銅炫绊壯爐的古、么；半‘體結構中形成 —構：方法。：種根據本發明的半導 :、二m;方法來形成1先，於-底材- 110中積开厂成v數個第門電層u; ’並於第-内金屬介電層丄1 U千形成稷數個弟一開口。在第一移除多餘的柄 ,^ ^ A, 開口中填入銅金屬並 ΐ: 餘的銅可以化學機械研磨法之類的方法來移除。接下來，在第一内金屬m的第二内金屬介電層120 ,並經由蝕列目10上儿積一口於上述填滿銅金屬的第一開义上衣程來形成第二開銅金屬並以諸如化學機械研磨法的^弟二開口中填入銅，以形成如第二圖所；二f來移除多餘的中，第一金屬層130是半導體尹構φ/一與130a，其而第一金屬声θ 」豆、、、口中之一金屬内連接線，弟孟屬層130a是本實施例中的熔絲。 3 :月的特徵之一是形成一。為了在經過蝕刻製程之接山丁二止層於烙、、、糸的上方層130a上至少仍銬可以，:文中所述，在第一金屬的方法中會先沉積一氧化：：：化矽層，所以，在本發明的第二内金屬介電層與第—二0與一氮化矽層150於上述化矽層140與氮化矽厣至’b上。在熔絲130a上的氧曰可以避免在蝕刻完成後，不僅露 544895544895 V. Description of the invention (6) The second silicon nitride layer formed one by one on the sides of the first opening and the second opening can avoid water vapor and the like: "Silicon layer 'The above dielectric layer further affects the present invention. Another preferred embodiment of the present invention is that the semiconductor structure is the ancient and modern copper dazzling furnace; the semi-'body structure is formed-structure: method. : A semiconductor according to the present invention :, two m; the method to form 1 first, in the-substrate-110 to open the factory to v several gate electrical layers u; 'and in the-inner metal dielectric layer 丄1 U thousand form a few brothers and one mouth. In the first removal of the excess handle, ^ ^ A, the opening is filled with copper metal and ΐ: the remaining copper can be removed by methods such as chemical mechanical polishing. Next, a second inner metal dielectric layer 120 is formed on the first inner metal m, and a second open copper metal is formed on the first enclosing coat process filled with copper metal through the etching column 10 to form a second open copper metal and Copper is filled in the second opening such as a chemical mechanical polishing method to form as shown in the second figure; second f is used to remove the excess, the first metal layer 130 is a semiconductor structure φ / a and 130a, and The first metal sound θ ′ is a metal inner connecting wire in the two ends, and the Si layer 130a is a fuse in this embodiment. 3: One of the characteristics of the month is the formation of one. In order to attach at least the soldering layer 130a above the soldering layer 130a after the etching process, as described in the article, in the first metal method, an oxide is first deposited: siliconized silicon Therefore, in the present invention, the second inner metal dielectric layer and the -20th and a silicon nitride layer 150 are on the siliconized layer 140 and the silicon nitride layer to b. Oxygen on fuse 130a can avoid exposure after the etching is completed, not only 544895

出半導體結構進而在整體電的接合墊’更同時會露出上述的炫絲部分路上造成不必要的困擾。在/儿積一第三内金屬介電㈣於上 ΐ:;:'刻第三内金屬介電柳= 第三Η二由/成一第三開口於第一金屬層130之上。在第四；全銅金屬並移除多餘的銅。接下*，沉積-—笛。屬；丨電層170於第三内金屬介電層160上，並开，成口 :開口於上述填滿銅金屬的第三開口之上。在第四 1 80。、番入銅金屬並移除多餘的銅，以形成一第二金屬層幵屬厗禝上述的步驟，在第四内金屬介電層170盥第:人 =80上形成一第五内金屬介電層19〇，一第六内：：：半二〇〇與一第三金屬層210。第三金屬層210可以是上述丨 ν體結構與外界連結的接合墊。迹化 4Ϊ:，化石夕保護層(passivatlonoxlde)22〇與 1 2 0 0盘/SiN) 2 30於第六内金屬介電i 。在、Λτ玉屬層210之上。本發明的另一特徵將敘述如^ 血這光罩的微影製程之後’將可以在接合墊上： ::上方分別形成-開口。換言之，在經過一道光i: ::衣程之後，不僅可以移除在第三金屬層2ιο上方的罩」與氧切保護層220以形成-開口 240於；屬層210之上。上述的微影製程更可以移 = 層130a上方的氮化石夕保護層23〇，氧化石夕保護層㈣，主第The semiconductor structure will be exposed, and the above-mentioned bright wire part will cause unnecessary troubles on the road. A third inner metal dielectric is formed on the upper surface of the first metal layer:;: 'Carved third inner metal dielectric willow = third third is formed by a third opening on the first metal layer 130. In the fourth; all copper metal and remove excess copper. Next, *, deposition-flute.丨 The electrical layer 170 is opened on the third inner metal dielectric layer 160 and formed into an opening: the opening is above the third opening filled with copper metal. In the fourth 1 80. 2. Insert copper metal and remove excess copper to form a second metal layer. The above steps are to form a fifth inner metal dielectric on the fourth inner metal dielectric layer 170: the first person = 80. Electrical layer 190, a sixth inner :: half a 200 and a third metal layer 210. The third metal layer 210 may be a bonding pad connected to the above-mentioned ν-body structure and the outside. Trace 4Ϊ: Fossil passivation layer (passivatlonoxlde) 22〇 and 12 00 disk / SiN) 2 30 in the sixth internal metal dielectric i. On the Δτ jade layer 210. Another feature of the present invention will describe that after the photolithography process of the mask such as blood, it will be possible to form an opening on the bonding pad: :: above. In other words, after a light i ::: clothing process, not only the cover above the third metal layer 2 and the oxygen cutting protective layer 220 can be removed to form an opening 240 on the metal layer 210. The above-mentioned lithography process can be further shifted to a protective layer of nitrided oxide 23 above the layer 130a, and a protective layer of oxided oxide ㈣.

544895 五、發明說明（8) 六内金屬介電層2 0 0，第五内金屬介電層丨9〇，介電層170，及第三内金屬介電層16〇，以形成口至屬於第一金屬層l30a上的蝕刻停止層之上。接著沉二一 :匕矽層2 60於氮化矽保護層23〇與開口24〇及開口25貝曰, ^在對氮化矽層260進行回蝕之後，將會露出作取接合墊的第三金屬層21〇。另—方面，在對末作為 ?回蝕刻之後’將會露出作為熔 ‘石層广:進乳化矽層U0與/或氮化矽層15〇。鸯層130a上之水氣ΐϋίΪ: Π，氮切層2 6 0可以用來防止金屬介電層，= 程中進入裸露出來的内 =絲上方的氧化石夕層mo與氮化石夕層150可以用离1電層。而蝕的過程中裸露出第一金屬声用來防止在回結構在電路上出現不必要的‘誤。& ’以防止上述的半導體露出半導體：：：接in 嶋刻製程中’將會出熔絲。此時二』至熔絲的上方且不會露扮演著相當重要的角色化！層140與氮化石夕層丨50將與氮化矽層15〇 ”、、，熔絲上方的氧化矽層14〇接合墊2Π以露出；=:Γ〇的餘刻製程可以钱刻至不露出义容絲。為了使|虫刻^刻終止於炼职…上方以 1 40與氮化矽層i 5 〇，除飞於上述熔絲上方的氧化矽層除了可以控制钱刻製程的參數之外，第12頁 544895 五、發明說明（9) 更可以從氤化矽層26〇，氧化度上來加以控制。例如，各40與虱化矽層】50的厚 5 0 0埃的時候，氧化矽斧^ ^矽層260的厚度為2〇〇〇土 ^Λ 1 5 00 ± 50〇^#5〇〇； 5〇〇A//t^ 矽層2 60的蝕刻的時候，、，來，在進行氮化矽層2 6 0，甚至是移广_ ，、 *熔絲Ϊ 3 〇a上方的氮化肛土疋才夕除虱化石夕 — 絲1 3 0 a的上方至少仍可一" σ弟二圖所示。在熔 1 30a不至於在蝕刻制 >、一乳化矽層1 40，使得熔絲蝕刻衣耘之後顯露出來。在候，可層 130a 未顯示藝中的鋼金屬銅金屬厚度一在進行切割本應用上以使用 ’使得於圖中銅熔絲層來作層來作般而言修補的發明中544895 V. Description of the invention (8) Six inner metal dielectric layers 2000, fifth inner metal dielectric layer 900, dielectric layer 170, and third inner metal dielectric layer 160, to form a mouth to belong to Above the etch stop layer on the first metal layer 130a. Then Shen Yiyi: the silicon layer 2 60 in the silicon nitride protective layer 23 and the opening 24 and the opening 25, ^ After the silicon nitride layer 260 is etched back, the first part for the bonding pad will be exposed. Tri-metal layer 21o. On the other hand, after the etching process is performed, it will be exposed as a molten layer. The stone layer is widened: the emulsified silicon layer U0 and / or the silicon nitride layer 150. Water and gas on the layer 130a: Π, the nitrogen cutting layer 2 6 0 can be used to prevent the metal dielectric layer, = enter the exposed inner part in the process = the oxide stone layer mo and the nitride stone layer 150 above the wire can Use 1 electric layer. The first metal sound is exposed during the etch process to prevent unnecessary 'errors' from appearing on the circuit in the return structure. & ’To prevent the above-mentioned semiconductor from being exposed Semiconductor ::: in in the engraving process’ will cause a fuse. At this time, the second one goes to the top of the fuse and will not be exposed. It plays a very important role! The layer 140 and the nitride nitride layer 丨 50 will be exposed to the silicon nitride layer 15 ″, and the silicon oxide layer 14 〇 above the fuse to bond the pad 2 Π to be exposed; the remaining process of =: Γ 〇 can be engraved until it is not exposed Yirongsi. In order to make the worm engraving stop at the refining position ... 1 40 and the silicon nitride layer i 5 〇, in addition to the silicon oxide layer flying above the fuse, in addition to controlling the parameters of the money engraving process Page 12 544895 V. Description of the invention (9) The silicon oxide layer 26 can be controlled by the degree of oxidation. For example, when the thickness of each silicon layer is 40 and the thickness is 50 angstroms, the silicon oxide can be controlled. The thickness of the silicon layer 260 is 20000 ^^ 1 500 ± 50〇 ^ # 500; 500A // t ^ When the silicon layer 260 is etched, The silicon nitride layer 2 6 0, or even the widening _, * nitrogen nitride anus soil above the fuse Ϊ 3 〇a to remove lice and fossils — at least still above the wire 1 3 0 a " As shown in the second figure of Figure σ. After melting 1 30a, it will not be etched, and an emulsified silicon layer 1 40 will make the fuse etched after exposure. At the moment, layer 130a does not show the steel and gold in the process. In cutting a copper thickness on the present application to use 'in that the copper layer to make the fuse FIG layer to make the invention In general patch

述半導體結構的梦w + A 雷射光修補工且：S電路胞出現缺陷的時上述半導1结；=:為熔絲的第-金屬以ΐ 路胞。與習知技為銅炫絲。里優::接二塾同一層（表層）的會比在表層的銅全=内層的銅金屬層的時候’可以很容易的‘ f度更溥。所以，的銅熔絲。用每射光修補工具來 β以上所、# 成銅溶絲的方法。本發:2 = 了一種在半導體結構中形 ::屬層來作為半導體：：半：體結構的内層之薄使用-節省成本，1雷射先工之’本發明可以南具奋易切割的元件來作第13頁 544895 五、發明言兒明（ίο) 為半導體結構中的熔絲。此外，在本發明中，可以在形成半導體結構之接合墊上方的開口的時候，同時在熔絲上形成一開口，也就是，本發明的方法可以在一道蝕刻製程中分別定義出接合墊與熔絲上方的開口。所以，本發明可以提升銅熔絲的適用性與熔絲製程的效率。Describe the dream w + A laser light repairer of the semiconductor structure and: when a defect occurs in the S circuit cell, the above-mentioned semiconducting 1 junction; =: the first metal of the fuse, and the circuit cell. And know-how for the copper dazzle silk. Li You :: The next layer (surface layer) will be easier than ‘f degree when the copper on the surface layer = the copper metal layer on the inner layer’. So, the copper fuse. A method of using β-ray repair tools to form copper dissolving wires. The hair: 2 = a type of semiconductor layer in the semiconductor structure: as a semi-conductor layer: as a semi-conductor: the thinner use of the inner layer of the body structure-saving costs, 1 laser forerunner, the invention can be easily cut Components to make on page 13 544895 V. Inventor Er Ming (ίο) is a fuse in a semiconductor structure. In addition, in the present invention, when an opening above a bonding pad of a semiconductor structure is formed, an opening is formed in the fuse at the same time, that is, the method of the present invention can separately define the bonding pad and the melting point in an etching process The opening above the wire. Therefore, the present invention can improve the applicability of copper fuses and the efficiency of the fuse process.

以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍内。The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

第14頁 544895 圖式簡單說明本發明之上述目的與優點，將以下列的實施例以及圖示，做詳細說明如下，其中：第一圖係一根據習知技藝的技術所形成之金屬熔絲的示意圖；第二圖係一具有根據本發明所揭露技術所形成的金屬熔絲之半導體結構的示意圖；以及第三圖係一第二圖的半導體結構在經過蝕刻氮化矽層 2 6 0的步驟之後的示意圖。主要部分之代表符號： 10 底材 20 第一内金屬介電層 22 第一金屬插塞 2 2a 第一金屬插塞 24 第二内金屬介電層 26 第一金屬層 2 6a 第一金屬層 28 第三内金屬介電層 30 第二金屬插塞 3 0 & 弟《—金屬插基 32 第四内金屬介電層Page 14 544895 The diagram briefly illustrates the above-mentioned objects and advantages of the present invention. The following embodiments and diagrams will be used to explain in detail as follows, where: The first diagram is a metal fuse formed according to the technology of the conventional art The second diagram is a schematic diagram of a semiconductor structure having a metal fuse formed according to the disclosed technology; and the third diagram is a semiconductor structure of the second diagram after etching the silicon nitride layer 2 6 0 Schematic diagram after the steps. Main symbols: 10 substrate 20 first inner metal dielectric layer 22 first metal plug 2 2a first metal plug 24 second inner metal dielectric layer 26 first metal layer 2 6a first metal layer 28 The third inner metal dielectric layer 30 The second metal plug 3 0 & the metal insert 32 The fourth inner metal dielectric layer

第15頁 544895 圖式簡單說明 34 第二二金屬層 34a 第二金屬層 36 保護層 10 0 底材 110 第一内金屬介電層 120 第二内金屬介電層 130 第一金屬層 1 3 0a 第- -金屬層（熔絲 140 氧化矽層 150 氮化矽層 160 第二内金屬介電層 170 第四内金屬介電層 180 第二金屬層 190 第五内金屬介電層 200 第六内金屬介電層 21 0 第二金屬層 220 氧化矽保護層 230 氮化矽保護層 240 開 V 250 開口 260 氮化矽層Page 15 544895 Brief description of the drawings 34 Second metal layer 34a Second metal layer 36 Protective layer 10 0 Substrate 110 First internal metal dielectric layer 120 Second internal metal dielectric layer 130 First metal layer 1 3 0a The first-metal layer (fuse 140 silicon oxide layer 150 silicon nitride layer 160 second inner metal dielectric layer 170 fourth inner metal dielectric layer 180 second metal layer 190 fifth fifth metal dielectric layer 200 sixth sixth Metal dielectric layer 21 0 Second metal layer 220 Silicon oxide protection layer 230 Silicon nitride protection layer 240 V 250 opening 260 Silicon nitride layer

第16頁Page 16

Claims

544895 六、申請專利範圍 1. 一種具有銅熔絲的半導體結構，該半導體結構包含：一底材；一第一金屬層位於該底材上；一銅熔絲位於該底材上，其中該銅熔絲與該第一金屬層位於同一層且該銅熔絲與該第一金屬層係彼此分離；一蝕刻終止層位於該銅熔絲上；一介電層位於該第一金屬層上；一金屬連接層位於該介電層中，該金屬連接層係與該第一金屬層電性耦合；544895 6. Scope of patent application 1. A semiconductor structure having a copper fuse, the semiconductor structure comprising: a substrate; a first metal layer on the substrate; a copper fuse on the substrate, wherein the copper The fuse and the first metal layer are located on the same layer and the copper fuse and the first metal layer are separated from each other; an etch stop layer is located on the copper fuse; a dielectric layer is located on the first metal layer; A metal connection layer is located in the dielectric layer, and the metal connection layer is electrically coupled with the first metal layer;

一第二金屬層位於該介電層上，其中該第二金屬層與該金屬連接層電性耦合；及一保護層位於該第二金屬層與該I虫刻終止層上，其中該保護層包含可曝露出該第二金屬層之一第一開口與可曝露出該银刻終止層之一第二開口。 2. 如申請專利範圍第1項之半導體結構，其中該第一金屬層係一銅金屬層。A second metal layer is located on the dielectric layer, wherein the second metal layer is electrically coupled to the metal connection layer; and a protection layer is located on the second metal layer and the I-etched termination layer, wherein the protection layer The method includes a first opening capable of exposing the second metal layer and a second opening capable of exposing the silver etch stop layer. 2. The semiconductor structure according to item 1 of the application, wherein the first metal layer is a copper metal layer.

3. 如申請專利範圍第1項之半導體結構，其中該第二金屬層係一銅金屬層。 4. 如申請專利範圍第1項之半導體結構，其中該蝕刻終止層包含一氮化石夕層與一氧化石夕層。3. The semiconductor structure according to item 1 of the application, wherein the second metal layer is a copper metal layer. 4. The semiconductor structure according to item 1 of the application, wherein the etch stop layer includes a nitrided oxide layer and a oxided oxide layer.

第17頁 544895 六、申請專利範圍 5. 如申請專利範圍第1項之半導體結構，其中該蝕刻終止層係一氮化$夕層。 6. 如申請專利範圍第1項之半導體結構，更包含一氮化矽層位於該等開口的側邊。 7. 如申請專利範圍第1項之半導體結構，其中該介電層係一低介電常數之内金屬介電層（Low K IMD layer)。 8. —種具有銅熔絲的半導體結構，該半導體結構包含：一底材；一第一金屬層位於該底材上；一銅溶絲位於該底材上，該第一金屬層與該銅炼絲係位於同一層且彼此分離；一氧化碎層位於該銅溶絲上；一第一氮化矽層位於該氧化矽層上；一介電層位於該第一金屬層上；一金屬連接層位於該介電層中，該金屬連接層係與該第一金屬層電性耦合；一第二金屬層位於該介電層上，該第二金屬層係與該金屬連接層電性耦合；一保護層位於該第二金屬層，與該第一氮化矽層上，其中該保護層包含可曝露出該第二金屬層之一第一開口與可曝露出該蝕刻終止層之一第二開口；及Page 17 544895 VI. Scope of patent application 5. For the semiconductor structure according to item 1 of the patent application scope, the etch stop layer is a nitrided layer. 6. For example, the semiconductor structure of the first patent application scope further includes a silicon nitride layer on the sides of the openings. 7. The semiconductor structure according to item 1 of the application, wherein the dielectric layer is a low K IMD layer with a low dielectric constant. 8. A semiconductor structure having a copper fuse, the semiconductor structure comprising: a substrate; a first metal layer on the substrate; a copper molten wire on the substrate, the first metal layer and the copper The spinning line is located on the same layer and separated from each other; an oxide broken layer is located on the copper-soluble wire; a first silicon nitride layer is located on the silicon oxide layer; a dielectric layer is located on the first metal layer; a metal connection A layer is located in the dielectric layer, the metal connection layer is electrically coupled with the first metal layer; a second metal layer is located on the dielectric layer, and the second metal layer is electrically coupled with the metal connection layer; A protective layer is located on the second metal layer and the first silicon nitride layer, wherein the protective layer includes a first opening that can expose the second metal layer and a second that can expose the etch stop layer. Speak; and

第18頁 544895 六、申請專利範圍一第二氮化矽層位於該第一開口與該第二開口的侧邊 9.如申請專利範圍第8項之半導體結構，其中該第一金屬層係銅金屬層。 1 0.如申請專利範圍第8項之半導體結構，其中該第二金屬層係銅金屬層。Page 18 544895 VI. Patent application scope-a second silicon nitride layer is located on the side of the first opening and the second opening 9. The semiconductor structure according to item 8 of the patent application scope, wherein the first metal layer is copper Metal layer. 10. The semiconductor structure according to item 8 of the application, wherein the second metal layer is a copper metal layer.

1 1.如申請專利範圍第8項之半導體結構，其中該第一金屬層係一金屬内連接線。 1 2.如申請專利範圍第8項之半導體結構，其中該第二金屬層係^一金屬内連接線。 1 3. —種銅熔絲的形成方法，上述的銅熔絲係位於一半導體結構中，該銅熔絲的形成方法包含：提供一底材；1 1. The semiconductor structure according to item 8 of the application, wherein the first metal layer is a metal interconnect. 1 2. The semiconductor structure according to item 8 of the patent application, wherein the second metal layer is a metal interconnect. 1 3. A method for forming a copper fuse, wherein the above-mentioned copper fuse is located in a semi-conductive structure, and the method for forming the copper fuse includes: providing a substrate;

形成一第一金屬層於該底材上；形成一銅熔絲於該底材上，其中該第一金屬層與該銅熔絲係位於同一層且該第一金屬層與該銅熔絲係彼此分離形成一蝕刻終止層於該銅熔絲上；形成一介電層於該第一金屬層上;Forming a first metal layer on the substrate; forming a copper fuse on the substrate, wherein the first metal layer and the copper fuse are located on the same layer and the first metal layer and the copper fuse are Separated from each other to form an etch stop layer on the copper fuse; forming a dielectric layer on the first metal layer;

第19頁 544895 該該；中出該更侧與與上其露中中右層層之，曝其其左接屬層口可，，的連金止開口法法口屬二終二開方方開金第亥第二成成二該該蝕一第形形第，，該與該的與。的該中上與口，絲；上絲與層層層開層溶上層溶口電電屬一屬銅絲碎銅開介介金第金之：熔化之一該該二一二項含銅氧項第於；於；第成第13包該該13該層合層合該形該第驟於於第於接麵屬^於以出圍步層層圍層連性金性層層露範成碎碎範碎屬電二電護護曝。利形化化利化金係第係保保可層專的氧氮專氮圍一層一層一該口止請層一一請一 g成屬成接成刻開停申止成成申成 %形金形連形蝕一刻如終形形如形。 tt一屬第li•刻 ‘ ·含上、第金及該該 4蝕15包邊六 11 該。中上其絲，熔法銅方該成於形層的碎絲化溶氮銅一之成項形 3 係第驟圍步範成利形專的請層申止如終刻 16蝕該中其法方成形的絲熔銅之項 3 ο IX 第層圍屬範金利銅專係請層申屬如金 - 7第Page 19 544895 This should be in the middle of the right side and the middle layer on the right side of the exposed, exposed its left part of the layer can be, and the gold method of the opening method is a two-end two-square Kaijin Dihai is the second and the eclipse, and the and the and. The upper and lower mouths and wires; the upper wires and the layers are opened layer by layer and the upper layer is dissolved. The electricity is a copper wire, broken copper, and intermediary gold. The first of the gold: melt one of the two or two items containing copper and oxygen. The first and the first; the 13th package; the 13th layer; the laminated layer; the first step; the first step; the first step; the outer layer; the outer layer; The broken fan is an electric second electric protection protection exposure. Change the shape, change the quality of the gold system of the first Baobao layer, special oxygen and nitrogen, and nitrogen surround each layer one by one. Please stop the layer one by one. One by one. The gold-shaped eclipse is like a final shape. tt1 belongs to the first li • carved ‘· Hangshang, the first gold, and the 4 eclipse 15 edging 6 11 the. The middle and upper wires, the molten copper square, should be formed in the broken layer of the dissolved layer of dissolved nitrogen. The first step of the 3rd step is Fan Chengli, please apply for the layer. Item 3 of the wire-melted copper formed by the French party ο IX The first layer is Fan Jinli Copper Specialty, please apply for the layer as gold-7

544895 六、申請專利範圍 / 18. 如申請專利範圍第1 3項之銅熔絲的形成方法，其中該 · 第二金屬層係銅金屬層。 19. 如申請專利範圍第1 3項之銅熔絲的形成方法，其中該第一金屬層係該半導體結構之一金屬内連接線。 20. 如申請專利範圍第1 3項之銅熔絲的形成方法，其中該第二金屬層係該半導體結構之一金屬内連接線。544895 6. Scope of patent application / 18. The method for forming a copper fuse according to item 13 of the patent application scope, wherein the second metal layer is a copper metal layer. 19. The method for forming a copper fuse according to item 13 of the application, wherein the first metal layer is a metal interconnection line of the semiconductor structure. 20. The method for forming a copper fuse according to item 13 of the application, wherein the second metal layer is a metal interconnection line of the semiconductor structure.

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