TW544860B

TW544860B - Structure, fabrication and operation method of flash memory

Info

Publication number: TW544860B
Application number: TW91109754A
Authority: TW
Inventors: Chih-Wei Hung; Chih-Ming Chen
Original assignee: Powerchip Semiconductor Corp
Priority date: 2002-05-10
Filing date: 2002-05-10
Publication date: 2003-08-01

Abstract

A structure of a flash memory device. The flash memory comprises a deep n-well formed in a substrate, a p-well in the deep n-well, a stacked gate structure on the substrate, source and drain regions in the substrate at two respective sides of the stacked gate, an n-well extending from the drain region to a position under the stacked-gate structure, an n pocket doped region under the stacked-gate structure and connected between the n-well and the source region. The flash memory uses avalanche induced hot electron injection for programming, and the F-N tunneling effect to perform erase operation.

Description

544860 五、發明說明（1) 本發明是有關於一種非游544860 V. Description of the invention (1) The present invention relates to a non-tourism

Mpmnrv，MVM、-从里非揮發性記憶體（non-Volati leMpmnrv, MVM,-non-volatile memory (non-Volati le

Memory，NVM) το 件，且牿别 η 士 ^日 / & 寺別疋有關於一種ρ型通道 (P-Channel)快閃記憶體开彼—a w y ^ 方法。牛之、、Ό構、製造方法與其操作取、：元件由於具有可多次進行資料之存入、讀點，所二已成個f 2入之資料在斷電後也不會消失之優揎菸I ρ ί為個電腦和電子設備所廣泛採用的一種非揮發性記憶體元件。 H开厂31的决閃°己^體元件係以摻雜的多晶矽製作浮置閘極（Fl0atlng Gate)與控制閘極（c〇ntr〇i Gate)。對此快閃記憶體元件進行程式化或抹除操作時，係、分別於源極、區汲極區與控制閘極上施加適當電壓，以使電子注入複晶矽浮置閘極中，或將電子從多晶矽浮置閘極中拉出。一般而言，快閃記憶體元件常用之電子注入模式可分為通道熱電子注入模式（Channel Hot-Electron 刀 injection ， CHEI)以及F-N 穿隧（Fowler-Nordheim Tunneling)模式等等，而且元件的程式化與抹除操作模式隨著電子注入與拉出之方式而改變。此外，快閃記憶體元件之結構可分為P型通道 (P-Channel)快閃記憶體元件與η型通道（n-Channel)快閃記憶體元件。由於p型通道快閃記憶體元件具有高電子注入效率、較高的元件縮小幅度（H i g h S c a 1 a b i 1 i t y )、可免於熱電洞注入所導致的可靠度問題、以及電子注入時具有較低的氧化層電場等異於η型快閃記憶體元件之特點，因Memory (NVM) το, and 牿士 ^ 日 / &Temple; there is a way to a p-channel flash memory (a w y ^). Niu Zhi, Ό structure, manufacturing method and its operation: Because the component has multiple times of data storage and reading points, the data that has become f 2 will not disappear even after the power is cut off. Smoke I ρ ί is a non-volatile memory element widely used in computers and electronic devices. The flash device of the H-factory 31 is a floating gate (F0atlng Gate) and a control gate (con gate) made of doped polycrystalline silicon. When programming or erasing the flash memory device, an appropriate voltage is applied to the source, the drain region, and the control gate, respectively, so that electrons are injected into the polycrystalline silicon floating gate, or The electrons are pulled from the polysilicon floating gate. Generally speaking, the common electron injection modes of flash memory devices can be divided into Channel Hot-Electron injection (CHEI) mode and FN tunneling (Fowler-Nordheim Tunneling) mode, etc., and the program of the device The erase and erase operation modes change with the way electrons are injected and pulled. In addition, the structure of the flash memory device can be divided into a P-channel flash memory device and an n-channel flash memory device. Due to the high electron injection efficiency of the p-channel flash memory device, a high component reduction (H igh S ca 1 abi 1 ity), the reliability problem caused by hot hole injection, and the The lower oxide layer electric field is different from the characteristics of η-type flash memory devices, because

8938twf.ptd 第5頁8938twf.ptd Page 5

〜五、發明說明（2) 對於p型通道快閃電子（Channel nE1 入資料以進行程式化道區拉出以進行抹除元件之結構、製造方法與其操作方法，可以層遭受到非常高的電場，以增加穿隧氧化層性，並可提高記憶體元件之積集度。曰 544860 此在未來仍具有相當大之發展空記憶體元件而言，其 ectron，CHE )注入模，並且利用F - N穿隧模铲彳：於P聖通道快閃記憶體元件是使用通壬工’而且電子僅由靠近汲極處注入，戶; 的效率甚低。因此，在程式化的過程中需j 以提供較大的電流，並藉以增加程式化的过使用的電壓升高時，常造成電子元件之可靠 (Rel iabi 1 i ty)降低，並且會限制元件尺寸有鑑於此，本發明之一目的在於提供一本發明之另〆目的在於提供一種快閃記構、製造方法與其操作方法，可以增加記憶率，並降低記憶胞讀取時之漏電流。有鑑於此，本發明提供一種快閃記憶體此快閃記憶體元件是由設置於第一導電型基電型第一井區、詨置於第二導電型第一井= 型第二井區、設篆於第一導電型基底上之堆分別設置於堆疊閘極結構兩侧的第一導電型區與汲極區、設董：於第一導電型第二井區中通常以通道熱式由沒極端寫式將電子由通遂熱電子進行以其電子注入施加較高電壓率。然而，當度窜小的程度。種快閃記憶體避免穿隧氧化的壽命和可靠憶體元件之結胞程式化之速元件之結構，底内之第二導中之第一導電豐問極結構、基底中之源極 ’從汲極區延 544860 五、發明說明（3) ^ ^ Ϊ堆疊結構下方並與源極區相距一間隔之第二導電二導费，、與投置於堆®閘極結構下方，龙分別連接第成1型第三井區與源極區之第二導電型口袋摻雜區所構口：，極結構下方，然後在源極側形成-口袋摻雜區，j f*二‘ f，之兩端分別連接源極區與η型井底。由於此口 ;ίΪί;η型井區具有相同之背景摻雜濃度，且口袋摻 tM ,1車又11型井&淺之接合面，因此口袋#雜區之崩潰低ϋ 井區之崩潰電壓低，施加於控制蘭極之電壓可情r;伏：左右。而且，藉由上述結構，本發明之快閃記【:體可以利用累增崩潰引發熱電子注入模式進行程式^，己 ί:ί ί7穿隧效應進行抹除。此外，將n蜇井區與汲極路連接在一起，而不舍於、％榀^ ^撕1 a 一 > M k — 堆最ΪΓ月於沒極側形成1型井區，且此Ω型井區延伸至二I木結構下方，然後在源極側形口袋摻雜 ϋ #雜區之兩端分別連垃、:店故c ^ ΧΛ丄、· Λ ▲接雜區與η型孑雜區具有較η型夺電壓較η型井區2 低於10伏特左右憶體可以利用累並以通道FN穿隧紐路連接在一，而不會於汲極和η型井丁區之間的形：： ) 此方法井 —. 導電型此第圖 ) 進行形成一第至堆疊閘間隔〇移案化光阻本發明提供一種快閃記憶體元件之製造方法，此 ^下列步驟：提供已依序形成一第二導電型：法 :广導電型第二井區與一堆疊間極結構刑 2。於此基底上形成—第一圖案化光阻層：電型一一 ^〜必你。接著，一袋植入步驟，於預定形成汲極區之美進仃一二導電型第三井區，且第二導電型第三井^征形成一第極結構下方並與預定形成一源極區之基底至堆疊閘除第一圖案化光阻層後，於基底上形成—距—間隔。移弟二圖案化光阻 =化光阻層暴露預定形成一汲極區之基底。匕弟— 第一口袋植入步驟，於預宗拟ΛF t u ’進行~ V. Description of the invention (2) For p-type channel flash electrons (Channel nE1 to enter data to program the channel area to pull out to erase the structure, manufacturing method and operation method of the element, the layer can be subjected to a very high electric field In order to increase the tunneling oxide layer property and improve the accumulation of memory elements. 544860 This will still have considerable development in the future. For empty memory elements, its ectron, CHE) injection mold, and use F- N tunneling mode scooping: The flash memory device in the P channel uses the tunnel technology, and the electrons are injected only near the drain, so the efficiency is very low. Therefore, in the process of programming, j is required to provide a larger current, and by increasing the programmed over-used voltage, the reliability of electronic components (Rel iabi 1 i ty) is often reduced, and the components are limited. In view of the size, an object of the present invention is to provide a flash memory structure, a manufacturing method and an operation method thereof, which can increase a memory rate and reduce a leakage current when a memory cell is read. In view of this, the present invention provides a flash memory. The flash memory element is provided in a first conductive type base type first well area and placed in a second conductive type first well = type second well area. 1. The first conductive type region and the drain region provided on both sides of the stacked gate structure are stacked on the first conductive type substrate, and the director is provided in the second conductive region of the first conductive type. The electrons are written by the passivation hot electrons and the electrons are injected at a higher voltage rate. However, the degree of channeling is small. This kind of flash memory avoids the tunneling oxidation lifetime and the structure of the reliable memory cell stylized speed element structure, the first conductive semiconductor structure in the second conductor in the bottom, the source in the substrate. The drain region extends 544860 V. Description of the invention (3) ^ ^ Ϊ The second conductive second conductive charge below the stacked structure and spaced apart from the source region, and placed under the stack® gate structure, the dragon is connected to the first Form a type-I third well region and a second conductivity type pocket doped region of the source region: below the pole structure, and then form a -pocket doped region on the source side, jf * II'f, both ends The source region and the n-type bottom are connected respectively. Because this n-type well area has the same background doping concentration, and the pocket is doped with tM, 1 car and 11-type wells with shallow junctions, the breakdown of pocket #miscellaneous area is low and the breakdown voltage of the well area is low. Low, the voltage applied to the control Lanji can be r; volt: left and right. Moreover, with the above-mentioned structure, the flash memory of the present invention [: the body can use the cumulative collapse-induced hot electron injection mode to perform the program ^: ί ί7 tunneling effect to erase. In addition, the n 蜇 well area is connected to the drain circuit, and the reluctance is not to be missed.% A ^> M k — the reactor most forms a type 1 well area on the pole side, and this Ω The well-type area extends below the two I-wood structure, and then doped with plutonium in the source-side pocket. #The two ends of the impurity region are connected to each other:: 店所 c ^ χΛ 丄, · Λ ▲ doped region and n-type dopant The region has a lower η-type voltage than the η-type well region 2 and is lower than about 10 volts. The memory body can be connected to one with a tunnel FN tunneling tunnel, and will not be between the drain and the η-type well region. Shape ::) This method well—. Conductive type, this figure) Performing the formation of a first to the stack gate interval, shifting the photoresist The present invention provides a method for manufacturing a flash memory device, the following steps: In order to form a second conductivity type: method: a wide conductivity type second well area and a stacked interpolar structure 2. Formed on this substrate-the first patterned photoresist layer: electrical type one by one ^ ~ must you. Next, a bag implantation step is performed to form a second-conductivity-type third well region in the beauty of the drain region, and the second-conductivity-type third well pattern forms below the first electrode structure and forms a source region. After removing the first patterned photoresist layer from the substrate to the stack gate, a distance-space is formed on the substrate. Dirt patterned photoresist = The photoresist layer is exposed to a substrate that is intended to form a drain region. Dagger—The first pocket implantation step is performed in the pre-parishment ΛF t u ’

544860 五、發明說明（4) 層，且此第二圖案化光阻層暴露預定然後，進行-第二口袋植人步驟，於堆基底。近預定形成源極區之基底中形成一第—ς木、…構下方靠區。移除篦-闰安π 1 弟一導電型口袋摻雜底中形成源極區與沒極區。之後，晶二:、口構兩侧之基 ?成-間隙壁，並於基底上丄第】==側壁弟三圖案化光阻層暴露汲極區之基底。以=化=層，且 =與具有間隙壁之堆疊閘極結構為軍幕，；== 三圖丄i導電型第三井區之接面。移除第口茱化先阻層後，於基底上形成一第—矛結構之間的間隙’並舆源二區與沒：形：：ί 移除部分第三導體層，以於源極區上 m 第一接觸窗與於第二導電型第三井區上形成一g - 導體層。接著，圖案化第— 弟一此镜-拉奴W 口示％乐一导體層以形成一第二接觸窗，接觸固使汲極區與第二導電型第三井區形成一短路 '層上形ii丄於基底上形成一内層介電層，並於内層介電 v成與弟二接觸窗電性連接之一導線。域，ί &明係先以圖案化光阻層覆蓋住預定形成源極之區 ^=後利用傾斜角離子植入法，以0度至丨8 0度之傾斜 ’從預定形成汲極之區域植入^型摻質，以於汲極側形、、,,η里井區，然後再進行一熱製程，以使摻質驅入基底中 :η型井區延伸至堆疊閘極結構下方。之後，再以另一 =圖案化光阻層覆蓋住預定形成汲極之區域，並利用傾斜離子植入法’以3 〇度之傾斜角，從預定形成源極之區域544860 V. Description of the invention (4) layer, and the second patterned photoresist layer is to be exposed. Then, a second pocket implantation step is performed on the pile substrate. A substrate is formed in the substrate near to form the source region. The source region and the non-electrode region are formed in the 篦-闰安 π 1 conductive pocket doped substrate. Afterwards, the crystals on the two sides of the mouth structure are formed into a spacer, and the first and second sidewalls are formed on the substrate. The third patterned photoresist layer exposes the substrate of the drain region. Take the = layer, and = and the stacked gate structure with a gap wall as the military curtain; == the interface of the third well 导电 i conductive type third well area. After removing the first resist layer, a gap between the first and second spear structures is formed on the substrate, and the source and second regions are hidden: Shape :: ί Remove part of the third conductor layer to the source region The upper m first contact window forms a g-conductor layer on the second conductive type third well region. Next, patterning the first-conductor-lanu W interface with a conductor layer to form a second contact window, the contact solidifies the drain region and the third conductive region of the second conductivity type to form a short-circuit layer. Form II 丄 forms an inner dielectric layer on the substrate, and the inner dielectric v forms a wire electrically connected to the second contact window. In the Ming Dynasty, the patterned photoresist layer was used to cover the region where the source electrode was to be formed ^ = and then the tilt angle ion implantation method was used to tilt the electrode from the predetermined drain electrode with a tilt of 0 ° to 80 °. A ^ -type dopant is implanted in the region to drain the lateral wells of the drain, and then a thermal process is performed to drive the dopant into the substrate: the η-type well region extends below the stacked gate structure . After that, another patterned photoresist layer is used to cover the area where the drain electrode is to be formed, and the inclined ion implantation method is used to form a source electrode from the area where the source electrode is to be formed at an inclination angle of 30 degrees.

544860 五、發明說明（5) 植入η〜型摻質，、口袋摻雜區之，以於源極侧形成一η— 口袋摻雜區，此η — 區。利用傾斜:t而分別連接11型井區與後續形成之ρ +源極袋摻雜區形成；：：3可以準確的使η型井區與η - 口共用~11型井Jg、域，而且兩個相鄰的記憶胞可以元件之積集度'，而不會有11型井區重疊之問題，可以增加本發明接J述操作一P通道恤種快閃_記憶體元件之操作方法，適用於由一 P型基底；、憶體元件，此P通道快閃記憶體元件是井區，設置於第一n型井區，設置於P型基底中；一P型型基底上，堆田—n型井區中；一堆疊閘極結構，設置於P 層、—浮置f閘極結構包括一控制閘極、一閘極介電設置於堆疊閘=與一穿隧氧化層；-源極與-汲極，分別設置於p型井區：構兩側如型基底中；-第二η型井區，源極相距一門°中，從汲極延伸至堆疊閘極結構下方並盥且η-型口袋；；“：：二型口袋摻雜區設置於間隔中，上述之操作方兩側分別連接第二η型井區與源極；控制閘極施加細通道快閃記憶體元件時，對 -負電流，以利用？f ’使汲極區接地，對源極施加 i南、音kk日日用累i日朋〉貝引發熱電子注入模式軺通運快閃記憶體；在 ^^式化p 制閘極施加一負電冑，斟二迢决閃5己fe、體兀件時，對控逢要 €壓對源極施加一第二正電壓，脸上 /予置’以利用通道FN穿將汲極由於太# M ^ 應抹除P通道快閃記憶體。由於本啦明之P型通道快閃記體利用累增崩潰引發熱電子注入模式，目此程 <逯度可544860 V. Description of the invention (5) Implant η-type dopants and pocket-doped regions to form an η-pocket-doped region on the source side, and this η- region. The inclination: t is used to connect the 11-type well area with the subsequent formation of the ρ + source pocket doped area; :: 3 can accurately share the η-well area with the η-port ~ 11-well Jg, domain, and The accumulation degree of two adjacent memory cells can be 'without the problem of overlap of the 11-type well area. The method for operating the flash memory device of a P-channel according to the present invention can be added. Applicable to a P-type substrate; and a memory element, this P-channel flash memory element is a well area, which is arranged in the first n-type well area and is arranged in the P-type substrate; on a P-type substrate, the field is piled up —N-type well area; a stacked gate structure disposed on the P layer, —a floating f gate structure including a control gate, a gate dielectric disposed on the stacked gate = and a tunneling oxide layer; —source The pole and the -drain are respectively located in the p-type well area: on both sides of the structure, such as in the base;-the second n-type well area, the source is located one door away from each other, extending from the drain to the bottom of the stacked gate structure and cleaned; η-type pocket; ":: the second-type pocket doped region is arranged in the space, and the above two sides of the operator are respectively connected to the second n-type well region and When the gate is applied with a thin-channel flash memory element, a negative-to-negative current is used to ground the drain region by applying? F 'to the source. Hot electron injection mode: flash memory is applied; a negative voltage is applied to the p-type gate, and when two flashes are used, the controller must apply pressure to the source and apply one to the source. The second positive voltage, face / preset 'to use the channel FN to pass the drain due to # M ^ should be erased from the P channel flash memory. Because Ben Laming ’s P-type flash memory uses cumulative collapse to cause heat Electron injection mode

8938twf.ptd 第9頁 544860 五、發明說明（6) --- 以維持在微秒之程度（低於5微秒）。而且淮一批兩、％仃程式化時，熱電洞可以由源極跑掉，並不會注入穿隊翁 A乳化層，因士卜8938twf.ptd Page 9 544860 V. Description of the invention (6) --- To maintain the level of microseconds (less than 5 microseconds). In addition, when Huai batches are stylized, the thermal holes can be run away from the source and will not be injected into the penetrating A emulsifying layer.

以k升元件可靠度。而本發明之P型通道快閃記情 T 源極側具有陡峭的接合，不需要一個耐高壓的汲1亟。因此，可以增加元件之積集度。口本發明提供一種快閃記憶體元件之操作方法，作-記憶胞陣列，此記憶胞陣列是由複數個記憶胞 = 車複歹數位…乂及複數條源極線，其中記憶胞排之一條位兀線，每一列之各記憶胞之源極皆耦接對岸+之二條源極線，每一列之各記憶胞之控制間極皆耦接對應之一條字兀線，此操作方法係在進行程式化動作時，於選一記憶胞所耦接之一字元線上施加一第一正電壓，將 ^ ^ t位兀線接地，並於選擇之記憶胞所耦円/^1 一一負電流（亦即，對源極線施加一負電壓)付’- V:V、用字70線之複數個非選擇之記憶胞所耦接 ΐ:兀：：二藉此防止共用字元線之非選擇記憶胞被程式化，在進订項取動作日卑，胺、既矛王線接地，於選擇之2产:张擇之記憶胞所耦接之字元 r n ^ ^ I所耦接之位元線施加一第二正φ “固非選擇之記憶胞所麵接之字元線施加！ ;:、：上;加未:動：時’於選擇之記憶胞所•接之浮置與源極線接二第四正擇之記憶胞所耦接之位元線在進行上述程式化操作；：共用同一字元線之其他未 8938twf.ptd 第10頁Reliability in k liter components. However, the P-channel flash memory of the present invention has a steep junction on the T source side, and does not need a high-voltage-resistant drain. Therefore, it is possible to increase the degree of accumulation of components. The present invention provides a method for operating a flash memory element, which is a memory cell array. The memory cell array is composed of a plurality of memory cells = a car complex, a digital ..., and a plurality of source lines. One of the memory cell rows Bit line, the source of each memory cell in each column is coupled to the opposite + two source lines, and the control pole of each memory cell in each column is coupled to a corresponding word line. This operation method is in progress When programming, a first positive voltage is applied to a character line coupled to a selected memory cell, grounding the ^ ^ t bit line, and a negative current coupled to the selected memory cell / ^ 1 (I.e., applying a negative voltage to the source line) Fu'-V: V, coupled by a plurality of non-selected memory cells of the word 70 line: Wu :: This prevents the common word line from being wrong. The selected memory cell is stylized, and the action is taken on the entry item. The amine and the spear king line are grounded. The second product is selected: the character line rn ^ ^ I coupled to Zhang Xie's memory cell. Apply a second positive φ "The character line that the non-selected memory cell faces is applied!;:,: On; plus: move : Time 'in the selected memory cell • The floating and source lines connected to the second and fourth positively selected memory cells are performing the above-mentioned stylized operation;: Other unshared word lines 8938twf.ptd Page 10

54獅U 五、發明說明（7) 選擇之記憶胞並不會輕胞所耦接之位元線為^ J二這是因為其他未選擇之記憶選擇之記憶胞並不會在、、择托此共用同一字元線之其他未電壓’也無法造成累増崩、潰弓貝;J J崩•，即使字元施加有不會程式化其他未選擇节:，、、、電子注入現象，當然就並不會產生崩潰引發熱電子、、t λ寺口此未&擇之記憶胞 ± 14l ^ ^ ^ Ah y /入現象，而不會被程式化。六-，因tI_二:呆乍係利用累增崩潰引發熱電子注入模二）主 '化^·速度可以維持在微秒之程度（低於5微 :Λ于程式化時’熱電洞可以由源極跑掉，並不 "主：s牙隧氧化層’因此可以提升元件可靠度。而本發明之Ρ型通道快閃記憶元件在源極側具有陡山肖的接合，不需要-個耐高壓的汲極接合。因此，可以增加元件之積集度。、為讓本發明之上述目白勺、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：圖式之標號說明： 100、20 0 : Ρ型基底 1 0 2 ·元件隔離結構 1 04、2 0 2 :深η型井區 106 、 204 :ρ型井區 108、108a ··氧化層 110、110a、114 :導體層54 Lion U V. Description of the invention (7) The selected memory cell will not be lightly coupled to the bit line ^ J2 This is because other unselected memory selected memory cells will not The other unvoltages that share the same character line can't cause accumulation and collapse; JJ collapses, even if the character is applied, it will not stylize other unselected sections: ,,,, and electron injection phenomena, of course, and There will be no collapse caused by thermionic electrons, t λ Sikou and the memory cell ± 14l ^ ^ ^ Ah y / entry phenomenon, and will not be stylized. VI-, due to tI_II: The drowsiness system uses a cumulative collapse to trigger the injection of thermoelectrons. 2) The speed can be maintained in microseconds (below 5 micro: Λ at the time of stylization. Running away from the source does not " main: the s-tunnel oxide layer 'can therefore improve the reliability of the device. The P-channel flash memory device of the present invention has a steep hillside junction on the source side, and does not require- A high-voltage-resistant drain junction. Therefore, the accumulation degree of the components can be increased. In order to make the above-mentioned objectives, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and cooperates with all The drawings are described in detail as follows: Symbols of the drawings: 100, 20 0: P-type substrate 1 0 2 · Isolation structure 1 04, 2 0 2: Deep η-type well area 106, 204: ρ-type well area 108, 108a · Oxide layer 110, 110a, 114: Conductor layer

8938twf.ptd 第11頁 544860 五、發明說明（8) 1 1 2 :介電層 1 1 6 :閘極頂蓋層 1 1 8、2 0 6 :堆疊閘極結構 120、124、134 :圖案化光阻層 1 2 2、2 1 2 : η型井區 126、214 :η -型口袋摻雜區 1 2 8、2 0 8 :源極區 1 3 0、1 3 0 a、2 1 0 :汲極區 1 3 2、2 2 6 :間隙壁 1 3 6、1 3 8 :接觸窗 140 :開口 1 4 2 :内層介電層 144 :插塞 1 4 6 :導線 2 1 6 :穿隧氧化層 2 1 8 :浮置閘極 2 2 0 :閘極介電層 2 2 2 :控制閘極 2 2 4 :閘極頂蓋層8938twf.ptd Page 11 544860 V. Description of the invention (8) 1 1 2: Dielectric layer 1 1 6: Gate cap layer 1 1 8, 2 0 6: Stacked gate structure 120, 124, 134: Patterned light Resist layers 1 2 2, 2 1 2: n-type well regions 126, 214: n-type pocket doped regions 1 2 8, 2 0 8: source regions 1 3 0, 1 3 0 a, 2 1 0: drain Polar region 1 3 2, 2 2 6: spacer wall 1 3 6, 1 3 8: contact window 140: opening 1 4 2: inner dielectric layer 144: plug 1 4 6: wire 2 1 6: tunneling oxide layer 2 1 8: floating gate 2 2 0: gate dielectric 2 2 2: control gate 2 2 4: gate capping layer

Qnl、Qn2、Qn3、Qn4、Qn5、Qn6、Qn7、Qn8、Qn9、QnlO、QnllQnl, Qn2, Qn3, Qn4, Qn5, Qn6, Qn7, Qn8, Qn9, QnlO, Qnll

Qnl2 :記憶胞 BLO、BL1、BL2 :位元線Qnl2: memory cells BLO, BL1, BL2: bit lines

Nwell : n型井區 Pwell : p型井區Nwell: n-well Pwell: p-well

8938twf.ptd 第12頁 544860 五、發明說明（9) SL0、SL1 :源極線 WL0、WL1、WL2、WL3 :字元線實施例第1 A圖至弟1 I圖所示為根據本發明一較佳實施例之一種快閃s己憶體的製造流程立體圖。在此係以雙反或閑式 (Bi N0R)型陣列快閃記憶體為例。 > 首先請參照第1 A圖，提供一p型基底1 〇〇，此？型基底 1 0 0已形成元件隔離結構1 〇 2，此元件隔離結構1 〇 2成條狀的佈局’並用以定義出主動區。形成元件隔離結構丨(^例如是區域氧化法（Local Oxidation，L0C0S)或淺溝渠隔離法（Shallow Trench Isolation，STI)。接著，在p 型基底 100中形成深η型井區1〇4，並在此深0型井區1〇4内形成作為記憶胞陣列區域之ρ型井區1〇6。之後，於ρ型基底ι〇〇表面形成一層氧化層108，做為穿隧氧化層之用，氧化層】⑽ 之形成方法例如是熱氧化法，其厚度例如是90埃至1 〇〇埃 μ炎接同著’、請參照第16圖，於氧化層108上形成-層導體層（未圖不），其材質例如是摻雜的多晶矽，此導體芦之用化學氣相沈積法形成-層未摻心晶硬 :是800埃Λ 入步驟以形成之，且此導體層之厚度例件隔離結構3的=將此”層圖案化，使其暴露出元 Α的表面，而形成如圖式之導體層110。電層(未V示1參：依^於基底⑽ 層¥體層（未圖不）與一層頂蓋層（未圖8938twf.ptd Page 12 544860 V. Description of the invention (9) SL0, SL1: source lines WL0, WL1, WL2, WL3: word line embodiments 1A through 1B are shown in accordance with the present invention. A perspective view of a manufacturing process of a flash memory device in a preferred embodiment. Here is an example of dual inversion or idle (Bi N0R) type array flash memory. > First, please refer to FIG. 1A to provide a p-type substrate 100. This? The type substrate 100 has formed an element isolation structure 102, and this element isolation structure 102 has a strip-shaped layout 'and is used to define an active area. Forming an element isolation structure (for example, a local oxidation method (LOCOS) or a shallow trench isolation method (STI). Next, a deep n-type well region 104 is formed in the p-type substrate 100, and In this deep 0-type well region 104, a p-type well region 10 is formed as a memory cell array region. After that, an oxide layer 108 is formed on the surface of the p-type substrate ιOO as a tunneling oxide layer. The method of forming the oxide layer is, for example, a thermal oxidation method, and its thickness is, for example, 90 angstroms to 100 angstroms. In the same manner, please refer to FIG. 16 to form a conductive layer (not shown) on the oxide layer 108 (not shown). (Not shown), the material is, for example, doped polycrystalline silicon, the conductor is formed by chemical vapor deposition-the layer is not doped with core crystals: it is formed by an 800 Å step, and the thickness of the conductor layer is an example Isolation structure == This pattern layer is patterned so that it exposes the surface of element A to form a conductive layer 110 as shown in the figure. The electrical layer (not shown in FIG. 1 depends on the base layer and the body layer (not shown). (Not shown) and a cover layer (not shown)

8938twf.ptd 第13頁 544860 五、發明說明（10) 不）後，利用罩幕將此頂蓋層、導體層圖案化，用— =，極頂蓋層116與做為控制閘極之用的導體層114 ’疋義義V體層114的同時，繼續以相同的罩幕 =。與氧化謂，使其分別形成介電層極頂蓋層U6、導體層(控制問極)114、介二圖不= 層（洋置閘極）U〇a與氧化層1〇83(穿隧曰 =立所構成。乳儿層）的堆豐結構介電層112之材質例如是氧化矽/氮化矽/氧 ^ 厚度例如是60埃/70埃/6〇埃左右，介 = :法例如是低壓化學氣相沈積法。當；2 = 材負也可以是氧切層、氧切/氮化梦層等1層⑴之導體層114之材質例如是摻雜的多晶如疋2000埃左右，導體層114 ^度例 (In-SUu)摻雜離子之方式列如是以臨場之。万式利用化學氣相沈積法以形成閘極頂蓋層11 6之材質例如是氮化是1 5 0 0埃左右，閘極頂芸且，、厗度例如積法。員|層之形成方法例如是化學氣相沈丄接著請參照第1D圖’於整個基底100上形成一戶圖宰化光阻層120，此圖幸彳卜# M 氣層圖案域。缺德，谁r 一〇暴露欲形成沒極的區極钍槿11 8值FI丁安口袋（P〇Cket)離子植入步驟，以堆疊閘構人圖案化光阻層120為罩幕，於堆疊閘極結構 544860 五、發明說明（11) 11 8侧靠近汲極之基底1 〇〇中的p型井區1 06植入摻質，〜二千型雷井/122。植入之摻質!1如是磷離子，植入能量為電子伏特左右，植入劑量為1 X 1 013原子/平方公分工，。其中，植入摻質之方法包括傾斜角離子植入法， 0二以〇度至180度之傾斜角植入摻質。因此，n型井區122 伸至堆疊閘極結構118之下方，並與欲形成源極了或相距一段距離。移除圖案化光阻層丨2 〇後，進行一，製，，此熱製程例如是在9〇(TC左右之溫度下，於含氣之環境中進行摻質之驅入（Drive-in)。接著請參照第1E圖，於整個基底1〇〇上形成另一層圖 :化光阻層124，此圖案化光阻層124暴露欲形成源極曰的口區 5 。然後，進行一口袋離子植入步驟，以堆疊閘極結構 118^與圖案化光阻層124為罩幕，於堆疊閘極結構118下方之靠近源極之基底100中的p型井區1〇6植入摻質，以形成η 、型口袋摻雜區1 26。植入之摻質例如是砷離子，植入能量為30至50仟電子伏特左右，植入劑量為丨χ i，原子/平方公分左右。其中，植入摻質之方法包括傾斜角離子植入法，例如是以30度之傾斜角植入摻質。因此，n—型口袋摻雜區1 2 6係位於預定形成源極侧之堆疊閘極結構丨丨8下方並與η型井區122連接。此η-型口袋摻雜區126係用於調整源極侧之累增崩潰電壓。之後，移除圖案化光阻層丨2 4。接著请麥照第1 F圖，以堆疊閘極結構丨丨8為罩幕，進行一離子植入製程，於堆疊閘極結構丨丨8兩側之基底丨〇〇中植入摻質，以形成源極區1 2 8與汲極區1 3 0。植入之摻質例 8938twf.ptd 第15頁 544860 五、發明說明（12) 如疋一氟化硼（BF2 )離子，植入能量為3 右，植入劑量為1 X 1 〇i5原子/平方公分卢τ电子伏特左成後，使得η-型口袋摻雜區126之一二。源極區128形另一端鄰接η型井區122。之後，於堆疊區128，而壁形成間隙壁1 3 2，形成間隙壁丨3 2之步驟例^ Β 1 1 8之侧層絕緣層（未圖示），此絕緣層之材質例如Α 3 ^先形成一利用非等向性1虫刻法移除部分絕緣層已於；：n f，然後 1 1 8之側壁形成間隙壁1 3 2。、且巧極結構接著請參照第1G圖，於整個基底丨化光阻層134，此圖宰化光阻居·異中成一層圖案後進仃一蝕刻步驟，以圖案化光阻層134與具有 : 132之堆疊閘極結構丨18為罩幕， ^ ^日，、土共岡1 9 9 > * 鄉刻暴底1 0 0直到暴露11型麻後績形成之接觸窗會貫穿汲極區 ^ #上井&區1 22間之接面使兩者電性短路連接在一起。托仕娃者巧苓照第1 H圖，移除圖案化光阻層1 3 4後，於閘 :觸窗1的η型井區I2上形成接觸窗138。接觸窗136與 2带+十、之材質例如是金屬鎢。接觸窗1 36與接觸窗丨38 一 /，…法例如是先於基底100上形成一層導體層（未圖 Γ μ _此導體層填滿閘極結構11 8間的間隙。接著，進行一子機械研磨製程或回蝕刻製程，直到暴露閘極頂蓋層，而於閘極結構Π8之間的源極區128上形成接觸窗並於閘極結構11 8之間的η型井區丨2 2上形成導體層8938twf.ptd Page 13 544860 V. After the description of the invention (10) No), use the cover to pattern this top cover layer and conductor layer, use-=, pole top cover layer 116 and the conductor for controlling the gate electrode Layer 114 '疋义义 V body layer 114' while continuing with the same mask =. And oxidation so that they form a dielectric layer cap layer U6, a conductor layer (controller) 114, a dielectric layer = layer (foreign gate) U〇a and an oxide layer 1083 (tunneling said = Material layer. The material of the dielectric layer 112 of the stack structure is, for example, silicon oxide / silicon nitride / oxygen. The thickness is, for example, about 60 angstroms / 70 angstroms / 60 angstroms. Chemical vapor deposition. When; 2 = material negative can also be oxygen cut layer, oxygen cut / nitriding dream layer and other 1 layer of ⑴ conductive layer 114 material such as doped polycrystalline such as 疋 about 2000 angstroms, conductive layer 114 ^ degree example ( In-SUu) doped ions are listed in the field. Wan Shi uses a chemical vapor deposition method to form the gate capping layer 116. The material of the gate capping layer 116 is, for example, about 150 angstroms, and the gate top layer is, for example, the product method. The method for forming the member layer is, for example, chemical vapor deposition. Next, please refer to FIG. 1D ′ to form a patterned photoresist layer 120 on the entire substrate 100, and this picture is lucky # M air layer pattern domain. Deficiency, who r 10 exposes the area of the electrode to form a pole electrode, hibiscus 11 8 value FI Ding An pocket (PoCket) ion implantation step, using the stack gate structured patterned photoresist layer 120 as a mask, stacked Gate structure 544860 V. Description of the invention (11) 11 The p-type well region 106 in the substrate 100 on the 8 side near the drain electrode is implanted with dopants, ~ 2,000 thunder mine / 122. The implanted dopant! 1 If it is phosphorus ion, the implantation energy is about electron volts, and the implantation dose is 1 X 1 013 atom / cm2. Among them, the method of implanting the dopant includes a tilt angle ion implantation method, and implanting the dopant at a tilt angle of 0 to 180 degrees. Therefore, the n-type well region 122 extends below the stacked gate structure 118 and is at a distance from the source to be formed. After the patterned photoresist layer is removed, a thermal process is performed, for example, at a temperature of about 90 (TC) in a gas-containing environment (Drive-in). Next, referring to FIG. 1E, another layer is formed on the entire substrate 100: a photoresist layer 124, and the patterned photoresist layer 124 exposes the mouth region 5 where the source electrode is to be formed. Then, a pocket ion is performed. In the implanting step, dopants are implanted in the p-type well region 106 in the substrate 100 near the source below the stacked gate structure 118 and the patterned photoresist layer 124 as a mask. In order to form η, type pocket doped regions 1 26. The implanted dopants are, for example, arsenic ions, the implantation energy is about 30 to 50 仟 electron volts, and the implantation dose is 丨 χ i, about atoms / cm 2. Among them, Methods for implanting dopants include tilt-angle ion implantation, such as implanting dopants at a tilt angle of 30 degrees. Therefore, the n-type pocket doped regions 1 2 6 are stacked gates on the source side. Structure 丨丨 8 and connected to n-type well region 122. This n-type pocket doped region 126 is used to adjust the source side accumulation The breakdown voltage. After that, the patterned photoresist layer is removed. 2 4. Then ask Mai to perform the ion implantation process on the stacked gate structure with the stacked gate structure as shown in Figure 1 F. 8丨 Dopants are implanted into the substrate on both sides of the 丨 8 to form the source region 1 2 8 and the drain region 1 3 0. Examples of implanted dopants 8938twf.ptd Page 15 544860 V. Description of the invention (12 ) Such as boron monofluoride (BF2) ions, the implantation energy is 3 right, and the implantation dose is 1 X 1 0 i5 atom / cm 2 Lu τ electron volt left, so that the n-type pocket doped region 126 One or two. The other end of the source region 128 is adjacent to the n-type well region 122. Then, in the stacked region 128, the wall forms a gap wall 1 3 2 to form a gap wall 丨 3 2 Side layer ^ Β 1 1 8 side layer Insulating layer (not shown). The material of this insulating layer, such as A 3 ^, is first formed by removing the part of the insulating layer using the anisotropic 1 engraving method: nf, then the side wall of 1 1 8 forms the gap 1 3 2. And the clever electrode structure Please refer to FIG. 1G, and then photoresist layer 134 is formed on the entire substrate. In the etching step, the patterned photoresist layer 134 and a stacked gate structure with: 132 are used as a mask. ^^^, Tugonggang 1 9 9 > * Countryside blast bottom 1 0 0 until exposed to type 11 The contact window formed by the anaesthesia will run through the drain region ^ # 上井 & area 1 22 The interface between the 22 makes them electrically short-circuited together. Toshiwa Qiaoling according to Figure 1H, remove the pattern After the photoresist layer 134, a contact window 138 is formed on the n-type well region I2 of the gate: contact window 1. The contact windows 136 and 2 are +10, and the material is, for example, metal tungsten. The contact window 1 36 and the contact window 丨 38 A method is, for example, to form a conductor layer on the substrate 100 (not shown). This conductor layer fills the gap between the gate structures 118. Then, a sub-step is performed. Mechanical grinding process or etch-back process until the gate cap layer is exposed, and a contact window is formed on the source region 128 between the gate structures Π8 and on the n-type well region between the gate structures 118 2 Forming a conductor layer

544860 五、發明說明（13) (未圖示）。然後，進行一微影餘刻步驟，移除η型井區】2 2 上之部分導體層而形成開口丨4〇，以隔離相鄰之記憶胞而形成接觸窗138，而且接觸窗138會貫穿汲極區13〇3與11型井區1 2 2間之接面使兩者電性短路連接在一起。然後，於基底1〇〇上形成一層内層介電層142，此内層介電層142並填滿開口 140。内層介電層142之材質例如是硼磷矽玻璃（BPSG)或磷矽破璃（PSG)，形成内層介電層142 之方法例如是化學氣相沈積法。然後進行一化學機械研磨製程，使内層介電層142之表面平坦化。接著請參照第1 I圖，於内層介電層丨42内形成斑接觸窗138電性連接之插塞144，插塞144之材質例如是鎢金屬。形成插塞144之方法例如是先於内層介電層142中形成暴露接觸窗丨38之開口（未圖示），然後於開口内填入導體材料以形成之。之後，於内層介電層142上形成與插塞144 連接之導線146。形成導體層146之方法例如是於基底 ^上形*成導體層（未圖示）後，^亍微影_步驟而形成条片、之導線1 46。後續完成快閃記憶體之製程為習知技藝者所周知，在此不再贅述。 κ 二發明係先以圖案化光阻層12〇覆蓋住預定形成源極域，然後利用傾斜角離子植入法’以0度至18〇度之傾二共=成没極之區域植入n型摻質，以於汲極側二：ί n型井區122會延伸至堆疊閘極結構 118下方。然後再進行一熱製程，以使換質驅入基底㈣中。之後，再以另-層圖案化光阻層124覆蓋住預定形成麵 8938twf.ptd 第17頁 544860544860 V. Description of the invention (13) (not shown). Then, a photolithography step is performed to remove a portion of the conductive layer on the n-type well area 2 2 to form an opening 丨 40 to isolate adjacent memory cells to form a contact window 138, and the contact window 138 will penetrate The junction between the drain region 1303 and the 11-type well region 1 2 2 makes them electrically short-circuited together. Then, an inner dielectric layer 142 is formed on the substrate 100, and the inner dielectric layer 142 fills the opening 140. The material of the inner dielectric layer 142 is, for example, borophosphosilicate glass (BPSG) or phosphorous silicon broken glass (PSG). The method for forming the inner dielectric layer 142 is, for example, chemical vapor deposition. Then, a chemical mechanical polishing process is performed to planarize the surface of the inner dielectric layer 142. Next, referring to FIG. 1I, a plug 144 for electrically connecting the spot contact window 138 in the inner dielectric layer 42 is formed. The material of the plug 144 is, for example, tungsten metal. The method of forming the plug 144 is, for example, forming an opening (not shown) that exposes the contact window 38 in the inner dielectric layer 142, and then filling the opening with a conductive material to form it. Thereafter, a conductive line 146 is formed on the inner dielectric layer 142 to be connected to the plug 144. The method of forming the conductive layer 146 is, for example, forming a conductive layer (not shown) on the substrate ^, and then performing a lithography step to form the strips and wires 146. The subsequent process of completing flash memory is well known to those skilled in the art, and will not be repeated here. The κ2 invention is to cover the predetermined source region with a patterned photoresist layer 120, and then use the tilt angle ion implantation method to implant the region of 0 ° to 180 ° with a total of n = 100% Type dopant, so that the drain side two: n-type well region 122 will extend below the stacked gate structure 118. Then, a thermal process is performed to drive the replacement into the substrate. After that, another-layer patterned photoresist layer 124 is used to cover the predetermined formation surface 8938twf.ptd page 17 544860

角，=£域，並利用傾斜角離子植入法，以30度之傾斜攸預定形成源極之區域植入n-型摻質，以於源極接n 口袋摻雜區126，此n— 口袋摻雜區126之兩端分別連棺入井區122與後續形成之源極區128。利用傾斜角離子連，可以準確的使η型井區122與η〜口袋摻雜區126形、、疋之區域，而且兩個相鄰的記憶胞可以共用一區I。’而不會有η型井區122重疊之問題，可以增加之積集度。 1千 =2。圖所&繪示為本發明之快閃記憶體之結構剖面圖。凊芩照第2圖，本發明之快閃記憶體是由ρ型基底 2〇〇、深η型井區202、ρ型井區204、堆疊閘極結構2〇6、極區208、汲極區210、η型井區212以及η—型口袋摻雜區^ 214所構成。堆疊閘極結構2〇6是由穿隧氧化層216、浮置閘極218、閘極介電層220、控制閘極222、閑極頂蓋層224 以及間隙壁2 2 6所構成。曰深η型井區202位於ρ型基底20 0中。ρ型井區2〇4位於深 η型井區中。堆疊閘極結構2〇6位於ρ型基底2〇〇上。源極區 2 08與汲極區210位於堆疊閘極結構2〇6兩側之ρ型基底2〇〇中。η型井區212位於ρ型井區2〇4中，且從汲極區21〇延伸至堆疊閘極結構20 6下方。η- 口袋摻雜區214位於堆疊閘極結構20 6下方，且位於源極區208與η型井區212之間。本發明於汲極側形成一η型井區2 1 2，且此η型井區2 i 2 延伸至堆疊閘極結構2 06下方，然後在源極侧形成一n_ 口袋摻雜區214，此η- 口袋摻雜區214之兩端分別連接源極區Angle, = £ domain, and using a tilt angle ion implantation method, an n-type dopant is implanted in a region that is intended to form a source at a tilt of 30 degrees, so that the source is connected to the n-pocket doped region 126. The two ends of the pocket doped region 126 are respectively connected to the well region 122 and the source region 128 formed subsequently. Utilizing the inclination angle ion connection, the n-type well region 122 and the n-pocket doped region 126 can be accurately made into a region of 、, 疋, and two adjacent memory cells can share a region I. There is no problem of overlapping n-type well regions 122, and the accumulation degree can be increased. 1 thousand = 2. The figure & shows a sectional view of the structure of the flash memory of the present invention. According to FIG. 2, the flash memory of the present invention includes a p-type substrate 200, a deep n-type well region 202, a p-type well region 204, a stacked gate structure 206, a pole region 208, and a drain electrode. Region 210, n-type well region 212, and n-type pocket doped region ^ 214. The stacked gate structure 206 is composed of a tunneling oxide layer 216, a floating gate 218, a gate dielectric layer 220, a control gate 222, a free-pole cap layer 224, and a spacer 226. The deep n-type well area 202 is located in the p-type base 200. The p-well area 204 is located in a deep n-well area. The stacked gate structure 206 is located on a p-type substrate 200. The source region 208 and the drain region 210 are located in a p-type substrate 2000 on both sides of the stacked gate structure 206. The n-type well region 212 is located in the p-type well region 204, and extends from the drain region 21o to below the stacked gate structure 206. The n-pocket doped region 214 is located below the stacked gate structure 206 and between the source region 208 and the n-well region 212. In the present invention, an n-type well region 2 1 2 is formed on the drain side, and the n-type well region 2 i 2 extends below the stacked gate structure 20 06, and then an n_ pocket doped region 214 is formed on the source side. The two ends of the n-pocket doped region 214 are respectively connected to the source region

8938twf.ptd 第18頁 5448608938twf.ptd Page 18 544860

$ 7Γ @ 乙 1 Z 2ϋ8與n型井區212 ^ — 具有相同之背景摻雜濃度，且“袋摻雜區2ΐ4 、-: 井區212淺之接合面，目此"袋摻雜區川乂 2 0 8之崩潰電壓較η型井區214對？型井區2〇4之崩低，施加於控制閘極222之電壓可低於1〇伏特卢^ ^ 且’藉由上述結構，本發明之快閃記憶體可以工。而潰引發熱電子注人模^進行程式化，i以通細穿^】進行抹除。此外，將n型井區21 2與汲極區21〇短路連接在〜一起，就可便於P-型通道記憶胞的讀取操作並提供隔離的 η型井區（Isolated Nwell)之電壓。第3圖所繪示為本發明之p型通道快閃記憶體之電路簡圖，在此係以B i NOR型陣列快閃記憶體為例。曰首先凊筝照第3圖，在第3圖中繪示複數個記憶胞^至 Qnl2、位元線BL0至位元線BL2、以及字元線WL〇至字元^ WL3。其中，§己憶胞Qnl、Qm、Qn?、Qnl()之汲極_馬接至位元線 BL0 ’ 3己t思胞Qn2、Qn5、Qn8、Qnll之 >及極麵接至位元線bli，記憶胞QnS、Qn6、Qn9、Qni2之 >及極麵接至位元線BL2。字元線 WL0連接記憶胞Qnl、Qm、Qn3之控制閘極，字元線wli連接記憶胞Q。4、QnS、Qn6控制閘極。字元線WL2連接記憶胞Qn7、 Qn8、Qn9之控制閘極。字元線WL3連接記憶胞QniQ、Qnu、Qni2 之控制閘極。記憶胞Qnl與Qn4、記憶胞Qn2與Qn5、記憶胞Qn3 與Qn6所屬之源極共用一條源極線SL0，記憶胞Qn7與11()、記憶胞Qn8與Qnll、記憶胞Qn9與Qnl2所屬之源極共用一條源極線 S L 1。源極線S L 0與源極線S L 1經由整個p型井區^ ^導通而$ 7Γ @ 乙 1 Z 2ϋ8 and n-type well region 212 ^ — have the same background doping concentration, and "bag doped region 2ΐ4,-: shallow junction surface of well region 212, hereby " bag doped region The breakdown voltage of 02 08 is lower than that of the n-type well area 214 and the 井 -type well area 204. The voltage applied to the control gate electrode 222 can be lower than 10 volts. ^ With the above structure, this The invented flash memory can work. The burst triggers the hot electron injection mold ^ to be programmed, and i is erased with a thin thread through ^]. In addition, the n-type well region 21 2 and the drain region 21 are short-circuited. Together, it can facilitate the reading operation of the P-channel memory cell and provide the voltage of the isolated n-type well (Isolated Nwell). Figure 3 shows the p-channel flash memory of the present invention. The circuit diagram is based on the B i NOR array flash memory as an example. Firstly, according to Figure 3, a plurality of memory cells ^ to Qnl2 and bit line BL0 are in place. The element line BL2, and the character line WL0 to the character ^ WL3. Among them, § has recalled the drains of the cells Qnl, Qm, Qn ?, Qnl () to the bit line BL0 '3, and the cell Qn2 , Qn5, Q n8 and Qnll are connected to bit line bli, and memory cells QnS, Qn6, Qn9, and Qni2 are connected to bit line BL2. Word line WL0 is connected to memory cells Qnl, Qm, and Qn3 The word gate wli is connected to the memory cell Q. 4, QnS, Qn6 controls the gate. The word line WL2 is connected to the control gates of the memory cells Qn7, Qn8, Qn9. The word line WL3 is connected to the memory cells QniQ, Qnu Control gates of Qni2. Memory cells Qnl and Qn4, memory cells Qn2 and Qn5, memory cells Qn3 and Qn6 share a source line SL0, memory cells Qn7 and 11 (), memory cells Qn8 and Qnll, memory The sources to which the cells Qn9 and Qnl2 belong share a source line SL 1. The source line SL 0 and the source line SL 1 are turned on through the entire p-type well region ^ ^

8938twf.ptd 第19頁 544860 五、發明說明（16) 具有相同電位。而且，每一個記憶胞心至仏12更包括從汲極區延伸至閘極結構下方之η型井區n 。 1 iNwe 11 接著請爹照表一、第4 A圖與第4 B圖，以明瞭本發明較佳實施例之p型通道快閃記憶體元件之操作模式，其係包括程式化（Program，第4A圖）、資料讀取^⑸㈦，以及抹除（Erase，第4B圖）等操作模式，並係以第3圖所示之記憶胞Qn5為例。當對記憶胞Qn5進行程式化時，係在控制閘極4 〇 8 (社丄）上施加一正偏壓Veg，其例如是8伏特至丨〇伏特左右；在源極402 (SL0)上施加一負電流—Is，其例如是_1〇〇微安培左右；將没極4 04 (BL1)接地。如此，在程式化時，由於在源極4 0 2施加一負電流’使電子可由空乏區中之電場得到動能而撞擊原子，而產生電子—電洞對，然後載子再藉由衝擊而獲得足夠之能量以產生許多非常熱載子（Very H〇t C a r r i e r)。於是，對控制閘極4 〇 8施加一電壓時，即可在浮置閘極40 6與源極402之間建立一個大的垂直電場，而得乂利用累立曰朋〉貝引發熱電子注入模式（Ava 1 anche I n(juced Hot Electron 電子穿過穿隧氧化層而注入洋置閘極406中，如第4A圖所示。而且本發明於^型井區與源極402之間形成有η —型口袋摻雜區412，此η -型口衣# 4區4 1 2具有較淺之接合面，因此可以降低^^ — 口袋摻雜區412對p +型源極區4〇2之崩潰電壓。 7 合在進行上述程式化操作時，記憶胞I與記憶胞Qn6並不运私式化。這是因為位元線BL〇與位元線BL2為浮置，因此8938twf.ptd Page 19 544860 V. Description of the invention (16) has the same potential. In addition, each memory cell to 仏 12 further includes an n-type well region n extending from the drain region to below the gate structure. 1 iNwe 11 Next, please refer to Table 1, Figure 4A and Figure 4B to understand the operation mode of the p-channel flash memory element in the preferred embodiment of the present invention, which includes the programmatic (Program, Section (Figure 4A), data reading ^ ⑸㈦, and erase (Erase, Figure 4B) and other operation modes, and the memory cell Qn5 shown in Figure 3 is used as an example. When the memory cell Qn5 is programmed, a positive bias voltage Veg is applied to the control gate 4 08 (community), which is, for example, about 8 volts to 丨 0 volts; applied to the source 402 (SL0) A negative current—Is, which is, for example, about 100 microamperes; ground electrode 4 04 (BL1) is grounded. In this way, when programming, a negative current is applied to the source 402 to cause electrons to gain kinetic energy from the electric field in the empty region and strike the atom, thereby generating an electron-hole pair, and then the carrier is obtained by the impact. Enough energy to produce many very hot carriers (Very Hot Carrier). Therefore, when a voltage is applied to the control gate 408, a large vertical electric field can be established between the floating gate 406 and the source 402, and the hot electron injection can be induced by using the Li Li Peng> Mode (Ava 1 anche I n (juced Hot Electron) The electrons pass through the tunneling oxide layer and are injected into the ocean gate 406, as shown in FIG. 4A. In addition, the present invention is formed between the ^ well region and the source electrode 402. η-type pocket doped region 412, this η-type mouthwear # 4 region 4 1 2 has a shallower junction surface, so it can be reduced ^ — pocket-doped region 412 to p + -type source region 4 0 2 Crash voltage. When performing the above-mentioned stylized operation, memory cell I and memory cell Qn6 are not privatized. This is because bit line BL0 and bit line BL2 are floating, so

544860 五、發明說明（17) 記憶胞Qn4與記憶胞Qn6並不會在源極側產生崩潰，即使字元線WL1施加有電壓，也無法造成累增崩潰引發熱電子注入現象，當然就不會程式化記憶胞Qn4與記憶胞(^6。此外，連接記憶胞Qnl、Qn2、Qn3之字元線WL0、連接記憶胞Qn7、Qn8、Qn9之字元線WL2、與連接記憶胞Qnl。、Qnll、544860 V. Description of the invention (17) Memory cell Qn4 and memory cell Qn6 will not cause a breakdown on the source side. Even if a voltage is applied to the word line WL1, it will not cause a cumulative breakdown and cause a hot electron injection phenomenon. Of course, it will not The stylized memory cell Qn4 and the memory cell (^ 6. In addition, the word line WL0 connecting the memory cell Qnl, Qn2, Qn3, the word line WL2 connecting the memory cell Qn7, Qn8, Qn9, and the connection memory cell Qnl., Qnll ,

Qnl2之字元線WL3的電壓為0伏特，因此記憶胞Qnl至Qn3與記憶胞Qn?至Qnl2並不會產生崩潰引發熱電子注入現象。且對同一條位元線而言，因為鎢導線陷入源極線中使得源極線具有低電阻特性，所以在程式化記憶胞Qn5時，對源極線 SL 0施加一負電流（施加一負電壓），使得崩潰只會產生在共用源極線SL0之記憶胞記憶胞Qn2與Qn5的源極側，而記憶胞Qng之字元線WL0並未施加任何電壓，因此記憶胞心並不會產生崩潰引發熱電子注入現象。另外，由於p型井區電阻為〜2千歐姆左右，位元線BL〇之電流幾乎不會經過p型井區，因此記憶胞Qn?至Qnw之源極側因為還需要通過一 p型井區電阻（〜2千歐姆），所以需要的崩潰電壓較高’也盔法造The voltage of the zigzag line WL3 of Qnl2 is 0 volts, so the memory cells Qnl to Qn3 and the memory cells Qn? To Qnl2 do not cause a breakdown and cause a hot electron injection phenomenon. And for the same bit line, because the tungsten wire is trapped in the source line so that the source line has a low resistance characteristic, when the memory cell Qn5 is programmed, a negative current is applied to the source line SL 0 (apply a negative Voltage), so that the breakdown will only occur on the source side of the memory cells Qn2 and Qn5 of the shared source line SL0, and no voltage is applied to the word line WL0 of the memory cell Qng, so the memory cell heart will not be generated The collapse triggered hot electron injection. In addition, since the resistance of the p-type well region is about 2 kiloohms, the current of the bit line BL0 will hardly pass through the p-type well region, so the source side of the memory cells Qn? To Qnw needs to pass through a p-type well. Zone resistance (~ 2 kohms), so higher breakdown voltage is needed 'also made by helmet method

成累增崩潰引發熱電子注入現象，當然就不會程式胞‘至Qnl2。 °己U 在進行記憶胞Qns之讀取操作時，記憶胞9 可設定如下"立元咖(没極404)之偏壓^，其 UHr特至3· 3伏特左右、字元線乳1(控制閘極408)、源1 "(源極402 )接地，而對其他字元線WL0、WL2、紅3於 ί雪ί壓Vcg ’其例如是3. 3伏特左右。由於浮置閘極406存有電子的記憶胞的通道關閉且電流很小，而浮置閘極4〇6Accumulation and collapse will cause the phenomenon of hot electron injection. Of course, it will not program the cell to Qnl2. ° 己 U When carrying out the reading operation of the memory cell Qns, the memory cell 9 can be set as follows " Liyuanca (Waiji 404) bias voltage ^, its UHr is about 3.3V, the character line milk 1 (Control gate 408), the source 1 " (source 402) is grounded, and the other word lines WL0, WL2, and red 3 are pressed Vcg ', which is, for example, about 3.3 volts. Because the channel of the memory cell containing the electrons in the floating gate 406 is closed and the current is small, the floating gate 406

544860 五、發明說明（18) 未存有電子的記憶胞的通道打胞之通道開關/通道電流大小來"^電流大，故可藉由記憶數位資訊是「丨」還是「〇」。判斷儲存於此記憶胞中的當對記憶胞QnS進行抹除時 4〇8)上施加一負偏壓Vcg，其例，在字元線WL〇(控制閘極線SL0(源極4〇2)施加一正偏厣伏特左右，對源極右，使沒極404與基底400浮二S ’其例如是1〇伏特左即會使η型井區充電至i 0伏特而^極402 ( 1 〇伏特、P+型）可在浮置閑極4〇6與基⑽〇之間而促進— 1合。如此，即以利用通道F-N穿隧效應將電一個大的電場，而得拉出，如第4B圖所示。子經由通這從浮置間議中本發明之快閃記憶區’使η型井區與汲極短路連接在」起=二成1型〗544860 V. Description of the invention (18) The channel switch / channel current of the memory cell that does not have an electronic memory cell has a large current. Therefore, it is possible to remember whether the digital information is "丨" or "〇". It is judged that a negative bias voltage Vcg is applied to the memory cell when the memory cell QnS is erased (408), for example, on the word line WL0 (control gate line SL0 (source electrode 402) A positive bias voltage is applied to the source to the right, so that the pole 404 and the substrate 400 are floated S ′, which is, for example, 10 volts left, which will cause the n-type well area to charge to i 0 volts and ^ pole 402 (1 〇 Volts, P + type) can be promoted between the floating idler 406 and the base ⑽0—in this way, the electric field can be pulled out by using the channel FN tunneling effect, as shown in the figure. As shown in Figure 4B, the sub-via through the flash memory region of the present invention 'makes the n-type well region and the drain short-circuited at "from = 20% type 1"

型通道記憶胞的讀取操作，並提，可便於P 電壓。而曰产、店k ,丨 1权仏^離的η型井區之準^ 之Λ山^ 形成一口袋摻雜區，此口袋摻雜 μ ‘为別連接源極區與η型井區。由於此口代” 型井區具有相同之背景摻雜濃度，且口、衣匕區^ 型井區淺之接合面，因此口袋摻雜；具有較The read operation of the memory cell of the type channel, and mention, can facilitate the P voltage. In addition, the production and store k, and the right of the n-type well region are formed to form a pocket doped region, and this pocket doped μ ′ is to connect the source region and the n-type well region. Because this mouth-type well area has the same background doping concentration, and the mouth and clothing area are shallow junction surfaces, the pocket is doped;

壓低。於是，在進行快閃記憶;丄=，知作k，施加於控制閘極之電壓可低於丨〇伏私式由於本發明之p型通道快閃記憶元件、1 。以維持在微秒之程度（低於5微秒）。而且//之速度熱電洞可以由源極跑掉，並不會注入穿丁^化時，才丨攻虱化層，因此Drive down. Therefore, when performing flash memory; 丄 =, known as k, the voltage applied to the control gate can be lower than 0 volt private type. Because of the p-type channel flash memory element 1 of the present invention. To maintain the level of microseconds (below 5 microseconds). Moreover, the speed of the hot hole can be run away from the source, and it will not be injected when the piercing layer is injected, so

544860 五、發明說明（19) 以提升兀件可罪度。而本發明之P型通道快閃記憶元件在 :極區和源極側都具有陡峭的接合，不像傳統的P-通道記胞一樣在汲極側需要一個耐高壓的接合，因此可以增加兀件之積集度。 ?然本發明已以一較佳實施例揭露如明當;〃脫㈣發:Ϊ: 護範圍當視後者=本發明之保 544860 圖式簡單說明第1 A圖至第1 I圖所繪示為本發明快閃記憶體之製造流程立體圖。第2圖所繪示為本發明之快閃記憶體之結構剖面圖。第3圖所繪示為本發明之p型通道快閃記憶體之電路簡圖。第4A圖所繪示為本發明之p型通道快閃記憶體之程式化操作模式示意圖。第4B圖所繪示為本發明之p型通道快閃記憶體之抹除操作模式示意圖。表一為本發明較佳實施例之P型通道快閃記憶體元件之程式化、資料讀取以及抹除等操作模式。544860 V. Description of the Invention (19) To increase the guilt of the element. The P-channel flash memory element of the present invention has a steep junction in both the polar region and the source side, unlike the conventional P-channel memory cell, which requires a high-voltage-resistant junction on the drain side, so it can be increased. The degree of integration of the pieces. However, the present invention has been disclosed as a clear example with a preferred embodiment; 〃 hair loss: Ϊ: protection range when the latter = the guarantee of the present invention 544860 diagrams briefly illustrated in Figures 1A to 1I This is a perspective view of the manufacturing process of the flash memory of the present invention. FIG. 2 is a cross-sectional view showing the structure of the flash memory of the present invention. FIG. 3 is a schematic circuit diagram of a p-channel flash memory according to the present invention. FIG. 4A is a schematic diagram of the programmed operation mode of the p-channel flash memory of the present invention. FIG. 4B is a schematic diagram of the erase operation mode of the p-channel flash memory of the present invention. Table 1 shows the operation modes of programming, data reading, and erasing of the P-channel flash memory device in the preferred embodiment of the present invention.

8938twf.ptd 第24頁 544860 表一程式化讀取抹除選擇位元線 BL1 接地 Vd 浮置非選擇位元線 BL0、BL2 浮置浮置马、. 浮置選擇字元線 WL1 +vcg 接地 Vcg 非選擇字元線 WL0、WL2、 WL3 〇伏特 Vcc 〇伏特選擇源極線 SL0 -Is 接地 +VS 非選擇源極線 SL1 〇安培〇伏特〇伏特8938twf.ptd Page 24 544860 Table 1 Programmable read erase select bit line BL1 ground Vd Float non-select bit line BL0, BL2 Float floating horse,. Float select word line WL1 + vcg Ground Vcg Unselected word line WL0, WL2, WL3 〇Voltage Vcc 〇Voltage selected source line SL0 -Is ground + VS Unselected source line SL1 〇Ampere 〇Voltage 〇Voltage

Claims

544860 六、申請專利範圍 β ^^ 1 · 一種快閃記憶體元件> & w 为結構包括：件之結構，該快閃記憶體元件之一第一導電型基底；一第二導電型第一并F ^ 於該基底中； Q ’該第二導電型第一井區設置 ' 一弟*導電型第二并p 於該第二導電型第一井區；：5玄第-導電型第二井區設置型基：：疊閘極結構’該堆疊開極結構設置於該第-導電一源極區與一；:及極區，於該堆疊閘極結構兩側的兮^源極區與該汲極區分別設置一篦-道予⑷μ - 弟一導電型基底中；於兮第弟三井區，該第二導電型第二井f外署於该弟一導電型第二井區以工电玉罘一开&汉置構下方並與該源極區相距—，從該汲極區延伸至該堆疊結一第二導電型口袋摻雜隔，以及設置於兮±4田日日隹^ ’該第二導電型口袋找；^广罝於4堆豐閘極結構下衣摻雜區之兩側分別連接該第-導雷刑^该弟二¥電型口袋摻雜區 2.如由4V電型苐三井區與該源極區。構，其中該^ — 述之快閃記憶體元件之結 3如 :^電型基底包括p型基底。構，其中二=專利範圍第1項所述之快閃記憶體元件之包括η型井區弟-導電型第-井區與該第二導電型第三井°區構，4复Ϊ I ΐ專利範圍第1項所述之快閃記憶體元件Μ 、中该弟一導電型第二井區包括？型井區。午之結 544860 六、申請專利範圍 5·如申構，其中該 6·如申構，其中該 7 ·如申構，其中該路連接一起 8 ·如申構’其中該導電型第三 9.如申構’其中該有第一導電第一井區、請專利範圍第二導電型請專利範圍源極區與該請專利範圍沒極區與該第1項所述之快閃記憶體元件口袋摻雜區包括η -型口袋換^，第1項所述之快閃記憶體元相:*區。 1干之ό士汲極區係摻雜Ρ型離子。第1項所述之快閃記憶體元件之& 第二導電型第三井區係以— j 請專利範圍電性短路係井區間之接請專利範圍第二導電型區之摻雜濃度相同。 10· —種快閃記憶列步驟：提供具第二導電型極結構；第7項所述之快閃記憶體元件之会士以一接觸窗貫穿該汲極區與該第面。第1項所述之快閃記憶體元件之屋士口袋摻雜區與該第二導電型第三井體元件之製造方法，該方法包括下型之一基底，該基底已依序形成一一第一導電型第二井區與一堆叠問於該基底上形成一第一圖案化光阻層，該第一圖案化光阻層暴露預定形成一汲極區之該基底； /、進行第口袅植入步驟，於預定形成該；:及極區之該基底中形成一第二導電型第三井區，且該第二導電型第^ 井區延伸至該堆疊閘極結構下方並與預定形成一源極區之該基底相距一間隔；544860 6. Scope of patent application β ^^ 1 · A flash memory element > & w is a structure including: a structure of one of the flash memory elements, a first conductivity type substrate; a second conductivity type first F ^ in the substrate; Q 'the second conductive type first well area is set up'; a brother * conductive type second and p in the second conductive type first well area; Type-type bases in two well areas :: stacked gate structure 'the stacked open-pole structure is provided in the -conducting one source region and one; and the pole region is located on both sides of the stacked gate structure. And a drain region are respectively provided in a base-conductor-type conductive substrate; in the second-conductor-type second well area of the second-conductor-type second well area, An industrial and electrical jade is opened under the Han structure and is spaced from the source region, extends from the drain region to the stacked junction, a second conductivity type pocket doped spacer, and is set at Xi ± 4 Tianri隹 ^ 'The second conductive type pocket is to be found; ^ Guang Ye is connected to the two sides of the doped region of the bottom of the 4 stack gate structure, respectively. - the guide Ray Penalty ^ ¥ brother two pocket-type-doped region 2 of a 4V Ti Mitsui type region and the source region. Structure, wherein the structure of the flash memory element described in the above example 3 is as follows: the type substrate includes a p-type substrate. Structure, where 2 = the flash memory element described in item 1 of the patent scope includes the n-type well area-conducting type-well area and the second conductivity type third-well area structure, 4 complex Ϊ I ΐ The flash memory element M described in the first item of the patent scope, and the second well area of the conductive one of the conductive type include? Well area. Noon knot 544860 6. Application scope of patent 5. Rushen structure, of which 6. Rushen structure, of which 7. Rushen structure, where the road is connected together 8. Rushen structure, where the conductive type is third 9. Such as the application of 'there is a first conductive first well area, patented range of the second conductive type patented range of the source area and the patented non-polar area and the flash memory device pocket described in the first item The doped region includes n-type pockets, and the flash memory element phase: * region described in item 1. 1 dry matter doped region is doped with P-type ions. The & second conductivity type third well region of the flash memory device described in item 1 is the same as the doping concentration of the second conductivity type region in the patent range of the electrical short circuit well interval in the patent range. . 10 · — A kind of flash memory Steps: Provide a flash memory device with a second conductivity type; the member of the flash memory element described in item 7 runs through the drain region and the first surface with a contact window. The method for manufacturing a house pocket doped region of a flash memory device described in item 1 and the second conductivity type third well body device, the method includes one of the following types of substrates, and the substrates have been sequentially formed one by one. A first conductive type second well region and a stack form a first patterned photoresist layer on the substrate, and the first patterned photoresist layer exposes the substrate that is intended to form a drain region;袅 An implantation step is formed on the substrate; and a second conductive type third well region is formed in the substrate of the polar region, and the second conductive type ^ well region extends below the stacked gate structure and is predetermined The substrate forming a source region is spaced apart;

544860 六、申請專利範圍移除該第一圖案化光阻層；於該基底上形成一第二圖案化光阻層，該第二圖案化光阻層暴露預定形成該源極區之該基底；進行一第二口袋植入步驟，於該堆疊閘極結構下方靠近該預定形成該源極區之該基底中形成一第二導電型口袋按雜區；移除該第二圖案化光阻層；於該堆疊閘極結構兩侧之該基底中形成該源極區與該 >及極區；於該堆疊閘極結構之側壁形成一間隙壁；於該基底上形成一第三圖案化光阻層，該第三圖案化光阻層暴露該汲極區之該基底；以該第三圖案化光阻層與具有該間隙壁之該堆疊閘極結構為罩幕^ "I虫刻該汲·極區之該基底直到貫穿該〉及極區與該第二導電型第二井區之接面；移除該第三圖案化光阻層；於該基底上形成一第一導體層，該第一導體層填滿該堆疊閘極結構之間的間隙，並與該源極區與該汲極區電性連接；移除部分該第一導體層，以於該源極區上形成一第一接觸窗與於該第二導電型第三井區上形成一第二導體層；圖案化該第二導體層以形成一第二接觸窗，該第二接觸窗使該汲極區與該第二導電型第三井區形成一短路連接，544860 6. Apply for a patent to remove the first patterned photoresist layer; form a second patterned photoresist layer on the substrate, and the second patterned photoresist layer exposes the substrate that is intended to form the source region; Performing a second pocket implantation step, forming a second conductive pocket-type impurity region in the substrate below the stacked gate structure near the predetermined formation of the source region; removing the second patterned photoresist layer; Forming the source region and the > and electrode regions in the substrate on both sides of the stacked gate structure; forming a gap wall on a sidewall of the stacked gate structure; forming a third patterned photoresist on the substrate Layer, the third patterned photoresist layer exposes the substrate of the drain region; the third patterned photoresist layer and the stacked gate structure with the spacer are used as a mask ^ " I insect carved the drain The substrate of the polar region up to the interface between the polar region and the second well type and the second well region; removing the third patterned photoresist layer; forming a first conductor layer on the substrate, the A first conductor layer fills a gap between the stacked gate structures, Electrically connected to the source region and the drain region; removing a portion of the first conductor layer to form a first contact window on the source region and forming a first contact window on the second conductive type third well region A second conductor layer; patterning the second conductor layer to form a second contact window, the second contact window forming a short-circuit connection between the drain region and the second conductive type third well region,

8938twf.ptd 第27頁 544860 六、申請專利範圍於該基底上形成一内層介電層；以及於該内層介電層上形成與該第二接觸窗電性連接之一導線。 11.如申請專利範圍第1 0項所述之快閃記憶體元件之製造方法，其中該第一口袋植入步驟包括一傾斜角離子植入法。 1 2.如申請專利範圍第1 0項所述之快閃記憶體元件之製造方法，其中該第一口袋植入步驟之傾斜角度包括0度至180度左右。 1 3.如申請專利範圍第1 0項所述之快閃記憶體元件之製造方法，其中該第二口袋植入步驟包括一傾斜角離子植入法。 1 4.如申請專利範圍第1 0項所述之快閃記憶體元件之製造方法，其中該第二口袋植入步驟之傾斜角度包括3 0度左右。 1 5.如申請專利範圍第1 0項所述之快閃記憶體元件之製造方法，其中於該第一口袋植入步驟之後與移除該第一圖案化光阻層之步驟之前更包括一摻質驅入製程。 1 6.如申請專利範圍第1 0項所述之快閃記憶體元件之製造方法，其中更包括於該内層介電層中形成一插塞，該插塞電性連接該導線與該第二接觸窗。 1 7.如申請專利範圍第1 0項所述之快閃記憶體元件之製造方法，其中該第一導電型基底包括p型基底。 1 8.如申請專利範圍第1 0項所述之快閃記憶體元件之8938twf.ptd Page 27 544860 6. Scope of patent application: An inner dielectric layer is formed on the substrate; and a wire electrically connected to the second contact window is formed on the inner dielectric layer. 11. The method for manufacturing a flash memory device according to item 10 of the scope of the patent application, wherein the first pocket implantation step includes an oblique angle ion implantation method. 1 2. The method for manufacturing a flash memory device as described in item 10 of the scope of patent application, wherein the inclination angle of the first pocket implantation step includes about 0 to 180 degrees. 1 3. The method for manufacturing a flash memory device as described in item 10 of the scope of patent application, wherein the second pocket implantation step includes an oblique angle ion implantation method. 14. The method for manufacturing a flash memory device as described in item 10 of the scope of the patent application, wherein the inclination angle of the second pocket implantation step includes about 30 degrees. 1 5. The method for manufacturing a flash memory device as described in item 10 of the patent application scope, further comprising a step after the first pocket implantation step and before the step of removing the first patterned photoresist layer. Spiking into the process. 16. The method for manufacturing a flash memory device as described in item 10 of the scope of patent application, further comprising forming a plug in the inner dielectric layer, the plug electrically connecting the wire to the second Contact window. 1 7. The method for manufacturing a flash memory device according to item 10 of the scope of patent application, wherein the first conductive type substrate includes a p-type substrate. 1 8. The flash memory device described in item 10 of the scope of patent application

8938twf.ptd 第28頁 544860 六、申請專利範圍製造方法，其中該第二導電型第一井區與該第二導電蜜第二井區包括η型井區。 1 9.如申請專利範圍第1 〇頊所述之快閃記憶體元件之製造方法，其中該第一導電塑第二井區包括ρ型井區。 2 〇 ·如申請專利範圍第1 0項所述之快閃記憶體元件之製造方法，其中該第二導電型口袋摻雜區包括η-型口袋摻雜區。 2 1 · —種快閃記憶體元件之操作方法，適用於操作一 ρ 通道快閃記憶體元件，該Ρ通道快閃記憶體元件包括一ρ塑基底；一第一η型井區，設置於該Ρ型基底中；一ρ型井區，設置於該第一 η型井區中；一堆疊閘極結構，設置於 "亥ρ型基底上，該堆疊閘極結構包括一控制閘極；一源極與汲極，分別設置於該堆疊閘極結構兩側的該ρ型基底 :兮 ί 型井區，設置於該ρ型井區中，從該汲極延伸〜ί ^ ^閘極結構下方並與該源極相距一間隔；以及一η 袋摻二二摻雜區設置於該堆疊閘極結構下方，且該η—型口法包括品之兩侧分別連接第二η型井區與該源極；且該方在施加~ 電流，道快閃 ^式化該ρ通道快閃記憶體元件時，對該控制閘極弟—正電壓，使該汲極區接地，對該源極施加一，利用累增崩潰引發熱電子注入模式程式化該？通冗憶體元件；以及加在抹除該ρ通道快閃記憶負電壓，將該汲極浮置體元件時，對該控制閘極施對該源極施加一第二正電8938twf.ptd Page 28 544860 VI. Patent Application Manufacturing method, wherein the second conductive type first well area and the second conductive honey second well area include n-type well areas. 19. The method for manufacturing a flash memory device as described in claim 10, wherein the first conductive plastic second well region includes a p-type well region. 2 0. The method for manufacturing a flash memory device as described in item 10 of the scope of the patent application, wherein the second conductive type pocket doped region includes an n-type pocket doped region. 2 1 · —A method of operating a flash memory device, suitable for operating a ρ-channel flash memory device. The P-channel flash memory device includes a ρ plastic substrate; a first n-type well area is provided in the In the P-type substrate; a ρ-type well region disposed in the first η-type well region; a stacked gate structure disposed on the " Hio-type substrate, the stacked gate structure including a control gate; A source electrode and a drain electrode are respectively disposed on the p-type substrates on both sides of the stacked gate structure: Xi-type well regions are disposed in the p-type well region and extend from the drain electrode ~ ^ ^ gate structure A gap between the lower gate electrode and the source electrode; and an n-bag doped two-doped region disposed below the stacked gate structure, and two sides of the n-type gate method are respectively connected to the second n-type well region and The source; and when applying ~ current to the channel to quickly flash the ρ channel flash memory element, the control gate brother-a positive voltage, grounds the drain region, and applies to the source First, stylized using the hot electron injection mode triggered by cumulative collapse? Pass the memory element; and when the negative voltage of the flash memory of the ρ channel is erased, when the drain is floated, the control gate is applied with a second positive voltage to the source.

544860 六、申請專利範圍反’以利用通道15^穿隧效應抹除該p通道快閃記憶體元件。 σ 22·、如申請專利範圍第21項所述之快閃記憶體元件之作方法’其&中該第〜正電壓包括8伏特至丨〇伏特左右。 23·、如申睛專利範圍第2 1項所述之快閃記憶體元件之木作方法，其i中該負電流為一 i⑽微安培左右。如申甘請/利範圍第21項所述之快閃記憶體元件之紅作方法，其中該負電壓為-10伏特左右。 2 5 ·如申請專利範圍第2丨項所^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 操作方法，JL中兮筮义 < 决閃Z 體7G件之卞讣力成、中忒第二正電壓為1 0伏牲产士 26. —種快閃記憶體元人特左右。憶胞陣列’該記憶胞陣列包方法’用以操作-記元線’複數位元線以及複數條源極： = 複= 成一行/列陣列，每一行此/、八中族二圮fe胞排對應之一條位元線’每一 ^二冗憶胞之汲極皆耦接所對應之一條源極線；每一 ^ c憶胞之源極皆耦接輕接對應之一條字元綠；該操作己憶胞之控制開極皆在進行程式化動作時，於選擇^包括： - ΛΑ ^ < 一記憶胞所耦接之一子兀線上施加一第一正電壓，於該柄接之 Lh , I 、/ L月匕所輛接之一位开、=接地’亚於該記憶胞所耗接之—源、極線施加一負電产- 同^用該字元線之複數個非選擇之記憶胞物：憶胞被程式化； -線之该些非選擇之記在進行讀取動作時’將選擇之讀記憶胞物妾之該字544860 6. Scope of patent application Inverted 'uses the channel 15 ^ tunneling effect to erase the p-channel flash memory element. σ 22. The method for operating a flash memory device as described in item 21 of the scope of the patent application, wherein the & positive voltage in the & includes about 8 volts to about 0 volts. 23. The method of making a flash memory device as described in item 21 of the patent application, wherein the negative current in i is about i⑽ microamperes. The red operation method of the flash memory device as described in claim 21, wherein the negative voltage is about -10 volts. 2 5 · As described in item 2 丨 of the scope of patent application For the 10-volt sire 26. —A kind of flash memory is about RMB 1 million. Memory cell array 'This memory cell array package method' is used to operate-the token line 'multiple bit lines and multiple sources: = complex = into a row / column array, each row of this /, eight middle family two cells A row corresponds to a bit line, and the drain of each ^ 2 redundant memory cell is coupled to a corresponding source line; the source of each ^ c memory cell is coupled to a corresponding one of the character green; In this operation, when the control open pole of the memory cell is performing a stylized action, the selection ^ includes:-ΛΑ ^ < a first positive voltage is applied to a sub-line coupled to a memory cell, and the handle is connected to Lh, I, / L Moon Dagger is connected one by one, = grounded 'is less than that consumed by the memory cell-a negative electricity is applied to the source and polar lines-the same as the non-selection of the word line The memory cell: The memory cell is stylized;-the non-selected notes of the line, when performing the reading action, 'will read the selected memory cell'

8938twf.ptd8938twf.ptd

544860 六、申請專利範圍元線接地，於該記憶胞所耦接之該位元線施加一第二正電壓’同時於複數個非選擇之記憶胞所耦接之該些字元線施加一第三正電壓；以及、進行抹除操作時，於選擇之該記憶胞所耦接之該字元線^施加一負電壓，將該記憶胞所耦接之該位元線接地，於該記憶胞所耦接之該源極線施加一第四正電壓。 ^ 2 7 ·如申睛專利範圍第2 6項所述之快閃記憶體元件之才木作方法’其中每—該些記憶胞包括：一Ρ型基底；一第一η型井區，設置於該ρ型基底中；一 Ρ型$井區，設置於該第一 η型井區中；隹且間極結構，設置於該Ρ型基底上，該堆疊閘極結構包括一控制閘極；分別設置於該堆疊閘極結構兩側的一源極與一汲極該Ρ型基底中；一第二 Π ~^f>J or ^ ^ ^ pa , 區’設置於該P型井區中，從該汲極延伸以及區’没置於該堆豐閘極結構下方，且之兩側分別連接第二η型井區與該源至该堆豐問極社据 _ 、°構下方並與該源極相距一間隔 11型口袋摻雜該η-型口袋摻雜區極0 2 8 ·如申t奮查1 ^你古，寻利範圍第2 6項所述之快閃記憶體元件之本 ' 一中該第一正電壓為8伏特到1 0伏特左右。 2 9 如申'^主_ y & \ /寻利範圍第2 6項所述之快閃記憶體元件之操作方法，其Φ * ^ τ该負電流為-1 0 0微安培左右。544860 VI. Patent application: The element line is grounded. A second positive voltage is applied to the bit line coupled to the memory cell. At the same time, a number of non-selected memory cells is coupled to the word lines. Three positive voltages; and, when performing an erasing operation, a negative voltage is applied to the word line ^ to which the selected memory cell is coupled, and the bit line to which the memory cell is coupled is grounded to the memory cell A fourth positive voltage is applied to the coupled source line. ^ 2 7 · The method of flash memory device operation as described in item 26 of Shenyan's patent scope, wherein each of the memory cells includes: a P-type substrate; a first n-type well area; In the p-type substrate; a P-type $ well region is disposed in the first n-type well region; and an interpolar structure is disposed on the P-type substrate, and the stacked gate structure includes a control gate; A source and a drain are respectively disposed in the P-type substrate on both sides of the stacked gate structure; a second Π ~ ^ f > J or ^ ^ ^ pa, region 'is disposed in the P-type well region, Extending from the drain electrode and the area is not placed under the gate structure of the reactor, and the two sides are respectively connected to the second n-type well area and the source to the structure of the reactor and the structure below the reactor structure The source electrodes are spaced from each other by an 11-type pocket doped with the n-type pocket doped region electrode 0 2 8 · As described in Fencha 1 ^ Youguo, the flash memory device described in Item 26 'The first positive voltage is about 8 volts to about 10 volts. 2 9 As described in the method of operation of the flash memory element described in item 26 of the main profit range, the Φ * ^ τ negative current is about -100 microamperes.

第31頁 544860 六、申請專利範圍 3 0.如申請專利範圍第2 6項所述之快閃記憶體元件之操作方法，其中該負電壓為-1 0伏特左右。 3 1.如申請專利範圍第2 6項所述之快閃記憶體元件之操作方法，其中該第二正電壓為1. 5伏特至3. 3伏特左右。 3 2.如申請專利範圍第2 6項所述之快閃記憶體元件之操作方法，其中該第三正電壓為3. 3伏特左右。 3 3.如申請專利範圍第2 6項所述之快閃記憶體元件之操作方法，其中該第四正電壓為1 0伏特左右。Page 31 544860 VI. Patent application scope 30. The method of operating a flash memory device as described in item 26 of the patent application scope, wherein the negative voltage is about -10 volts. 3 1. The method of operating a flash memory element as described in item 26 of the scope of patent application, wherein the second positive voltage is from about 1.5 volts to about 3.3 volts. 3 2. The method of operating a flash memory element as described in item 26 of the scope of patent application, wherein the third positive voltage is about 3.3 volts. 3 3. The method of operating a flash memory device as described in item 26 of the scope of patent application, wherein the fourth positive voltage is about 10 volts.

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